diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h new file mode 100644 index 0000000..4d322f3 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h
@@ -0,0 +1,82 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + +#include "FreeRTOSConfig.h" + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the general purpose registers, CS and ES (only in far +; memory mode) registers the usCriticalNesting Value and the Stack Pointer +; of the active Task onto the task stack +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO + + PUSH AX ; Save AX Register to stack. + PUSH HL + MOV A, CS ; Save CS register. + XCH A, X + MOV A, ES ; Save ES register. + PUSH AX + PUSH DE ; Save the remaining general purpose registers. + PUSH BC + MOVW AX, usCriticalNesting ; Save the usCriticalNesting value. + PUSH AX + MOVW AX, pxCurrentTCB ; Save the Stack pointer. + MOVW HL, AX + MOVW AX, SP + MOVW [HL], AX + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Restores the task Stack Pointer then use this to restore usCriticalNesting, +; general purpose registers and the CS and ES (only in far memory mode) +; of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVW AX, pxCurrentTCB ; Restore the Stack pointer. + MOVW HL, AX + MOVW AX, [HL] + MOVW SP, AX + POP AX ; Restore usCriticalNesting value. + MOVW usCriticalNesting, AX + POP BC ; Restore the necessary general purpose registers. + POP DE + POP AX ; Restore the ES register. + MOV ES, A + XCH A, X ; Restore the CS register. + MOV CS, A + POP HL ; Restore general purpose register HL. + POP AX ; Restore AX. + ENDM +;------------------------------------------------------------------------------
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/port.c new file mode 100644 index 0000000..18fc494 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/port.c
@@ -0,0 +1,225 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include <stdlib.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* The critical nesting value is initialised to a non zero value to ensure +interrupts don't accidentally become enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING (( uint16_t ) 10) + +/* Initial PSW value allocated to a newly created task. + * 1100011000000000 + * ||||||||-------------- Fill byte + * |||||||--------------- Carry Flag cleared + * |||||----------------- In-service priority Flags set to low level + * ||||------------------ Register bank Select 0 Flag cleared + * |||------------------- Auxiliary Carry Flag cleared + * ||-------------------- Register bank Select 1 Flag cleared + * |--------------------- Zero Flag set + * ---------------------- Global Interrupt Flag set (enabled) + */ +#define portPSW (0xc6UL) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Most ports implement critical sections by placing the interrupt flags on +the stack before disabling interrupts. Exiting the critical section is then +simply a case of popping the flags from the stack. As 78K0 IAR does not use +a frame pointer this cannot be done as modifying the stack will clobber all +the stack variables. Instead each task maintains a count of the critical +section nesting depth. Each time a critical section is entered the count is +incremented. Each time a critical section is left the count is decremented - +with interrupts only being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick. + */ +static void prvSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t *pulLocal; + + #if configMEMORY_MODE == 1 + { + /* Parameters are passed in on the stack, and written using a 32bit value + hence a space is left for the second two bytes. */ + pxTopOfStack--; + + /* Write in the parameter value. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) pvParameters; + pxTopOfStack--; + + /* These values are just spacers. The return address of the function + would normally be written here. */ + *pxTopOfStack = ( StackType_t ) 0xcdcd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xcdcd; + pxTopOfStack--; + + /* The start address / PSW value is also written in as a 32bit value, + so leave a space for the second two bytes. */ + pxTopOfStack--; + + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* An initial value for the AX register. */ + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + } + #else + { + /* Task function address is written to the stack first. As it is + written as a 32bit value a space is left on the stack for the second + two bytes. */ + pxTopOfStack--; + + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* The parameter is passed in AX. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + } + #endif + + /* An initial value for the HL register. */ + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + + /* CS and ES registers. */ + *pxTopOfStack = ( StackType_t ) 0x0F00; + pxTopOfStack--; + + /* Finally the remaining general purpose registers DE and BC */ + *pxTopOfStack = ( StackType_t ) 0xDEDE; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBCBC; + pxTopOfStack--; + + /* Finally the critical section nesting count is set to zero when the task + first starts. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + vPortStart(); + + /* Should not get here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the 78K0R port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Setup channel 5 of the TAU to generate the tick interrupt. */ + + /* First the Timer Array Unit has to be enabled. */ + TAU0EN = 1; + + /* To configure the Timer Array Unit all Channels have to first be stopped. */ + TT0 = 0xff; + + /* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt + priority. */ + TMMK05 = 1; + + /* Clear Timer Array Unit Channel 5 interrupt flag. */ + TMIF05 = 0; + + /* Set Timer Array Unit Channel 5 interrupt priority */ + TMPR005 = 0; + TMPR105 = 0; + + /* Set Timer Array Unit Channel 5 Mode as interval timer. */ + TMR05 = 0x0000; + + /* Set the compare match value according to the tick rate we want. */ + TDR05 = ( TickType_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); + + /* Set Timer Array Unit Channel 5 output mode */ + TOM0 &= ~0x0020; + + /* Set Timer Array Unit Channel 5 output level */ + TOL0 &= ~0x0020; + + /* Set Timer Array Unit Channel 5 output enable */ + TOE0 &= ~0x0020; + + /* Interrupt of Timer Array Unit Channel 5 enabled */ + TMMK05 = 0; + + /* Start Timer Array Unit Channel 5.*/ + TS0 |= 0x0020; +} +/*-----------------------------------------------------------*/ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26 new file mode 100644 index 0000000..aa49f1a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26
@@ -0,0 +1,138 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + +#include "ISR_Support.h" +;------------------------------------------------------------------------------ + +#if __CORE__ != __78K0R__ + #error "This file is only for 78K0R Devices" +#endif + +#define CS 0xFFFFC +#define ES 0xFFFFD + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Tick ISR Prototype +;------------------------------------------------------------------------------ +; EXTERN ?CL78K0R_V2_L00 + + PUBWEAK `??MD_INTTM05??INTVEC 68` + PUBLIC MD_INTTM05 + +MD_INTTM05 SYMBOL "MD_INTTM05" +`??MD_INTTM05??INTVEC 68` SYMBOL "??INTVEC 68", MD_INTTM05 + + + +;------------------------------------------------------------------------------ +; Yield to another task. Implemented as a software interrupt. The return +; address and PSW will have been saved to the stack automatically before +; this code runs. +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +; +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler to select the next task. + portRESTORE_CONTEXT ; Restore the context of the next task to run. + retb + + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +; +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; An interrupt stack frame is used so the task + ; is started using a RETI instruction. + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +; +;------------------------------------------------------------------------------ + +MD_INTTM05: + + portSAVE_CONTEXT ; Save the context of the current task. + call xTaskIncrementTick ; Call the timer tick function. +#if configUSE_PREEMPTION == 1 + call vTaskSwitchContext ; Call the scheduler to select the next task. +#endif + portRESTORE_CONTEXT ; Restore the context of the next task to run. + reti + + + +; REQUIRE ?CL78K0R_V2_L00 + COMMON INTVEC:CODE:ROOT(1) ; Set ISR location to the Interrupt vector table. + ORG 68 +`??MD_INTTM05??INTVEC 68`: + DW MD_INTTM05 + + COMMON INTVEC:CODE:ROOT(1) ; Set ISR location to the Interrupt vector table. + ORG 126 +`??vPortYield??INTVEC 126`: + DW vPortYield + + ; Set value for the usCriticalNesting. + RSEG NEAR_ID:CONST:SORT:NOROOT(1) +`?<Initializer for usCriticalNesting>`: + DW 10 + +;#endif + + END \ No newline at end of file
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h new file mode 100644 index 0000000..4267246 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h
@@ -0,0 +1,145 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if (configUSE_16_BIT_TICKS==1) + typedef unsigned int TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm ( "DI" ) +#define portENABLE_INTERRUPTS() __asm ( "EI" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortStart( void ); +#define portYIELD() __asm( "BRK" ) +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext() +#define portNOP() __asm( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + + +static __interrupt void P0_isr (void); + +/* --------------------------------------------------------------------------*/ +/* Option-bytes and security ID */ +/* --------------------------------------------------------------------------*/ +#define OPT_BYTES_SIZE 4 +#define SECU_ID_SIZE 10 +#define WATCHDOG_DISABLED 0x00 +#define LVI_ENABLED 0xFE +#define LVI_DISABLED 0xFF +#define RESERVED_FF 0xFF +#define OCD_DISABLED 0x04 +#define OCD_ENABLED 0x81 +#define OCD_ENABLED_ERASE 0x80 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c new file mode 100644 index 0000000..1171f8a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
@@ -0,0 +1,300 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* IAR includes. */ +#include <intrinsics.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt. A default that uses the PIT is provided in the official demo application. +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt. A default that uses the PIT is provided in the official demo application. +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user +mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable has to be stored as part of the task context and must be initialised to +a non zero value to ensure interrupts don't inadvertently become unmasked before +the scheduler starts. As it is stored as part of the task context it will +automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero +then a floating point context must be saved and restored for the task. */ +uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +uint32_t ulPortInterruptNesting = 0UL; + + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + The fist real value on the stack is the status register, which is set for + system mode, with interrupts enabled. A few NULLs are added first to ensure + GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + the floating point hardware must call vPortTaskUsesFPU() before executing + any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + vPortRestoreTaskContext(); + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + a non-privileged mode or the binary point register was not set to its lowest + possible value. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + portENABLE_INTERRUPTS(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ +uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); +} +/*-----------------------------------------------------------*/ + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h new file mode 100644 index 0000000..d079fc0 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -0,0 +1,113 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + EXTERN vTaskSwitchContext + EXTERN ulCriticalNesting + EXTERN pxCurrentTCB + EXTERN ulPortTaskHasFPUContext + EXTERN ulAsmAPIPriorityMask + +portSAVE_CONTEXT macro + + ; Save the LR and SPSR onto the system mode stack before switching to + ; system mode to save the remaining system mode registers + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + ; Push the critical nesting count + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + ; Does the task have a floating point context that needs saving? If + ; ulPortTaskHasFPUContext is 0 then no. + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + ; Save the floating point context, if any + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} +#if configFPU_D32 == 1 + VPUSHNE {D16-D31} +#endif ; configFPU_D32 + PUSHNE {R1} + + ; Save ulPortTaskHasFPUContext itself + PUSH {R3} + + ; Save the stack pointer in the TCB + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + endm + +; /**********************************************************************/ + +portRESTORE_CONTEXT macro + + ; Set the SP to point to the stack of the task being restored. + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + ; Is there a floating point context to restore? If the restored + ; ulPortTaskHasFPUContext is zero then no. + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + ; Restore the floating point context, if any + POPNE {R0} +#if configFPU_D32 == 1 + VPOPNE {D16-D31} +#endif ; configFPU_D32 + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + ; Restore the critical section nesting depth + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + ; Restore all system mode registers other than the SP (which is already + ; being used) + POP {R0-R12, R14} + + ; Return to the task code, loading CPSR on the way. CPSR has the interrupt + ; enable bit set appropriately for the task about to execute. + RFEIA sp! + + endm + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s new file mode 100644 index 0000000..674049c --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
@@ -0,0 +1,176 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + INCLUDE FreeRTOSConfig.h + INCLUDE portmacro.h + + EXTERN vTaskSwitchContext + EXTERN ulPortYieldRequired + EXTERN ulPortInterruptNesting + EXTERN vApplicationIRQHandler + + PUBLIC FreeRTOS_SWI_Handler + PUBLIC FreeRTOS_IRQ_Handler + PUBLIC vPortRestoreTaskContext + +SYS_MODE EQU 0x1f +SVC_MODE EQU 0x13 +IRQ_MODE EQU 0x12 + + SECTION .text:CODE:ROOT(2) + ARM + + INCLUDE portASM.h + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC handler is used to yield a task. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_SWI_Handler + + PRESERVE8 + + ; Save the context of the current task and select a new task to run. + portSAVE_CONTEXT + LDR R0, =vTaskSwitchContext + BLX R0 + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; vPortRestoreTaskContext is used to start the scheduler. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortRestoreTaskContext + + PRESERVE8 + + ; Switch to system mode + CPS #SYS_MODE + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; IRQ interrupt handler used when individual priorities cannot be masked +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_IRQ_Handler + + PRESERVE8 + + ; Return to the interrupted instruction. + SUB lr, lr, #4 + + ; Push the return address and SPSR + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + ; Change to supervisor mode to allow reentry. + CPS #SVC_MODE + + ; Push used registers. + PUSH {r0-r4, r12} + + ; Increment nesting count. r3 holds the address of ulPortInterruptNesting + ; for future use. r1 holds the original ulPortInterruptNesting value for + ; future use. + LDR r3, =ulPortInterruptNesting + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + ; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + ; future use. + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + PUSH {r0-r4, lr} + + ; Call the port part specific handler. + LDR r0, =vApplicationIRQHandler + BLX r0 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + + ; Write to the EOI register. + LDR r4, =configEOI_ADDRESS + STR r0, [r4] + + ; Restore the old nesting count + STR r1, [r3] + + ; A context switch is never performed if the nesting count is not 0. + CMP r1, #0 + BNE exit_without_switch + + ; Did the interrupt request a context switch? r1 holds the address of + ; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + ; use. + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch + ; No context switch. Restore used registers, LR_irq and SPSR before + ; returning. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit + ; A context switch is to be performed. Clear the context switch pending + ; flag. + MOV r0, #0 + STR r0, [r1] + + ; Restore used registers, LR-irq and SPSR before saving the context + ; to the task stack. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + ; Call the function that selects the new task to execute. + ; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + ; instructions, or 8 byte aligned stack allocated data. LR does not need + ; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. + LDR r0, =vTaskSwitchContext + BLX r0 + + ; Restore the context of, and branch to, the task selected to execute next. + portRESTORE_CONTEXT + + END + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h new file mode 100644 index 0000000..f5ae853 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
@@ -0,0 +1,162 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* IAR includes. */ +#ifdef __ICCARM__ + + #include <intrinsics.h> + + #ifdef __cplusplus + extern "C" { + #endif + + /*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + + /* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + + /*-----------------------------------------------------------*/ + + /* Hardware specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + + /*-----------------------------------------------------------*/ + + /* Task utilities. */ + + /* Called at the end of an ISR that can cause a context switch. */ + #define portEND_SWITCHING_ISR( xSwitchRequired )\ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + #define portYIELD() __asm volatile ( "SWI 0" ); __ISB() + + + /*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + extern uint32_t ulPortSetInterruptMask( void ); + extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + + #define portENTER_CRITICAL() vPortEnterCritical(); + #define portEXIT_CRITICAL() vPortExitCritical(); + #define portDISABLE_INTERRUPTS() __disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */ + #define portENABLE_INTERRUPTS() __enable_irq() + #define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */ + #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __set_interrupt_state(x) + + /*-----------------------------------------------------------*/ + + /* Task function macros as described on the FreeRTOS.org WEB site. These are + not required for this port but included in case common demo code that uses these + macros is used. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + + /* Prototype of the FreeRTOS tick handler. This must be installed as the + handler for whichever peripheral is used to generate the RTOS tick. */ + void FreeRTOS_Tick_Handler( void ); + + /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + before any floating point instructions are executed. */ + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + + /* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + #define portNOP() __asm volatile( "NOP" ) + + + #ifdef __cplusplus + } /* extern C */ + #endif + + /* Suppress warnings that are generated by the IAR tools, but cannot be + fixed in the source code because to do so would cause other compilers to + generate warnings. */ + #pragma diag_suppress=Pe191 + #pragma diag_suppress=Pa082 + +#endif /* __ICCARM__ */ + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c new file mode 100644 index 0000000..69d8723 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c
@@ -0,0 +1,439 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include <stdlib.h> + +/* IAR includes. */ +#include <intrinsics.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS + #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET + #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configUNIQUE_INTERRUPT_PRIORITIES + #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif /* configSETUP_TICK_INTERRUPT */ + +#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 + #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 +#endif + +#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/* In case security extensions are implemented. */ +#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #define configCLEAR_TICK_INTERRUPT() +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* In all GICs 255 can be written to the priority mask register to unmask all +(but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary +point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user +mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* Macro to unmask all interrupt priorities. */ +#define portCLEAR_INTERRUPT_MASK() \ +{ \ + __disable_irq(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm( "DSB \n" \ + "ISB \n" ); \ + __enable_irq(); \ +} + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable has to be stored as part of the task context and must be initialised to +a non zero value to ensure interrupts don't inadvertently become unmasked before +the scheduler starts. As it is stored as part of the task context it will +automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero +then a floating point context must be saved and restored for the task. */ +uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +uint32_t ulPortInterruptNesting = 0UL; + + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + The fist real value on the stack is the status register, which is set for + system mode, with interrupts enabled. A few NULLs are added first to ensure + GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + the floating point hardware must call vPortTaskUsesFPU() before executing + any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Only continue if the binary point value is set to its lowest possible + setting. See the comments in vPortValidateInterruptPriority() below for + more information. */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + + if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) + { + /* Start the timer that generates the tick ISR. */ + configSETUP_TICK_INTERRUPT(); + + __enable_irq(); + vPortRestoreTaskContext(); + } + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + a non-privileged mode or the binary point register was not set to its lowest + possible value. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ + ulPortSetInterruptMask(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + portCLEAR_INTERRUPT_MASK(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ + /* Set interrupt mask before altering scheduler structures. The tick + handler runs at the lowest priority, so interrupts cannot already be masked, + so there is no need to save and restore the current mask value. */ + __disable_irq(); + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm( "DSB \n" + "ISB \n" ); + __enable_irq(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + /* Ensure all interrupt priorities are active again. */ + portCLEAR_INTERRUPT_MASK(); + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ +uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); +} +/*-----------------------------------------------------------*/ + +void vPortClearInterruptMask( uint32_t ulNewMaskValue ) +{ + if( ulNewMaskValue == pdFALSE ) + { + portCLEAR_INTERRUPT_MASK(); + } +} +/*-----------------------------------------------------------*/ + +uint32_t ulPortSetInterruptMask( void ) +{ +uint32_t ulReturn; + + __disable_irq(); + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) + { + /* Interrupts were already masked. */ + ulReturn = pdTRUE; + } + else + { + ulReturn = pdFALSE; + portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); + __asm( "DSB \n" + "ISB \n" ); + } + __enable_irq(); + + return ulReturn; +} +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + /* The following assertion will fail if a service routine (ISR) for + an interrupt that has been assigned a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + function. ISR safe FreeRTOS API functions must *only* be called + from interrupts that have been assigned a priority at or below + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Numerically low interrupt priority numbers represent logically high + interrupt priorities, therefore the priority of the interrupt must + be set to a value equal to or numerically *higher* than + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + FreeRTOS maintains separate thread and ISR API functions to ensure + interrupt entry is as fast and simple as possible. + + The following links provide detailed information: + http://www.freertos.org/RTOS-Cortex-M3-M4.html + http://www.freertos.org/FAQHelp.html */ + configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); + + /* Priority grouping: The interrupt controller (GIC) allows the bits + that define each interrupt's priority to be split between bits that + define the interrupt's pre-emption priority bits and bits that define + the interrupt's sub-priority. For simplicity all bits must be defined + to be pre-emption priority bits. The following assertion will fail if + this is not the case (if some bits represent a sub-priority). + + The priority grouping is configured by the GIC's binary point register + (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest + possible value (which may be above 0). */ + configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); + } + +#endif /* configASSERT_DEFINED */ + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h new file mode 100644 index 0000000..7c15091 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h
@@ -0,0 +1,115 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + EXTERN vTaskSwitchContext + EXTERN ulCriticalNesting + EXTERN pxCurrentTCB + EXTERN ulPortTaskHasFPUContext + EXTERN ulAsmAPIPriorityMask + +portSAVE_CONTEXT macro + + ; Save the LR and SPSR onto the system mode stack before switching to + ; system mode to save the remaining system mode registers + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + ; Push the critical nesting count + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + ; Does the task have a floating point context that needs saving? If + ; ulPortTaskHasFPUContext is 0 then no. + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + ; Save the floating point context, if any + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} + VPUSHNE {D16-D31} + PUSHNE {R1} + + ; Save ulPortTaskHasFPUContext itself + PUSH {R3} + + ; Save the stack pointer in the TCB + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + endm + +; /**********************************************************************/ + +portRESTORE_CONTEXT macro + + ; Set the SP to point to the stack of the task being restored. + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + ; Is there a floating point context to restore? If the restored + ; ulPortTaskHasFPUContext is zero then no. + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + ; Restore the floating point context, if any + POPNE {R0} + VPOPNE {D16-D31} + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + ; Restore the critical section nesting depth + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + ; Ensure the priority mask is correct for the critical nesting depth + LDR R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS + CMP R1, #0 + MOVEQ R4, #255 + LDRNE R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) + STR R4, [r2] + + ; Restore all system mode registers other than the SP (which is already + ; being used) + POP {R0-R12, R14} + + ; Return to the task code, loading CPSR on the way. + RFEIA sp! + + endm + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s new file mode 100644 index 0000000..d50e561 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
@@ -0,0 +1,177 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + INCLUDE FreeRTOSConfig.h + INCLUDE portmacro.h + + EXTERN vApplicationIRQHandler + EXTERN vTaskSwitchContext + EXTERN ulPortYieldRequired + EXTERN ulPortInterruptNesting + + PUBLIC FreeRTOS_SWI_Handler + PUBLIC FreeRTOS_IRQ_Handler + PUBLIC vPortRestoreTaskContext + +SYS_MODE EQU 0x1f +SVC_MODE EQU 0x13 +IRQ_MODE EQU 0x12 + + + SECTION .text:CODE:ROOT(2) + ARM + + INCLUDE portASM.h + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SVC handler is used to yield a task. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_SWI_Handler + + PRESERVE8 + + ; Save the context of the current task and select a new task to run. + portSAVE_CONTEXT + LDR R0, =vTaskSwitchContext + BLX R0 + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; vPortRestoreTaskContext is used to start the scheduler. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortRestoreTaskContext + ; Switch to system mode + CPS #SYS_MODE + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; PL390 GIC interrupt handler +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +FreeRTOS_IRQ_Handler + + ; Return to the interrupted instruction. + SUB lr, lr, #4 + + ; Push the return address and SPSR + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + ; Change to supervisor mode to allow reentry. + CPS #SVC_MODE + + ; Push used registers. + PUSH {r0-r4, r12} + + ; Increment nesting count. r3 holds the address of ulPortInterruptNesting + ; for future use. r1 holds the original ulPortInterruptNesting value for + ; future use. + LDR r3, =ulPortInterruptNesting + LDR r1, [r3] + ADD r4, r1, #1 + STR r4, [r3] + + ; Read value from the interrupt acknowledge register, which is stored in r0 + ; for future parameter and interrupt clearing use. + LDR r2, =portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS + LDR r0, [r2] + + ; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + ; future use. _RB_ Is this ever necessary if start of stack is 8-byte aligned? + MOV r2, sp + AND r2, r2, #4 + SUB sp, sp, r2 + + ; Call the interrupt handler. r4 is pushed to maintain alignment. + PUSH {r0-r4, lr} + LDR r1, =vApplicationIRQHandler + BLX r1 + POP {r0-r4, lr} + ADD sp, sp, r2 + + CPSID i + + ; Write the value read from ICCIAR to ICCEOIR + LDR r4, =portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS + STR r0, [r4] + + ; Restore the old nesting count + STR r1, [r3] + + ; A context switch is never performed if the nesting count is not 0 + CMP r1, #0 + BNE exit_without_switch + + ; Did the interrupt request a context switch? r1 holds the address of + ; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + ; use. + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch + ; No context switch. Restore used registers, LR_irq and SPSR before + ; returning. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit + ; A context switch is to be performed. Clear the context switch pending + ; flag. + MOV r0, #0 + STR r0, [r1] + + ; Restore used registers, LR-irq and SPSR before saving the context + ; to the task stack. + POP {r0-r4, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + ; Call the function that selects the new task to execute. + ; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + ; instructions, or 8 byte aligned stack allocated data. LR does not need + ; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. + LDR r0, =vTaskSwitchContext + BLX r0 + + ; Restore the context of, and branch to, the task selected to execute next. + portRESTORE_CONTEXT + + + END + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h new file mode 100644 index 0000000..4f6c303 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h
@@ -0,0 +1,209 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/* IAR includes. */ +#ifdef __ICCARM__ + + #include <intrinsics.h> + + #ifdef __cplusplus + extern "C" { + #endif + + /*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + + /* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long + + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; + + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 + + /*-----------------------------------------------------------*/ + + /* Hardware specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 + + /*-----------------------------------------------------------*/ + + /* Task utilities. */ + + /* Called at the end of an ISR that can cause a context switch. */ + #define portEND_SWITCHING_ISR( xSwitchRequired )\ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ + } + + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + #define portYIELD() __asm( "SWI 0" ); + + + /*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + + extern void vPortEnterCritical( void ); + extern void vPortExitCritical( void ); + extern uint32_t ulPortSetInterruptMask( void ); + extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); + + /* These macros do not globally disable/enable interrupts. They do mask off + interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ + #define portENTER_CRITICAL() vPortEnterCritical(); + #define portEXIT_CRITICAL() vPortExitCritical(); + #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() + #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) + + /*-----------------------------------------------------------*/ + + /* Task function macros as described on the FreeRTOS.org WEB site. These are + not required for this port but included in case common demo code that uses these + macros is used. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + + /* Prototype of the FreeRTOS tick handler. This must be installed as the + handler for whichever peripheral is used to generate the RTOS tick. */ + void FreeRTOS_Tick_Handler( void ); + + /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + before any floating point instructions are executed. */ + void vPortTaskUsesFPU( void ); + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + + #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) + #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + + /* Architecture specific optimisations. */ + #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #endif + + #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) + + #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + #ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #endif /* configASSERT */ + + #define portNOP() __asm volatile( "NOP" ) + + + #ifdef __cplusplus + } /* extern C */ + #endif + + /* Suppress warnings that are generated by the IAR tools, but cannot be + fixed in the source code because to do so would cause other compilers to + generate warnings. */ + #pragma diag_suppress=Pe191 + #pragma diag_suppress=Pa082 + +#endif /* __ICCARM__ */ + + +/* The number of bits to shift for an interrupt priority is dependent on the +number of bits implemented by the interrupt controller. */ +#if configUNIQUE_INTERRUPT_PRIORITIES == 16 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 32 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 64 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 128 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 +#elif configUNIQUE_INTERRUPT_PRIORITIES == 256 + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else + #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware +#endif + +/* Interrupt controller access addresses. */ +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) + +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c new file mode 100644 index 0000000..41b7d43 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c
@@ -0,0 +1,218 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM CM0 port. + *----------------------------------------------------------*/ + +/* IAR includes. */ +#include "intrinsics.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to manipulate the NVIC. */ +#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 ) +#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 ) +#define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 ) +#define portNVIC_SYSTICK_CLK 0x00000004 +#define portNVIC_SYSTICK_INT 0x00000002 +#define portNVIC_SYSTICK_ENABLE 0x00000001 +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is +defined. The value 255 should also ensure backward compatibility. +FreeRTOS.org versions prior to V4.3.0 did not include this definition. */ +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 0 +#endif + +/* Each task maintains its own interrupt status in the critical nesting +variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11..R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* Make PendSV and SysTick the lowest priority interrupts. */ + *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; + *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortYield( void ) +{ + /* Set a PendSV to request a context switch. */ + *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; + + /* Barriers are normally not required but do ensure the code is completely + within the specified behaviour for the architecture. */ + __DSB(); + __ISB(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + __DSB(); + __ISB(); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ +uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +static void prvSetupTimerInterrupt( void ) +{ + /* Stop and reset the SysTick. */ + *(portNVIC_SYSTICK_CTRL) = 0UL; + *(portNVIC_SYSTICK_CURRENT_VALUE) = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} +/*-----------------------------------------------------------*/ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s new file mode 100644 index 0000000..76f48c4 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s
@@ -0,0 +1,131 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include <FreeRTOSConfig.h> + + RSEG CODE:CODE(2) + thumb + + EXTERN vPortYieldFromISR + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC vSetMSP + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC ulSetInterruptMaskFromISR + PUBLIC vClearInterruptMaskFromISR + +/*-----------------------------------------------------------*/ + +vSetMSP + msr msp, r0 + bx lr + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + + ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [r3] + + subs r0, r0, #32 /* Make space for the remaining low registers. */ + str r0, [r2] /* Save the new top of stack. */ + stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */ + mov r4, r8 /* Store the high registers. */ + mov r5, r9 + mov r6, r10 + mov r7, r11 + stmia r0!, {r4-r7} + + push {r3, r14} + cpsid i + bl vTaskSwitchContext + cpsie i + pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */ + + ldr r1, [r2] + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ + adds r0, r0, #16 /* Move to the high registers. */ + ldmia r0!, {r4-r7} /* Pop the high registers. */ + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + + msr psp, r0 /* Remember the new top of stack for the task. */ + + subs r0, r0, #32 /* Go back for the low registers that are not automatically restored. */ + ldmia r0!, {r4-r7} /* Pop low registers. */ + + bx r3 + +/*-----------------------------------------------------------*/ + +vPortSVCHandler; + /* This function is no longer used, but retained for backward + compatibility. */ + bx lr + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector + table offset register that can be used to locate the initial stack value. + Not all M0 parts have the application vector table at address 0. */ + + ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */ + ldr r1, [r3] + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + movs r0, #2 /* Switch to the psp stack. */ + msr CONTROL, r0 + isb + pop {r0-r5} /* Pop the registers that are saved automatically. */ + mov lr, r5 /* lr is now in r5. */ + pop {r3} /* The return address is now in r3. */ + pop {r2} /* Pop and discard the XPSR. */ + cpsie i /* The first task has its context and interrupts can be enabled. */ + bx r3 /* Jump to the user defined task code. */ + +/*-----------------------------------------------------------*/ + +ulSetInterruptMaskFromISR + mrs r0, PRIMASK + cpsid i + bx lr + +/*-----------------------------------------------------------*/ + +vClearInterruptMaskFromISR + msr PRIMASK, r0 + bx lr + + END
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h new file mode 100644 index 0000000..11f362c --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h
@@ -0,0 +1,122 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +extern void vPortYield( void ); +#define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 ) +#define portNVIC_PENDSVSET 0x10000000 +#define portYIELD() vPortYield() +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + + +/* Critical section management. */ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulSetInterruptMaskFromISR( void ); +extern void vClearInterruptMaskFromISR( uint32_t ulMask ); + +#define portDISABLE_INTERRUPTS() __asm volatile( "cpsid i" ) +#define portENABLE_INTERRUPTS() __asm volatile( "cpsie i" ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define portNOP() + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in +the source code because to do so would cause other compilers to generate +warnings. */ +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c new file mode 100644 index 0000000..b0394fb --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c
@@ -0,0 +1,899 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 ) +#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 ) +#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) +#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 ) +#define portNVIC_SYSTICK_CLK ( 0x00000004 ) +#define portNVIC_SYSTICK_INT ( 0x00000002 ) +#define portNVIC_SYSTICK_ENABLE ( 0x00000001 ) +#define portNVIC_PENDSVSET ( 0x10000000 ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if( configRUN_FREERTOS_SECURE_ONLY == 1 ) + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if( configENABLE_MPU == 1 ) + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if( configENABLE_FPU == 1 ) + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if( configENABLE_TRUSTZONE == 1 ) + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Stop and reset the SysTick. */ + *( portNVIC_SYSTICK_CTRL ) = 0UL; + *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ +volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile( "dsb" ::: "memory" ); + __asm volatile( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile( "dsb" ::: "memory" ); + __asm volatile( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ +uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ +#if( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ +#endif /* configENABLE_MPU */ + +uint32_t ulPC; + +#if( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0; + #if( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ +#endif /* configENABLE_TRUSTZONE */ +uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + { + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != NULL ); + SecureContext_LoadContext( xSecureContext ); + } + break; + + case portSVC_FREE_SECURE_CONTEXT: + { + /* R0 contains the secure context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 ); + } + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + { + #if( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + } + break; + + #if( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + { + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ulPC >= ( uint32_t ) __syscalls_flash_start__ && + ulPC <= ( uint32_t ) __syscalls_flash_end__ ) + { + vRaisePrivilege(); + } + } + break; + #endif /* configENABLE_MPU */ + + default: + { + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } + } +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI; + *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI; + + #if( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr1 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h new file mode 100644 index 0000000..6314e96 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
@@ -0,0 +1,113 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__ (( naked )); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__ (( naked )); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked )); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s new file mode 100644 index 0000000..36872fa --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
@@ -0,0 +1,377 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMaskFromISR + PUBLIC vClearInterruptMaskFromISR + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + beq running_privileged /* If the result of previous AND operation was 0, branch. */ + movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + bx lr /* Return. */ + running_privileged: + movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + orrs r0, r1 /* r0 = r0 | r1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + movs r5, #4 /* r5 = 4. */ + str r5, [r2] /* Program RNR = 4. */ + ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */ + movs r5, #5 /* r5 = 5. */ + str r5, [r2] /* Program RNR = 5. */ + ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */ + movs r5, #6 /* r5 = 6. */ + str r5, [r2] /* Program RNR = 6. */ + ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */ + movs r5, #7 /* r5 = 7. */ + str r5, [r2] /* Program RNR = 7. */ + ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + ldr r5, =xSecureContext + str r1, [r5] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + msr control, r3 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r4 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r3 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + movs r1, #1 /* r1 = 1. */ + bics r0, r1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMaskFromISR: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMaskFromISR: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ + +PendSV_Handler: + mrs r1, psp /* Read PSP in r1. */ + ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + + cbz r0, save_ns_context /* No secure context to save. */ + push {r0-r2, r14} + bl SecureContext_SaveContext + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* LR = r3. */ + lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r2, [r3] /* Read pxCurrentTCB. */ +#if ( configENABLE_MPU == 1 ) + subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + str r1, [r2] /* Save the new top of stack in TCB. */ + mrs r2, psplim /* r2 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ +#else /* configENABLE_MPU */ + subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + str r1, [r2] /* Save the new top of stack in TCB. */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ +#endif /* configENABLE_MPU */ + b select_next_task + + save_ns_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r2, [r3] /* Read pxCurrentTCB. */ + #if ( configENABLE_MPU == 1 ) + subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + str r1, [r2] /* Save the new top of stack in TCB. */ + adds r1, r1, #16 /* r1 = r1 + 16. */ + stmia r1!, {r4-r7} /* Store the low registers that are not saved automatically. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r1!, {r4-r7} /* Store the high registers that are not saved automatically. */ + mrs r2, psplim /* r2 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + subs r1, r1, #48 /* r1 = r1 - 48. */ + stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + str r1, [r2] /* Save the new top of stack in TCB. */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r1!, {r0, r2-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r1!, {r4-r7} /* Store the high registers that are not saved automatically. */ + #endif /* configENABLE_MPU */ + + select_next_task: + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */ + + #if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + movs r5, #4 /* r5 = 4. */ + str r5, [r2] /* Program RNR = 4. */ + ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */ + movs r5, #5 /* r5 = 5. */ + str r5, [r2] /* Program RNR = 5. */ + ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */ + movs r5, #6 /* r5 = 6. */ + str r5, [r2] /* Program RNR = 6. */ + ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */ + movs r5, #7 /* r5 = 7. */ + str r5, [r2] /* Program RNR = 7. */ + ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */ + stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + movs r5, #1 /* r5 = 1. */ + orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + + #if ( configENABLE_MPU == 1 ) + ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + msr control, r3 /* Restore the CONTROL register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r2] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + push {r1,r4} + bl SecureContext_LoadContext /* Restore the secure context. */ + pop {r1,r4} + mov lr, r4 /* LR = r4. */ + lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r1 /* Remember the new top of stack for the task. */ + bx lr + #else /* configENABLE_MPU */ + ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + mov lr, r3 /* LR = r3. */ + ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r2] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + push {r1,r3} + bl SecureContext_LoadContext /* Restore the secure context. */ + pop {r1,r3} + mov lr, r3 /* LR = r3. */ + lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r1 /* Remember the new top of stack for the task. */ + bx lr + #endif /* configENABLE_MPU */ + + restore_ns_context: + adds r1, r1, #16 /* Move to the high registers. */ + ldmia r1!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r1 /* Remember the new top of stack for the task. */ + subs r1, r1, #32 /* Go back to the low registers. */ + ldmia r1!, {r4-r7} /* Restore the low registers that are not automatically restored. */ + bx lr +/*-----------------------------------------------------------*/ + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stacking_used_msp + mrs r0, psp + b vPortSVCHandler_C + stacking_used_msp: + mrs r0, msp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + ldr r1, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */ + cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */ + beq free_secure_context + bx lr /* There is no secure context (xSecureContext is NULL). */ + free_secure_context: + svc 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h new file mode 100644 index 0000000..969c563 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -0,0 +1,299 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__(( always_inline )) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( 7UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ +typedef struct MPURegionSettings +{ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ +} MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ +typedef struct MPU_SETTINGS +{ + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ +} xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 0 +#define portSVC_FREE_SECURE_CONTEXT 1 +#define portSVC_START_SCHEDULER 2 +#define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#define portYIELD() vPortYield() +#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x ) +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#if( configENABLE_TRUSTZONE == 1 ) + /** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + + /** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#else + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) + #define portCLEAN_UP_TCB( pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + /** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + + /** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + + /** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c new file mode 100644 index 0000000..8a42230 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c
@@ -0,0 +1,204 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first addess of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t *pucStackStart; /**< First location of the stack memory. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + #if( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged.. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize ) +#endif /* configENABLE_MPU */ +{ + uint8_t *pucStackMemory = NULL; + uint32_t ulIPSR; + SecureContextHandle_t xSecureContextHandle = NULL; + #if( configENABLE_MPU == 1 ) + uint32_t *pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Allocate the context structure. */ + xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) ); + + if( xSecureContextHandle != NULL ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte because the hardware decrements the stack + * pointer before writing i.e. if stack pointer is 0x2, a push + * operation will decrement the stack pointer to 0x1 and then + * write at 0x1. */ + xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContextHandle->pucStackLimit = pucStackMemory; + + #if( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart; + pulCurrentStackPointer--; + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart; + + } + #endif /* configENABLE_MPU */ + } + else + { + /* Free the context to avoid memory leak and make sure to return + * NULL to indicate failure. */ + vPortFree( xSecureContextHandle ); + xSecureContextHandle = NULL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Ensure that valid parameters are passed. */ + secureportASSERT( xSecureContextHandle != NULL ); + + /* Free the stack space. */ + vPortFree( xSecureContextHandle->pucStackLimit ); + + /* Free the context itself. */ + vPortFree( xSecureContextHandle ); + } +} +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h new file mode 100644 index 0000000..a98a7d0 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h
@@ -0,0 +1,111 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include <stdint.h> + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no task's context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Opaque handle. + */ +struct SecureContext; +typedef struct SecureContext* SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle ); + +#endif /* __SECURE_CONTEXT_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c new file mode 100644 index 0000000..6df620d --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c
@@ -0,0 +1,48 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/* Functions implemented in assembler file. */ +extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle ); +extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle ); + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle ) +{ + SecureContext_LoadContextAsm( xSecureContextHandle ); +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle ) +{ + SecureContext_SaveContextAsm( xSecureContextHandle ); +} +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s new file mode 100644 index 0000000..947e70a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
@@ -0,0 +1,76 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* xSecureContextHandle value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */ +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* xSecureContextHandle value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */ + str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */ + stmia r1!, {r2} /* Store CONTROL value on the stack. */ +#else /* configENABLE_MPU */ + str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */ +#endif /* configENABLE_MPU */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c new file mode 100644 index 0000000..c4f613f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -0,0 +1,450 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include <stdint.h> + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if( configAPPLICATION_ALLOCATED_HEAP == 1 ) + /* The application writer has already defined the array used for the RTOS + * heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart, *pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/** + * @brief Gets set to the top bit of an size_t type. + * + * When this bit in the xBlockSize member of an BlockLink_t structure is set + * then the block belongs to the application. When the bit is free the block is + * still part of the free heap space. + */ +static size_t xBlockAllocatedBit = 0; +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ +BlockLink_t *pxFirstFreeBlock; +uint8_t *pucAlignedHeap; +size_t uxAddress; +size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) +{ +BlockLink_t *pxIterator; +uint8_t *puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ +BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; +void *pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number of + * bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); + secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + + #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ +uint8_t *puc = ( uint8_t * ) pv; +BlockLink_t *pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h new file mode 100644 index 0000000..aae5cfc --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
@@ -0,0 +1,51 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include <stdlib.h> + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void *pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void *pv ); + +#endif /* __SECURE_HEAP_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c new file mode 100644 index 0000000..60ef1e8 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c
@@ -0,0 +1,105 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include <stdint.h> + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h new file mode 100644 index 0000000..3954e13 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h
@@ -0,0 +1,53 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h new file mode 100644 index 0000000..f392537 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
@@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry)) __attribute__((used)) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ;; ); \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c new file mode 100644 index 0000000..b0394fb --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 ) +#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 ) +#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) +#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 ) +#define portNVIC_SYSTICK_CLK ( 0x00000004 ) +#define portNVIC_SYSTICK_INT ( 0x00000002 ) +#define portNVIC_SYSTICK_ENABLE ( 0x00000001 ) +#define portNVIC_PENDSVSET ( 0x10000000 ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if( configRUN_FREERTOS_SECURE_ONLY == 1 ) + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if( configENABLE_MPU == 1 ) + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if( configENABLE_FPU == 1 ) + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if( configENABLE_TRUSTZONE == 1 ) + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Stop and reset the SysTick. */ + *( portNVIC_SYSTICK_CTRL ) = 0UL; + *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ +volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile( "dsb" ::: "memory" ); + __asm volatile( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile( "dsb" ::: "memory" ); + __asm volatile( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ +uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ +#if( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ +#endif /* configENABLE_MPU */ + +uint32_t ulPC; + +#if( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0; + #if( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ +#endif /* configENABLE_TRUSTZONE */ +uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + { + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != NULL ); + SecureContext_LoadContext( xSecureContext ); + } + break; + + case portSVC_FREE_SECURE_CONTEXT: + { + /* R0 contains the secure context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 ); + } + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + { + #if( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + } + break; + + #if( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + { + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ulPC >= ( uint32_t ) __syscalls_flash_start__ && + ulPC <= ( uint32_t ) __syscalls_flash_end__ ) + { + vRaisePrivilege(); + } + } + break; + #endif /* configENABLE_MPU */ + + default: + { + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } + } +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI; + *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI; + + #if( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr1 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h new file mode 100644 index 0000000..6314e96 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__ (( naked )); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__ (( naked )); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked )); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s new file mode 100644 index 0000000..b84c356 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
@@ -0,0 +1,303 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMaskFromISR + PUBLIC vClearInterruptMaskFromISR + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + +#if ( configENABLE_FPU == 1 ) + #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0. +#endif +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */ + beq running_privileged /* If the result of previous AND operation was 0, branch. */ + movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + bx lr /* Return. */ + running_privileged: + movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ + +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + movs r1, #1 /* r1 = 1. */ + orrs r0, r1 /* r0 = r0 | r1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */ + str r3, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */ + movs r4, #5 /* r4 = 5. */ + str r4, [r2] /* Program RNR = 5. */ + ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */ + movs r4, #6 /* r4 = 6. */ + str r4, [r2] /* Program RNR = 6. */ + ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */ + movs r4, #7 /* r4 = 7. */ + str r4, [r2] /* Program RNR = 7. */ + ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */ + str r3, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + msr control, r2 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r3 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r2 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + movs r1, #1 /* r1 = 1. */ + bics r0, r1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ + nop +/*-----------------------------------------------------------*/ + +ulSetInterruptMaskFromISR: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMaskFromISR: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ +#if ( configENABLE_MPU == 1 ) + subs r0, r0, #44 /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r2, control /* r2 = CONTROL. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r0!, {r1-r7} /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */ +#else /* configENABLE_MPU */ + subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ + mov r4, r8 /* r4 = r8. */ + mov r5, r9 /* r5 = r9. */ + mov r6, r10 /* r6 = r10. */ + mov r7, r11 /* r7 = r11. */ + stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */ +#endif /* configENABLE_MPU */ + + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */ + str r3, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */ + movs r4, #5 /* r4 = 5. */ + str r4, [r2] /* Program RNR = 5. */ + ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */ + movs r4, #6 /* r4 = 6. */ + str r4, [r2] /* Program RNR = 6. */ + ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */ + movs r4, #7 /* r4 = 7. */ + str r4, [r2] /* Program RNR = 7. */ + ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */ + ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */ + stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r3, [r2] /* Read the value of MPU_CTRL. */ + movs r4, #1 /* r4 = 1. */ + orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */ + str r3, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + adds r0, r0, #28 /* Move to the high registers. */ + ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + subs r0, r0, #44 /* Move to the starting of the saved context. */ + ldmia r0!, {r1-r7} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */ + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r2 /* Restore the CONTROL register value for the task. */ + bx r3 +#else /* configENABLE_MPU */ + adds r0, r0, #24 /* Move to the high registers. */ + ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */ + mov r8, r4 /* r8 = r4. */ + mov r9, r5 /* r9 = r5. */ + mov r10, r6 /* r10 = r6. */ + mov r11, r7 /* r11 = r7. */ + msr psp, r0 /* Remember the new top of stack for the task. */ + subs r0, r0, #40 /* Move to the starting of the saved context. */ + ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + bx r3 +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +SVC_Handler: + movs r0, #4 + mov r1, lr + tst r0, r1 + beq stacking_used_msp + mrs r0, psp + b vPortSVCHandler_C + stacking_used_msp: + mrs r0, msp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + + END
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h new file mode 100644 index 0000000..969c563 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -0,0 +1,299 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M23" +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__(( always_inline )) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( 7UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ +typedef struct MPURegionSettings +{ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ +} MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ +typedef struct MPU_SETTINGS +{ + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ +} xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 0 +#define portSVC_FREE_SECURE_CONTEXT 1 +#define portSVC_START_SCHEDULER 2 +#define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#define portYIELD() vPortYield() +#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x ) +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#if( configENABLE_TRUSTZONE == 1 ) + /** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + + /** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#else + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) + #define portCLEAN_UP_TCB( pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + /** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + + /** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + + /** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c new file mode 100644 index 0000000..33303c3 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c
@@ -0,0 +1,619 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM CM3 port. + *----------------------------------------------------------*/ + +/* IAR includes. */ +#include <intrinsics.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + /* The way the SysTick is clocked is not modified in case it is not the same + as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have +occurred while the SysTick counter is stopped during tickless idle +calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should +have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is +defined. The value 255 should also ensure backward compatibility. +FreeRTOS.org versions prior to V4.3.0 did not include this definition. */ +#ifndef configKERNEL_INTERRUPT_PRIORITY + #define configKERNEL_INTERRUPT_PRIORITY 255 +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting +variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + #if( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + functions can be called. ISR safe functions are those that end in + "FromISR". FreeRTOS maintains separate thread and ISR API functions to + ensure interrupt entry is as fast and simple as possible. + + Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + priority bits matches the number of priority bits actually queried + from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + priority bits matches the number of priority bits actually queried + from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* conifgASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; + portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + executes all interrupts must be unmasked. There is therefore no need to + save and then restore the interrupt mask value as its value is already + known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + is accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + tick periods. -1 is used because this code will execute part way + through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + method as that will mask interrupts that should exit sleep mode. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_interrupt() + call above. */ + __enable_interrupt(); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + set its parameter to 0 to indicate that its implementation contains + its own wait for interrupt or wait for event instruction, and so wfi + should not be executed again. However, the original expected idle + time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + if( xModifiableIdleTime > 0 ) + { + __DSB(); + __WFI(); + __ISB(); + } + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + out of sleep mode to execute immediately. see comments above + __disable_interrupt() call above. */ + __enable_interrupt(); + __DSB(); + __ISB(); + + /* Disable interrupts again because the clock is about to be stopped + and interrupts that execute while the clock is stopped will increase + any slippage between the time maintained by the RTOS and calendar + time. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* Disable the SysTick clock without reading the + portNVIC_SYSTICK_CTRL_REG register to ensure the + portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + the time the SysTick is stopped for is accounted for as best it can + be, but using the tickless mode will inevitably result in some tiny + drift of the time maintained by the kernel with respect to calendar + time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + been set back to the current reload value (the reload back being + correct for the entire expected idle time) or if the SysTick is yet + to count to zero (in which case an interrupt other than the SysTick + must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + reloaded with ulReloadValue. Reset the + portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + underflowed because the post sleep hook did something + that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + function exits, the tick value maintained by the tick is stepped + forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + Work out how long the sleep lasted rounded to complete tick + periods (not the ulReload value which accounted for part + ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrpts enabled. */ + __enable_interrupt(); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + an interrupt that has been assigned a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + function. ISR safe FreeRTOS API functions must *only* be called + from interrupts that have been assigned a priority at or below + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Numerically low interrupt priority numbers represent logically high + interrupt priorities, therefore the priority of the interrupt must + be set to a value equal to or numerically *higher* than + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Interrupts that use the FreeRTOS API must not be left at their + default priority of zero as that is the highest possible priority, + which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + and therefore also guaranteed to be invalid. + + FreeRTOS maintains separate thread and ISR API functions to ensure + interrupt entry is as fast and simple as possible. + + The following links provide detailed information: + http://www.freertos.org/RTOS-Cortex-M3-M4.html + http://www.freertos.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + that define each interrupt's priority to be split between bits that + define the interrupt's pre-emption priority bits and bits that define + the interrupt's sub-priority. For simplicity all bits must be defined + to be pre-emption priority bits. The following assertion will fail if + this is not the case (if some bits represent a sub-priority). + + If the application only uses CMSIS libraries for interrupt + configuration then the correct setting can be achieved on all Cortex-M + devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + scheduler. Note however that some vendor specific peripheral libraries + assume a non-zero priority group setting, in which cases using a value + of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ + + + + + + + + + + + + + + + + + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s new file mode 100644 index 0000000..f91e1a6 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
@@ -0,0 +1,103 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include <FreeRTOSConfig.h> + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + + + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + isb + ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ + ldr r2, [r3] + + stmdb r0!, {r4-r11} /* Save the remaining registers. */ + str r0, [r2] /* Save the new top of stack into the first member of the TCB. */ + + stmdb sp!, {r3, r14} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r3, r14} + + ldr r1, [r3] + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ + ldmia r0!, {r4-r11} /* Pop the registers. */ + msr psp, r0 + isb + bx r14 + + +/*-----------------------------------------------------------*/ + +vPortSVCHandler: + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [r3] + ldr r0, [r1] + /* Pop the core registers. */ + ldmia r0!, {r4-r11} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + orr r14, r14, #13 + bx r14 + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Call SVC to start the first task, ensuring interrupts are enabled. */ + cpsie i + cpsie f + dsb + isb + svc 0 + + END
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h new file mode 100644 index 0000000..e508089 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
@@ -0,0 +1,180 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ +#include <intrinsics.h> + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Compiler directives. */ +#define portWEAK_SYMBOL __attribute__( ( weak ) ) + +/*-----------------------------------------------------------*/ + + +/* Scheduler utilities. */ +#define portYIELD() \ +{ \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ +} + +#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD() +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() \ +{ \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ +} + +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not necessary for to use this port. They are defined so the common demo files +(which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in +the source code because to do so would cause other compilers to generate +warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c new file mode 100644 index 0000000..b0394fb --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c
@@ -0,0 +1,899 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 ) +#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 ) +#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) +#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 ) +#define portNVIC_SYSTICK_CLK ( 0x00000004 ) +#define portNVIC_SYSTICK_INT ( 0x00000002 ) +#define portNVIC_SYSTICK_ENABLE ( 0x00000001 ) +#define portNVIC_PENDSVSET ( 0x10000000 ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if( configRUN_FREERTOS_SECURE_ONLY == 1 ) + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if( configENABLE_MPU == 1 ) + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if( configENABLE_FPU == 1 ) + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if( configENABLE_TRUSTZONE == 1 ) + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Stop and reset the SysTick. */ + *( portNVIC_SYSTICK_CTRL ) = 0UL; + *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ +volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile( "dsb" ::: "memory" ); + __asm volatile( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile( "dsb" ::: "memory" ); + __asm volatile( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ +uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ +#if( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ +#endif /* configENABLE_MPU */ + +uint32_t ulPC; + +#if( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0; + #if( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ +#endif /* configENABLE_TRUSTZONE */ +uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + { + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != NULL ); + SecureContext_LoadContext( xSecureContext ); + } + break; + + case portSVC_FREE_SECURE_CONTEXT: + { + /* R0 contains the secure context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 ); + } + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + { + #if( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + } + break; + + #if( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + { + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ulPC >= ( uint32_t ) __syscalls_flash_start__ && + ulPC <= ( uint32_t ) __syscalls_flash_end__ ) + { + vRaisePrivilege(); + } + } + break; + #endif /* configENABLE_MPU */ + + default: + { + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } + } +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI; + *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI; + + #if( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr1 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h new file mode 100644 index 0000000..6314e96 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
@@ -0,0 +1,113 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__ (( naked )); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__ (( naked )); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked )); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s new file mode 100644 index 0000000..8d9bcc9 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -0,0 +1,326 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + EXTERN pxCurrentTCB + EXTERN xSecureContext + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + EXTERN SecureContext_SaveContext + EXTERN SecureContext_LoadContext + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vPortAllocateSecureContext + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMaskFromISR + PUBLIC vClearInterruptMaskFromISR + PUBLIC PendSV_Handler + PUBLIC SVC_Handler + PUBLIC vPortFreeSecureContext +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vPortAllocateSecureContext: + svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */ + ldr r5, =xSecureContext + str r1, [r5] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + msr control, r3 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r4 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ + ldr r4, =xSecureContext + str r1, [r4] /* Set xSecureContext to this task's value for the same. */ + msr psplim, r2 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r3 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMaskFromISR: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMaskFromISR: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ + +PendSV_Handler: + mrs r1, psp /* Read PSP in r1. */ + ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */ + + cbz r0, save_ns_context /* No secure context to save. */ + push {r0-r2, r14} + bl SecureContext_SaveContext + pop {r0-r3} /* LR is now in r3. */ + mov lr, r3 /* LR = r3. */ + lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r2, [r3] /* Read pxCurrentTCB. */ +#if ( configENABLE_MPU == 1 ) + subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + str r1, [r2] /* Save the new top of stack in TCB. */ + mrs r2, psplim /* r2 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ +#else /* configENABLE_MPU */ + subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ + str r1, [r2] /* Save the new top of stack in TCB. */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ +#endif /* configENABLE_MPU */ + b select_next_task + + save_ns_context: + ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r2, [r3] /* Read pxCurrentTCB. */ + #if ( configENABLE_FPU == 1 ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */ + it eq + vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */ + #endif /* configENABLE_FPU */ + #if ( configENABLE_MPU == 1 ) + subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */ + str r1, [r2] /* Save the new top of stack in TCB. */ + adds r1, r1, #16 /* r1 = r1 + 16. */ + stm r1, {r4-r11} /* Store the registers that are not saved automatically. */ + mrs r2, psplim /* r2 = PSPLIM. */ + mrs r3, control /* r3 = CONTROL. */ + mov r4, lr /* r4 = LR/EXC_RETURN. */ + subs r1, r1, #16 /* r1 = r1 - 16. */ + stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */ + #else /* configENABLE_MPU */ + subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ + str r1, [r2] /* Save the new top of stack in TCB. */ + adds r1, r1, #12 /* r1 = r1 + 12. */ + stm r1, {r4-r11} /* Store the registers that are not saved automatically. */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + subs r1, r1, #12 /* r1 = r1 - 12. */ + stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #endif /* configENABLE_MPU */ + + select_next_task: + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r3, [r2] /* Read pxCurrentTCB. */ + ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */ + + #if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */ + ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r4, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r4, #4 /* r4 = 4. */ + str r4, [r2] /* Program RNR = 4. */ + adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ + #endif /* configENABLE_MPU */ + + #if ( configENABLE_MPU == 1 ) + ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + msr control, r3 /* Restore the CONTROL register value for the task. */ + mov lr, r4 /* LR = r4. */ + ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r2] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + push {r1,r4} + bl SecureContext_LoadContext /* Restore the secure context. */ + pop {r1,r4} + mov lr, r4 /* LR = r4. */ + lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r1 /* Remember the new top of stack for the task. */ + bx lr + #else /* configENABLE_MPU */ + ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ + mov lr, r3 /* LR = r3. */ + ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ + str r0, [r2] /* Restore the task's xSecureContext. */ + cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ + push {r1,r3} + bl SecureContext_LoadContext /* Restore the secure context. */ + pop {r1,r3} + mov lr, r3 /* LR = r3. */ + lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ + msr psp, r1 /* Remember the new top of stack for the task. */ + bx lr + #endif /* configENABLE_MPU */ + + restore_ns_context: + ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */ + #if ( configENABLE_FPU == 1 ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */ + it eq + vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */ + #endif /* configENABLE_FPU */ + msr psp, r1 /* Remember the new top of stack for the task. */ + bx lr +/*-----------------------------------------------------------*/ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + +vPortFreeSecureContext: + /* r0 = uint32_t *pulTCB. */ + ldr r1, [r0] /* The first item in the TCB is the top of the stack. */ + ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */ + cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */ + it ne + svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + + END
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h new file mode 100644 index 0000000..c09b3ce --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -0,0 +1,299 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__(( always_inline )) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( 7UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ +typedef struct MPURegionSettings +{ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ +} MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ +typedef struct MPU_SETTINGS +{ + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ +} xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 0 +#define portSVC_FREE_SECURE_CONTEXT 1 +#define portSVC_START_SCHEDULER 2 +#define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#define portYIELD() vPortYield() +#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x ) +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#if( configENABLE_TRUSTZONE == 1 ) + /** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + + /** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#else + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) + #define portCLEAN_UP_TCB( pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + /** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + + /** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + + /** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c new file mode 100644 index 0000000..8a42230 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c
@@ -0,0 +1,204 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief CONTROL value for privileged tasks. + * + * Bit[0] - 0 --> Thread mode is privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_PRIVILEGED 0x02 + +/** + * @brief CONTROL value for un-privileged tasks. + * + * Bit[0] - 1 --> Thread mode is un-privileged. + * Bit[1] - 1 --> Thread mode uses PSP. + */ +#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03 +/*-----------------------------------------------------------*/ + +/** + * @brief Structure to represent secure context. + * + * @note Since stack grows down, pucStackStart is the highest address while + * pucStackLimit is the first addess of the allocated memory. + */ +typedef struct SecureContext +{ + uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */ + uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */ + uint8_t *pucStackStart; /**< First location of the stack memory. */ +} SecureContext_t; +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_Init( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* No stack for thread mode until a task's context is loaded. */ + secureportSET_PSPLIM( securecontextNO_STACK ); + secureportSET_PSP( securecontextNO_STACK ); + + #if( configENABLE_MPU == 1 ) + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } + #else /* configENABLE_MPU */ + { + /* Configure thread mode to use PSP and to be privileged.. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } + #endif /* configENABLE_MPU */ + } +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged ) +#else /* configENABLE_MPU */ + secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize ) +#endif /* configENABLE_MPU */ +{ + uint8_t *pucStackMemory = NULL; + uint32_t ulIPSR; + SecureContextHandle_t xSecureContextHandle = NULL; + #if( configENABLE_MPU == 1 ) + uint32_t *pulCurrentStackPointer = NULL; + #endif /* configENABLE_MPU */ + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Allocate the context structure. */ + xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) ); + + if( xSecureContextHandle != NULL ) + { + /* Allocate the stack space. */ + pucStackMemory = pvPortMalloc( ulSecureStackSize ); + + if( pucStackMemory != NULL ) + { + /* Since stack grows down, the starting point will be the last + * location. Note that this location is next to the last + * allocated byte because the hardware decrements the stack + * pointer before writing i.e. if stack pointer is 0x2, a push + * operation will decrement the stack pointer to 0x1 and then + * write at 0x1. */ + xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize; + + /* The stack cannot go beyond this location. This value is + * programmed in the PSPLIM register on context switch.*/ + xSecureContextHandle->pucStackLimit = pucStackMemory; + + #if( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart; + pulCurrentStackPointer--; + if( ulIsTaskPrivileged ) + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; + } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } + #else /* configENABLE_MPU */ + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart; + + } + #endif /* configENABLE_MPU */ + } + else + { + /* Free the context to avoid memory leak and make sure to return + * NULL to indicate failure. */ + vPortFree( xSecureContextHandle ); + xSecureContextHandle = NULL; + } + } + } + + return xSecureContextHandle; +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* Ensure that valid parameters are passed. */ + secureportASSERT( xSecureContextHandle != NULL ); + + /* Free the stack space. */ + vPortFree( xSecureContextHandle->pucStackLimit ); + + /* Free the context itself. */ + vPortFree( xSecureContextHandle ); + } +} +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h new file mode 100644 index 0000000..a98a7d0 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h
@@ -0,0 +1,111 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __SECURE_CONTEXT_H__ +#define __SECURE_CONTEXT_H__ + +/* Standard includes. */ +#include <stdint.h> + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" + +/** + * @brief PSP value when no task's context is loaded. + */ +#define securecontextNO_STACK 0x0 + +/** + * @brief Opaque handle. + */ +struct SecureContext; +typedef struct SecureContext* SecureContextHandle_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Initializes the secure context management system. + * + * PSP is set to NULL and therefore a task must allocate and load a context + * before calling any secure side function in the thread mode. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureContext_Init( void ); + +/** + * @brief Allocates a context on the secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] ulSecureStackSize Size of the stack to allocate on secure side. + * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise. + * + * @return Opaque context handle if context is successfully allocated, NULL + * otherwise. + */ +#if( configENABLE_MPU == 1 ) + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged ); +#else /* configENABLE_MPU */ + SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize ); +#endif /* configENABLE_MPU */ + +/** + * @brief Frees the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the + * context to be freed. + */ +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle ); + +/** + * @brief Loads the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be loaded. + */ +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle ); + +/** + * @brief Saves the given context. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + * + * @param[in] xSecureContextHandle Context handle corresponding to the context + * to be saved. + */ +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle ); + +#endif /* __SECURE_CONTEXT_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c new file mode 100644 index 0000000..6df620d --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c
@@ -0,0 +1,48 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Secure context includes. */ +#include "secure_context.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/* Functions implemented in assembler file. */ +extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle ); +extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle ); + +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle ) +{ + SecureContext_LoadContextAsm( xSecureContextHandle ); +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle ) +{ + SecureContext_SaveContextAsm( xSecureContextHandle ); +} +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s new file mode 100644 index 0000000..759a21f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
@@ -0,0 +1,73 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + SECTION .text:CODE:NOROOT(2) + THUMB + + PUBLIC SecureContext_LoadContextAsm + PUBLIC SecureContext_SaveContextAsm +/*-----------------------------------------------------------*/ + +SecureContext_LoadContextAsm: + /* xSecureContextHandle value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */ +#if ( configENABLE_MPU == 1 ) + ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */ + msr control, r3 /* CONTROL = r3. */ +#endif /* configENABLE_MPU */ + msr psplim, r2 /* PSPLIM = r2. */ + msr psp, r1 /* PSP = r1. */ + + load_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + +SecureContext_SaveContextAsm: + /* xSecureContextHandle value is in r0. */ + mrs r1, ipsr /* r1 = IPSR. */ + cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */ + mrs r1, psp /* r1 = PSP. */ +#if ( configENABLE_FPU == 1 ) + vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */ + vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */ +#endif /* configENABLE_FPU */ +#if ( configENABLE_MPU == 1 ) + mrs r2, control /* r2 = CONTROL. */ + stmdb r1!, {r2} /* Store CONTROL value on the stack. */ +#endif /* configENABLE_MPU */ + str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */ + movs r1, #0 /* r1 = securecontextNO_STACK. */ + msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */ + msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */ + + save_ctx_therad_mode: + bx lr +/*-----------------------------------------------------------*/ + + END
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c new file mode 100644 index 0000000..c4f613f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -0,0 +1,450 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include <stdint.h> + +/* Secure context heap includes. */ +#include "secure_heap.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Total heap size. + */ +#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) ) + +/* No test marker by default. */ +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +/* No tracing by default. */ +#ifndef traceMALLOC + #define traceMALLOC( pvReturn, xWantedSize ) +#endif + +/* No tracing by default. */ +#ifndef traceFREE + #define traceFREE( pv, xBlockSize ) +#endif + +/* Block sizes must not get too small. */ +#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) +/*-----------------------------------------------------------*/ + +/* Allocate the memory for the heap. */ +#if( configAPPLICATION_ALLOCATED_HEAP == 1 ) + /* The application writer has already defined the array used for the RTOS + * heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#else /* configAPPLICATION_ALLOCATED_HEAP */ + static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/** + * @brief The linked list structure. + * + * This is used to link free blocks in order of their memory address. + */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */ + size_t xBlockSize; /**< The size of the free block. */ +} BlockLink_t; +/*-----------------------------------------------------------*/ + +/** + * @brief Called automatically to setup the required heap structures the first + * time pvPortMalloc() is called. + */ +static void prvHeapInit( void ); + +/** + * @brief Inserts a block of memory that is being freed into the correct + * position in the list of free memory blocks. + * + * The block being freed will be merged with the block in front it and/or the + * block behind it if the memory blocks are adjacent to each other. + * + * @param[in] pxBlockToInsert The block being freed. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ); +/*-----------------------------------------------------------*/ + +/** + * @brief The size of the structure placed at the beginning of each allocated + * memory block must by correctly byte aligned. + */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + +/** + * @brief Create a couple of list links to mark the start and end of the list. + */ +static BlockLink_t xStart, *pxEnd = NULL; + +/** + * @brief Keeps track of the number of free bytes remaining, but says nothing + * about fragmentation. + */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/** + * @brief Gets set to the top bit of an size_t type. + * + * When this bit in the xBlockSize member of an BlockLink_t structure is set + * then the block belongs to the application. When the bit is free the block is + * still part of the free heap space. + */ +static size_t xBlockAllocatedBit = 0; +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) +{ +BlockLink_t *pxFirstFreeBlock; +uint8_t *pucAlignedHeap; +size_t uxAddress; +size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( secureportBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) +{ +BlockLink_t *pxIterator; +uint8_t *puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void *pvPortMalloc( size_t xWantedSize ) +{ +BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; +void *pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size is increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( xWantedSize > 0 ) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number of + * bytes. */ + if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. */ + xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); + secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size was + * not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the single + * block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned by + * the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + + #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif + + secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void *pv ) +{ +uint8_t *puc = ( uint8_t * ) pv; +BlockLink_t *pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + secureportDISABLE_NON_SECURE_INTERRUPTS(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + } + secureportENABLE_NON_SECURE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h new file mode 100644 index 0000000..aae5cfc --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
@@ -0,0 +1,51 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __SECURE_HEAP_H__ +#define __SECURE_HEAP_H__ + +/* Standard includes. */ +#include <stdlib.h> + +/** + * @brief Allocates memory from heap. + * + * @param[in] xWantedSize The size of the memory to be allocated. + * + * @return Pointer to the memory region if the allocation is successful, NULL + * otherwise. + */ +void *pvPortMalloc( size_t xWantedSize ); + +/** + * @brief Frees the previously allocated memory. + * + * @param[in] pv Pointer to the memory to be freed. + */ +void vPortFree( void *pv ); + +#endif /* __SECURE_HEAP_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c new file mode 100644 index 0000000..60ef1e8 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c
@@ -0,0 +1,105 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include <stdint.h> + +/* Secure init includes. */ +#include "secure_init.h" + +/* Secure port macros. */ +#include "secure_port_macros.h" + +/** + * @brief Constants required to manipulate the SCB. + */ +#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */ +#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL ) +#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS ) +#define secureinitSCB_AIRCR_PRIS_POS ( 14UL ) +#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS ) + +/** + * @brief Constants required to manipulate the FPU. + */ +#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define secureinitFPCCR_LSPENS_POS ( 29UL ) +#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS ) +#define secureinitFPCCR_TS_POS ( 26UL ) +#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS ) + +#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */ +#define secureinitNSACR_CP10_POS ( 10UL ) +#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS ) +#define secureinitNSACR_CP11_POS ( 11UL ) +#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS ) +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) | + ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) | + ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK ); + } +} +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void ) +{ + uint32_t ulIPSR; + + /* Read the Interrupt Program Status Register (IPSR) value. */ + secureportREAD_IPSR( ulIPSR ); + + /* Do nothing if the processor is running in the Thread Mode. IPSR is zero + * when the processor is running in the Thread Mode. */ + if( ulIPSR != 0 ) + { + /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is + * permitted. CP11 should be programmed to the same value as CP10. */ + *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); + + /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + * that we can enable/disable lazy stacking in port.c file. */ + *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK ); + + /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP + * registers (S16-S31) are also pushed to stack on exception entry and + * restored on exception return. */ + *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK ); + } +} +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h new file mode 100644 index 0000000..3954e13 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h
@@ -0,0 +1,53 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __SECURE_INIT_H__ +#define __SECURE_INIT_H__ + +/** + * @brief De-prioritizes the non-secure exceptions. + * + * This is needed to ensure that the non-secure PendSV runs at the lowest + * priority. Context switch is done in the non-secure PendSV handler. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_DePrioritizeNSExceptions( void ); + +/** + * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access. + * + * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point + * Registers are not leaked to the non-secure side. + * + * @note This function must be called in the handler mode. It is no-op if called + * in the thread mode. + */ +void SecureInit_EnableNSFPUAccess( void ); + +#endif /* __SECURE_INIT_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h new file mode 100644 index 0000000..f392537 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
@@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __SECURE_PORT_MACROS_H__ +#define __SECURE_PORT_MACROS_H__ + +/** + * @brief Byte alignment requirements. + */ +#define secureportBYTE_ALIGNMENT 8 +#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 ) + +/** + * @brief Macro to declare a function as non-secure callable. + */ +#if defined( __IAR_SYSTEMS_ICC__ ) + #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root +#else + #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry)) __attribute__((used)) +#endif + +/** + * @brief Set the secure PRIMASK value. + */ +#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Set the non-secure PRIMASK value. + */ +#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \ + __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" ) + +/** + * @brief Read the PSP value in the given variable. + */ +#define secureportREAD_PSP( pucOutCurrentStackPointer ) \ + __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) ) + +/** + * @brief Set the PSP to the given value. + */ +#define secureportSET_PSP( pucCurrentStackPointer ) \ + __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) ) + +/** + * @brief Set the PSPLIM to the given value. + */ +#define secureportSET_PSPLIM( pucStackLimit ) \ + __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) ) + +/** + * @brief Set the NonSecure MSP to the given value. + */ +#define secureportSET_MSP_NS( pucMainStackPointer ) \ + __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) ) + +/** + * @brief Set the CONTROL register to the given value. + */ +#define secureportSET_CONTROL( ulControl ) \ + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" ) + +/** + * @brief Read the Interrupt Program Status Register (IPSR) value in the given + * variable. + */ +#define secureportREAD_IPSR( ulIPSR ) \ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) ) + +/** + * @brief PRIMASK value to enable interrupts. + */ +#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0 + +/** + * @brief PRIMASK value to disable interrupts. + */ +#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1 + +/** + * @brief Disable secure interrupts. + */ +#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Disable non-secure interrupts. + * + * This effectively disables context switches. + */ +#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL ) + +/** + * @brief Enable non-secure interrupts. + */ +#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL ) + +/** + * @brief Assert definition. + */ +#define secureportASSERT( x ) \ + if( ( x ) == 0 ) \ + { \ + secureportDISABLE_SECURE_INTERRUPTS(); \ + secureportDISABLE_NON_SECURE_INTERRUPTS(); \ + for( ;; ); \ + } + +#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c new file mode 100644 index 0000000..b0394fb --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/* Portasm includes. */ +#include "portasm.h" + +#if( configENABLE_TRUSTZONE == 1 ) + /* Secure components includes. */ + #include "secure_context.h" + #include "secure_init.h" +#endif /* configENABLE_TRUSTZONE */ + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/** + * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only + * i.e. the processor boots as secure and never jumps to the non-secure side. + * The Trust Zone support in the port must be disabled in order to run FreeRTOS + * on the secure side. The following are the valid configuration seetings: + * + * 1. Run FreeRTOS on the Secure Side: + * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 + * + * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1 + * + * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support: + * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0 + */ +#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) + #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the NVIC. + */ +#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 ) +#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 ) +#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 ) +#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) +#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 ) +#define portNVIC_SYSTICK_CLK ( 0x00000004 ) +#define portNVIC_SYSTICK_INT ( 0x00000002 ) +#define portNVIC_SYSTICK_ENABLE ( 0x00000001 ) +#define portNVIC_PENDSVSET ( 0x10000000 ) +#define portMIN_INTERRUPT_PRIORITY ( 255UL ) +#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) +#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the SCB. + */ +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the FPU. + */ +#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */ +#define portCPACR_CP10_VALUE ( 3UL ) +#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE +#define portCPACR_CP10_POS ( 20UL ) +#define portCPACR_CP11_POS ( 22UL ) + +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */ +#define portFPCCR_ASPEN_POS ( 31UL ) +#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS ) +#define portFPCCR_LSPEN_POS ( 30UL ) +#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to manipulate the MPU. + */ +#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) ) + +#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) ) + +#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) ) + +#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) ) + +#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) ) + +#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) ) + +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ + +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) + +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) + +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) + +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) + +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) + +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) + +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +/* Enable privileged access to unmapped region. */ +#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL ) + +/* Enable MPU. */ +#define portMPU_ENABLE ( 1UL << 0UL ) + +/* Expected value of the portMPU_TYPE register. */ +#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ +/*-----------------------------------------------------------*/ + +/** + * @brief Constants required to set up the initial stack. + */ +#define portINITIAL_XPSR ( 0x01000000 ) + +#if( configRUN_FREERTOS_SECURE_ONLY == 1 ) + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF FD + * 1111 1111 1111 1111 1111 1111 1111 1101 + * + * Bit[6] - 1 --> The exception was taken from the Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 1 --> The exception was taken to the Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#else + /** + * @brief Initial EXC_RETURN value. + * + * FF FF FF BC + * 1111 1111 1111 1111 1111 1111 1011 1100 + * + * Bit[6] - 0 --> The exception was taken from the Non-Secure state. + * Bit[5] - 1 --> Do not skip stacking of additional state context. + * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context. + * Bit[3] - 1 --> Return to the Thread mode. + * Bit[2] - 1 --> Restore registers from the process stack. + * Bit[1] - 0 --> Reserved, 0. + * Bit[0] - 0 --> The exception was taken to the Non-Secure state. + */ + #define portINITIAL_EXC_RETURN ( 0xffffffbc ) +#endif /* configRUN_FREERTOS_SECURE_ONLY */ + +/** + * @brief CONTROL register privileged bit mask. + * + * Bit[0] in CONTROL register tells the privilege: + * Bit[0] = 0 ==> The task is privileged. + * Bit[0] = 1 ==> The task is not privileged. + */ +#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL ) + +/** + * @brief Initial CONTROL register values. + */ +#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 ) +#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 ) + +/** + * @brief Let the user override the pre-loading of the initial LR with the + * address of prvTaskExitError() in case it messes up unwinding of the stack + * in the debugger. + */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/** + * @brief If portPRELOAD_REGISTERS then registers will be given an initial value + * when a task is created. This helps in debugging at the cost of code size. + */ +#define portPRELOAD_REGISTERS 1 + +/** + * @brief A task is created without a secure context, and must call + * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes + * any secure calls. + */ +#define portNO_SECURE_CONTEXT 0 +/*-----------------------------------------------------------*/ + +/** + * @brief Setup the timer to generate the tick interrupts. + */ +static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Used to catch tasks that attempt to return from their implementing + * function. + */ +static void prvTaskExitError( void ); + +#if( configENABLE_MPU == 1 ) + /** + * @brief Setup the Memory Protection Unit (MPU). + */ + static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_MPU */ + +#if( configENABLE_FPU == 1 ) + /** + * @brief Setup the Floating Point Unit (FPU). + */ + static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; +#endif /* configENABLE_FPU */ + +/** + * @brief Yield the processor. + */ +void vPortYield( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Enter critical section. + */ +void vPortEnterCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Exit from critical section. + */ +void vPortExitCritical( void ) PRIVILEGED_FUNCTION; + +/** + * @brief SysTick handler. + */ +void SysTick_Handler( void ) PRIVILEGED_FUNCTION; + +/** + * @brief C part of SVC handler. + */ +portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + +/** + * @brief Each task maintains its own interrupt status in the critical nesting + * variable. + */ +static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL; + +#if( configENABLE_TRUSTZONE == 1 ) + /** + * @brief Saved as part of the task context to indicate which context the + * task is using on the secure side. + */ + portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT; +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Stop and reset the SysTick. */ + *( portNVIC_SYSTICK_CTRL ) = 0UL; + *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ +volatile uint32_t ulDummy = 0UL; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). Artificially force an assert() + * to be triggered if configASSERT() is defined, then stop here so + * application writers can catch the error. */ + configASSERT( ulCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + + while( ulDummy == 0 ) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being + * defined but never called. ulDummy is used purely to quieten other + * warnings about code appearing after this function is called - making + * ulDummy volatile makes the compiler think the function could return + * and therefore not output an 'unreachable code' warning for code that + * appears after it. */ + } +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __privileged_functions_start__; + extern uint32_t * __privileged_functions_end__; + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + extern uint32_t * __unprivileged_flash_start__; + extern uint32_t * __unprivileged_flash_end__; + extern uint32_t * __privileged_sram_start__; + extern uint32_t * __privileged_sram_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __privileged_functions_start__[]; + extern uint32_t __privileged_functions_end__[]; + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + extern uint32_t __unprivileged_flash_start__[]; + extern uint32_t __unprivileged_flash_end__[]; + extern uint32_t __privileged_sram_start__[]; + extern uint32_t __privileged_sram_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ + + /* Check that the MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* MAIR0 - Index 0. */ + portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + /* MAIR0 - Index 1. */ + portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* Setup privileged flash as Read Only so that privileged tasks can + * read it but not modify. */ + portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged flash as Read Only by both privileged and + * unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup unprivileged syscalls flash as Read Only by both privileged + * and unprivileged tasks. All tasks can read it but no-one can modify. */ + portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_ONLY ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Setup RAM containing kernel data for privileged access only. */ + portMPU_RNR_REG = portPRIVILEGED_RAM_REGION; + portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Enable mem fault. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE; + + /* Enable MPU with privileged background access i.e. unmapped + * regions have privileged access. */ + portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE ); + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +#if( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ + { + #if( configENABLE_TRUSTZONE == 1 ) + { + /* Enable non-secure access to the FPU. */ + SecureInit_EnableNSFPUAccess(); + } + #endif /* configENABLE_TRUSTZONE */ + + /* CP10 = 11 ==> Full access to FPU i.e. both privileged and + * unprivileged code should be able to access FPU. CP11 should be + * programmed to the same value as CP10. */ + *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) | + ( portCPACR_CP11_VALUE << portCPACR_CP11_POS ) + ); + + /* ASPEN = 1 ==> Hardware should automatically preserve floating point + * context on exception entry and restore on exception return. + * LSPEN = 1 ==> Enable lazy context save of FP state. */ + *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); + } +#endif /* configENABLE_FPU */ +/*-----------------------------------------------------------*/ + +void vPortYield( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Set a PendSV to request a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile( "dsb" ::: "memory" ); + __asm volatile( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + portDISABLE_INTERRUPTS(); + ulCriticalNesting++; + + /* Barriers are normally not required but do ensure the code is + * completely within the specified behaviour for the architecture. */ + __asm volatile( "dsb" ::: "memory" ); + __asm volatile( "isb" ); +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */ +{ + configASSERT( ulCriticalNesting ); + ulCriticalNesting--; + + if( ulCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */ +{ +uint32_t ulPreviousMask; + + ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Pend a context switch. */ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */ +{ +#if( configENABLE_MPU == 1 ) + #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being + * exported from linker scripts. */ + extern uint32_t * __syscalls_flash_start__; + extern uint32_t * __syscalls_flash_end__; + #else + /* Declaration when these variable are exported from linker scripts. */ + extern uint32_t __syscalls_flash_start__[]; + extern uint32_t __syscalls_flash_end__[]; + #endif /* defined( __ARMCC_VERSION ) */ +#endif /* configENABLE_MPU */ + +uint32_t ulPC; + +#if( configENABLE_TRUSTZONE == 1 ) + uint32_t ulR0; + #if( configENABLE_MPU == 1 ) + uint32_t ulControl, ulIsTaskPrivileged; + #endif /* configENABLE_MPU */ +#endif /* configENABLE_TRUSTZONE */ +uint8_t ucSVCNumber; + + /* Register are stored on the stack in the following order - R0, R1, R2, R3, + * R12, LR, PC, xPSR. */ + ulPC = pulCallerStackAddress[ 6 ]; + ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ]; + + switch( ucSVCNumber ) + { + #if( configENABLE_TRUSTZONE == 1 ) + case portSVC_ALLOCATE_SECURE_CONTEXT: + { + /* R0 contains the stack size passed as parameter to the + * vPortAllocateSecureContext function. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + #if( configENABLE_MPU == 1 ) + { + /* Read the CONTROL register value. */ + __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) ); + + /* The task that raised the SVC is privileged if Bit[0] + * in the CONTROL register is 0. */ + ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 ); + + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged ); + } + #else + { + /* Allocate and load a context for the secure task. */ + xSecureContext = SecureContext_AllocateContext( ulR0 ); + } + #endif /* configENABLE_MPU */ + + configASSERT( xSecureContext != NULL ); + SecureContext_LoadContext( xSecureContext ); + } + break; + + case portSVC_FREE_SECURE_CONTEXT: + { + /* R0 contains the secure context handle to be freed. */ + ulR0 = pulCallerStackAddress[ 0 ]; + + /* Free the secure context. */ + SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 ); + } + break; + #endif /* configENABLE_TRUSTZONE */ + + case portSVC_START_SCHEDULER: + { + #if( configENABLE_TRUSTZONE == 1 ) + { + /* De-prioritize the non-secure exceptions so that the + * non-secure pendSV runs at the lowest priority. */ + SecureInit_DePrioritizeNSExceptions(); + + /* Initialize the secure context management system. */ + SecureContext_Init(); + } + #endif /* configENABLE_TRUSTZONE */ + + #if( configENABLE_FPU == 1 ) + { + /* Setup the Floating Point Unit (FPU). */ + prvSetupFPU(); + } + #endif /* configENABLE_FPU */ + + /* Setup the context of the first task so that the first task starts + * executing. */ + vRestoreContextOfFirstTask(); + } + break; + + #if( configENABLE_MPU == 1 ) + case portSVC_RAISE_PRIVILEGE: + { + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ulPC >= ( uint32_t ) __syscalls_flash_start__ && + ulPC <= ( uint32_t ) __syscalls_flash_end__ ) + { + vRaisePrivilege(); + } + } + break; + #endif /* configENABLE_MPU */ + + default: + { + /* Incorrect SVC call. */ + configASSERT( pdFALSE ); + } + } +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */ +#else + StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */ +#endif /* configENABLE_MPU */ +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + #if( portPRELOAD_REGISTERS == 0 ) + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */ + *pxTopOfStack = portINITIAL_EXC_RETURN; + + #if( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #else /* portPRELOAD_REGISTERS */ + { + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */ + + #if( configENABLE_MPU == 1 ) + { + pxTopOfStack--; + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */ + } + } + #endif /* configENABLE_MPU */ + + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + + #if( configENABLE_TRUSTZONE == 1 ) + { + pxTopOfStack--; + *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */ + } + #endif /* configENABLE_TRUSTZONE */ + } + #endif /* portPRELOAD_REGISTERS */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI; + *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI; + + #if( configENABLE_MPU == 1 ) + { + /* Setup the Memory Protection Unit (MPU). */ + prvSetupMPU(); + } + #endif /* configENABLE_MPU */ + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + prvSetupTimerInterrupt(); + + /* Initialize the critical nesting count ready for the first task. */ + ulCriticalNesting = 0; + + /* Start the first task. */ + vStartFirstTask(); + + /* Should never get here as the tasks will now be executing. Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimization does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */ +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) + { + uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; + int32_t lIndex = 0; + + /* Setup MAIR0. */ + xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK ); + xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK ); + + /* This function is called automatically when the task is created - in + * which case the stack region parameters will be valid. At all other + * times the stack parameters will not be valid and it is assumed that + * the stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ) | + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_EXECUTE_NEVER ); + + xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_ATTR_INDEX0 ) | + ( portMPU_RLAR_REGION_ENABLE ); + } + + /* User supplied configurable regions. */ + for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ ) + { + /* If xRegions is NULL i.e. the task has not specified any MPU + * region, the else part ensures that all the configurable MPU + * regions are invalidated. */ + if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) ) + { + /* Translate the generic region definition contained in xRegions + * into the ARMv8 specific MPU settings that are then stored in + * xMPUSettings. */ + ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK; + ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1; + ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK; + + /* Start address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) | + ( portMPU_REGION_NON_SHAREABLE ); + + /* RO/RW. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY ); + } + else + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE ); + } + + /* XN. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER ); + } + + /* End Address. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | + ( portMPU_RLAR_REGION_ENABLE ); + + /* Normal memory/ Device memory. */ + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) + { + /* Attr1 in MAIR0 is configured as device memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1; + } + else + { + /* Attr1 in MAIR0 is configured as normal memory. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0; + } + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL; + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL; + } + + lIndex++; + } + } +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h new file mode 100644 index 0000000..6314e96 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef __PORT_ASM_H__ +#define __PORT_ASM_H__ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* MPU wrappers includes. */ +#include "mpu_wrappers.h" + +/** + * @brief Restore the context of the first task so that the first task starts + * executing. + */ +void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +BaseType_t xIsPrivileged( void ) __attribute__ (( naked )); + +/** + * @brief Raises the privilege level by clearing the bit 0 of the CONTROL + * register. + * + * @note This is a privileged function and should only be called from the kenrel + * code. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + * + * Bit 0 of the CONTROL register defines the privilege level of Thread Mode. + * Bit[0] = 0 --> The processor is running privileged + * Bit[0] = 1 --> The processor is running unprivileged. + */ +void vResetPrivilege( void ) __attribute__ (( naked )); + +/** + * @brief Starts the first task. + */ +void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Disables interrupts. + */ +uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Enables interrupts. + */ +void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief PendSV Exception handler. + */ +void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief SVC Handler. + */ +void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +/** + * @brief Allocate a Secure context for the calling task. + * + * @param[in] ulSecureStackSize The size of the stack to be allocated on the + * secure side for the calling task. + */ +void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked )); + +/** + * @brief Free the task's secure context. + * + * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task. + */ +void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; + +#endif /* __PORT_ASM_H__ */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s new file mode 100644 index 0000000..31623f2 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -0,0 +1,242 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + PUBLIC vRestoreContextOfFirstTask + PUBLIC vRaisePrivilege + PUBLIC vStartFirstTask + PUBLIC ulSetInterruptMaskFromISR + PUBLIC vClearInterruptMaskFromISR + PUBLIC PendSV_Handler + PUBLIC SVC_Handler +/*-----------------------------------------------------------*/ + +/*---------------- Unprivileged Functions -------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +/*----------------- Privileged Functions --------------------*/ + +/*-----------------------------------------------------------*/ + + SECTION privileged_functions:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +vRestoreContextOfFirstTask: + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r3, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r3, #4 /* r3 = 4. */ + str r3, [r2] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + msr control, r2 /* Set this task's CONTROL value. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r3 /* Finally, branch to EXC_RETURN. */ +#else /* configENABLE_MPU */ + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ + msr psplim, r1 /* Set this task's PSPLIM value. */ + movs r1, #2 /* r1 = 2. */ + msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + adds r0, #32 /* Discard everything up to r0. */ + msr psp, r0 /* This is now the new top of stack to use in the task. */ + isb + bx r2 /* Finally, branch to EXC_RETURN. */ +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +vRaisePrivilege: + mrs r0, control /* Read the CONTROL register. */ + bic r0, r0, #1 /* Clear the bit 0. */ + msr control, r0 /* Write back the new CONTROL value. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + +vStartFirstTask: + ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */ + ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */ + ldr r0, [r0] /* The first entry in vector table is stack pointer. */ + msr msp, r0 /* Set the MSP back to the start of the stack. */ + cpsie i /* Globally enable interrupts. */ + cpsie f + dsb + isb + svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */ +/*-----------------------------------------------------------*/ + +ulSetInterruptMaskFromISR: + mrs r0, PRIMASK + cpsid i + bx lr +/*-----------------------------------------------------------*/ + +vClearInterruptMaskFromISR: + msr PRIMASK, r0 + bx lr +/*-----------------------------------------------------------*/ + +PendSV_Handler: + mrs r0, psp /* Read PSP in r0. */ +#if ( configENABLE_FPU == 1 ) + tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */ + it eq + vstmdbeq r0!, {s16-s31} /* Store the FPU registers which are not saved automatically. */ +#endif /* configENABLE_FPU */ +#if ( configENABLE_MPU == 1 ) + mrs r1, psplim /* r1 = PSPLIM. */ + mrs r2, control /* r2 = CONTROL. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */ +#else /* configENABLE_MPU */ + mrs r2, psplim /* r2 = PSPLIM. */ + mov r3, lr /* r3 = LR/EXC_RETURN. */ + stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ +#endif /* configENABLE_MPU */ + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + str r0, [r1] /* Save the new top of stack in TCB. */ + + cpsid i + bl vTaskSwitchContext + cpsie i + + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ + ldr r1, [r2] /* Read pxCurrentTCB. */ + ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ + +#if ( configENABLE_MPU == 1 ) + dmb /* Complete outstanding transfers before disabling MPU. */ + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */ + str r4, [r2] /* Disable MPU. */ + + adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */ + ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */ + ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */ + str r3, [r2] /* Program MAIR0. */ + ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */ + movs r3, #4 /* r3 = 4. */ + str r3, [r2] /* Program RNR = 4. */ + adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */ + ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */ + ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */ + stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */ + + ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */ + ldr r4, [r2] /* Read the value of MPU_CTRL. */ + orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */ + str r4, [r2] /* Enable MPU. */ + dsb /* Force memory writes before continuing. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_MPU == 1 ) + ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */ +#else /* configENABLE_MPU */ + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ +#endif /* configENABLE_MPU */ + +#if ( configENABLE_FPU == 1 ) + tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */ + it eq + vldmiaeq r0!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */ +#endif /* configENABLE_FPU */ + + #if ( configENABLE_MPU == 1 ) + msr psplim, r1 /* Restore the PSPLIM register value for the task. */ + msr control, r2 /* Restore the CONTROL register value for the task. */ +#else /* configENABLE_MPU */ + msr psplim, r2 /* Restore the PSPLIM register value for the task. */ +#endif /* configENABLE_MPU */ + msr psp, r0 /* Remember the new top of stack for the task. */ + bx r3 +/*-----------------------------------------------------------*/ + +SVC_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vPortSVCHandler_C +/*-----------------------------------------------------------*/ + + END
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h new file mode 100644 index 0000000..c09b3ce --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -0,0 +1,299 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *------------------------------------------------------------------------------ + */ + +#ifndef configENABLE_FPU + #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU. +#endif /* configENABLE_FPU */ + +#ifndef configENABLE_MPU + #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU. +#endif /* configENABLE_MPU */ + +#ifndef configENABLE_TRUSTZONE + #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone. +#endif /* configENABLE_TRUSTZONE */ + +/*-----------------------------------------------------------*/ + +/** + * @brief Type definitions. + */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * Architecture specifics. + */ +#define portARCH_NAME "Cortex-M33" +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portNOP() +#define portINLINE __inline +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__(( always_inline )) +#endif +#define portHAS_STACK_OVERFLOW_CHECKING 1 +#define portDONT_DISCARD __root +/*-----------------------------------------------------------*/ + +/** + * @brief Extern declarations. + */ +extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */; + +extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */; +extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */; + +extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; +extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; + +#if( configENABLE_TRUSTZONE == 1 ) + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; +#endif /* configENABLE_TRUSTZONE */ + +#if( configENABLE_MPU == 1 ) + extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; + extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief MPU specific constants. + */ +#if( configENABLE_MPU == 1 ) + #define portUSING_MPU_WRAPPERS 1 + #define portPRIVILEGE_BIT ( 0x80000000UL ) +#else + #define portPRIVILEGE_BIT ( 0x0UL ) +#endif /* configENABLE_MPU */ + + +/* MPU regions. */ +#define portPRIVILEGED_FLASH_REGION ( 0UL ) +#define portUNPRIVILEGED_FLASH_REGION ( 1UL ) +#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL ) +#define portPRIVILEGED_RAM_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( 7UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +/* Device memory attributes used in MPU_MAIR registers. + * + * 8-bit values encoded as follows: + * Bit[7:4] - 0000 - Device Memory + * Bit[3:2] - 00 --> Device-nGnRnE + * 01 --> Device-nGnRE + * 10 --> Device-nGRE + * 11 --> Device-GRE + * Bit[1:0] - 00, Reserved. + */ +#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */ +#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */ +#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */ +#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */ + +/* Normal memory attributes used in MPU_MAIR registers. */ +#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */ +#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */ + +/* Attributes used in MPU_RBAR registers. */ +#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL ) +#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL ) +#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL ) + +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL ) +#define portMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL ) +#define portMPU_REGION_READ_ONLY ( 3UL << 1UL ) + +#define portMPU_REGION_EXECUTE_NEVER ( 1UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Settings to define an MPU region. + */ +typedef struct MPURegionSettings +{ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ +} MPURegionSettings_t; + +/** + * @brief MPU settings as stored in the TCB. + */ +typedef struct MPU_SETTINGS +{ + uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */ + MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */ +} xMPU_SETTINGS; +/*-----------------------------------------------------------*/ + +/** + * @brief SVC numbers. + */ +#define portSVC_ALLOCATE_SECURE_CONTEXT 0 +#define portSVC_FREE_SECURE_CONTEXT 1 +#define portSVC_START_SCHEDULER 2 +#define portSVC_RAISE_PRIVILEGE 3 +/*-----------------------------------------------------------*/ + +/** + * @brief Scheduler utilities. + */ +#define portYIELD() vPortYield() +#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/** + * @brief Critical section management. + */ +#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x ) +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/** + * @brief Task function macros as described on the FreeRTOS.org WEB site. + */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#if( configENABLE_TRUSTZONE == 1 ) + /** + * @brief Allocate a secure context for the task. + * + * Tasks are not created with a secure context. Any task that is going to call + * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a + * secure context before it calls any secure function. + * + * @param[in] ulSecureStackSize The size of the secure stack to be allocated. + */ + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize ) + + /** + * @brief Called when a task is deleted to delete the task's secure context, + * if it has one. + * + * @param[in] pxTCB The TCB of the task being deleted. + */ + #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB ) +#else + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) + #define portCLEAN_UP_TCB( pxTCB ) +#endif /* configENABLE_TRUSTZONE */ +/*-----------------------------------------------------------*/ + +#if( configENABLE_MPU == 1 ) + /** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ + #define portIS_PRIVILEGED() xIsPrivileged() + + /** + * @brief Raise an SVC request to raise privilege. + * + * The SVC handler checks that the SVC was raised from a system call and only + * then it raises the privilege. If this is called from any other place, + * the privilege is not raised. + */ + #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + + /** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ + #define portRESET_PRIVILEGE() vResetPrivilege() +#else + #define portIS_PRIVILEGED() + #define portRAISE_PRIVILEGE() + #define portRESET_PRIVILEGE() +#endif /* configENABLE_MPU */ +/*-----------------------------------------------------------*/ + +/** + * @brief Barriers. + */ +#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" ) +/*-----------------------------------------------------------*/ + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c new file mode 100644 index 0000000..cf89048 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
@@ -0,0 +1,656 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM CM4F port. + *----------------------------------------------------------*/ + +/* IAR includes. */ +#include <intrinsics.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __ARMVFP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + /* The way the SysTick is clocked is not modified in case it is not the same + as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 +r0p1 port. */ +#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have +occurred while the SysTick counter is stopped during tickless idle +calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should +have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Turn the VFP on. + */ +extern void vPortEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting +variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* This port can be used on all revisions of the Cortex-M7 core other than + the r0p1 parts. r0p1 parts should use the port from the + /source/portable/GCC/ARM_CM7/r0p1 directory. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + + #if( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + functions can be called. ISR safe functions are those that end in + "FromISR". FreeRTOS maintains separate thread and ISR API functions to + ensure interrupt entry is as fast and simple as possible. + + Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + priority bits matches the number of priority bits actually queried + from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + priority bits matches the number of priority bits actually queried + from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* conifgASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; + portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + executes all interrupts must be unmasked. There is therefore no need to + save and then restore the interrupt mask value as its value is already + known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + is accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + tick periods. -1 is used because this code will execute part way + through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + method as that will mask interrupts that should exit sleep mode. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_interrupt() + call above. */ + __enable_interrupt(); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + set its parameter to 0 to indicate that its implementation contains + its own wait for interrupt or wait for event instruction, and so wfi + should not be executed again. However, the original expected idle + time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + if( xModifiableIdleTime > 0 ) + { + __DSB(); + __WFI(); + __ISB(); + } + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + out of sleep mode to execute immediately. see comments above + __disable_interrupt() call above. */ + __enable_interrupt(); + __DSB(); + __ISB(); + + /* Disable interrupts again because the clock is about to be stopped + and interrupts that execute while the clock is stopped will increase + any slippage between the time maintained by the RTOS and calendar + time. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* Disable the SysTick clock without reading the + portNVIC_SYSTICK_CTRL_REG register to ensure the + portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + the time the SysTick is stopped for is accounted for as best it can + be, but using the tickless mode will inevitably result in some tiny + drift of the time maintained by the kernel with respect to calendar + time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + been set back to the current reload value (the reload back being + correct for the entire expected idle time) or if the SysTick is yet + to count to zero (in which case an interrupt other than the SysTick + must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + reloaded with ulReloadValue. Reset the + portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + underflowed because the post sleep hook did something + that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + function exits, the tick value maintained by the tick is stepped + forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + Work out how long the sleep lasted rounded to complete tick + periods (not the ulReload value which accounted for part + ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrpts enabled. */ + __enable_interrupt(); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + an interrupt that has been assigned a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + function. ISR safe FreeRTOS API functions must *only* be called + from interrupts that have been assigned a priority at or below + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Numerically low interrupt priority numbers represent logically high + interrupt priorities, therefore the priority of the interrupt must + be set to a value equal to or numerically *higher* than + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Interrupts that use the FreeRTOS API must not be left at their + default priority of zero as that is the highest possible priority, + which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + and therefore also guaranteed to be invalid. + + FreeRTOS maintains separate thread and ISR API functions to ensure + interrupt entry is as fast and simple as possible. + + The following links provide detailed information: + http://www.freertos.org/RTOS-Cortex-M3-M4.html + http://www.freertos.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + that define each interrupt's priority to be split between bits that + define the interrupt's pre-emption priority bits and bits that define + the interrupt's sub-priority. For simplicity all bits must be defined + to be pre-emption priority bits. The following assertion will fail if + this is not the case (if some bits represent a sub-priority). + + If the application only uses CMSIS libraries for interrupt + configuration then the correct setting can be achieved on all Cortex-M + devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + scheduler. Note however that some vendor specific peripheral libraries + assume a non-zero priority group setting, in which cases using a value + of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ + + + + + + + + + + + + + + + + + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s new file mode 100644 index 0000000..8f37baa --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
@@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include <FreeRTOSConfig.h> + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC vPortEnableVFP + + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + stmdb r0!, {r4-r11, r14} + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r0, r3} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + + /* Is the task using the FPU context? If so, pop the high vfp registers + too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ + #if WORKAROUND_PMU_CM001 == 1 + push { r14 } + pop { pc } + #endif + #endif + + bx r14 + + +/*-----------------------------------------------------------*/ + +vPortSVCHandler: + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [r3] + ldr r0, [r1] + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Clear the bit that indicates the FPU is in use in case the FPU was used + before the scheduler was started - which would otherwise result in the + unnecessary leaving of space in the SVC stack for lazy saving of FPU + registers. */ + mov r0, #0 + msr control, r0 + /* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc 0 + +/*-----------------------------------------------------------*/ + +vPortEnableVFP: + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [r0] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + + + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h new file mode 100644 index 0000000..445a2dd --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
@@ -0,0 +1,173 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ +#include <intrinsics.h> + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +#define portYIELD() \ +{ \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ +} + +#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD() +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() \ +{ \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ +} + +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not necessary for to use this port. They are defined so the common demo files +(which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in +the source code because to do so would cause other compilers to generate +warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c new file mode 100644 index 0000000..6fb38e8 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c
@@ -0,0 +1,747 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM CM4F port. + *----------------------------------------------------------*/ + +/* IAR includes. */ +#include <intrinsics.h> + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining +all the API functions to use the MPU wrappers. That should only be done when +task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#warning This is not yet a documented port as it has not been fully tested, so no demo projects that use this port are provided. + +#ifndef __ARMVFP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + /* The way the SysTick is clocked is not modified in case it is not the same + as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) ) +#define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) ) +#define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) ) +#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL ) + +/* Constants required to access and manipulate the MPU. */ +#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) ) +#define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) ) +#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ +#define portMPU_ENABLE ( 0x01UL ) +#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) +#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) +#define portMPU_REGION_VALID ( 0x10UL ) +#define portMPU_REGION_ENABLE ( 0x01UL ) +#define portPERIPHERALS_START_ADDRESS 0x40000000UL +#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7 +r0p1 port. */ +#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) ) +#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL ) +#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) +#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) +#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) +#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) + +/* Offsets in the stack to the parameters when inside the SVC handler. */ +#define portOFFSET_TO_PC ( 6 ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have +occurred while the SysTick counter is stopped during tickless idle +calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should +have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Configure a number of standard MPU regions that are used by all tasks. + */ +static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; + +/* + * Return the smallest MPU region size that a given number of bytes will fit + * into. The region size is returned as the value that should be programmed + * into the region attribute register for that region. + */ +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION; + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION; + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION; + +/* + * Turn the VFP on. + */ +extern void vPortEnableVFP( void ); + +/* + * The C portion of the SVC handler. + */ +void vPortSVCHandler_C( uint32_t *pulParam ); + +/* + * Called from the SVC handler used to start the scheduler. + */ +extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION; + +/** + * @brief Calls the port specific code to raise the privilege. + * + * @return pdFALSE if privilege was raised, pdTRUE otherwise. + */ +extern BaseType_t xPortRaisePrivilege( void ); + +/** + * @brief If xRunningPrivileged is not pdTRUE, calls the port specific + * code to reset the privilege, otherwise does nothing. + */ +extern void vPortResetPrivilege( BaseType_t xRunningPrivileged ); +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting +variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) +{ + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + if( xRunPrivileged == pdTRUE ) + { + *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED; + } + else + { + *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED; + } + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler_C( uint32_t *pulParam ) +{ +uint8_t ucSVCNumber; + + /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and + xPSR. The first argument (r0) is pulParam[ 0 ]. */ + ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ]; + switch( ucSVCNumber ) + { + case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI; + vPortRestoreContextOfFirstTask(); + break; + + case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + /* Barriers are normally not required + but do ensure the code is completely + within the specified behaviour for the + architecture. */ + __asm volatile( "dsb" ::: "memory" ); + __asm volatile( "isb" ); + + break; + + case portSVC_RAISE_PRIVILEGE : __asm volatile + ( + " mrs r1, control \n" /* Obtain current control value. */ + " bic r1, r1, #1 \n" /* Set privilege bit. */ + " msr control, r1 \n" /* Write back new control value. */ + ::: "r1", "memory" + ); + break; + + default : /* Unknown SVC call. */ + break; + } +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + /* This port can be used on all revisions of the Cortex-M7 core other than + the r0p1 parts. r0p1 parts should use the port from the + /source/portable/GCC/ARM_CM7/r0p1 directory. */ + configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); + configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + + #if( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + functions can be called. ISR safe functions are those that end in + "FromISR". FreeRTOS maintains separate thread and ISR API functions to + ensure interrupt entry is as fast and simple as possible. + + Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + priority bits matches the number of priority bits actually queried + from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + priority bits matches the number of priority bits actually queried + from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* conifgASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; + portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; + + /* Configure the regions in the MPU that are common to all tasks. */ + prvSetupMPU(); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + BaseType_t xRunningPrivileged = xPortRaisePrivilege(); + + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + vPortResetPrivilege( xRunningPrivileged ); + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ +BaseType_t xRunningPrivileged = xPortRaisePrivilege(); + + configASSERT( uxCriticalNesting ); + + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } + + vPortResetPrivilege( xRunningPrivileged ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + executes all interrupts must be unmasked. There is therefore no need to + save and then restore the interrupt mask value as its value is already + known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupMPU( void ) +{ +extern uint32_t __privileged_functions_end__[]; +extern uint32_t __FLASH_segment_start__[]; +extern uint32_t __FLASH_segment_end__[]; +extern uint32_t __privileged_data_start__[]; +extern uint32_t __privileged_data_end__[]; + + /* Check the expected MPU is present. */ + if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) + { + /* First setup the entire flash for unprivileged read only access. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portUNPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the first 16K for privileged only access (even though less + than 10K is actually being used). This is where the kernel code is + placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_FLASH_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Setup the privileged data RAM region. This is where the kernel data + is placed. */ + portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portPRIVILEGED_RAM_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) | + ( portMPU_REGION_ENABLE ); + + /* By default allow everything to access the general peripherals. The + system peripherals and registers are protected. */ + portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) | + ( portMPU_REGION_VALID ) | + ( portGENERAL_PERIPHERALS_REGION ); + + portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) | + ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) | + ( portMPU_REGION_ENABLE ); + + /* Enable the memory fault exception. */ + portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE; + + /* Enable the MPU with the background region configured. */ + portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE ); + } +} +/*-----------------------------------------------------------*/ + +static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) +{ +uint32_t ulRegionSize, ulReturnValue = 4; + + /* 32 is the smallest region size, 31 is the largest valid value for + ulReturnValue. */ + for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) + { + if( ulActualSizeInBytes <= ulRegionSize ) + { + break; + } + else + { + ulReturnValue++; + } + } + + /* Shift the code by one before returning so it can be written directly + into the the correct bit position of the attribute register. */ + return ( ulReturnValue << 1UL ); +} +/*-----------------------------------------------------------*/ + +void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) +{ +extern uint32_t __SRAM_segment_start__[]; +extern uint32_t __SRAM_segment_end__[]; +extern uint32_t __privileged_data_start__[]; +extern uint32_t __privileged_data_end__[]; +int32_t lIndex; +uint32_t ul; + + if( xRegions == NULL ) + { + /* No MPU regions are specified so allow access to all RAM. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) | + ( portMPU_REGION_ENABLE ); + + /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have + just removed the privileged only parameters. */ + xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress = + ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */ + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION + 1 ); + + xMPUSettings->xRegion[ 1 ].ulRegionAttribute = + ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) | + ( portMPU_REGION_ENABLE ); + + /* Invalidate all other regions. */ + for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID; + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + } + } + else + { + /* This function is called automatically when the task is created - in + which case the stack region parameters will be valid. At all other + times the stack parameters will not be valid and it is assumed that the + stack region has already been configured. */ + if( ulStackDepth > 0 ) + { + /* Define the region that allows access to the stack. */ + xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = + ( ( uint32_t ) pxBottomOfStack ) | + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION ); /* Region number. */ + + xMPUSettings->xRegion[ 0 ].ulRegionAttribute = + ( portMPU_REGION_READ_WRITE ) | /* Read and write. */ + ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) | + ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | + ( portMPU_REGION_ENABLE ); + } + + lIndex = 0; + + for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) + { + if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) + { + /* Translate the generic region definition contained in + xRegions into the CM3 specific MPU settings that are then + stored in xMPUSettings. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = + ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) | + ( portMPU_REGION_VALID ) | + ( portSTACK_REGION + ul ); /* Region number. */ + + xMPUSettings->xRegion[ ul ].ulRegionAttribute = + ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | + ( xRegions[ lIndex ].ulParameters ) | + ( portMPU_REGION_ENABLE ); + } + else + { + /* Invalidate the region. */ + xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID; + xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; + } + + lIndex++; + } + } +} +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + an interrupt that has been assigned a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + function. ISR safe FreeRTOS API functions must *only* be called + from interrupts that have been assigned a priority at or below + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Numerically low interrupt priority numbers represent logically high + interrupt priorities, therefore the priority of the interrupt must + be set to a value equal to or numerically *higher* than + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Interrupts that use the FreeRTOS API must not be left at their + default priority of zero as that is the highest possible priority, + which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + and therefore also guaranteed to be invalid. + + FreeRTOS maintains separate thread and ISR API functions to ensure + interrupt entry is as fast and simple as possible. + + The following links provide detailed information: + http://www.freertos.org/RTOS-Cortex-M3-M4.html + http://www.freertos.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + that define each interrupt's priority to be split between bits that + define the interrupt's pre-emption priority bits and bits that define + the interrupt's sub-priority. For simplicity all bits must be defined + to be pre-emption priority bits. The following assertion will fail if + this is not the case (if some bits represent a sub-priority). + + If the application only uses CMSIS libraries for interrupt + configuration then the correct setting can be achieved on all Cortex-M + devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + scheduler. Note however that some vendor specific peripheral libraries + assume a non-zero priority group setting, in which cases using a value + of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ + + + + + + + + + + + + + + + + + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s new file mode 100644 index 0000000..60a5e57 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s
@@ -0,0 +1,199 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include <FreeRTOSConfig.h> + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vPortSVCHandler_C + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC vPortEnableVFP + PUBLIC vPortRestoreContextOfFirstTask + PUBLIC xIsPrivileged + PUBLIC vResetPrivilege + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + mrs r1, control + stmdb r0!, {r1, r4-r11, r14} + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r0, r3} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + msr basepri, r0 + dsb + isb + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + /* Move onto the second item in the TCB... */ + add r1, r1, #4 + /* Region Base Address register. */ + ldr r2, =0xe000ed9c + /* Read 4 sets of MPU registers. */ + ldmia r1!, {r4-r11} + /* Write 4 sets of MPU registers. */ + stmia r2!, {r4-r11} + /* Pop the registers that are not automatically saved on exception entry. */ + ldmia r0!, {r3-r11, r14} + msr control, r3 + + /* Is the task using the FPU context? If so, pop the high vfp registers + too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + + bx r14 + + +/*-----------------------------------------------------------*/ + +vPortSVCHandler: + #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + #else + mrs r0, psp + #endif + b vPortSVCHandler_C + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask: + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Clear the bit that indicates the FPU is in use in case the FPU was used + before the scheduler was started - which would otherwise result in the + unnecessary leaving of space in the SVC stack for lazy saving of FPU + registers. */ + mov r0, #0 + msr control, r0 + /* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc 0 + +/*-----------------------------------------------------------*/ + +vPortRestoreContextOfFirstTask: + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Restore the context. */ + ldr r3, =pxCurrentTCB + ldr r1, [r3] + /* The first item in the TCB is the task top of stack. */ + ldr r0, [r1] + /* Move onto the second item in the TCB... */ + add r1, r1, #4 + /* Region Base Address register. */ + ldr r2, =0xe000ed9c + /* Read 4 sets of MPU registers. */ + ldmia r1!, {r4-r11} + /* Write 4 sets of MPU registers. */ + stmia r2!, {r4-r11} + /* Pop the registers that are not automatically saved on exception entry. */ + ldmia r0!, {r3-r11, r14} + msr control, r3 + /* Restore the task stack pointer. */ + msr psp, r0 + mov r0, #0 + msr basepri, r0 + bx r14 + +/*-----------------------------------------------------------*/ + +vPortEnableVFP: + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [r0] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + +/*-----------------------------------------------------------*/ + +xIsPrivileged: + mrs r0, control /* r0 = CONTROL. */ + tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */ + ite ne + movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */ + moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */ + bx lr /* Return. */ +/*-----------------------------------------------------------*/ + +vResetPrivilege: + mrs r0, control /* r0 = CONTROL. */ + orr r0, r0, #1 /* r0 = r0 | 1. */ + msr control, r0 /* CONTROL = r0. */ + bx lr /* Return to the caller. */ +/*-----------------------------------------------------------*/ + + END
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h new file mode 100644 index 0000000..493066a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -0,0 +1,228 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ +#include <intrinsics.h> + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* MPU specific constants. */ +#define portUSING_MPU_WRAPPERS 1 +#define portPRIVILEGE_BIT ( 0x80000000UL ) + +#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) +#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) +#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) +#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) +#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) + +#define portUNPRIVILEGED_FLASH_REGION ( 0UL ) +#define portPRIVILEGED_FLASH_REGION ( 1UL ) +#define portPRIVILEGED_RAM_REGION ( 2UL ) +#define portGENERAL_PERIPHERALS_REGION ( 3UL ) +#define portSTACK_REGION ( 4UL ) +#define portFIRST_CONFIGURABLE_REGION ( 5UL ) +#define portLAST_CONFIGURABLE_REGION ( 7UL ) +#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) +#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ + +#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" ) + +typedef struct MPU_REGION_REGISTERS +{ + uint32_t ulRegionBaseAddress; + uint32_t ulRegionAttribute; +} xMPU_REGION_REGISTERS; + +/* Plus 1 to create space for the stack region. */ +typedef struct MPU_SETTINGS +{ + xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ]; +} xMPU_SETTINGS; + + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* SVC numbers for various services. */ +#define portSVC_START_SCHEDULER 0 +#define portSVC_YIELD 1 +#define portSVC_RAISE_PRIVILEGE 2 + +/* Scheduler utilities. */ +#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) : "memory" ) +#define portYIELD_WITHIN_API() \ +{ \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ +} + +#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API() +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() \ +{ \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ +} + +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not necessary for to use this port. They are defined so the common demo files +(which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() +/*-----------------------------------------------------------*/ + +extern BaseType_t xIsPrivileged( void ); +extern void vResetPrivilege( void ); + +/** + * @brief Checks whether or not the processor is privileged. + * + * @return 1 if the processor is already privileged, 0 otherwise. + */ +#define portIS_PRIVILEGED() xIsPrivileged() + +/** + * @brief Raise an SVC request to raise privilege. +*/ +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); + +/** + * @brief Lowers the privilege level by setting the bit 0 of the CONTROL + * register. + */ +#define portRESET_PRIVILEGE() vResetPrivilege() +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in +the source code because to do so would cause other compilers to generate +warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt new file mode 100644 index 0000000..2116456 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt
@@ -0,0 +1,18 @@ +There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers. +The best option depends on the revision of the ARM Cortex-M7 core in use. The +revision is specified by an 'r' number, and a 'p' number, so will look something +like 'r0p1'. Check the documentation for the microcontroller in use to find the +revision of the Cortex-M7 core used in that microcontroller. If in doubt, use +the FreeRTOS port provided specifically for r0p1 revisions, as that can be used +with all core revisions. + +The first option is to use the ARM Cortex-M4F port, and the second option is to +use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround. + +If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be +used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in +the /FreeRTOS/Source/portable/IAR/ARM_CM4F directory. + +If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM +Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1 +directory. \ No newline at end of file
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c new file mode 100644 index 0000000..4b3e628 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c
@@ -0,0 +1,644 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ARM CM4F port. + *----------------------------------------------------------*/ + +/* IAR includes. */ +#include <intrinsics.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __ARMVFP__ + #error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) + #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html +#endif + +#ifndef configSYSTICK_CLOCK_HZ + #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ + /* Ensure the SysTick is clocked at the same frequency as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + /* The way the SysTick is clocked is not modified in case it is not the same + as the core. */ + #define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have +occurred while the SysTick counter is stopped during tickless idle +calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* For strict compliance with the Cortex-M spec the task start address should +have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt( void ); + +/* + * Exception handlers. + */ +void xPortSysTickHandler( void ); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +extern void vPortStartFirstTask( void ); + +/* + * Turn the VFP on. + */ +extern void vPortEnableVFP( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting +variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if( configUSE_TICKLESS_IDLE == 1 ) + static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if( configASSERT_DEFINED == 1 ) + static uint8_t ucMaxSysCallPriority = 0; + static uint32_t ulMaxPRIGROUPValue = 0; + static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Simulate the stack frame as it would be created by a context switch + interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( uxCriticalNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler( void ) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + + #if( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + functions can be called. ISR safe functions are those that end in + "FromISR". FreeRTOS maintains separate thread and ISR API functions to + ensure interrupt entry is as fast and simple as possible. + + Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= ( uint8_t ) 0x01; + } + + #ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + priority bits matches the number of priority bits actually queried + from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS ); + } + #endif + + #ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + priority bits matches the number of priority bits actually queried + from the hardware. */ + configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); + } + #endif + + /* Shift the priority group value back to its position within the AIRCR + register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } + #endif /* conifgASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; + portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( uxCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( uxCriticalNesting == 1 ) + { + configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + configASSERT( uxCriticalNesting ); + uxCriticalNesting--; + if( uxCriticalNesting == 0 ) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler( void ) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + executes all interrupts must be unmasked. There is therefore no need to + save and then restore the interrupt mask value as its value is already + known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* A context switch is required. Context switching is performed in + the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if( configUSE_TICKLESS_IDLE == 1 ) + + __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + is accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + tick periods. -1 is used because this code will execute part way + through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) ); + if( ulReloadValue > ulStoppedTimerCompensation ) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + method as that will mask interrupts that should exit sleep mode. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* If a context switch is pending or a task is waiting for the scheduler + to be unsuspended then abandon the low power entry. */ + if( eTaskConfirmSleepModeStatus() == eAbortSleep ) + { + /* Restart from whatever is left in the count register to complete + this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above __disable_interrupt() + call above. */ + __enable_interrupt(); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + set its parameter to 0 to indicate that its implementation contains + its own wait for interrupt or wait for event instruction, and so wfi + should not be executed again. However, the original expected idle + time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING( xModifiableIdleTime ); + if( xModifiableIdleTime > 0 ) + { + __DSB(); + __WFI(); + __ISB(); + } + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + out of sleep mode to execute immediately. see comments above + __disable_interrupt() call above. */ + __enable_interrupt(); + __DSB(); + __ISB(); + + /* Disable interrupts again because the clock is about to be stopped + and interrupts that execute while the clock is stopped will increase + any slippage between the time maintained by the RTOS and calendar + time. */ + __disable_interrupt(); + __DSB(); + __ISB(); + + /* Disable the SysTick clock without reading the + portNVIC_SYSTICK_CTRL_REG register to ensure the + portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + the time the SysTick is stopped for is accounted for as best it can + be, but using the tickless mode will inevitably result in some tiny + drift of the time maintained by the kernel with respect to calendar + time*/ + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT ); + + /* Determine if the SysTick clock has already counted to zero and + been set back to the current reload value (the reload back being + correct for the entire expected idle time) or if the SysTick is yet + to count to zero (in which case an interrupt other than the SysTick + must have brought the system out of sleep mode). */ + if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 ) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + reloaded with ulReloadValue. Reset the + portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + period. */ + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG ); + + /* Don't allow a tiny value, or values that have somehow + underflowed because the post sleep hook did something + that took too long. */ + if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) ) + { + ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + function exits, the tick value maintained by the tick is stepped + forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + Work out how long the sleep lasted rounded to complete tick + periods (not the ulReload value which accounted for part + ticks). */ + ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + period remains. */ + portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick( ulCompleteTickPeriods ); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrpts enabled. */ + __enable_interrupt(); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__weak void vPortSetupTimerInterrupt( void ) +{ + /* Calculate the constants required to configure the tick interrupt. */ + #if( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); + } + #endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); +} +/*-----------------------------------------------------------*/ + +#if( configASSERT_DEFINED == 1 ) + + void vPortValidateInterruptPriority( void ) + { + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); + + /* Is the interrupt number a user defined interrupt? */ + if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + an interrupt that has been assigned a priority above + configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + function. ISR safe FreeRTOS API functions must *only* be called + from interrupts that have been assigned a priority at or below + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Numerically low interrupt priority numbers represent logically high + interrupt priorities, therefore the priority of the interrupt must + be set to a value equal to or numerically *higher* than + configMAX_SYSCALL_INTERRUPT_PRIORITY. + + Interrupts that use the FreeRTOS API must not be left at their + default priority of zero as that is the highest possible priority, + which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + and therefore also guaranteed to be invalid. + + FreeRTOS maintains separate thread and ISR API functions to ensure + interrupt entry is as fast and simple as possible. + + The following links provide detailed information: + http://www.freertos.org/RTOS-Cortex-M3-M4.html + http://www.freertos.org/FAQHelp.html */ + configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + that define each interrupt's priority to be split between bits that + define the interrupt's pre-emption priority bits and bits that define + the interrupt's sub-priority. For simplicity all bits must be defined + to be pre-emption priority bits. The following assertion will fail if + this is not the case (if some bits represent a sub-priority). + + If the application only uses CMSIS libraries for interrupt + configuration then the correct setting can be achieved on all Cortex-M + devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + scheduler. Note however that some vendor specific peripheral libraries + assume a non-zero priority group setting, in which cases using a value + of zero will result in unpredictable behaviour. */ + configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); + } + +#endif /* configASSERT_DEFINED */ + + + + + + + + + + + + + + + + + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s new file mode 100644 index 0000000..37ac1a7 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
@@ -0,0 +1,151 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include <FreeRTOSConfig.h> + + RSEG CODE:CODE(2) + thumb + + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + + PUBLIC xPortPendSVHandler + PUBLIC vPortSVCHandler + PUBLIC vPortStartFirstTask + PUBLIC vPortEnableVFP + + +/*-----------------------------------------------------------*/ + +xPortPendSVHandler: + mrs r0, psp + isb + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r2, [r3] + + /* Is the task using the FPU context? If so, push high vfp registers. */ + tst r14, #0x10 + it eq + vstmdbeq r0!, {s16-s31} + + /* Save the core registers. */ + stmdb r0!, {r4-r11, r14} + + /* Save the new top of stack into the first member of the TCB. */ + str r0, [r2] + + stmdb sp!, {r0, r3} + mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY + cpsid i + msr basepri, r0 + dsb + isb + cpsie i + bl vTaskSwitchContext + mov r0, #0 + msr basepri, r0 + ldmia sp!, {r0, r3} + + /* The first item in pxCurrentTCB is the task top of stack. */ + ldr r1, [r3] + ldr r0, [r1] + + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + + /* Is the task using the FPU context? If so, pop the high vfp registers + too. */ + tst r14, #0x10 + it eq + vldmiaeq r0!, {s16-s31} + + msr psp, r0 + isb + #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */ + #if WORKAROUND_PMU_CM001 == 1 + push { r14 } + pop { pc } + #endif + #endif + + bx r14 + + +/*-----------------------------------------------------------*/ + +vPortSVCHandler: + /* Get the location of the current TCB. */ + ldr r3, =pxCurrentTCB + ldr r1, [r3] + ldr r0, [r1] + /* Pop the core registers. */ + ldmia r0!, {r4-r11, r14} + msr psp, r0 + isb + mov r0, #0 + msr basepri, r0 + bx r14 + +/*-----------------------------------------------------------*/ + +vPortStartFirstTask + /* Use the NVIC offset register to locate the stack. */ + ldr r0, =0xE000ED08 + ldr r0, [r0] + ldr r0, [r0] + /* Set the msp back to the start of the stack. */ + msr msp, r0 + /* Clear the bit that indicates the FPU is in use in case the FPU was used + before the scheduler was started - which would otherwise result in the + unnecessary leaving of space in the SVC stack for lazy saving of FPU + registers. */ + mov r0, #0 + msr control, r0 + /* Call SVC to start the first task. */ + cpsie i + cpsie f + dsb + isb + svc 0 + +/*-----------------------------------------------------------*/ + +vPortEnableVFP: + /* The FPU enable bits are in the CPACR. */ + ldr.w r0, =0xE000ED88 + ldr r1, [r0] + + /* Enable CP10 and CP11 coprocessors, then save back. */ + orr r1, r1, #( 0xf << 20 ) + str r1, [r0] + bx r14 + + + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h new file mode 100644 index 0000000..cce737e --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -0,0 +1,176 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* IAR includes. */ +#include <intrinsics.h> + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +#define portYIELD() \ +{ \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + __DSB(); \ + __ISB(); \ +} + +#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD() +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() \ +{ \ + /* Errata work around. */ \ + __disable_interrupt(); \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + __enable_interrupt(); \ +} + +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __set_BASEPRI( x ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not necessary for to use this port. They are defined so the common demo files +(which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/*-----------------------------------------------------------*/ + +#ifdef configASSERT + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +/*-----------------------------------------------------------*/ + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in +the source code because to do so would cause other compilers to generate +warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c new file mode 100644 index 0000000..85ce365 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c
@@ -0,0 +1,316 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include <stdlib.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + /* Check the configuration. */ + #if( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#ifndef configSETUP_TICK_INTERRUPT + #error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt. +#endif + +#ifndef configCLEAR_TICK_INTERRUPT + #error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt. +#endif + +/* A critical section is exited when the critical section nesting count reaches +this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Tasks are not created with a floating point context, but can be given a +floating point context after they have been created. A variable is stored as +part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task +does not have an FPU context, or any other value if the task does have an FPU +context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + +/* Constants required to setup the initial task context. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) + +/* Masks all bits in the APSR other than the mode bits. */ +#define portAPSR_MODE_BITS_MASK ( 0x1F ) + +/* The value of the mode bits in the APSR when the CPU is executing in user +mode. */ +#define portAPSR_USER_MODE ( 0x10 ) + +/* Let the user override the pre-loading of the initial LR with the address of +prvTaskExitError() in case it messes up unwinding of the stack in the +debugger. */ +#ifdef configTASK_RETURN_ADDRESS + #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else + #define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/*-----------------------------------------------------------*/ + +/* + * Starts the first task executing. This function is necessarily written in + * assembly code so is implemented in portASM.s. + */ +extern void vPortRestoreTaskContext( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* A variable is used to keep track of the critical section nesting. This +variable has to be stored as part of the task context and must be initialised to +a non zero value to ensure interrupts don't inadvertently become unmasked before +the scheduler starts. As it is stored as part of the task context it will +automatically be set to 0 when the first task is started. */ +volatile uint32_t ulCriticalNesting = 9999UL; + +/* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then +a floating point context must be saved and restored for the task. */ +volatile uint32_t ulPortTaskHasFPUContext = pdFALSE; + +/* Set to 1 to pend a context switch from an ISR. */ +volatile uint32_t ulPortYieldRequired = pdFALSE; + +/* Counts the interrupt nesting depth. A context switch is only performed if +if the nesting depth is 0. */ +volatile uint32_t ulPortInterruptNesting = 0UL; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. + + The fist real value on the stack is the status register, which is set for + system mode, with interrupts enabled. A few NULLs are added first to ensure + GDB does not try decoding a non-existent return address. */ + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) NULL; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL ) + { + /* The task will start in THUMB mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Next the return address, which in this case is the start of the task. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + + /* Next all the registers other than the stack pointer. */ + *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The task will start with a critical nesting count of 0 as interrupts are + enabled. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + pxTopOfStack--; + + /* The task will start without a floating point context. A task that uses + the floating point hardware must call vPortTaskUsesFPU() before executing + any floating point instructions. */ + *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( ulPortInterruptNesting == ~0UL ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +uint32_t ulAPSR; + + /* Only continue if the CPU is not in User mode. The CPU must be in a + Privileged mode for the scheduler to start. */ + __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; + configASSERT( ulAPSR != portAPSR_USER_MODE ); + + if( ulAPSR != portAPSR_USER_MODE ) + { + /* Start the timer that generates the tick ISR. */ + portDISABLE_INTERRUPTS(); + configSETUP_TICK_INTERRUPT(); + + /* Start the first task executing. */ + vPortRestoreTaskContext(); + } + + /* Will only get here if vTaskStartScheduler() was called with the CPU in + a non-privileged mode or the binary point register was not set to its lowest + possible value. prvTaskExitError() is referenced to prevent a compiler + warning about it being defined but not referenced in the case that the user + defines their own exit address. */ + ( void ) prvTaskExitError; + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( ulCriticalNesting == 1000UL ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + assert() if it is being called from an interrupt context. Only API + functions that end in "FromISR" can be used in an interrupt. Only assert if + the critical nesting count is 1 to protect against recursive calls if the + assert function also uses a critical section. */ + if( ulCriticalNesting == 1 ) + { + configASSERT( ulPortInterruptNesting == 0 ); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as the critical section is being + exited. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then all interrupt + priorities must be re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Critical nesting has reached zero so all interrupt priorities + should be unmasked. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +void FreeRTOS_Tick_Handler( void ) +{ +uint32_t ulInterruptStatus; + + ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + + /* Increment the RTOS tick. */ + if( xTaskIncrementTick() != pdFALSE ) + { + ulPortYieldRequired = pdTRUE; + } + + portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus ); + + configCLEAR_TICK_INTERRUPT(); +} +/*-----------------------------------------------------------*/ + +void vPortTaskUsesFPU( void ) +{ +uint32_t ulInitialFPSCR = 0; + + /* A task is registering the fact that it needs an FPU context. Set the + FPU flag (which is saved as part of the task context). */ + ulPortTaskHasFPUContext = pdTRUE; + + /* Initialise the floating point status register. */ + __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); +} +/*-----------------------------------------------------------*/ + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s new file mode 100644 index 0000000..5c9add7 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s
@@ -0,0 +1,247 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + +#include "FreeRTOSConfig.h" + + SECTION .text:CODE:ROOT(2) + arm + + /* Variables and functions. */ + EXTERN pxCurrentTCB + EXTERN vTaskSwitchContext + EXTERN vApplicationIRQHandler + EXTERN ulPortInterruptNesting + EXTERN ulPortTaskHasFPUContext + EXTERN ulPortYieldRequired + EXTERN ulCriticalNesting + + PUBLIC FreeRTOS_IRQ_Handler + PUBLIC FreeRTOS_SVC_Handler + PUBLIC vPortRestoreTaskContext + +SYS_MODE EQU 0x1f +SVC_MODE EQU 0x13 +IRQ_MODE EQU 0x12 + +portSAVE_CONTEXT MACRO + + /* Save the LR and SPSR onto the system mode stack before switching to + system mode to save the remaining system mode registers. */ + SRSDB sp!, #SYS_MODE + CPS #SYS_MODE + PUSH {R0-R12, R14} + + /* Push the critical nesting count. */ + LDR R2, =ulCriticalNesting + LDR R1, [R2] + PUSH {R1} + + /* Does the task have a floating point context that needs saving? If + ulPortTaskHasFPUContext is 0 then no. */ + LDR R2, =ulPortTaskHasFPUContext + LDR R3, [R2] + CMP R3, #0 + + /* Save the floating point context, if any. */ + FMRXNE R1, FPSCR + VPUSHNE {D0-D15} +#if configFPU_D32 == 1 + VPUSHNE {D16-D31} +#endif /* configFPU_D32 */ + PUSHNE {R1} + + /* Save ulPortTaskHasFPUContext itself. */ + PUSH {R3} + + /* Save the stack pointer in the TCB. */ + LDR R0, =pxCurrentTCB + LDR R1, [R0] + STR SP, [R1] + + ENDM + +; /**********************************************************************/ + +portRESTORE_CONTEXT MACRO + + /* Set the SP to point to the stack of the task being restored. */ + LDR R0, =pxCurrentTCB + LDR R1, [R0] + LDR SP, [R1] + + /* Is there a floating point context to restore? If the restored + ulPortTaskHasFPUContext is zero then no. */ + LDR R0, =ulPortTaskHasFPUContext + POP {R1} + STR R1, [R0] + CMP R1, #0 + + /* Restore the floating point context, if any. */ + POPNE {R0} +#if configFPU_D32 == 1 + VPOPNE {D16-D31} +#endif /* configFPU_D32 */ + VPOPNE {D0-D15} + VMSRNE FPSCR, R0 + + /* Restore the critical section nesting depth. */ + LDR R0, =ulCriticalNesting + POP {R1} + STR R1, [R0] + + /* Restore all system mode registers other than the SP (which is already + being used). */ + POP {R0-R12, R14} + + /* Return to the task code, loading CPSR on the way. */ + RFEIA sp! + + ENDM + + + + +/****************************************************************************** + * SVC handler is used to yield. + *****************************************************************************/ +FreeRTOS_SVC_Handler: + /* Save the context of the current task and select a new task to run. */ + portSAVE_CONTEXT + LDR R0, =vTaskSwitchContext + BLX R0 + portRESTORE_CONTEXT + + +/****************************************************************************** + * vPortRestoreTaskContext is used to start the scheduler. + *****************************************************************************/ +vPortRestoreTaskContext: + /* Switch to system mode. */ + CPS #SYS_MODE + portRESTORE_CONTEXT + +FreeRTOS_IRQ_Handler: + /* Return to the interrupted instruction. */ + SUB lr, lr, #4 + + /* Push the return address and SPSR. */ + PUSH {lr} + MRS lr, SPSR + PUSH {lr} + + /* Change to supervisor mode to allow reentry. */ + CPS #SVC_MODE + + /* Push used registers. */ + PUSH {r0-r3, r12} + + /* Increment nesting count. r3 holds the address of ulPortInterruptNesting + for future use. r1 holds the original ulPortInterruptNesting value for + future use. */ + LDR r3, =ulPortInterruptNesting + LDR r1, [r3] + ADD r0, r1, #1 + STR r0, [r3] + + /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for + future use. */ + MOV r0, sp + AND r2, r0, #4 + SUB sp, sp, r2 + + /* Call the interrupt handler. */ + PUSH {r0-r3, lr} + LDR r1, =vApplicationIRQHandler + BLX r1 + POP {r0-r3, lr} + ADD sp, sp, r2 + + CPSID i + DSB + ISB + + /* Write to the EOI register. */ + LDR r2, =configEOI_ADDRESS + STR r0, [r2] + + /* Restore the old nesting count. */ + STR r1, [r3] + + /* A context switch is never performed if the nesting count is not 0. */ + CMP r1, #0 + BNE exit_without_switch + + /* Did the interrupt request a context switch? r1 holds the address of + ulPortYieldRequired and r0 the value of ulPortYieldRequired for future + use. */ + LDR r1, =ulPortYieldRequired + LDR r0, [r1] + CMP r0, #0 + BNE switch_before_exit + +exit_without_switch: + /* No context switch. Restore used registers, LR_irq and SPSR before + returning. */ + POP {r0-r3, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + MOVS PC, LR + +switch_before_exit: + /* A context swtich is to be performed. Clear the context switch pending + flag. */ + MOV r0, #0 + STR r0, [r1] + + /* Restore used registers, LR-irq and SPSR before saving the context + to the task stack. */ + POP {r0-r3, r12} + CPS #IRQ_MODE + POP {LR} + MSR SPSR_cxsf, LR + POP {LR} + portSAVE_CONTEXT + + /* Call the function that selects the new task to execute. + vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD + instructions, or 8 byte aligned stack allocated data. LR does not need + saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */ + LDR R0, =vTaskSwitchContext + BLX R0 + + /* Restore the context of, and branch to, the task selected to execute + next. */ + portRESTORE_CONTEXT + + END + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h new file mode 100644 index 0000000..b6c075c --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h
@@ -0,0 +1,181 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include <intrinsics.h> + +#ifdef __cplusplus + extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do +not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 + +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* Called at the end of an ISR that can cause a context switch. */ +#define portEND_SWITCHING_ISR( xSwitchRequired )\ +{ \ +extern volatile uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ +} + +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() __asm volatile ( "SWI 0 \n" \ + "ISB " ); + + +/*----------------------------------------------------------- + * Critical section control + *----------------------------------------------------------*/ + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +extern uint32_t ulPortSetInterruptMask( void ); +extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); +extern void vPortInstallFreeRTOSVectorTable( void ); + +/* The I bit within the CPSR. */ +#define portINTERRUPT_ENABLE_BIT ( 1 << 7 ) + +/* In the absence of a priority mask register, these functions and macros +globally enable and disable interrupts. */ +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); +#define portENABLE_INTERRUPTS() __asm volatile ( "CPSIE i \n" ); +#define portDISABLE_INTERRUPTS() __asm volatile ( "CPSID i \n" \ + "DSB \n" \ + "ISB " ); +#pragma inline +static inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void ) +{ +volatile uint32_t ulCPSR; + + __asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) ); + ulCPSR &= portINTERRUPT_ENABLE_BIT; + portDISABLE_INTERRUPTS(); + return ulCPSR; +} + +#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) if( x == 0 ) portENABLE_INTERRUPTS() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are +not required for this port but included in case common demo code that uses these +macros is used. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prototype of the FreeRTOS tick handler. This must be installed as the +handler for whichever peripheral is used to generate the RTOS tick. */ +void FreeRTOS_Tick_Handler( void ); + +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() +before any floating point instructions are executed. */ +void vPortTaskUsesFPU( void ); +#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + +#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) +#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + + /* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + + /*-----------------------------------------------------------*/ + + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +#define portNOP() __asm volatile( "NOP" ) +#define portINLINE inline + +/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in +the source code because to do so would cause other compilers to generate +warnings. */ +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus + } /* extern C */ +#endif + + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ATMega323/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ATMega323/port.c new file mode 100644 index 0000000..0914f40 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ATMega323/port.c
@@ -0,0 +1,339 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include <stdlib.h> + +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the AVR/IAR port. + *----------------------------------------------------------*/ + +/* Start tasks with interrupts enables. */ +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 ) + +/* Hardware constants for timer 1. */ +#define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) 0x08 ) +#define portPRESCALE_64 ( ( uint8_t ) 0x03 ) +#define portCLOCK_PRESCALER ( ( uint32_t ) 64 ) +#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) 0x10 ) + +/* The number of bytes used on the hardware stack by the task start address. */ +#define portBYTES_USED_BY_RETURN_ADDRESS ( 2 ) +/*-----------------------------------------------------------*/ + +/* Stores the critical section nesting. This must not be initialised to 0. +It will be initialised when a task starts. */ +#define portNO_CRITICAL_NESTING ( ( UBaseType_t ) 0 ) +UBaseType_t uxCriticalNesting = 0x50; + + +/* + * Perform hardware setup to enable ticks from timer 1, compare match A. + */ +static void prvSetupTimerInterrupt( void ); + +/* + * The IAR compiler does not have full support for inline assembler, so + * these are defined in the portmacro assembler file. + */ +extern void vPortYieldFromTick( void ); +extern void vPortStart( void ); + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint16_t usAddress; +StackType_t *pxTopOfHardwareStack; + + /* Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging. */ + + *pxTopOfStack = 0x11; + pxTopOfStack--; + *pxTopOfStack = 0x22; + pxTopOfStack--; + *pxTopOfStack = 0x33; + pxTopOfStack--; + + /* Remember where the top of the hardware stack is - this is required + below. */ + pxTopOfHardwareStack = pxTopOfStack; + + + /* Simulate how the stack would look after a call to vPortYield(). */ + + /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */ + + + + /* The IAR compiler requires two stacks per task. First there is the + hardware call stack which uses the AVR stack pointer. Second there is the + software stack (local variables, parameter passing, etc.) which uses the + AVR Y register. + + This function places both stacks within the memory block passed in as the + first parameter. The hardware stack is placed at the bottom of the memory + block. A gap is then left for the hardware stack to grow. Next the software + stack is placed. The amount of space between the software and hardware + stacks is defined by configCALL_STACK_SIZE. + + + + The first part of the stack is the hardware stack. Place the start + address of the task on the hardware stack. */ + usAddress = ( uint16_t ) pxCode; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + + /* Leave enough space for the hardware stack before starting the software + stack. The '- 2' is because we have already used two spaces for the + address of the start of the task. */ + pxTopOfStack -= ( configCALL_STACK_SIZE - 2 ); + + + + /* Next simulate the stack as if after a call to portSAVE_CONTEXT(). + portSAVE_CONTEXT places the flags on the stack immediately after r0 + to ensure the interrupts get disabled as soon as possible, and so ensuring + the stack use is minimal should a context switch interrupt occur. */ + *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */ + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next place the address of the hardware stack. This is required so + the AVR stack pointer can be restored to point to the hardware stack. */ + pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS; + usAddress = ( uint16_t ) pxTopOfHardwareStack; + + /* SPL */ + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + /* SPH */ + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + + + + /* Now the remaining registers. */ + *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */ + pxTopOfStack--; + + /* Place the parameter on the stack in the expected location. */ + usAddress = ( uint16_t ) pvParameters; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + usAddress >>= 8; + *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff ); + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */ + pxTopOfStack--; + + /* The Y register is not stored as it is used as the software stack and + gets saved into the task control block. */ + + *pxTopOfStack = ( StackType_t ) 0x30; /* R30 Z */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */ + + pxTopOfStack--; + *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */ + + /*lint +e950 +e611 +e923 */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. + Normally we would just call portRESTORE_CONTEXT() here, but as the IAR + compiler does not fully support inline assembler we have to make a call.*/ + vPortStart(); + + /* Should not get here! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Setup timer 1 compare match A to generate a tick interrupt. + */ +static void prvSetupTimerInterrupt( void ) +{ +uint32_t ulCompareMatch; +uint8_t ucHighByte, ucLowByte; + + /* Using 16bit timer 1 to generate the tick. Correct fuses must be + selected for the configCPU_CLOCK_HZ clock. */ + + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* We only have 16 bits so have to scale to get our required tick rate. */ + ulCompareMatch /= portCLOCK_PRESCALER; + + /* Adjust for correct value. */ + ulCompareMatch -= ( uint32_t ) 1; + + /* Setup compare match value for compare match A. Interrupts are disabled + before this is called so we need not worry here. */ + ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + ulCompareMatch >>= 8; + ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff ); + OCR1AH = ucHighByte; + OCR1AL = ucLowByte; + + /* Setup clock source and compare match behaviour. */ + ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64; + TCCR1B = ucLowByte; + + /* Enable the interrupt - this is okay as interrupt are currently globally + disabled. */ + TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE; +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 1 + + /* + * Tick ISR for preemptive scheduler. We can use a __task attribute as + * the context is saved at the start of vPortYieldFromTick(). The tick + * count is incremented after the context is saved. + */ + __task void SIG_OUTPUT_COMPARE1A( void ) + { + vPortYieldFromTick(); + asm( "reti" ); + } + +#else + + /* + * Tick ISR for the cooperative scheduler. All this does is increment the + * tick count. We don't need to switch context, this can only be done by + * manual calls to taskYIELD(); + * + * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90. DO NOT INSTALL + * IT HERE USING THE USUAL PRAGMA. + */ + __interrupt void SIG_OUTPUT_COMPARE1A( void ) + { + xTaskIncrementTick(); + } +#endif +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + uxCriticalNesting--; + if( uxCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } +} + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h new file mode 100644 index 0000000..20acd2c --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h
@@ -0,0 +1,112 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* +Changes from V1.2.3 + + + portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it + base 16. +*/ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint8_t +#define portBASE_TYPE char +#define portPOINTER_SIZE_TYPE uint16_t + +typedef portSTACK_TYPE StackType_t; +typedef signed char BaseType_t; +typedef unsigned char UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() asm( "cli" ) +#define portENABLE_INTERRUPTS() asm( "sei" ) +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 1 +#define portNOP() asm( "nop" ) +/*-----------------------------------------------------------*/ + +/* Kernel utilities. */ +void vPortYield( void ); +#define portYIELD() vPortYield() + +#ifdef IAR_MEGA_AVR + #define outb( PORT, VALUE ) PORT = VALUE +#endif +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90 new file mode 100644 index 0000000..6e33f48 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90
@@ -0,0 +1,245 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + +#include <iom323.h> + +; Declare all extern symbols here - including any ISRs that are referenced in +; the vector table. + +; ISR functions +; ------------- +EXTERN SIG_OUTPUT_COMPARE1A +EXTERN SIG_UART_RECV +EXTERN SIG_UART_DATA + + +; Functions used by scheduler +; --------------------------- +EXTERN vTaskSwitchContext +EXTERN pxCurrentTCB +EXTERN xTaskIncrementTick +EXTERN uxCriticalNesting + +; Functions implemented in this file +; ---------------------------------- +PUBLIC vPortYield +PUBLIC vPortYieldFromTick +PUBLIC vPortStart + + +; Interrupt vector table. +; ----------------------- +; +; For simplicity the RTOS tick interrupt routine uses the __task keyword. +; As the IAR compiler does not permit a function to be declared using both +; __task and __interrupt, the use of __task necessitates that the interrupt +; vector table be setup manually. +; +; To write an ISR, implement the ISR function using the __interrupt keyword +; but do not install the interrupt using the "#pragma vector=ABC" method. +; Instead manually place the name of the ISR in the vector table using an +; ORG and jmp instruction as demonstrated below. +; You will also have to add an EXTERN statement at the top of the file. + + ASEG + + + ORG TIMER1_COMPA_vect ; Vector address + jmp SIG_OUTPUT_COMPARE1A ; ISR + + ORG USART_RXC_vect ; Vector address + jmp SIG_UART_RECV ; ISR + + ORG USART_UDRE_vect ; Vector address + jmp SIG_UART_DATA ; ISR + + + RSEG CODE + + + +; Saving and Restoring a Task Context and Task Switching +; ------------------------------------------------------ +; +; The IAR compiler does not fully support inline assembler, so saving and +; restoring a task context has to be written in an asm file. +; +; vPortYield() and vPortYieldFromTick() are usually written in C. Doing +; so in this case would required calls to be made to portSAVE_CONTEXT() and +; portRESTORE_CONTEXT(). This is dis-advantageous as the context switch +; function would require two extra jump and return instructions over the +; WinAVR equivalent. +; +; To avoid this I have opted to implement both vPortYield() and +; vPortYieldFromTick() in this assembly file. For convenience +; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros. + +portSAVE_CONTEXT MACRO + st -y, r0 ; First save the r0 register - we need to use this. + in r0, SREG ; Obtain the SREG value so we can disable interrupts... + cli ; ... as soon as possible. + st -y, r0 ; Store the SREG as it was before we disabled interrupts. + + in r0, SPL ; Next store the hardware stack pointer. The IAR... + st -y, r0 ; ... compiler uses the hardware stack as a call stack ... + in r0, SPH ; ... only. + st -y, r0 + + st -y, r1 ; Now store the rest of the registers. Dont store the ... + st -y, r2 ; ... the Y register here as it is used as the software + st -y, r3 ; stack pointer and will get saved into the TCB. + st -y, r4 + st -y, r5 + st -y, r6 + st -y, r7 + st -y, r8 + st -y, r9 + st -y, r10 + st -y, r11 + st -y, r12 + st -y, r13 + st -y, r14 + st -y, r15 + st -y, r16 + st -y, r17 + st -y, r18 + st -y, r19 + st -y, r20 + st -y, r21 + st -y, r22 + st -y, r23 + st -y, r24 + st -y, r25 + st -y, r26 + st -y, r27 + st -y, r30 + st -y, r31 + lds r0, uxCriticalNesting + st -y, r0 ; Store the critical nesting counter. + + lds r26, pxCurrentTCB ; Finally save the software stack pointer (Y ... + lds r27, pxCurrentTCB + 1 ; ... register) into the TCB. + st x+, r28 + st x+, r29 + + ENDM + + +portRESTORE_CONTEXT MACRO + lds r26, pxCurrentTCB + lds r27, pxCurrentTCB + 1 ; Restore the software stack pointer from ... + ld r28, x+ ; the TCB into the software stack pointer (... + ld r29, x+ ; ... the Y register). + + ld r0, y+ + sts uxCriticalNesting, r0 + ld r31, y+ ; Restore the registers down to R0. The Y + ld r30, y+ ; register is missing from this list as it + ld r27, y+ ; has already been restored. + ld r26, y+ + ld r25, y+ + ld r24, y+ + ld r23, y+ + ld r22, y+ + ld r21, y+ + ld r20, y+ + ld r19, y+ + ld r18, y+ + ld r17, y+ + ld r16, y+ + ld r15, y+ + ld r14, y+ + ld r13, y+ + ld r12, y+ + ld r11, y+ + ld r10, y+ + ld r9, y+ + ld r8, y+ + ld r7, y+ + ld r6, y+ + ld r5, y+ + ld r4, y+ + ld r3, y+ + ld r2, y+ + ld r1, y+ + + ld r0, y+ ; The next thing on the stack is the ... + out SPH, r0 ; ... hardware stack pointer. + ld r0, y+ + out SPL, r0 + + ld r0, y+ ; Next there is the SREG register. + out SREG, r0 + + ld r0, y+ ; Finally we have finished with r0, so restore r0. + + ENDM + + + +; vPortYield() and vPortYieldFromTick() +; ------------------------------------- +; +; Manual and preemptive context switch functions respectively. +; The IAR compiler does not fully support inline assembler, +; so these are implemented here rather than the more usually +; place of within port.c. + +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +vPortYieldFromTick: + portSAVE_CONTEXT ; Save the context of the current task. + call xTaskIncrementTick ; Call the timer tick function. + tst r16 + breq SkipTaskSwitch + call vTaskSwitchContext ; Call the scheduler. +SkipTaskSwitch: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ret ; ... scheduler decided should run. + +; vPortStart() +; ------------ +; +; Again due to the lack of inline assembler, this is required +; to get access to the portRESTORE_CONTEXT macro. + +vPortStart: + portRESTORE_CONTEXT + ret + + +; Just a filler for unused interrupt vectors. +vNoISR: + reti + + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82 new file mode 100644 index 0000000..2df712c --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82
@@ -0,0 +1,310 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Exception and interrupt vectors. + * + * This file maps all events supported by an AVR32UC. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32UC devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include <avr32/io.h> +#include "intc.h" + + +//! @{ +//! \verbatim + + +// Start of Exception Vector Table. + + // EVBA must be aligned with a power of two strictly greater than the EVBA- + // relative offset of the last vector. + COMMON EVTAB:CODE:ROOT(9) + + + // Force EVBA initialization. + EXTERN ??init_EVBA + REQUIRE ??init_EVBA + + // Export symbol. + PUBLIC ??EVBA + PUBLIC _evba +??EVBA: +_evba: + + ORG 0x000 + // Unrecoverable Exception. +_handle_Unrecoverable_Exception: + rjmp $ + + ORG 0x004 + // TLB Multiple Hit: UNUSED IN AVR32UC. +_handle_TLB_Multiple_Hit: + rjmp $ + + ORG 0x008 + // Bus Error Data Fetch. +_handle_Bus_Error_Data_Fetch: + rjmp $ + + ORG 0x00C + // Bus Error Instruction Fetch. +_handle_Bus_Error_Instruction_Fetch: + rjmp $ + + ORG 0x010 + // NMI. +_handle_NMI: + rjmp $ + + ORG 0x014 + // Instruction Address. +_handle_Instruction_Address: + rjmp $ + + ORG 0x018 + // ITLB Protection. +_handle_ITLB_Protection: + rjmp $ + + ORG 0x01C + // Breakpoint. +_handle_Breakpoint: + rjmp $ + + ORG 0x020 + // Illegal Opcode. +_handle_Illegal_Opcode: + rjmp $ + + ORG 0x024 + // Unimplemented Instruction. +_handle_Unimplemented_Instruction: + rjmp $ + + ORG 0x028 + // Privilege Violation. +_handle_Privilege_Violation: + rjmp $ + + ORG 0x02C + // Floating-Point: UNUSED IN AVR32UC. +_handle_Floating_Point: + rjmp $ + + ORG 0x030 + // Coprocessor Absent: UNUSED IN AVR32UC. +_handle_Coprocessor_Absent: + rjmp $ + + ORG 0x034 + // Data Address (Read). +_handle_Data_Address_Read: + rjmp $ + + ORG 0x038 + // Data Address (Write). +_handle_Data_Address_Write: + rjmp $ + + ORG 0x03C + // DTLB Protection (Read). +_handle_DTLB_Protection_Read: + rjmp $ + + ORG 0x040 + // DTLB Protection (Write). +_handle_DTLB_Protection_Write: + rjmp $ + + ORG 0x044 + // DTLB Modified: UNUSED IN AVR32UC. +_handle_DTLB_Modified: + rjmp $ + + ORG 0x050 + // ITLB Miss: UNUSED IN AVR32UC. +_handle_ITLB_Miss: + rjmp $ + + ORG 0x060 + // DTLB Miss (Read): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Read: + rjmp $ + + ORG 0x070 + // DTLB Miss (Write): UNUSED IN AVR32UC. +_handle_DTLB_Miss_Write: + rjmp $ + + ORG 0x100 + // Supervisor Call. +_handle_Supervisor_Call: + lddpc pc, __SCALLYield + + +// Interrupt support. +// The interrupt controller must provide the offset address relative to EVBA. +// Important note: +// All interrupts call a C function named _get_interrupt_handler. +// This function will read group and interrupt line number to then return in +// R12 a pointer to a user-provided interrupt handler. + + ALIGN 2 + +_int0: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int0_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int0_normal: +#endif + mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int1: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int1_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int1_normal: +#endif + mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int2: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int2_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int2_normal: +#endif + mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + +_int3: + // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the + // CPU upon interrupt entry. +#if 1 // B1832: interrupt stack changed to exception stack if exception is detected. + mfsr r12, AVR32_SR + bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE + cp.w r12, 110b + brlo _int3_normal + lddsp r12, sp[0 * 4] + stdsp sp[6 * 4], r12 + lddsp r12, sp[1 * 4] + stdsp sp[7 * 4], r12 + lddsp r12, sp[3 * 4] + sub sp, -6 * 4 + rete +_int3_normal: +#endif + mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function. + mcall __get_interrupt_handler + cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function. + movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler. + rete // If this was a spurious interrupt (R12 == NULL), return from event handler. + + +// Constant data area. + + ALIGN 2 + + // Import symbols. + EXTERN SCALLYield + EXTERN _get_interrupt_handler +__SCALLYield: + DC32 SCALLYield +__get_interrupt_handler: + DC32 _get_interrupt_handler + + // Values to store in the interrupt priority registers for the various interrupt priority levels. + // The interrupt priority registers contain the interrupt priority level and + // the EVBA-relative interrupt vector offset. + PUBLIC ipr_val +ipr_val: + DC32 (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\ + (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\ + (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\ + (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba) + + + END + + +//! \endverbatim +//! @}
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c new file mode 100644 index 0000000..61f941e --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c
@@ -0,0 +1,406 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS port source for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* AVR32 UC3 includes. */ +#include <avr32/io.h> +#include <intrinsics.h> +#include "gpio.h" + +#if configDBG + #include "usart.h" +#endif + +#if( configTICK_USE_TC==1 ) + #include "tc.h" +#endif + + +/* Constants required to setup the task context. */ +#define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */ +#define portINSTRUCTION_SIZE ( ( StackType_t ) 0 ) + +/* Each task maintains its own critical nesting variable. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) +volatile uint32_t ulCriticalNesting = 9999UL; + +#if( configTICK_USE_TC==0 ) + static void prvScheduleNextTick( void ); +#else + static void prvClearTcInt( void ); +#endif + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ + +/* + * Low-level initialization routine called during startup, before the main + * function. + */ +int __low_level_init(void) +{ + #if configHEAP_INIT + #pragma segment = "HEAP" + BaseType_t *pxMem; + #endif + + /* Enable exceptions. */ + ENABLE_ALL_EXCEPTIONS(); + + /* Initialize interrupt handling. */ + INTC_init_interrupts(); + + #if configHEAP_INIT + { + /* Initialize the heap used by malloc. */ + for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); ) + { + *pxMem++ = 0xA5A5A5A5; + } + } + #endif + + /* Code section present if and only if the debug trace is activated. */ + #if configDBG + { + static const gpio_map_t DBG_USART_GPIO_MAP = + { + { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION }, + { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION } + }; + + static const usart_options_t DBG_USART_OPTIONS = + { + .baudrate = configDBG_USART_BAUDRATE, + .charlength = 8, + .paritytype = USART_NO_PARITY, + .stopbits = USART_1_STOPBIT, + .channelmode = USART_NORMAL_CHMODE + }; + + /* Initialize the USART used for the debug trace with the configured parameters. */ + extern volatile avr32_usart_t *volatile stdio_usart_base; + stdio_usart_base = configDBG_USART; + gpio_enable_module( DBG_USART_GPIO_MAP, + sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) ); + usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ); + } + #endif + + /* Request initialization of data segments. */ + return 1; +} +/*-----------------------------------------------------------*/ + +/* Added as there is no such function in FreeRTOS. */ +void *pvPortRealloc( void *pv, size_t xWantedSize ) +{ +void *pvReturn; + + vTaskSuspendAll(); + { + pvReturn = realloc( pv, xWantedSize ); + } + xTaskResumeAll(); + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to +simply increment the system tick. */ +/* The preemptive scheduler is defined as "naked" as the full context is saved +on entry as part of the context switch. */ +#pragma shadow_registers = full // Naked. +static void vTick( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_OS_INT(); + + #if( configTICK_USE_TC==1 ) + /* Clear the interrupt flag. */ + prvClearTcInt(); + #else + /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) + clock cycles from now. */ + prvScheduleNextTick(); + #endif + + /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS + calls in a critical section . */ + portENTER_CRITICAL(); + xTaskIncrementTick(); + portEXIT_CRITICAL(); + + /* Restore the context of the "elected task". */ + portRESTORE_CONTEXT_OS_INT(); +} +/*-----------------------------------------------------------*/ + +#pragma shadow_registers = full // Naked. +void SCALLYield( void ) +{ + /* Save the context of the interrupted task. */ + portSAVE_CONTEXT_SCALL(); + vTaskSwitchContext(); + portRESTORE_CONTEXT_SCALL(); +} +/*-----------------------------------------------------------*/ + +/* The code generated by the GCC compiler uses the stack in different ways at +different optimisation levels. The interrupt flags can therefore not always +be saved to the stack. Instead the critical section nesting level is stored +in a variable, which is then saved as part of the stack context. */ +#pragma optimize = no_inline +void vPortEnterCritical( void ) +{ + /* Disable interrupts */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +#pragma optimize = no_inline +void vPortExitCritical( void ) +{ + if(ulCriticalNesting > portNO_CRITICAL_NESTING) + { + ulCriticalNesting--; + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + /* Enable all interrupt/exception. */ + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* When the task starts, it will expect to find the function parameter in R12. */ + pxTopOfStack--; + *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */ + *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */ + *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */ + *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */ + *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */ + *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */ + *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */ + *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + portRESTORE_CONTEXT(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the AVR32 port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ) +clock cycles from now. */ +#if( configTICK_USE_TC==0 ) + static void prvScheduleFirstTick(void) + { + uint32_t lCycles; + + lCycles = Get_system_register(AVR32_COUNT); + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception + // generation feature does not get disabled. + if(0 == lCycles) + { + lCycles++; + } + Set_system_register(AVR32_COMPARE, lCycles); + } + + #pragma optimize = no_inline + static void prvScheduleNextTick(void) + { + uint32_t lCycles, lCount; + + lCycles = Get_system_register(AVR32_COMPARE); + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception + // generation feature does not get disabled. + if(0 == lCycles) + { + lCycles++; + } + lCount = Get_system_register(AVR32_COUNT); + if( lCycles < lCount ) + { // We missed a tick, recover for the next. + lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ); + } + Set_system_register(AVR32_COMPARE, lCycles); + } +#else + #pragma optimize = no_inline + static void prvClearTcInt(void) + { + AVR32_TC.channel[configTICK_TC_CHANNEL].sr; + } +#endif +/*-----------------------------------------------------------*/ + +/* Setup the timer to generate the tick interrupts. */ +static void prvSetupTimerInterrupt(void) +{ + #if( configTICK_USE_TC==1 ) + + volatile avr32_tc_t *tc = &AVR32_TC; + + // Options for waveform genration. + tc_waveform_opt_t waveform_opt = + { + .channel = configTICK_TC_CHANNEL, /* Channel selection. */ + + .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */ + .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */ + .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */ + .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */ + + .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */ + .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */ + .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */ + .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */ + + .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */ + .enetrg = FALSE, /* External event trigger enable. */ + .eevt = 0, /* External event selection. */ + .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */ + .cpcdis = FALSE, /* Counter disable when RC compare. */ + .cpcstop = FALSE, /* Counter clock stopped with RC compare. */ + + .burst = FALSE, /* Burst signal selection. */ + .clki = FALSE, /* Clock inversion. */ + .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */ + }; + + tc_interrupt_t tc_interrupt = + { + .etrgs=0, + .ldrbs=0, + .ldras=0, + .cpcs =1, + .cpbs =0, + .cpas =0, + .lovrs=0, + .covfs=0, + }; + + #endif + + /* Disable all interrupt/exception. */ + portDISABLE_INTERRUPTS(); + + /* Register the compare interrupt handler to the interrupt controller and + enable the compare interrupt. */ + + #if( configTICK_USE_TC==1 ) + { + INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0); + + /* Initialize the timer/counter. */ + tc_init_waveform(tc, &waveform_opt); + + /* Set the compare triggers. + Remember TC counter is 16-bits, so counting second is not possible! + That's why we configure it to count ms. */ + tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ ); + + tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt ); + + /* Start the timer/counter. */ + tc_start(tc, configTICK_TC_CHANNEL); + } + #else + { + INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0); + prvScheduleFirstTick(); + } + #endif +}
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h new file mode 100644 index 0000000..de74a38 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h
@@ -0,0 +1,654 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS port header for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + *****************************************************************************/ + +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ +#include <avr32/io.h> +#include "intc.h" +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS ) +#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS ) +#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS ) + +#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL) + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 4 +#define portNOP() {__asm__ __volatile__ ("nop");} +/*-----------------------------------------------------------*/ + + +/*-----------------------------------------------------------*/ + +/* INTC-specific. */ +#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception() +#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception() + +#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt() +#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt() + +#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev) +#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev) + + +/* + * Debug trace. + * Activated if and only if configDBG is nonzero. + * Prints a formatted string to stdout. + * The current source file name and line number are output with a colon before + * the formatted string. + * A carriage return and a linefeed are appended to the output. + * stdout is redirected to the USART configured by configDBG_USART. + * The parameters are the same as for the standard printf function. + * There is no return value. + * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc, + * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock. + */ +#if configDBG + #define portDBG_TRACE(...) \ + { \ + fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \ + printf(__VA_ARGS__); \ + fputs("\r\n", stdout); \ + } +#else + #define portDBG_TRACE(...) +#endif + + +/* Critical section management. */ +#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS() +#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS() + + +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); + +#define portENTER_CRITICAL() vPortEnterCritical(); +#define portEXIT_CRITICAL() vPortExitCritical(); + + +/* Added as there is no such function in FreeRTOS. */ +extern void *pvPortRealloc( void *pv, size_t xSize ); +/*-----------------------------------------------------------*/ + + +/*=============================================================================================*/ + +/* + * Restore Context for cases other than INTi. + */ +#define portRESTORE_CONTEXT() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + /* R0-R7 should not be used below this line */ \ + /* Skip PC and SR (will do it at the end) */ \ + "sub sp, -2*4 \n\t"\ + /* Restore R8..R12 and LR */ \ + "ldm sp++, r8-r12, lr \n\t"\ + /* Restore SR */ \ + "ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */\ + "mtsr "ASTRINGZ(AVR32_SR)", r0 \n\t"\ + /* Restore r0 */ \ + "ld.w r0, sp[-9*4] \n\t"\ + /* Restore PC */ \ + "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + + +/* + * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions. + * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception. + * + * Had to make different versions because registers saved on the system stack + * are not the same between INT0..3 exceptions and the scall exception. + */ + +// Task context stack layout: + // R8 (*) + // R9 (*) + // R10 (*) + // R11 (*) + // R12 (*) + // R14/LR (*) + // R15/PC (*) + // SR (*) + // R0 + // R1 + // R2 + // R3 + // R4 + // R5 + // R6 + // R7 + // ulCriticalNesting +// (*) automatically done for INT0..INT3, but not for SCALL + +/* + * The ISR used for the scheduler tick depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ +#define portSAVE_CONTEXT_OS_INT() \ +{ \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ("stm --sp, r0-r7"); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ +} + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ +#define portRESTORE_CONTEXT_OS_INT() \ +{ \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ +} + +#else + +/* + * portSAVE_CONTEXT_OS_INT() for OS Tick exception. + */ +#define portSAVE_CONTEXT_OS_INT() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0 \n\t"\ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + /* NOTE: we don't enter a critical section here because all interrupt handlers */ \ + /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \ + /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \ + /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp \n"\ + \ + "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \ + ); \ +} + +/* + * portRESTORE_CONTEXT_OS_INT() for Tick exception. + */ +#define portRESTORE_CONTEXT_OS_INT() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + __asm__ __volatile__ ( \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \ + ); \ + \ + /* Else */ \ + /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + /* Restore all registers */ \ + \ + __asm__ __volatile__ ( \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n"\ + \ + "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + +#endif + + +/* + * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception. + * + * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode. + * + */ +#define portSAVE_CONTEXT_SCALL() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \ + /* If SR[M2:M0] == 001 */ \ + /* PC and SR are on the stack. */ \ + /* Else (other modes) */ \ + /* Nothing on the stack. */ \ + \ + /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \ + /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \ + /* in an interrupt|exception handler. */ \ + \ + __asm__ __volatile__ ( \ + /* in order to save R0-R7 */ \ + "sub sp, 6*4 \n\t"\ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* in order to save R8-R12 and LR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp,-16*4 \n\t"\ + /* Copy PC and SR in other places in the stack. */ \ + "ld.w r0, r7[-2*4] \n\t" /* Read SR */\ + "st.w r7[-8*4], r0 \n\t" /* Copy SR */\ + "ld.w r0, r7[-1*4] \n\t" /* Read PC */\ + "st.w r7[-7*4], r0 \n\t" /* Copy PC */\ + \ + /* Save R8..R12 and LR on the stack. */ \ + "stm --r7, r8-r12, lr \n\t"\ + \ + /* Arriving here we have the following stack organizations: */ \ + /* R8..R12, LR, PC, SR, R0..R7. */ \ + \ + /* Now we can finalize the save. */ \ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0" \ + ); \ + \ + /* Disable the its which may cause a context switch (i.e. cause a change of */ \ + /* pxCurrentTCB). */ \ + /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \ + /* critical section because it is a global structure. */ \ + portENTER_CRITICAL(); \ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + __asm__ __volatile__ ( \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp" \ + ); \ +} + +/* + * portRESTORE_CONTEXT() for SupervisorCALL exception. + */ +#define portRESTORE_CONTEXT_SCALL() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + __asm__ __volatile__ ( \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0]" \ + ); \ + \ + /* Leave pxCurrentTCB variable access critical section */ \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* skip PC and SR */ \ + /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \ + "sub r7, sp, -10*4 \n\t"\ + /* Restore r8-r12 and LR */ \ + "ldm r7++, r8-r12, lr \n\t"\ + \ + /* RETS will take care of the extra PC and SR restore. */ \ + /* So, we have to prepare the stack for this. */ \ + "ld.w r0, r7[-8*4] \n\t" /* Read SR */\ + "st.w r7[-2*4], r0 \n\t" /* Copy SR */\ + "ld.w r0, r7[-7*4] \n\t" /* Read PC */\ + "st.w r7[-1*4], r0 \n\t" /* Copy PC */\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + "sub sp, -6*4 \n\t"\ + \ + "rets" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + + +/* + * The ISR used depends on whether the cooperative or + * the preemptive scheduler is being used. + */ +#if configUSE_PREEMPTION == 0 + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ +#define portENTER_SWITCHING_ISR() \ +{ \ + /* Save R0..R7 */ \ + __asm__ __volatile__ ("stm --sp, r0-r7"); \ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context save. */ \ +} + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ +#define portEXIT_SWITCHING_ISR() \ +{ \ + __asm__ __volatile__ ( \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* With the cooperative scheduler, as there is no context switch by interrupt, */ \ + /* there is also no context restore. */ \ + "rete" \ + ); \ +} + +#else + +/* + * ISR entry and exit macros. These are only required if a task switch + * is required from the ISR. + */ +#define portENTER_SWITCHING_ISR() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + /* When we come here */ \ + /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \ + \ + __asm__ __volatile__ ( \ + /* Save R0..R7 */ \ + "stm --sp, r0-r7 \n\t"\ + \ + /* Save ulCriticalNesting variable - R0 is overwritten */ \ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w --sp, r0 \n\t"\ + \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case we don't want to do a task switch because we don't know what the stack */ \ + /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \ + /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \ + /* will just be restoring the interrupt handler, no way!!! */ \ + /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ + \ + /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "st.w r0[0], sp \n"\ + \ + "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \ + ); \ +} + + +/* + * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 + */ +#define portEXIT_SWITCHING_ISR() \ +{ \ + extern volatile uint32_t ulCriticalNesting; \ + extern volatile void *volatile pxCurrentTCB; \ + \ + __asm__ __volatile__ ( \ + /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \ + /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \ + /* level and allow other lower interrupt level to occur). */ \ + /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \ + /* did not previously save SP in its TCB. */ \ + "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\ + "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\ + "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\ + "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\ + \ + /* If a switch is required then we just need to call */ \ + /* vTaskSwitchContext() as the context has already been */ \ + /* saved. */ \ + "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\ + "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \ + ); \ + \ + /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\ + portENTER_CRITICAL(); \ + vTaskSwitchContext(); \ + portEXIT_CRITICAL(); \ + \ + __asm__ __volatile__ ( \ + "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ + /* Restore the context of which ever task is now the highest */ \ + /* priority that is ready to run. */ \ + \ + /* Restore all registers */ \ + \ + /* Set SP to point to new stack */ \ + "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\ + "ld.w r0, r8[0] \n\t"\ + "ld.w sp, r0[0] \n"\ + \ + "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\ + \ + /* Restore ulCriticalNesting variable */ \ + "ld.w r0, sp++ \n\t"\ + "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\ + "st.w r8[0], r0 \n\t"\ + \ + /* Restore R0..R7 */ \ + "ldm sp++, r0-r7 \n\t"\ + \ + /* Now, the stack should be R8..R12, LR, PC and SR */ \ + "rete" \ + ); \ + \ + /* Force import of global symbols from assembly */ \ + ulCriticalNesting; \ + pxCurrentTCB; \ +} + +#endif + + +#define portYIELD() {__asm__ __volatile__ ("scall");} + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c new file mode 100644 index 0000000..30b5ee8 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c
@@ -0,0 +1,93 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief System-specific implementation of the \ref __read function used by + the standard library. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include <yfuns.h> +#include <avr32/io.h> +#include "usart.h" + + +_STD_BEGIN + + +#pragma module_name = "?__read" + + +extern volatile avr32_usart_t *volatile stdio_usart_base; + + +/*! \brief Reads a number of bytes, at most \a size, into the memory area + * pointed to by \a buffer. + * + * \param handle File handle to read from. + * \param buffer Pointer to buffer to write read bytes to. + * \param size Number of bytes to read. + * + * \return The number of bytes read, \c 0 at the end of the file, or + * \c _LLIO_ERROR on failure. + */ +size_t __read(int handle, uint8_t *buffer, size_t size) +{ + int nChars = 0; + + // This implementation only reads from stdin. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDIN) + { + return _LLIO_ERROR; + } + + for (; size > 0; --size) + { + int c = usart_getchar(stdio_usart_base); + if (c < 0) + break; + + *buffer++ = c; + ++nChars; + } + + return nChars; +} + + +_STD_END
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c new file mode 100644 index 0000000..859487e --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c
@@ -0,0 +1,103 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief System-specific implementation of the \ref __write function used by + the standard library. + * + * - Compiler: IAR EWAVR32 + * - Supported devices: All AVR32 devices with a USART module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support and FAQ: http://support.atmel.no/ + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include <yfuns.h> +#include <avr32/io.h> +#include "usart.h" + + +_STD_BEGIN + + +#pragma module_name = "?__write" + + +//! Pointer to the base of the USART module instance to use for stdio. +__no_init volatile avr32_usart_t *volatile stdio_usart_base; + + +/*! \brief Writes a number of bytes, at most \a size, from the memory area + * pointed to by \a buffer. + * + * If \a buffer is zero then \ref __write performs flushing of internal buffers, + * if any. In this case, \a handle can be \c -1 to indicate that all handles + * should be flushed. + * + * \param handle File handle to write to. + * \param buffer Pointer to buffer to read bytes to write from. + * \param size Number of bytes to write. + * + * \return The number of bytes written, or \c _LLIO_ERROR on failure. + */ +size_t __write(int handle, const uint8_t *buffer, size_t size) +{ + size_t nChars = 0; + + if (buffer == 0) + { + // This means that we should flush internal buffers. + return 0; + } + + // This implementation only writes to stdout and stderr. + // For all other file handles, it returns failure. + if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) + { + return _LLIO_ERROR; + } + + for (; size != 0; --size) + { + if (usart_putchar(stdio_usart_base, *buffer++) < 0) + { + return _LLIO_ERROR; + } + + ++nChars; + } + + return nChars; +} + + +_STD_END
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h new file mode 100644 index 0000000..8f9ddb4 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
@@ -0,0 +1,1914 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S64.h +// Object : AT91SAM7S64 definitions +// Generated : AT91 SW Application Group 07/16/2004 (07:43:08) +// +// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// +// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// +// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// +// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// +// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// +// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// +// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// +// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// +// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// +// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// +// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// +// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7S64_H +#define AT91SAM7S64_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYSC { + AT91_REG SYSC_AIC_SMR[32]; // Source Mode Register + AT91_REG SYSC_AIC_SVR[32]; // Source Vector Register + AT91_REG SYSC_AIC_IVR; // IRQ Vector Register + AT91_REG SYSC_AIC_FVR; // FIQ Vector Register + AT91_REG SYSC_AIC_ISR; // Interrupt Status Register + AT91_REG SYSC_AIC_IPR; // Interrupt Pending Register + AT91_REG SYSC_AIC_IMR; // Interrupt Mask Register + AT91_REG SYSC_AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG SYSC_AIC_IECR; // Interrupt Enable Command Register + AT91_REG SYSC_AIC_IDCR; // Interrupt Disable Command Register + AT91_REG SYSC_AIC_ICCR; // Interrupt Clear Command Register + AT91_REG SYSC_AIC_ISCR; // Interrupt Set Command Register + AT91_REG SYSC_AIC_EOICR; // End of Interrupt Command Register + AT91_REG SYSC_AIC_SPU; // Spurious Vector Register + AT91_REG SYSC_AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG SYSC_AIC_FFER; // Fast Forcing Enable Register + AT91_REG SYSC_AIC_FFDR; // Fast Forcing Disable Register + AT91_REG SYSC_AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG SYSC_DBGU_CR; // Control Register + AT91_REG SYSC_DBGU_MR; // Mode Register + AT91_REG SYSC_DBGU_IER; // Interrupt Enable Register + AT91_REG SYSC_DBGU_IDR; // Interrupt Disable Register + AT91_REG SYSC_DBGU_IMR; // Interrupt Mask Register + AT91_REG SYSC_DBGU_CSR; // Channel Status Register + AT91_REG SYSC_DBGU_RHR; // Receiver Holding Register + AT91_REG SYSC_DBGU_THR; // Transmitter Holding Register + AT91_REG SYSC_DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG SYSC_DBGU_C1R; // Chip ID1 Register + AT91_REG SYSC_DBGU_C2R; // Chip ID2 Register + AT91_REG SYSC_DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG SYSC_DBGU_RPR; // Receive Pointer Register + AT91_REG SYSC_DBGU_RCR; // Receive Counter Register + AT91_REG SYSC_DBGU_TPR; // Transmit Pointer Register + AT91_REG SYSC_DBGU_TCR; // Transmit Counter Register + AT91_REG SYSC_DBGU_RNPR; // Receive Next Pointer Register + AT91_REG SYSC_DBGU_RNCR; // Receive Next Counter Register + AT91_REG SYSC_DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG SYSC_DBGU_TNCR; // Transmit Next Counter Register + AT91_REG SYSC_DBGU_PTCR; // PDC Transfer Control Register + AT91_REG SYSC_DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG SYSC_PIOA_PER; // PIO Enable Register + AT91_REG SYSC_PIOA_PDR; // PIO Disable Register + AT91_REG SYSC_PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG SYSC_PIOA_OER; // Output Enable Register + AT91_REG SYSC_PIOA_ODR; // Output Disable Registerr + AT91_REG SYSC_PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG SYSC_PIOA_IFER; // Input Filter Enable Register + AT91_REG SYSC_PIOA_IFDR; // Input Filter Disable Register + AT91_REG SYSC_PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG SYSC_PIOA_SODR; // Set Output Data Register + AT91_REG SYSC_PIOA_CODR; // Clear Output Data Register + AT91_REG SYSC_PIOA_ODSR; // Output Data Status Register + AT91_REG SYSC_PIOA_PDSR; // Pin Data Status Register + AT91_REG SYSC_PIOA_IER; // Interrupt Enable Register + AT91_REG SYSC_PIOA_IDR; // Interrupt Disable Register + AT91_REG SYSC_PIOA_IMR; // Interrupt Mask Register + AT91_REG SYSC_PIOA_ISR; // Interrupt Status Register + AT91_REG SYSC_PIOA_MDER; // Multi-driver Enable Register + AT91_REG SYSC_PIOA_MDDR; // Multi-driver Disable Register + AT91_REG SYSC_PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG SYSC_PIOA_PPUDR; // Pull-up Disable Register + AT91_REG SYSC_PIOA_PPUER; // Pull-up Enable Register + AT91_REG SYSC_PIOA_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG SYSC_PIOA_ASR; // Select A Register + AT91_REG SYSC_PIOA_BSR; // Select B Register + AT91_REG SYSC_PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG SYSC_PIOA_OWER; // Output Write Enable Register + AT91_REG SYSC_PIOA_OWDR; // Output Write Disable Register + AT91_REG SYSC_PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[469]; // + AT91_REG SYSC_PMC_SCER; // System Clock Enable Register + AT91_REG SYSC_PMC_SCDR; // System Clock Disable Register + AT91_REG SYSC_PMC_SCSR; // System Clock Status Register + AT91_REG Reserved13[1]; // + AT91_REG SYSC_PMC_PCER; // Peripheral Clock Enable Register + AT91_REG SYSC_PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG SYSC_PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved14[1]; // + AT91_REG SYSC_PMC_MOR; // Main Oscillator Register + AT91_REG SYSC_PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved15[1]; // + AT91_REG SYSC_PMC_PLLR; // PLL Register + AT91_REG SYSC_PMC_MCKR; // Master Clock Register + AT91_REG Reserved16[3]; // + AT91_REG SYSC_PMC_PCKR[8]; // Programmable Clock Register + AT91_REG SYSC_PMC_IER; // Interrupt Enable Register + AT91_REG SYSC_PMC_IDR; // Interrupt Disable Register + AT91_REG SYSC_PMC_SR; // Status Register + AT91_REG SYSC_PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved17[36]; // + AT91_REG SYSC_RSTC_RCR; // Reset Control Register + AT91_REG SYSC_RSTC_RSR; // Reset Status Register + AT91_REG SYSC_RSTC_RMR; // Reset Mode Register + AT91_REG Reserved18[5]; // + AT91_REG SYSC_RTTC_RTMR; // Real-time Mode Register + AT91_REG SYSC_RTTC_RTAR; // Real-time Alarm Register + AT91_REG SYSC_RTTC_RTVR; // Real-time Value Register + AT91_REG SYSC_RTTC_RTSR; // Real-time Status Register + AT91_REG SYSC_PITC_PIMR; // Period Interval Mode Register + AT91_REG SYSC_PITC_PISR; // Period Interval Status Register + AT91_REG SYSC_PITC_PIVR; // Period Interval Value Register + AT91_REG SYSC_PITC_PIIR; // Period Interval Image Register + AT91_REG SYSC_WDTC_WDCR; // Watchdog Control Register + AT91_REG SYSC_WDTC_WDMR; // Watchdog Mode Register + AT91_REG SYSC_WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved19[5]; // + AT91_REG SYSC_SYSC_VRPM; // Voltage Regulator Power Mode Register +} AT91S_SYSC, *AT91PS_SYSC; + +// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- +#define AT91C_SYSC_PSTDBY ((unsigned int) 0x1 << 0) // (SYSC) Voltage Regulator Power Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_C1R; // Chip ID1 Register + AT91_REG DBGU_C2R; // Chip ID2 Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_SYSC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_SYSC_ICERST ((unsigned int) 0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_SYSC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_SYSC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_SYSC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_SYSC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_SYSC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brown-out Detection Status +#define AT91C_SYSC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_SYSC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_SYSC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_SYSC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_SYSC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_SYSC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brown-out Reset. +#define AT91C_SYSC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_SYSC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_SYSC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_SYSC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_SYSC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_SYSC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_SYSC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_SYSC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_SYSC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_SYSC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_SYSC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_SYSC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_SYSC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_SYSC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_SYSC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_SYSC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_SYSC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_SYSC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_SYSC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_SYSC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_SYSC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_SYSC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_SYSC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_SYSC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_SYSC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_SYSC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_SYSC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_SYSC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_SYSC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 2) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG SSC_RC0R; // Receive Compare 0 Register + AT91_REG SSC_RC1R; // Receive Compare 1 Register + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved2[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG US_XXR; // XON_XOFF Register + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved1[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG TWI_SMR; // Slave Mode Register + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved0[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled +#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read +#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access +#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0 +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register + AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 +// ***************************************************************************** +// ========== Register definition for SYSC peripheral ========== +#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC) Receive Compare 0 Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC) Receive Compare 1 Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +#define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +#define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +#define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved +#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved +#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved +#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved +#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved +#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_BASE_SYSC ((AT91PS_SYSC) 0xFFFFF000) // (SYSC) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte) + +#endif
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h new file mode 100644 index 0000000..7d2657a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
@@ -0,0 +1,1812 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7S64.h +// Object : AT91SAM7S64 definitions +// Generated : AT91 SW Application Group 07/16/2004 (07:43:09) +// +// CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004// +// CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004// +// CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004// +// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002// +// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// +// CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004// +// CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003// +// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002// +// CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003// +// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002// +// CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003// +// CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +// *** Register offset in AT91S_SYSC structure *** +#define SYSC_AIC_SMR ( 0) // Source Mode Register +#define SYSC_AIC_SVR (128) // Source Vector Register +#define SYSC_AIC_IVR (256) // IRQ Vector Register +#define SYSC_AIC_FVR (260) // FIQ Vector Register +#define SYSC_AIC_ISR (264) // Interrupt Status Register +#define SYSC_AIC_IPR (268) // Interrupt Pending Register +#define SYSC_AIC_IMR (272) // Interrupt Mask Register +#define SYSC_AIC_CISR (276) // Core Interrupt Status Register +#define SYSC_AIC_IECR (288) // Interrupt Enable Command Register +#define SYSC_AIC_IDCR (292) // Interrupt Disable Command Register +#define SYSC_AIC_ICCR (296) // Interrupt Clear Command Register +#define SYSC_AIC_ISCR (300) // Interrupt Set Command Register +#define SYSC_AIC_EOICR (304) // End of Interrupt Command Register +#define SYSC_AIC_SPU (308) // Spurious Vector Register +#define SYSC_AIC_DCR (312) // Debug Control Register (Protect) +#define SYSC_AIC_FFER (320) // Fast Forcing Enable Register +#define SYSC_AIC_FFDR (324) // Fast Forcing Disable Register +#define SYSC_AIC_FFSR (328) // Fast Forcing Status Register +#define SYSC_DBGU_CR (512) // Control Register +#define SYSC_DBGU_MR (516) // Mode Register +#define SYSC_DBGU_IER (520) // Interrupt Enable Register +#define SYSC_DBGU_IDR (524) // Interrupt Disable Register +#define SYSC_DBGU_IMR (528) // Interrupt Mask Register +#define SYSC_DBGU_CSR (532) // Channel Status Register +#define SYSC_DBGU_RHR (536) // Receiver Holding Register +#define SYSC_DBGU_THR (540) // Transmitter Holding Register +#define SYSC_DBGU_BRGR (544) // Baud Rate Generator Register +#define SYSC_DBGU_C1R (576) // Chip ID1 Register +#define SYSC_DBGU_C2R (580) // Chip ID2 Register +#define SYSC_DBGU_FNTR (584) // Force NTRST Register +#define SYSC_DBGU_RPR (768) // Receive Pointer Register +#define SYSC_DBGU_RCR (772) // Receive Counter Register +#define SYSC_DBGU_TPR (776) // Transmit Pointer Register +#define SYSC_DBGU_TCR (780) // Transmit Counter Register +#define SYSC_DBGU_RNPR (784) // Receive Next Pointer Register +#define SYSC_DBGU_RNCR (788) // Receive Next Counter Register +#define SYSC_DBGU_TNPR (792) // Transmit Next Pointer Register +#define SYSC_DBGU_TNCR (796) // Transmit Next Counter Register +#define SYSC_DBGU_PTCR (800) // PDC Transfer Control Register +#define SYSC_DBGU_PTSR (804) // PDC Transfer Status Register +#define SYSC_PIOA_PER (1024) // PIO Enable Register +#define SYSC_PIOA_PDR (1028) // PIO Disable Register +#define SYSC_PIOA_PSR (1032) // PIO Status Register +#define SYSC_PIOA_OER (1040) // Output Enable Register +#define SYSC_PIOA_ODR (1044) // Output Disable Registerr +#define SYSC_PIOA_OSR (1048) // Output Status Register +#define SYSC_PIOA_IFER (1056) // Input Filter Enable Register +#define SYSC_PIOA_IFDR (1060) // Input Filter Disable Register +#define SYSC_PIOA_IFSR (1064) // Input Filter Status Register +#define SYSC_PIOA_SODR (1072) // Set Output Data Register +#define SYSC_PIOA_CODR (1076) // Clear Output Data Register +#define SYSC_PIOA_ODSR (1080) // Output Data Status Register +#define SYSC_PIOA_PDSR (1084) // Pin Data Status Register +#define SYSC_PIOA_IER (1088) // Interrupt Enable Register +#define SYSC_PIOA_IDR (1092) // Interrupt Disable Register +#define SYSC_PIOA_IMR (1096) // Interrupt Mask Register +#define SYSC_PIOA_ISR (1100) // Interrupt Status Register +#define SYSC_PIOA_MDER (1104) // Multi-driver Enable Register +#define SYSC_PIOA_MDDR (1108) // Multi-driver Disable Register +#define SYSC_PIOA_MDSR (1112) // Multi-driver Status Register +#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register +#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register +#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register +#define SYSC_PIOA_ASR (1136) // Select A Register +#define SYSC_PIOA_BSR (1140) // Select B Register +#define SYSC_PIOA_ABSR (1144) // AB Select Status Register +#define SYSC_PIOA_OWER (1184) // Output Write Enable Register +#define SYSC_PIOA_OWDR (1188) // Output Write Disable Register +#define SYSC_PIOA_OWSR (1192) // Output Write Status Register +#define SYSC_PMC_SCER (3072) // System Clock Enable Register +#define SYSC_PMC_SCDR (3076) // System Clock Disable Register +#define SYSC_PMC_SCSR (3080) // System Clock Status Register +#define SYSC_PMC_PCER (3088) // Peripheral Clock Enable Register +#define SYSC_PMC_PCDR (3092) // Peripheral Clock Disable Register +#define SYSC_PMC_PCSR (3096) // Peripheral Clock Status Register +#define SYSC_PMC_MOR (3104) // Main Oscillator Register +#define SYSC_PMC_MCFR (3108) // Main Clock Frequency Register +#define SYSC_PMC_PLLR (3116) // PLL Register +#define SYSC_PMC_MCKR (3120) // Master Clock Register +#define SYSC_PMC_PCKR (3136) // Programmable Clock Register +#define SYSC_PMC_IER (3168) // Interrupt Enable Register +#define SYSC_PMC_IDR (3172) // Interrupt Disable Register +#define SYSC_PMC_SR (3176) // Status Register +#define SYSC_PMC_IMR (3180) // Interrupt Mask Register +#define SYSC_RSTC_RCR (3328) // Reset Control Register +#define SYSC_RSTC_RSR (3332) // Reset Status Register +#define SYSC_RSTC_RMR (3336) // Reset Mode Register +#define SYSC_RTTC_RTMR (3360) // Real-time Mode Register +#define SYSC_RTTC_RTAR (3364) // Real-time Alarm Register +#define SYSC_RTTC_RTVR (3368) // Real-time Value Register +#define SYSC_RTTC_RTSR (3372) // Real-time Status Register +#define SYSC_PITC_PIMR (3376) // Period Interval Mode Register +#define SYSC_PITC_PISR (3380) // Period Interval Status Register +#define SYSC_PITC_PIVR (3384) // Period Interval Value Register +#define SYSC_PITC_PIIR (3388) // Period Interval Image Register +#define SYSC_WDTC_WDCR (3392) // Watchdog Control Register +#define SYSC_WDTC_WDMR (3396) // Watchdog Mode Register +#define SYSC_WDTC_WDSR (3400) // Watchdog Status Register +#define SYSC_SYSC_VRPM (3424) // Voltage Regulator Power Mode Register +// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- +#define AT91C_SYSC_PSTDBY (0x1 << 0) // (SYSC) Voltage Regulator Power Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_C1R (64) // Chip ID1 Register +#define DBGU_C2R (68) // Chip ID2 Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pad Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_SYSC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_SYSC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_SYSC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_SYSC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_SYSC_KEY (0xFF << 24) // (RSTC) Password +// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_SYSC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_SYSC_BODSTS (0x1 << 1) // (RSTC) Brown-out Detection Status +#define AT91C_SYSC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_SYSC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_SYSC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_SYSC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_SYSC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_SYSC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brown-out Reset. +#define AT91C_SYSC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_SYSC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_SYSC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_SYSC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_SYSC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_SYSC_BODIEN (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_SYSC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_SYSC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_SYSC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_SYSC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_SYSC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_SYSC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_SYSC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_SYSC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_SYSC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_SYSC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_SYSC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_SYSC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_SYSC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_SYSC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_SYSC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_SYSC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_SYSC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_SYSC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_SYSC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_SYSC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_SYSC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_SYSC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_SYSC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_SYSC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 2) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_RC0R (56) // Receive Compare 0 Register +#define SSC_RC1R (60) // Receive Compare 1 Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_XXR (72) // XON_XOFF Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_SMR ( 8) // Slave Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled +#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read +#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access +#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel 0 +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4 +#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5 +#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6 +#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 +// ***************************************************************************** +// ========== Register definition for SYSC peripheral ========== +#define AT91C_SYSC_SYSC_VRPM (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register +#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_RC0R (0xFFFD4038) // (SSC) Receive Compare 0 Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_RC1R (0xFFFD403C) // (SSC) Receive Compare 1 Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +#define AT91C_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +#define AT91C_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +#define AT91C_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 +#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 +#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data +#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 +#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave +#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave +#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock +#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync +#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock +#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data +#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data +#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock +#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync +#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data +#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data +#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock +#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send +#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send +#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect +#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready +#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready +#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator +#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data +#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 +#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 +#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock +#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data +#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data +#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send +#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send +#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data +#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller +#define AT91C_ID_3_Reserved ( 3) // Reserved +#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_15_Reserved (15) // Reserved +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_BASE_SYSC (0xFFFFF000) // (SYSC) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00010000) // Internal ROM size in byte (64 Kbyte) + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h new file mode 100644 index 0000000..ae4f35f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
@@ -0,0 +1,2715 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X128.h +// Object : AT91SAM7X128 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +// +// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X128_H +#define AT91SAM7X128_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte) + +#endif
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h new file mode 100644 index 0000000..96b680a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
@@ -0,0 +1,2446 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X128.h +// Object : AT91SAM7X128 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +// +// CVS Reference : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_CIDR (64) // Chip ID Register +#define DBGU_EXID (68) // Chip ID Extension Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_VREG structure *** +#define VREG_MR ( 0) // Voltage Regulator Mode Register +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +#define UDP_TXVC (116) // Transceiver Control Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN_MB structure *** +#define CAN_MB_MMR ( 0) // MailBox Mode Register +#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register +#define CAN_MB_MID ( 8) // MailBox ID Register +#define CAN_MB_MFID (12) // MailBox Family ID Register +#define CAN_MB_MSR (16) // MailBox Status Register +#define CAN_MB_MDL (20) // MailBox Data Low Register +#define CAN_MB_MDH (24) // MailBox Data High Register +#define CAN_MB_MCR (28) // MailBox Control Register +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN structure *** +#define CAN_MR ( 0) // Mode Register +#define CAN_IER ( 4) // Interrupt Enable Register +#define CAN_IDR ( 8) // Interrupt Disable Register +#define CAN_IMR (12) // Interrupt Mask Register +#define CAN_SR (16) // Status Register +#define CAN_BR (20) // Baudrate Register +#define CAN_TIM (24) // Timer Register +#define CAN_TIMESTP (28) // Time Stamp Register +#define CAN_ECR (32) // Error Counter Register +#define CAN_TCR (36) // Transfer Command Register +#define CAN_ACR (40) // Abort Command Register +#define CAN_VR (252) // Version Register +#define CAN_MB0 (512) // CAN Mailbox 0 +#define CAN_MB1 (544) // CAN Mailbox 1 +#define CAN_MB2 (576) // CAN Mailbox 2 +#define CAN_MB3 (608) // CAN Mailbox 3 +#define CAN_MB4 (640) // CAN Mailbox 4 +#define CAN_MB5 (672) // CAN Mailbox 5 +#define CAN_MB6 (704) // CAN Mailbox 6 +#define CAN_MB7 (736) // CAN Mailbox 7 +#define CAN_MB8 (768) // CAN Mailbox 8 +#define CAN_MB9 (800) // CAN Mailbox 9 +#define CAN_MB10 (832) // CAN Mailbox 10 +#define CAN_MB11 (864) // CAN Mailbox 11 +#define CAN_MB12 (896) // CAN Mailbox 12 +#define CAN_MB13 (928) // CAN Mailbox 13 +#define CAN_MB14 (960) // CAN Mailbox 14 +#define CAN_MB15 (992) // CAN Mailbox 15 +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +// *** Register offset in AT91S_EMAC structure *** +#define EMAC_NCR ( 0) // Network Control Register +#define EMAC_NCFGR ( 4) // Network Configuration Register +#define EMAC_NSR ( 8) // Network Status Register +#define EMAC_TSR (20) // Transmit Status Register +#define EMAC_RBQP (24) // Receive Buffer Queue Pointer +#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer +#define EMAC_RSR (32) // Receive Status Register +#define EMAC_ISR (36) // Interrupt Status Register +#define EMAC_IER (40) // Interrupt Enable Register +#define EMAC_IDR (44) // Interrupt Disable Register +#define EMAC_IMR (48) // Interrupt Mask Register +#define EMAC_MAN (52) // PHY Maintenance Register +#define EMAC_PTR (56) // Pause Time Register +#define EMAC_PFR (60) // Pause Frames received Register +#define EMAC_FTO (64) // Frames Transmitted OK Register +#define EMAC_SCF (68) // Single Collision Frame Register +#define EMAC_MCF (72) // Multiple Collision Frame Register +#define EMAC_FRO (76) // Frames Received OK Register +#define EMAC_FCSE (80) // Frame Check Sequence Error Register +#define EMAC_ALE (84) // Alignment Error Register +#define EMAC_DTF (88) // Deferred Transmission Frame Register +#define EMAC_LCOL (92) // Late Collision Register +#define EMAC_ECOL (96) // Excessive Collision Register +#define EMAC_TUND (100) // Transmit Underrun Error Register +#define EMAC_CSE (104) // Carrier Sense Error Register +#define EMAC_RRE (108) // Receive Ressource Error Register +#define EMAC_ROV (112) // Receive Overrun Errors Register +#define EMAC_RSE (116) // Receive Symbol Errors Register +#define EMAC_ELE (120) // Excessive Length Errors Register +#define EMAC_RJA (124) // Receive Jabbers Register +#define EMAC_USF (128) // Undersize Frames Register +#define EMAC_STE (132) // SQE Test Error Register +#define EMAC_RLE (136) // Receive Length Field Mismatch Register +#define EMAC_TPF (140) // Transmitted Pause Frames Register +#define EMAC_HRB (144) // Hash Address Bottom[31:0] +#define EMAC_HRT (148) // Hash Address Top[63:32] +#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (184) // Type ID Checking Register +#define EMAC_TPQ (188) // Transmit Pause Quantum Register +#define EMAC_USRIO (192) // USER Input/Output Register +#define EMAC_WOL (196) // Wake On LAN Register +#define EMAC_REV (252) // Revision Register +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_AES structure *** +#define AES_CR ( 0) // Control Register +#define AES_MR ( 4) // Mode Register +#define AES_IER (16) // Interrupt Enable Register +#define AES_IDR (20) // Interrupt Disable Register +#define AES_IMR (24) // Interrupt Mask Register +#define AES_ISR (28) // Interrupt Status Register +#define AES_KEYWxR (32) // Key Word x Register +#define AES_IDATAxR (64) // Input Data x Register +#define AES_ODATAxR (80) // Output Data x Register +#define AES_IVxR (96) // Initialization Vector x Register +#define AES_VR (252) // AES Version Register +#define AES_RPR (256) // Receive Pointer Register +#define AES_RCR (260) // Receive Counter Register +#define AES_TPR (264) // Transmit Pointer Register +#define AES_TCR (268) // Transmit Counter Register +#define AES_RNPR (272) // Receive Next Pointer Register +#define AES_RNCR (276) // Receive Next Counter Register +#define AES_TNPR (280) // Transmit Next Pointer Register +#define AES_TNCR (284) // Transmit Next Counter Register +#define AES_PTCR (288) // PDC Transfer Control Register +#define AES_PTSR (292) // PDC Transfer Status Register +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_TDES structure *** +#define TDES_CR ( 0) // Control Register +#define TDES_MR ( 4) // Mode Register +#define TDES_IER (16) // Interrupt Enable Register +#define TDES_IDR (20) // Interrupt Disable Register +#define TDES_IMR (24) // Interrupt Mask Register +#define TDES_ISR (28) // Interrupt Status Register +#define TDES_KEY1WxR (32) // Key 1 Word x Register +#define TDES_KEY2WxR (40) // Key 2 Word x Register +#define TDES_KEY3WxR (48) // Key 3 Word x Register +#define TDES_IDATAxR (64) // Input Data x Register +#define TDES_ODATAxR (80) // Output Data x Register +#define TDES_IVxR (96) // Initialization Vector x Register +#define TDES_VR (252) // TDES Version Register +#define TDES_RPR (256) // Receive Pointer Register +#define TDES_RCR (260) // Receive Counter Register +#define TDES_TPR (264) // Transmit Pointer Register +#define TDES_TCR (268) // Transmit Counter Register +#define TDES_RNPR (272) // Receive Next Pointer Register +#define TDES_RNCR (276) // Receive Next Counter Register +#define TDES_TNPR (280) // Transmit Next Pointer Register +#define TDES_TNCR (284) // Transmit Next Counter Register +#define TDES_PTCR (288) // PDC Transfer Control Register +#define TDES_PTSR (292) // PDC Transfer Status Register +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES (19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte) + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h new file mode 100644 index 0000000..6b73f8a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
@@ -0,0 +1,2715 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// +// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7X256_H +#define AT91SAM7X256_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved24[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[4]; // Programmable Clock Register + AT91_REG Reserved4[4]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; + +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; + +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; + +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[21]; // + AT91_REG MC_FMR; // MC Flash Mode Register + AT91_REG MC_FCR; // MC Flash Command Register + AT91_REG MC_FSR; // MC Flash Status Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG Reserved0[1]; // + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved1[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; + +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; + +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register + AT91_REG Reserved3[2]; // + AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register + AT91_REG Reserved4[3]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) +#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +typedef struct _AT91S_CAN_MB { + AT91_REG CAN_MB_MMR; // MailBox Mode Register + AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register + AT91_REG CAN_MB_MID; // MailBox ID Register + AT91_REG CAN_MB_MFID; // MailBox Family ID Register + AT91_REG CAN_MB_MSR; // MailBox Status Register + AT91_REG CAN_MB_MDL; // MailBox Data Low Register + AT91_REG CAN_MB_MDH; // MailBox Data High Register + AT91_REG CAN_MB_MCR; // MailBox Control Register +} AT91S_CAN_MB, *AT91PS_CAN_MB; + +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +typedef struct _AT91S_CAN { + AT91_REG CAN_MR; // Mode Register + AT91_REG CAN_IER; // Interrupt Enable Register + AT91_REG CAN_IDR; // Interrupt Disable Register + AT91_REG CAN_IMR; // Interrupt Mask Register + AT91_REG CAN_SR; // Status Register + AT91_REG CAN_BR; // Baudrate Register + AT91_REG CAN_TIM; // Timer Register + AT91_REG CAN_TIMESTP; // Time Stamp Register + AT91_REG CAN_ECR; // Error Counter Register + AT91_REG CAN_TCR; // Transfer Command Register + AT91_REG CAN_ACR; // Abort Command Register + AT91_REG Reserved0[52]; // + AT91_REG CAN_VR; // Version Register + AT91_REG Reserved1[64]; // + AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 + AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 + AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 + AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 + AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 + AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 + AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 + AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 + AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 + AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 + AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 + AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 + AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 + AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 + AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 + AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 +} AT91S_CAN, *AT91PS_CAN; + +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_NCR; // Network Control Register + AT91_REG EMAC_NCFGR; // Network Configuration Register + AT91_REG EMAC_NSR; // Network Status Register + AT91_REG Reserved0[2]; // + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG EMAC_PTR; // Pause Time Register + AT91_REG EMAC_PFR; // Pause Frames received Register + AT91_REG EMAC_FTO; // Frames Transmitted OK Register + AT91_REG EMAC_SCF; // Single Collision Frame Register + AT91_REG EMAC_MCF; // Multiple Collision Frame Register + AT91_REG EMAC_FRO; // Frames Received OK Register + AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTF; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_TUND; // Transmit Underrun Error Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_RRE; // Receive Ressource Error Register + AT91_REG EMAC_ROV; // Receive Overrun Errors Register + AT91_REG EMAC_RSE; // Receive Symbol Errors Register + AT91_REG EMAC_ELE; // Excessive Length Errors Register + AT91_REG EMAC_RJA; // Receive Jabbers Register + AT91_REG EMAC_USF; // Undersize Frames Register + AT91_REG EMAC_STE; // SQE Test Error Register + AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register + AT91_REG EMAC_TPF; // Transmitted Pause Frames Register + AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] + AT91_REG EMAC_HRT; // Hash Address Top[63:32] + AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes + AT91_REG EMAC_TID; // Type ID Checking Register + AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register + AT91_REG EMAC_USRIO; // USER Input/Output Register + AT91_REG EMAC_WOL; // Wake On LAN Register + AT91_REG Reserved1[13]; // + AT91_REG EMAC_REV; // Revision Register +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; + +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_AES { + AT91_REG AES_CR; // Control Register + AT91_REG AES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG AES_IER; // Interrupt Enable Register + AT91_REG AES_IDR; // Interrupt Disable Register + AT91_REG AES_IMR; // Interrupt Mask Register + AT91_REG AES_ISR; // Interrupt Status Register + AT91_REG AES_KEYWxR[4]; // Key Word x Register + AT91_REG Reserved1[4]; // + AT91_REG AES_IDATAxR[4]; // Input Data x Register + AT91_REG AES_ODATAxR[4]; // Output Data x Register + AT91_REG AES_IVxR[4]; // Initialization Vector x Register + AT91_REG Reserved2[35]; // + AT91_REG AES_VR; // AES Version Register + AT91_REG AES_RPR; // Receive Pointer Register + AT91_REG AES_RCR; // Receive Counter Register + AT91_REG AES_TPR; // Transmit Pointer Register + AT91_REG AES_TCR; // Transmit Counter Register + AT91_REG AES_RNPR; // Receive Next Pointer Register + AT91_REG AES_RNCR; // Receive Next Counter Register + AT91_REG AES_TNPR; // Transmit Next Pointer Register + AT91_REG AES_TNCR; // Transmit Next Counter Register + AT91_REG AES_PTCR; // PDC Transfer Control Register + AT91_REG AES_PTSR; // PDC Transfer Status Register +} AT91S_AES, *AT91PS_AES; + +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START ((unsigned int) 0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST ((unsigned int) 0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER ((unsigned int) 0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY ((unsigned int) 0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD ((unsigned int) 0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC ((unsigned int) 0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD ((unsigned int) 0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT ((unsigned int) 0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT ((unsigned int) 0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT ((unsigned int) 0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT ((unsigned int) 0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT ((unsigned int) 0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY ((unsigned int) 0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY ((unsigned int) 0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX ((unsigned int) 0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX ((unsigned int) 0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF ((unsigned int) 0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE ((unsigned int) 0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD ((unsigned int) 0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ ((unsigned int) 0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +typedef struct _AT91S_TDES { + AT91_REG TDES_CR; // Control Register + AT91_REG TDES_MR; // Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TDES_IER; // Interrupt Enable Register + AT91_REG TDES_IDR; // Interrupt Disable Register + AT91_REG TDES_IMR; // Interrupt Mask Register + AT91_REG TDES_ISR; // Interrupt Status Register + AT91_REG TDES_KEY1WxR[2]; // Key 1 Word x Register + AT91_REG TDES_KEY2WxR[2]; // Key 2 Word x Register + AT91_REG TDES_KEY3WxR[2]; // Key 3 Word x Register + AT91_REG Reserved1[2]; // + AT91_REG TDES_IDATAxR[2]; // Input Data x Register + AT91_REG Reserved2[2]; // + AT91_REG TDES_ODATAxR[2]; // Output Data x Register + AT91_REG Reserved3[2]; // + AT91_REG TDES_IVxR[2]; // Initialization Vector x Register + AT91_REG Reserved4[37]; // + AT91_REG TDES_VR; // TDES Version Register + AT91_REG TDES_RPR; // Receive Pointer Register + AT91_REG TDES_RCR; // Receive Counter Register + AT91_REG TDES_TPR; // Transmit Pointer Register + AT91_REG TDES_TCR; // Transmit Counter Register + AT91_REG TDES_RNPR; // Receive Next Pointer Register + AT91_REG TDES_RNCR; // Receive Next Counter Register + AT91_REG TDES_TNPR; // Transmit Next Pointer Register + AT91_REG TDES_TNCR; // Transmit Next Counter Register + AT91_REG TDES_PTCR; // PDC Transfer Control Register + AT91_REG TDES_PTSR; // PDC Transfer Status Register +} AT91S_TDES, *AT91PS_TDES; + +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START ((unsigned int) 0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST ((unsigned int) 0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER ((unsigned int) 0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD ((unsigned int) 0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD ((unsigned int) 0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD ((unsigned int) 0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL ((unsigned int) 0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO ((unsigned int) 0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC ((unsigned int) 0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD ((unsigned int) 0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT ((unsigned int) 0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT ((unsigned int) 0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT ((unsigned int) 0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT ((unsigned int) 0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY ((unsigned int) 0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX ((unsigned int) 0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX ((unsigned int) 0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF ((unsigned int) 0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE ((unsigned int) 0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD ((unsigned int) 0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR ((AT91_REG *) 0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR ((AT91_REG *) 0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR ((AT91_REG *) 0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR ((AT91_REG *) 0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR ((AT91_REG *) 0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR ((AT91_REG *) 0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR ((AT91_REG *) 0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR ((AT91_REG *) 0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR ((AT91_REG *) 0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR ((AT91_REG *) 0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR ((AT91_REG *) 0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR ((AT91_REG *) 0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR ((AT91_REG *) 0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR ((AT91_REG *) 0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR ((AT91_REG *) 0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR ((AT91_REG *) 0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR ((AT91_REG *) 0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR ((AT91_REG *) 0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER ((AT91_REG *) 0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR ((AT91_REG *) 0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR ((AT91_REG *) 0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR ((AT91_REG *) 0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR ((AT91_REG *) 0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR ((AT91_REG *) 0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR ((AT91_REG *) 0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR ((AT91_REG *) 0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR ((AT91_REG *) 0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR ((AT91_REG *) 0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR ((AT91_REG *) 0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR ((AT91_REG *) 0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR ((AT91_REG *) 0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR ((AT91_REG *) 0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR ((AT91_REG *) 0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR ((AT91_REG *) 0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR ((AT91_REG *) 0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR ((AT91_REG *) 0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR ((AT91_REG *) 0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR ((AT91_REG *) 0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR ((AT91_REG *) 0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR ((AT91_REG *) 0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER ((AT91_REG *) 0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR ((AT91_REG *) 0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR ((AT91_REG *) 0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR ((AT91_REG *) 0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface +#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 +#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller +#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC +#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter +#define AT91C_ID_AES ((unsigned int) 18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES ((unsigned int) 19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved +#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved +#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved +#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved +#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved +#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved +#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved +#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved +#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved +#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved +#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES ((AT91PS_PDC) 0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES ((AT91PS_AES) 0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES ((AT91PS_PDC) 0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES ((AT91PS_TDES) 0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte) + +#endif
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h new file mode 100644 index 0000000..5b8dfe8 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
@@ -0,0 +1,2446 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7X256.h +// Object : AT91SAM7X256 definitions +// Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +// +// CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// +// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// +// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// +// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// +// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// +// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// +// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// +// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// +// CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// +// CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// +// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_CIDR (64) // Chip ID Register +#define DBGU_EXID (68) // Chip ID Extension Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLR (12) // PLL Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MOR (32) // Main Oscillator Register +#define PMC_MCFR (36) // Main Clock Frequency Register +#define PMC_PLLR (44) // PLL Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RSTC structure *** +#define RSTC_RCR ( 0) // Reset Control Register +#define RSTC_RSR ( 4) // Reset Status Register +#define RSTC_RMR ( 8) // Reset Mode Register +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTTC structure *** +#define RTTC_RTMR ( 0) // Real-time Mode Register +#define RTTC_RTAR ( 4) // Real-time Alarm Register +#define RTTC_RTVR ( 8) // Real-time Value Register +#define RTTC_RTSR (12) // Real-time Status Register +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PITC structure *** +#define PITC_PIMR ( 0) // Period Interval Mode Register +#define PITC_PISR ( 4) // Period Interval Status Register +#define PITC_PIVR ( 8) // Period Interval Value Register +#define PITC_PIIR (12) // Period Interval Image Register +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_WDTC structure *** +#define WDTC_WDCR ( 0) // Watchdog Control Register +#define WDTC_WDMR ( 4) // Watchdog Mode Register +#define WDTC_WDSR ( 8) // Watchdog Status Register +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_VREG structure *** +#define VREG_MR ( 0) // Voltage Regulator Mode Register +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_FMR (96) // MC Flash Mode Register +#define MC_FCR (100) // MC Flash Command Register +#define MC_FSR (104) // MC Flash Status Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number +// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key +// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC_CH structure *** +#define PWMC_CMR ( 0) // Channel Mode Register +#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register +#define PWMC_CPRDR ( 8) // Channel Period Register +#define PWMC_CCNTR (12) // Channel Counter Register +#define PWMC_CUPDR (16) // Channel Update Register +#define PWMC_Reserved (20) // Reserved +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_PWMC structure *** +#define PWMC_MR ( 0) // PWMC Mode Register +#define PWMC_ENA ( 4) // PWMC Enable Register +#define PWMC_DIS ( 8) // PWMC Disable Register +#define PWMC_SR (12) // PWMC Status Register +#define PWMC_IER (16) // PWMC Interrupt Enable Register +#define PWMC_IDR (20) // PWMC Interrupt Disable Register +#define PWMC_IMR (24) // PWMC Interrupt Mask Register +#define PWMC_ISR (28) // PWMC Interrupt Status Register +#define PWMC_VR (252) // PWMC Version Register +#define PWMC_CH (512) // PWMC Channel +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +#define UDP_TXVC (116) // Transceiver Control Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN_MB structure *** +#define CAN_MB_MMR ( 0) // MailBox Mode Register +#define CAN_MB_MAM ( 4) // MailBox Acceptance Mask Register +#define CAN_MB_MID ( 8) // MailBox ID Register +#define CAN_MB_MFID (12) // MailBox Family ID Register +#define CAN_MB_MSR (16) // MailBox Status Register +#define CAN_MB_MDL (20) // MailBox Data Low Register +#define CAN_MB_MDH (24) // MailBox Data High Register +#define CAN_MB_MCR (28) // MailBox Control Register +// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- +#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark +#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority +#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type +#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB) +#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB) +// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- +#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode +#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode +#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version +// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- +// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- +// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- +#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value +#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code +#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request +#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort +#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready +#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored +// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- +// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- +// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- +#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox +#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Control Area Network Interface +// ***************************************************************************** +// *** Register offset in AT91S_CAN structure *** +#define CAN_MR ( 0) // Mode Register +#define CAN_IER ( 4) // Interrupt Enable Register +#define CAN_IDR ( 8) // Interrupt Disable Register +#define CAN_IMR (12) // Interrupt Mask Register +#define CAN_SR (16) // Status Register +#define CAN_BR (20) // Baudrate Register +#define CAN_TIM (24) // Timer Register +#define CAN_TIMESTP (28) // Time Stamp Register +#define CAN_ECR (32) // Error Counter Register +#define CAN_TCR (36) // Transfer Command Register +#define CAN_ACR (40) // Abort Command Register +#define CAN_VR (252) // Version Register +#define CAN_MB0 (512) // CAN Mailbox 0 +#define CAN_MB1 (544) // CAN Mailbox 1 +#define CAN_MB2 (576) // CAN Mailbox 2 +#define CAN_MB3 (608) // CAN Mailbox 3 +#define CAN_MB4 (640) // CAN Mailbox 4 +#define CAN_MB5 (672) // CAN Mailbox 5 +#define CAN_MB6 (704) // CAN Mailbox 6 +#define CAN_MB7 (736) // CAN Mailbox 7 +#define CAN_MB8 (768) // CAN Mailbox 8 +#define CAN_MB9 (800) // CAN Mailbox 9 +#define CAN_MB10 (832) // CAN Mailbox 10 +#define CAN_MB11 (864) // CAN Mailbox 11 +#define CAN_MB12 (896) // CAN Mailbox 12 +#define CAN_MB13 (928) // CAN Mailbox 13 +#define CAN_MB14 (960) // CAN Mailbox 14 +#define CAN_MB15 (992) // CAN Mailbox 15 +// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- +#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable +#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode +#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode +#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame +#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame +#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode +#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze +#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat +// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- +#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag +#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag +#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag +#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag +#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag +#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag +#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag +#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag +#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag +#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag +#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag +#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag +#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag +#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag +#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag +#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag +#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag +#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag +#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag +#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag +#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag +#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag +#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag +#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag +#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error +#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error +#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error +#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error +#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error +// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- +// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- +// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- +#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy +#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy +#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy +// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- +#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment +#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment +#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment +#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment +#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler +#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode +// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- +#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field +// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- +// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- +#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter +#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter +// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- +#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field +// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 +// ***************************************************************************** +// *** Register offset in AT91S_EMAC structure *** +#define EMAC_NCR ( 0) // Network Control Register +#define EMAC_NCFGR ( 4) // Network Configuration Register +#define EMAC_NSR ( 8) // Network Status Register +#define EMAC_TSR (20) // Transmit Status Register +#define EMAC_RBQP (24) // Receive Buffer Queue Pointer +#define EMAC_TBQP (28) // Transmit Buffer Queue Pointer +#define EMAC_RSR (32) // Receive Status Register +#define EMAC_ISR (36) // Interrupt Status Register +#define EMAC_IER (40) // Interrupt Enable Register +#define EMAC_IDR (44) // Interrupt Disable Register +#define EMAC_IMR (48) // Interrupt Mask Register +#define EMAC_MAN (52) // PHY Maintenance Register +#define EMAC_PTR (56) // Pause Time Register +#define EMAC_PFR (60) // Pause Frames received Register +#define EMAC_FTO (64) // Frames Transmitted OK Register +#define EMAC_SCF (68) // Single Collision Frame Register +#define EMAC_MCF (72) // Multiple Collision Frame Register +#define EMAC_FRO (76) // Frames Received OK Register +#define EMAC_FCSE (80) // Frame Check Sequence Error Register +#define EMAC_ALE (84) // Alignment Error Register +#define EMAC_DTF (88) // Deferred Transmission Frame Register +#define EMAC_LCOL (92) // Late Collision Register +#define EMAC_ECOL (96) // Excessive Collision Register +#define EMAC_TUND (100) // Transmit Underrun Error Register +#define EMAC_CSE (104) // Carrier Sense Error Register +#define EMAC_RRE (108) // Receive Ressource Error Register +#define EMAC_ROV (112) // Receive Overrun Errors Register +#define EMAC_RSE (116) // Receive Symbol Errors Register +#define EMAC_ELE (120) // Excessive Length Errors Register +#define EMAC_RJA (124) // Receive Jabbers Register +#define EMAC_USF (128) // Undersize Frames Register +#define EMAC_STE (132) // SQE Test Error Register +#define EMAC_RLE (136) // Receive Length Field Mismatch Register +#define EMAC_TPF (140) // Transmitted Pause Frames Register +#define EMAC_HRB (144) // Hash Address Bottom[31:0] +#define EMAC_HRT (148) // Hash Address Top[63:32] +#define EMAC_SA1L (152) // Specific Address 1 Bottom, First 4 bytes +#define EMAC_SA1H (156) // Specific Address 1 Top, Last 2 bytes +#define EMAC_SA2L (160) // Specific Address 2 Bottom, First 4 bytes +#define EMAC_SA2H (164) // Specific Address 2 Top, Last 2 bytes +#define EMAC_SA3L (168) // Specific Address 3 Bottom, First 4 bytes +#define EMAC_SA3H (172) // Specific Address 3 Top, Last 2 bytes +#define EMAC_SA4L (176) // Specific Address 4 Bottom, First 4 bytes +#define EMAC_SA4H (180) // Specific Address 4 Top, Last 2 bytes +#define EMAC_TID (184) // Type ID Checking Register +#define EMAC_TPQ (188) // Transmit Pause Quantum Register +#define EMAC_USRIO (192) // USER Input/Output Register +#define EMAC_WOL (196) // Wake On LAN Register +#define EMAC_REV (252) // Revision Register +// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission. +#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt. +#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame +#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame +// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC) +#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC) +#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer +#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer +#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable +#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS +#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC) +#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS +// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- +#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go +#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC) +#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC) +// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- +#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII +// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- +#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address +#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable +#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable +#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable +// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- +#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +// *** Register offset in AT91S_ADC structure *** +#define ADC_CR ( 0) // ADC Control Register +#define ADC_MR ( 4) // ADC Mode Register +#define ADC_CHER (16) // ADC Channel Enable Register +#define ADC_CHDR (20) // ADC Channel Disable Register +#define ADC_CHSR (24) // ADC Channel Status Register +#define ADC_SR (28) // ADC Status Register +#define ADC_LCDR (32) // ADC Last Converted Data Register +#define ADC_IER (36) // ADC Interrupt Enable Register +#define ADC_IDR (40) // ADC Interrupt Disable Register +#define ADC_IMR (44) // ADC Interrupt Mask Register +#define ADC_CDR0 (48) // ADC Channel Data Register 0 +#define ADC_CDR1 (52) // ADC Channel Data Register 1 +#define ADC_CDR2 (56) // ADC Channel Data Register 2 +#define ADC_CDR3 (60) // ADC Channel Data Register 3 +#define ADC_CDR4 (64) // ADC Channel Data Register 4 +#define ADC_CDR5 (68) // ADC Channel Data Register 5 +#define ADC_CDR6 (72) // ADC Channel Data Register 6 +#define ADC_CDR7 (76) // ADC Channel Data Register 7 +#define ADC_RPR (256) // Receive Pointer Register +#define ADC_RCR (260) // Receive Counter Register +#define ADC_TPR (264) // Transmit Pointer Register +#define ADC_TCR (268) // Transmit Counter Register +#define ADC_RNPR (272) // Receive Next Pointer Register +#define ADC_RNCR (276) // Receive Next Counter Register +#define ADC_TNPR (280) // Transmit Next Pointer Register +#define ADC_TNCR (284) // Transmit Next Counter Register +#define ADC_PTCR (288) // PDC Transfer Control Register +#define ADC_PTSR (292) // PDC Transfer Status Register +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_AES structure *** +#define AES_CR ( 0) // Control Register +#define AES_MR ( 4) // Mode Register +#define AES_IER (16) // Interrupt Enable Register +#define AES_IDR (20) // Interrupt Disable Register +#define AES_IMR (24) // Interrupt Mask Register +#define AES_ISR (28) // Interrupt Status Register +#define AES_KEYWxR (32) // Key Word x Register +#define AES_IDATAxR (64) // Input Data x Register +#define AES_ODATAxR (80) // Output Data x Register +#define AES_IVxR (96) // Initialization Vector x Register +#define AES_VR (252) // AES Version Register +#define AES_RPR (256) // Receive Pointer Register +#define AES_RCR (260) // Receive Counter Register +#define AES_TPR (264) // Transmit Pointer Register +#define AES_TCR (268) // Transmit Counter Register +#define AES_RNPR (272) // Receive Next Pointer Register +#define AES_RNCR (276) // Receive Next Counter Register +#define AES_TNPR (280) // Transmit Next Pointer Register +#define AES_TNCR (284) // Transmit Next Counter Register +#define AES_PTCR (288) // PDC Transfer Control Register +#define AES_PTSR (292) // PDC Transfer Status Register +// -------- AES_CR : (AES Offset: 0x0) Control Register -------- +#define AT91C_AES_START (0x1 << 0) // (AES) Starts Processing +#define AT91C_AES_SWRST (0x1 << 8) // (AES) Software Reset +#define AT91C_AES_LOADSEED (0x1 << 16) // (AES) Random Number Generator Seed Loading +// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- +#define AT91C_AES_CIPHER (0x1 << 0) // (AES) Processing Mode +#define AT91C_AES_PROCDLY (0xF << 4) // (AES) Processing Delay +#define AT91C_AES_SMOD (0x3 << 8) // (AES) Start Mode +#define AT91C_AES_SMOD_MANUAL (0x0 << 8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. +#define AT91C_AES_SMOD_AUTO (0x1 << 8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). +#define AT91C_AES_SMOD_PDC (0x2 << 8) // (AES) PDC Mode (cf datasheet). +#define AT91C_AES_OPMOD (0x7 << 12) // (AES) Operation Mode +#define AT91C_AES_OPMOD_ECB (0x0 << 12) // (AES) ECB Electronic CodeBook mode. +#define AT91C_AES_OPMOD_CBC (0x1 << 12) // (AES) CBC Cipher Block Chaining mode. +#define AT91C_AES_OPMOD_OFB (0x2 << 12) // (AES) OFB Output Feedback mode. +#define AT91C_AES_OPMOD_CFB (0x3 << 12) // (AES) CFB Cipher Feedback mode. +#define AT91C_AES_OPMOD_CTR (0x4 << 12) // (AES) CTR Counter mode. +#define AT91C_AES_LOD (0x1 << 15) // (AES) Last Output Data Mode +#define AT91C_AES_CFBS (0x7 << 16) // (AES) Cipher Feedback Data Size +#define AT91C_AES_CFBS_128_BIT (0x0 << 16) // (AES) 128-bit. +#define AT91C_AES_CFBS_64_BIT (0x1 << 16) // (AES) 64-bit. +#define AT91C_AES_CFBS_32_BIT (0x2 << 16) // (AES) 32-bit. +#define AT91C_AES_CFBS_16_BIT (0x3 << 16) // (AES) 16-bit. +#define AT91C_AES_CFBS_8_BIT (0x4 << 16) // (AES) 8-bit. +#define AT91C_AES_CKEY (0xF << 20) // (AES) Countermeasure Key +#define AT91C_AES_CTYPE (0x1F << 24) // (AES) Countermeasure Type +#define AT91C_AES_CTYPE_TYPE1_EN (0x1 << 24) // (AES) Countermeasure type 1 is enabled. +#define AT91C_AES_CTYPE_TYPE2_EN (0x2 << 24) // (AES) Countermeasure type 2 is enabled. +#define AT91C_AES_CTYPE_TYPE3_EN (0x4 << 24) // (AES) Countermeasure type 3 is enabled. +#define AT91C_AES_CTYPE_TYPE4_EN (0x8 << 24) // (AES) Countermeasure type 4 is enabled. +#define AT91C_AES_CTYPE_TYPE5_EN (0x10 << 24) // (AES) Countermeasure type 5 is enabled. +// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_AES_DATRDY (0x1 << 0) // (AES) DATRDY +#define AT91C_AES_ENDRX (0x1 << 1) // (AES) PDC Read Buffer End +#define AT91C_AES_ENDTX (0x1 << 2) // (AES) PDC Write Buffer End +#define AT91C_AES_RXBUFF (0x1 << 3) // (AES) PDC Read Buffer Full +#define AT91C_AES_TXBUFE (0x1 << 4) // (AES) PDC Write Buffer Empty +#define AT91C_AES_URAD (0x1 << 8) // (AES) Unspecified Register Access Detection +// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- +// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- +// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_AES_URAT (0x7 << 12) // (AES) Unspecified Register Access Type Status +#define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode. +#define AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing. +#define AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing. +#define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY (0x3 << 12) // (AES) Output data register read during the sub-keys generation. +#define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation. +#define AT91C_AES_URAT_WO_REG_READ (0x5 << 12) // (AES) Write-only register read access. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Triple Data Encryption Standard +// ***************************************************************************** +// *** Register offset in AT91S_TDES structure *** +#define TDES_CR ( 0) // Control Register +#define TDES_MR ( 4) // Mode Register +#define TDES_IER (16) // Interrupt Enable Register +#define TDES_IDR (20) // Interrupt Disable Register +#define TDES_IMR (24) // Interrupt Mask Register +#define TDES_ISR (28) // Interrupt Status Register +#define TDES_KEY1WxR (32) // Key 1 Word x Register +#define TDES_KEY2WxR (40) // Key 2 Word x Register +#define TDES_KEY3WxR (48) // Key 3 Word x Register +#define TDES_IDATAxR (64) // Input Data x Register +#define TDES_ODATAxR (80) // Output Data x Register +#define TDES_IVxR (96) // Initialization Vector x Register +#define TDES_VR (252) // TDES Version Register +#define TDES_RPR (256) // Receive Pointer Register +#define TDES_RCR (260) // Receive Counter Register +#define TDES_TPR (264) // Transmit Pointer Register +#define TDES_TCR (268) // Transmit Counter Register +#define TDES_RNPR (272) // Receive Next Pointer Register +#define TDES_RNCR (276) // Receive Next Counter Register +#define TDES_TNPR (280) // Transmit Next Pointer Register +#define TDES_TNCR (284) // Transmit Next Counter Register +#define TDES_PTCR (288) // PDC Transfer Control Register +#define TDES_PTSR (292) // PDC Transfer Status Register +// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- +#define AT91C_TDES_START (0x1 << 0) // (TDES) Starts Processing +#define AT91C_TDES_SWRST (0x1 << 8) // (TDES) Software Reset +// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- +#define AT91C_TDES_CIPHER (0x1 << 0) // (TDES) Processing Mode +#define AT91C_TDES_TDESMOD (0x1 << 1) // (TDES) Single or Triple DES Mode +#define AT91C_TDES_KEYMOD (0x1 << 4) // (TDES) Key Mode +#define AT91C_TDES_SMOD (0x3 << 8) // (TDES) Start Mode +#define AT91C_TDES_SMOD_MANUAL (0x0 << 8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. +#define AT91C_TDES_SMOD_AUTO (0x1 << 8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). +#define AT91C_TDES_SMOD_PDC (0x2 << 8) // (TDES) PDC Mode (cf datasheet). +#define AT91C_TDES_OPMOD (0x3 << 12) // (TDES) Operation Mode +#define AT91C_TDES_OPMOD_ECB (0x0 << 12) // (TDES) ECB Electronic CodeBook mode. +#define AT91C_TDES_OPMOD_CBC (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode. +#define AT91C_TDES_OPMOD_OFB (0x2 << 12) // (TDES) OFB Output Feedback mode. +#define AT91C_TDES_OPMOD_CFB (0x3 << 12) // (TDES) CFB Cipher Feedback mode. +#define AT91C_TDES_LOD (0x1 << 15) // (TDES) Last Output Data Mode +#define AT91C_TDES_CFBS (0x3 << 16) // (TDES) Cipher Feedback Data Size +#define AT91C_TDES_CFBS_64_BIT (0x0 << 16) // (TDES) 64-bit. +#define AT91C_TDES_CFBS_32_BIT (0x1 << 16) // (TDES) 32-bit. +#define AT91C_TDES_CFBS_16_BIT (0x2 << 16) // (TDES) 16-bit. +#define AT91C_TDES_CFBS_8_BIT (0x3 << 16) // (TDES) 8-bit. +// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- +#define AT91C_TDES_DATRDY (0x1 << 0) // (TDES) DATRDY +#define AT91C_TDES_ENDRX (0x1 << 1) // (TDES) PDC Read Buffer End +#define AT91C_TDES_ENDTX (0x1 << 2) // (TDES) PDC Write Buffer End +#define AT91C_TDES_RXBUFF (0x1 << 3) // (TDES) PDC Read Buffer Full +#define AT91C_TDES_TXBUFE (0x1 << 4) // (TDES) PDC Write Buffer Empty +#define AT91C_TDES_URAD (0x1 << 8) // (TDES) Unspecified Register Access Detection +// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- +// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- +// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- +#define AT91C_TDES_URAT (0x3 << 12) // (TDES) Unspecified Register Access Type Status +#define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode. +#define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing. +#define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing. +#define AT91C_TDES_URAT_WO_REG_READ (0x3 << 12) // (TDES) Write-only register read access. + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register +#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register +// ========== Register definition for PDC_SPI1 peripheral ========== +#define AT91C_SPI1_PTCR (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register +#define AT91C_SPI1_RPR (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register +#define AT91C_SPI1_TNCR (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register +#define AT91C_SPI1_TPR (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register +#define AT91C_SPI1_TNPR (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register +#define AT91C_SPI1_TCR (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register +#define AT91C_SPI1_RCR (0xFFFE4104) // (PDC_SPI1) Receive Counter Register +#define AT91C_SPI1_RNPR (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register +#define AT91C_SPI1_RNCR (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register +#define AT91C_SPI1_PTSR (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register +// ========== Register definition for SPI1 peripheral ========== +#define AT91C_SPI1_IMR (0xFFFE401C) // (SPI1) Interrupt Mask Register +#define AT91C_SPI1_IER (0xFFFE4014) // (SPI1) Interrupt Enable Register +#define AT91C_SPI1_MR (0xFFFE4004) // (SPI1) Mode Register +#define AT91C_SPI1_RDR (0xFFFE4008) // (SPI1) Receive Data Register +#define AT91C_SPI1_IDR (0xFFFE4018) // (SPI1) Interrupt Disable Register +#define AT91C_SPI1_SR (0xFFFE4010) // (SPI1) Status Register +#define AT91C_SPI1_TDR (0xFFFE400C) // (SPI1) Transmit Data Register +#define AT91C_SPI1_CR (0xFFFE4000) // (SPI1) Control Register +#define AT91C_SPI1_CSR (0xFFFE4030) // (SPI1) Chip Select Register +// ========== Register definition for PDC_SPI0 peripheral ========== +#define AT91C_SPI0_PTCR (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register +#define AT91C_SPI0_TPR (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register +#define AT91C_SPI0_TCR (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register +#define AT91C_SPI0_RCR (0xFFFE0104) // (PDC_SPI0) Receive Counter Register +#define AT91C_SPI0_PTSR (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register +#define AT91C_SPI0_RNPR (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register +#define AT91C_SPI0_RPR (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register +#define AT91C_SPI0_TNCR (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register +#define AT91C_SPI0_RNCR (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register +#define AT91C_SPI0_TNPR (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register +// ========== Register definition for SPI0 peripheral ========== +#define AT91C_SPI0_IER (0xFFFE0014) // (SPI0) Interrupt Enable Register +#define AT91C_SPI0_SR (0xFFFE0010) // (SPI0) Status Register +#define AT91C_SPI0_IDR (0xFFFE0018) // (SPI0) Interrupt Disable Register +#define AT91C_SPI0_CR (0xFFFE0000) // (SPI0) Control Register +#define AT91C_SPI0_MR (0xFFFE0004) // (SPI0) Mode Register +#define AT91C_SPI0_IMR (0xFFFE001C) // (SPI0) Interrupt Mask Register +#define AT91C_SPI0_TDR (0xFFFE000C) // (SPI0) Transmit Data Register +#define AT91C_SPI0_RDR (0xFFFE0008) // (SPI0) Receive Data Register +#define AT91C_SPI0_CSR (0xFFFE0030) // (SPI0) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for CAN_MB0 peripheral ========== +#define AT91C_CAN_MB0_MDL (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register +#define AT91C_CAN_MB0_MAM (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register +#define AT91C_CAN_MB0_MCR (0xFFFD021C) // (CAN_MB0) MailBox Control Register +#define AT91C_CAN_MB0_MID (0xFFFD0208) // (CAN_MB0) MailBox ID Register +#define AT91C_CAN_MB0_MSR (0xFFFD0210) // (CAN_MB0) MailBox Status Register +#define AT91C_CAN_MB0_MFID (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register +#define AT91C_CAN_MB0_MDH (0xFFFD0218) // (CAN_MB0) MailBox Data High Register +#define AT91C_CAN_MB0_MMR (0xFFFD0200) // (CAN_MB0) MailBox Mode Register +// ========== Register definition for CAN_MB1 peripheral ========== +#define AT91C_CAN_MB1_MDL (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register +#define AT91C_CAN_MB1_MID (0xFFFD0228) // (CAN_MB1) MailBox ID Register +#define AT91C_CAN_MB1_MMR (0xFFFD0220) // (CAN_MB1) MailBox Mode Register +#define AT91C_CAN_MB1_MSR (0xFFFD0230) // (CAN_MB1) MailBox Status Register +#define AT91C_CAN_MB1_MAM (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register +#define AT91C_CAN_MB1_MDH (0xFFFD0238) // (CAN_MB1) MailBox Data High Register +#define AT91C_CAN_MB1_MCR (0xFFFD023C) // (CAN_MB1) MailBox Control Register +#define AT91C_CAN_MB1_MFID (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register +// ========== Register definition for CAN_MB2 peripheral ========== +#define AT91C_CAN_MB2_MCR (0xFFFD025C) // (CAN_MB2) MailBox Control Register +#define AT91C_CAN_MB2_MDH (0xFFFD0258) // (CAN_MB2) MailBox Data High Register +#define AT91C_CAN_MB2_MID (0xFFFD0248) // (CAN_MB2) MailBox ID Register +#define AT91C_CAN_MB2_MDL (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register +#define AT91C_CAN_MB2_MMR (0xFFFD0240) // (CAN_MB2) MailBox Mode Register +#define AT91C_CAN_MB2_MAM (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register +#define AT91C_CAN_MB2_MFID (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register +#define AT91C_CAN_MB2_MSR (0xFFFD0250) // (CAN_MB2) MailBox Status Register +// ========== Register definition for CAN_MB3 peripheral ========== +#define AT91C_CAN_MB3_MFID (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register +#define AT91C_CAN_MB3_MAM (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register +#define AT91C_CAN_MB3_MID (0xFFFD0268) // (CAN_MB3) MailBox ID Register +#define AT91C_CAN_MB3_MCR (0xFFFD027C) // (CAN_MB3) MailBox Control Register +#define AT91C_CAN_MB3_MMR (0xFFFD0260) // (CAN_MB3) MailBox Mode Register +#define AT91C_CAN_MB3_MSR (0xFFFD0270) // (CAN_MB3) MailBox Status Register +#define AT91C_CAN_MB3_MDL (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register +#define AT91C_CAN_MB3_MDH (0xFFFD0278) // (CAN_MB3) MailBox Data High Register +// ========== Register definition for CAN_MB4 peripheral ========== +#define AT91C_CAN_MB4_MID (0xFFFD0288) // (CAN_MB4) MailBox ID Register +#define AT91C_CAN_MB4_MMR (0xFFFD0280) // (CAN_MB4) MailBox Mode Register +#define AT91C_CAN_MB4_MDH (0xFFFD0298) // (CAN_MB4) MailBox Data High Register +#define AT91C_CAN_MB4_MFID (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register +#define AT91C_CAN_MB4_MSR (0xFFFD0290) // (CAN_MB4) MailBox Status Register +#define AT91C_CAN_MB4_MCR (0xFFFD029C) // (CAN_MB4) MailBox Control Register +#define AT91C_CAN_MB4_MDL (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register +#define AT91C_CAN_MB4_MAM (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB5 peripheral ========== +#define AT91C_CAN_MB5_MSR (0xFFFD02B0) // (CAN_MB5) MailBox Status Register +#define AT91C_CAN_MB5_MCR (0xFFFD02BC) // (CAN_MB5) MailBox Control Register +#define AT91C_CAN_MB5_MFID (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register +#define AT91C_CAN_MB5_MDH (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register +#define AT91C_CAN_MB5_MID (0xFFFD02A8) // (CAN_MB5) MailBox ID Register +#define AT91C_CAN_MB5_MMR (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register +#define AT91C_CAN_MB5_MDL (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register +#define AT91C_CAN_MB5_MAM (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register +// ========== Register definition for CAN_MB6 peripheral ========== +#define AT91C_CAN_MB6_MFID (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register +#define AT91C_CAN_MB6_MID (0xFFFD02C8) // (CAN_MB6) MailBox ID Register +#define AT91C_CAN_MB6_MAM (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register +#define AT91C_CAN_MB6_MSR (0xFFFD02D0) // (CAN_MB6) MailBox Status Register +#define AT91C_CAN_MB6_MDL (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register +#define AT91C_CAN_MB6_MCR (0xFFFD02DC) // (CAN_MB6) MailBox Control Register +#define AT91C_CAN_MB6_MDH (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register +#define AT91C_CAN_MB6_MMR (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register +// ========== Register definition for CAN_MB7 peripheral ========== +#define AT91C_CAN_MB7_MCR (0xFFFD02FC) // (CAN_MB7) MailBox Control Register +#define AT91C_CAN_MB7_MDH (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register +#define AT91C_CAN_MB7_MFID (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register +#define AT91C_CAN_MB7_MDL (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register +#define AT91C_CAN_MB7_MID (0xFFFD02E8) // (CAN_MB7) MailBox ID Register +#define AT91C_CAN_MB7_MMR (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register +#define AT91C_CAN_MB7_MAM (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register +#define AT91C_CAN_MB7_MSR (0xFFFD02F0) // (CAN_MB7) MailBox Status Register +// ========== Register definition for CAN peripheral ========== +#define AT91C_CAN_TCR (0xFFFD0024) // (CAN) Transfer Command Register +#define AT91C_CAN_IMR (0xFFFD000C) // (CAN) Interrupt Mask Register +#define AT91C_CAN_IER (0xFFFD0004) // (CAN) Interrupt Enable Register +#define AT91C_CAN_ECR (0xFFFD0020) // (CAN) Error Counter Register +#define AT91C_CAN_TIMESTP (0xFFFD001C) // (CAN) Time Stamp Register +#define AT91C_CAN_MR (0xFFFD0000) // (CAN) Mode Register +#define AT91C_CAN_IDR (0xFFFD0008) // (CAN) Interrupt Disable Register +#define AT91C_CAN_ACR (0xFFFD0028) // (CAN) Abort Command Register +#define AT91C_CAN_TIM (0xFFFD0018) // (CAN) Timer Register +#define AT91C_CAN_SR (0xFFFD0010) // (CAN) Status Register +#define AT91C_CAN_BR (0xFFFD0014) // (CAN) Baudrate Register +#define AT91C_CAN_VR (0xFFFD00FC) // (CAN) Version Register +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_ISR (0xFFFDC024) // (EMAC) Interrupt Status Register +#define AT91C_EMAC_SA4H (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes +#define AT91C_EMAC_SA1L (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes +#define AT91C_EMAC_ELE (0xFFFDC078) // (EMAC) Excessive Length Errors Register +#define AT91C_EMAC_LCOL (0xFFFDC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_RLE (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register +#define AT91C_EMAC_WOL (0xFFFDC0C4) // (EMAC) Wake On LAN Register +#define AT91C_EMAC_DTF (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TUND (0xFFFDC064) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_NCR (0xFFFDC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4L (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes +#define AT91C_EMAC_RSR (0xFFFDC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_SA3L (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes +#define AT91C_EMAC_TSR (0xFFFDC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_IDR (0xFFFDC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_RSE (0xFFFDC074) // (EMAC) Receive Symbol Errors Register +#define AT91C_EMAC_ECOL (0xFFFDC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_TID (0xFFFDC0B8) // (EMAC) Type ID Checking Register +#define AT91C_EMAC_HRB (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] +#define AT91C_EMAC_TBQP (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer +#define AT91C_EMAC_USRIO (0xFFFDC0C0) // (EMAC) USER Input/Output Register +#define AT91C_EMAC_PTR (0xFFFDC038) // (EMAC) Pause Time Register +#define AT91C_EMAC_SA2H (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes +#define AT91C_EMAC_ROV (0xFFFDC070) // (EMAC) Receive Overrun Errors Register +#define AT91C_EMAC_ALE (0xFFFDC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_RJA (0xFFFDC07C) // (EMAC) Receive Jabbers Register +#define AT91C_EMAC_RBQP (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_TPF (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register +#define AT91C_EMAC_NCFGR (0xFFFDC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_HRT (0xFFFDC094) // (EMAC) Hash Address Top[63:32] +#define AT91C_EMAC_USF (0xFFFDC080) // (EMAC) Undersize Frames Register +#define AT91C_EMAC_FCSE (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_TPQ (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register +#define AT91C_EMAC_MAN (0xFFFDC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_FTO (0xFFFDC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_REV (0xFFFDC0FC) // (EMAC) Revision Register +#define AT91C_EMAC_IMR (0xFFFDC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_SCF (0xFFFDC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_PFR (0xFFFDC03C) // (EMAC) Pause Frames received Register +#define AT91C_EMAC_MCF (0xFFFDC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_NSR (0xFFFDC008) // (EMAC) Network Status Register +#define AT91C_EMAC_SA2L (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes +#define AT91C_EMAC_FRO (0xFFFDC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_IER (0xFFFDC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA1H (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes +#define AT91C_EMAC_CSE (0xFFFDC068) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_SA3H (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes +#define AT91C_EMAC_RRE (0xFFFDC06C) // (EMAC) Receive Ressource Error Register +#define AT91C_EMAC_STE (0xFFFDC084) // (EMAC) SQE Test Error Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for PDC_AES peripheral ========== +#define AT91C_AES_TPR (0xFFFA4108) // (PDC_AES) Transmit Pointer Register +#define AT91C_AES_PTCR (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register +#define AT91C_AES_RNPR (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register +#define AT91C_AES_TNCR (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register +#define AT91C_AES_TCR (0xFFFA410C) // (PDC_AES) Transmit Counter Register +#define AT91C_AES_RCR (0xFFFA4104) // (PDC_AES) Receive Counter Register +#define AT91C_AES_RNCR (0xFFFA4114) // (PDC_AES) Receive Next Counter Register +#define AT91C_AES_TNPR (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register +#define AT91C_AES_RPR (0xFFFA4100) // (PDC_AES) Receive Pointer Register +#define AT91C_AES_PTSR (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register +// ========== Register definition for AES peripheral ========== +#define AT91C_AES_IVxR (0xFFFA4060) // (AES) Initialization Vector x Register +#define AT91C_AES_MR (0xFFFA4004) // (AES) Mode Register +#define AT91C_AES_VR (0xFFFA40FC) // (AES) AES Version Register +#define AT91C_AES_ODATAxR (0xFFFA4050) // (AES) Output Data x Register +#define AT91C_AES_IDATAxR (0xFFFA4040) // (AES) Input Data x Register +#define AT91C_AES_CR (0xFFFA4000) // (AES) Control Register +#define AT91C_AES_IDR (0xFFFA4014) // (AES) Interrupt Disable Register +#define AT91C_AES_IMR (0xFFFA4018) // (AES) Interrupt Mask Register +#define AT91C_AES_IER (0xFFFA4010) // (AES) Interrupt Enable Register +#define AT91C_AES_KEYWxR (0xFFFA4020) // (AES) Key Word x Register +#define AT91C_AES_ISR (0xFFFA401C) // (AES) Interrupt Status Register +// ========== Register definition for PDC_TDES peripheral ========== +#define AT91C_TDES_RNCR (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register +#define AT91C_TDES_TCR (0xFFFA810C) // (PDC_TDES) Transmit Counter Register +#define AT91C_TDES_RCR (0xFFFA8104) // (PDC_TDES) Receive Counter Register +#define AT91C_TDES_TNPR (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register +#define AT91C_TDES_RNPR (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register +#define AT91C_TDES_RPR (0xFFFA8100) // (PDC_TDES) Receive Pointer Register +#define AT91C_TDES_TNCR (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register +#define AT91C_TDES_TPR (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register +#define AT91C_TDES_PTSR (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register +#define AT91C_TDES_PTCR (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register +// ========== Register definition for TDES peripheral ========== +#define AT91C_TDES_KEY2WxR (0xFFFA8028) // (TDES) Key 2 Word x Register +#define AT91C_TDES_KEY3WxR (0xFFFA8030) // (TDES) Key 3 Word x Register +#define AT91C_TDES_IDR (0xFFFA8014) // (TDES) Interrupt Disable Register +#define AT91C_TDES_VR (0xFFFA80FC) // (TDES) TDES Version Register +#define AT91C_TDES_IVxR (0xFFFA8060) // (TDES) Initialization Vector x Register +#define AT91C_TDES_ODATAxR (0xFFFA8050) // (TDES) Output Data x Register +#define AT91C_TDES_IMR (0xFFFA8018) // (TDES) Interrupt Mask Register +#define AT91C_TDES_MR (0xFFFA8004) // (TDES) Mode Register +#define AT91C_TDES_CR (0xFFFA8000) // (TDES) Control Register +#define AT91C_TDES_IER (0xFFFA8010) // (TDES) Interrupt Enable Register +#define AT91C_TDES_ISR (0xFFFA801C) // (TDES) Interrupt Status Register +#define AT91C_TDES_IDATAxR (0xFFFA8040) // (TDES) Input Data x Register +#define AT91C_TDES_KEY1WxR (0xFFFA8020) // (TDES) Key 1 Word x Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_NPCS00 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_NPCS01 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_NPCS02 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1 +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_NPCS03 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_MISO0 (AT91C_PIO_PA16) // SPI 0 Master In Slave +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_MOSI0 (AT91C_PIO_PA17) // SPI 0 Master Out Slave +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_SPCK0 (AT91C_PIO_PA18) // SPI 0 Serial Clock +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock +#define AT91C_PA2_NPCS11 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync +#define AT91C_PA21_NPCS10 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock +#define AT91C_PA22_SPCK1 (AT91C_PIO_PA22) // SPI 1 Serial Clock +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data +#define AT91C_PA23_MOSI1 (AT91C_PIO_PA23) // SPI 1 Master Out Slave +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data +#define AT91C_PA24_MISO1 (AT91C_PIO_PA24) // SPI 1 Master In Slave +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock +#define AT91C_PA25_NPCS11 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync +#define AT91C_PA26_NPCS12 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data +#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input +#define AT91C_PA29_NPCS13 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send +#define AT91C_PA3_NPCS12 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0 +#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send +#define AT91C_PA4_NPCS13 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock +#define AT91C_PA7_NPCS01 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send +#define AT91C_PA8_NPCS02 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send +#define AT91C_PA9_NPCS03 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 +#define AT91C_PB10_NPCS11 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 +#define AT91C_PB11_NPCS12 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error +#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 +#define AT91C_PB13_NPCS01 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 +#define AT91C_PB14_NPCS02 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_ERXDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected +#define AT91C_PB16_NPCS13 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock +#define AT91C_PB17_NPCS03 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0 +#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1 +#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3 +#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2 +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1 +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1 +#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2 +#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_ECRS_ECRSDV (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0 +#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_CAN (15) // Control Area Network Controller +#define AT91C_ID_EMAC (16) // Ethernet MAC +#define AT91C_ID_ADC (17) // Analog-to-Digital Converter +#define AT91C_ID_AES (18) // Advanced Encryption Standard 128-bit +#define AT91C_ID_TDES (19) // Triple Data Encryption Standard +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_29_Reserved (29) // Reserved +#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_PDC_SPI1 (0xFFFE4100) // (PDC_SPI1) Base Address +#define AT91C_BASE_SPI1 (0xFFFE4000) // (SPI1) Base Address +#define AT91C_BASE_PDC_SPI0 (0xFFFE0100) // (PDC_SPI0) Base Address +#define AT91C_BASE_SPI0 (0xFFFE0000) // (SPI0) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_CAN_MB0 (0xFFFD0200) // (CAN_MB0) Base Address +#define AT91C_BASE_CAN_MB1 (0xFFFD0220) // (CAN_MB1) Base Address +#define AT91C_BASE_CAN_MB2 (0xFFFD0240) // (CAN_MB2) Base Address +#define AT91C_BASE_CAN_MB3 (0xFFFD0260) // (CAN_MB3) Base Address +#define AT91C_BASE_CAN_MB4 (0xFFFD0280) // (CAN_MB4) Base Address +#define AT91C_BASE_CAN_MB5 (0xFFFD02A0) // (CAN_MB5) Base Address +#define AT91C_BASE_CAN_MB6 (0xFFFD02C0) // (CAN_MB6) Base Address +#define AT91C_BASE_CAN_MB7 (0xFFFD02E0) // (CAN_MB7) Base Address +#define AT91C_BASE_CAN (0xFFFD0000) // (CAN) Base Address +#define AT91C_BASE_EMAC (0xFFFDC000) // (EMAC) Base Address +#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_PDC_AES (0xFFFA4100) // (PDC_AES) Base Address +#define AT91C_BASE_AES (0xFFFA4000) // (AES) Base Address +#define AT91C_BASE_PDC_TDES (0xFFFA8100) // (PDC_TDES) Base Address +#define AT91C_BASE_TDES (0xFFFA8000) // (TDES) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbyte) +#define AT91C_IFLASH (0x00100000) // Internal ROM base address +#define AT91C_IFLASH_SIZE (0x00040000) // Internal ROM size in byte (256 Kbyte) + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h new file mode 100644 index 0000000..18e0b3b --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h
@@ -0,0 +1,105 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h new file mode 100644 index 0000000..9d012c4 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
@@ -0,0 +1,3265 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7S64.h +//* Object : AT91SAM7S64 inlined functions +//* Generated : AT91 SW Application Group 07/16/2004 (07:43:09) +//* +//* CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003// +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// +//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002// +//*---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7S64_H +#define lib_AT91SAM7S64_H + +/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg endpoints to be enabled +{ + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg endpoints to be enabled +{ + pUDP->UDP_GLBSTATE &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA10_DTXD ) | + ((unsigned int) AT91C_PA9_DRXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA14_PWM3 ) | + ((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PA25_PWM2 ) | + ((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PA24_PWM1 ) | + ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PA23_PWM0 ) | + ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA17_TD ) | + ((unsigned int) AT91C_PA15_TF ) | + ((unsigned int) AT91C_PA19_RK ) | + ((unsigned int) AT91C_PA18_RD ) | + ((unsigned int) AT91C_PA20_RF ) | + ((unsigned int) AT91C_PA16_TK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPIO +//* \brief Configure PIO controllers to drive SPI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_NPCS0 ) | + ((unsigned int) AT91C_PA13_MOSI ) | + ((unsigned int) AT91C_PA31_NPCS1 ) | + ((unsigned int) AT91C_PA12_MISO ) | + ((unsigned int) AT91C_PA14_SPCK ), // Peripheral A + ((unsigned int) AT91C_PA9_NPCS1 ) | + ((unsigned int) AT91C_PA30_NPCS2 ) | + ((unsigned int) AT91C_PA10_NPCS2 ) | + ((unsigned int) AT91C_PA22_NPCS3 ) | + ((unsigned int) AT91C_PA3_NPCS3 ) | + ((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA26_TIOA2 ) | + ((unsigned int) AT91C_PA27_TIOB2 ) | + ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TIOA1 ) | + ((unsigned int) AT91C_PA16_TIOB1 ) | + ((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA0_TIOA0 ) | + ((unsigned int) AT91C_PA1_TIOB0 ) | + ((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA17_PCK1 ) | + ((unsigned int) AT91C_PA21_PCK1 ) | + ((unsigned int) AT91C_PA31_PCK2 ) | + ((unsigned int) AT91C_PA18_PCK2 ) | + ((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA3_TWD ) | + ((unsigned int) AT91C_PA4_TWCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA21_RXD1 ) | + ((unsigned int) AT91C_PA27_DTR1 ) | + ((unsigned int) AT91C_PA26_DCD1 ) | + ((unsigned int) AT91C_PA22_TXD1 ) | + ((unsigned int) AT91C_PA24_RTS1 ) | + ((unsigned int) AT91C_PA23_SCK1 ) | + ((unsigned int) AT91C_PA28_DSR1 ) | + ((unsigned int) AT91C_PA29_RI1 ) | + ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA5_RXD0 ) | + ((unsigned int) AT91C_PA6_TXD0 ) | + ((unsigned int) AT91C_PA7_RTS0 ) | + ((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A + ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A + ((unsigned int) AT91C_PA20_IRQ0 ) | + ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B +} + +#endif // lib_AT91SAM7S64_H
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h new file mode 100644 index 0000000..805a2bc --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
@@ -0,0 +1,4558 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X128.h +//* Object : AT91SAM7X128 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:23) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7X128_H +#define lib_AT91SAM7X128_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in µsecond, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR CAN + ***************************************************************************** */ +#define STANDARD_FORMAT 0 +#define EXTENDED_FORMAT 1 + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitMailboxRegisters() +//* \brief Configure the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, + int mode_reg, + int acceptance_mask_reg, + int id_reg, + int data_low_reg, + int data_high_reg, + int control_reg) +{ + CAN_Mailbox->CAN_MB_MCR = 0x0; + CAN_Mailbox->CAN_MB_MMR = mode_reg; + CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; + CAN_Mailbox->CAN_MB_MID = id_reg; + CAN_Mailbox->CAN_MB_MDL = data_low_reg; + CAN_Mailbox->CAN_MB_MDH = data_high_reg; + CAN_Mailbox->CAN_MB_MCR = control_reg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EnableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_EnableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR |= AT91C_CAN_CANEN; + + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DisableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_DisableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR &= ~AT91C_CAN_CANEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_EnableIt +//* \brief Enable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_EnableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pCAN->CAN_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_DisableIt +//* \brief Disable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_DisableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pCAN->CAN_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetStatus +//* \brief Return CAN Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInterruptMaskStatus +//* \brief Return CAN Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsInterruptMasked +//* \brief Test if CAN Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsInterruptMasked( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsStatusSet +//* \brief Test if CAN Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsStatusSet( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgModeReg +//* \brief Configure the Mode Register of the CAN controller +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgModeReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pCAN->CAN_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetModeReg +//* \brief Return the Mode Register of the CAN controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetModeReg ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgBaudrateReg +//* \brief Configure the Baudrate of the CAN controller for the network +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgBaudrateReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int baudrate_cfg) +{ + //* Write to the BR register + pCAN->CAN_BR = baudrate_cfg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetBaudrate +//* \brief Return the Baudrate of the CAN controller for the network value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetBaudrate ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_BR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInternalCounter +//* \brief Return CAN Timer Regsiter Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInternalCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetTimestamp +//* \brief Return CAN Timestamp Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetTimestamp ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIMESTP; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetErrorCounter +//* \brief Return CAN Error Counter Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetErrorCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_ECR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitTransferRequest +//* \brief Request for a transfer on the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitTransferRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int transfer_cmd) +{ + pCAN->CAN_TCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitAbortRequest +//* \brief Abort the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitAbortRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int abort_cmd) +{ + pCAN->CAN_ACR = abort_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageModeReg +//* \brief Program the Message Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mode) +{ + CAN_Mailbox->CAN_MB_MMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageModeReg +//* \brief Return the Message Mode Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageIDReg +//* \brief Program the Message ID Register +//* \brief Version == 0 for Standard messsage, Version == 1 for Extended +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int id, + unsigned char version) +{ + if(version==0) // IDvA Standard Format + CAN_Mailbox->CAN_MB_MID = id<<18; + else // IDvB Extended Format + CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageIDReg +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg +//* \brief Program the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mask) +{ + CAN_Mailbox->CAN_MB_MAM = mask; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg +//* \brief Return the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MAM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetFamilyID +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetFamilyID ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MFID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageCtrl +//* \brief Request and config for a transfer on the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageCtrlReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int message_ctrl_cmd) +{ + CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageStatus +//* \brief Return CAN Mailbox Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageStatus ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataLow +//* \brief Program data low value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDL = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataLow +//* \brief Return data low value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataHigh +//* \brief Program data high value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDH = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataHigh +//* \brief Return data high value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDH; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_Open +//* \brief Open a CAN Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR AES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_EnableIt +//* \brief Enable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_EnableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pAES->AES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_DisableIt +//* \brief Disable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_DisableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pAES->AES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetStatus +//* \brief Return AES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetInterruptMaskStatus +//* \brief Return AES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsInterruptMasked +//* \brief Test if AES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsInterruptMasked( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsStatusSet +//* \brief Test if AES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsStatusSet( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgModeReg +//* \brief Configure the Mode Register of the AES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgModeReg ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pAES->AES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetModeReg +//* \brief Return the Mode Register of the AES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetModeReg ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + return pAES->AES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_StartProcessing ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SoftReset +//* \brief Reset AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SoftReset ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_LoadNewSeed +//* \brief Load New Seed in the random number generator +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_LoadNewSeed ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_LOADSEED; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetCryptoKey +//* \brief Set Cryptographic Key x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetCryptoKey ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int keyword + ) +{ + pAES->AES_KEYWxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_InputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int indata + ) +{ + pAES->AES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetOutputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index + ) +{ + return pAES->AES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetInitializationVector +//* \brief Set Initialization Vector (or Counter) x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetInitializationVector ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int initvector + ) +{ + pAES->AES_IVxR[index] = initvector; +} + +/* ***************************************************************************** + SOFTWARE API FOR TDES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_EnableIt +//* \brief Enable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_EnableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pTDES->TDES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_DisableIt +//* \brief Disable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_DisableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pTDES->TDES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetStatus +//* \brief Return TDES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetInterruptMaskStatus +//* \brief Return TDES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsInterruptMasked +//* \brief Test if TDES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsInterruptMasked( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsStatusSet +//* \brief Test if TDES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsStatusSet( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgModeReg +//* \brief Configure the Mode Register of the TDES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgModeReg ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pTDES->TDES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetModeReg +//* \brief Return the Mode Register of the TDES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetModeReg ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + return pTDES->TDES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_StartProcessing ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SoftReset +//* \brief Reset TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SoftReset ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey1 +//* \brief Set Cryptographic Key 1 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey1 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY1WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey2 +//* \brief Set Cryptographic Key 2 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey2 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY2WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey3 +//* \brief Set Cryptographic Key 3 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey3 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY3WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_InputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int indata + ) +{ + pTDES->TDES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetOutputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index + ) +{ + return pTDES->TDES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetInitializationVector +//* \brief Set Initialization Vector x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetInitializationVector ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int initvector + ) +{ + pTDES->TDES_IVxR[index] = initvector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA27_DRXD ) | + ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB30_PCK2 ) | + ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A + ((unsigned int) AT91C_PB20_PCK0 ) | + ((unsigned int) AT91C_PB0_PCK0 ) | + ((unsigned int) AT91C_PB22_PCK2 ) | + ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA30_PCK2 ) | + ((unsigned int) AT91C_PA13_PCK1 ) | + ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_RK ) | + ((unsigned int) AT91C_PA22_TK ) | + ((unsigned int) AT91C_PA21_TF ) | + ((unsigned int) AT91C_PA24_RD ) | + ((unsigned int) AT91C_PA26_RF ) | + ((unsigned int) AT91C_PA23_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB26_RI1 ) | + ((unsigned int) AT91C_PB24_DSR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA7_SCK1 ) | + ((unsigned int) AT91C_PA8_RTS1 ) | + ((unsigned int) AT91C_PA6_TXD1 ) | + ((unsigned int) AT91C_PA5_RXD1 ) | + ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_RXD0 ) | + ((unsigned int) AT91C_PA4_CTS0 ) | + ((unsigned int) AT91C_PA3_RTS0 ) | + ((unsigned int) AT91C_PA2_SCK0 ) | + ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI1 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPIO +//* \brief Configure PIO controllers to drive SPI1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB16_NPCS13 ) | + ((unsigned int) AT91C_PB10_NPCS11 ) | + ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA4_NPCS13 ) | + ((unsigned int) AT91C_PA29_NPCS13 ) | + ((unsigned int) AT91C_PA21_NPCS10 ) | + ((unsigned int) AT91C_PA22_SPCK1 ) | + ((unsigned int) AT91C_PA25_NPCS11 ) | + ((unsigned int) AT91C_PA2_NPCS11 ) | + ((unsigned int) AT91C_PA24_MISO1 ) | + ((unsigned int) AT91C_PA3_NPCS12 ) | + ((unsigned int) AT91C_PA26_NPCS12 ) | + ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI0 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPIO +//* \brief Configure PIO controllers to drive SPI0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB13_NPCS01 ) | + ((unsigned int) AT91C_PB17_NPCS03 ) | + ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA16_MISO0 ) | + ((unsigned int) AT91C_PA13_NPCS01 ) | + ((unsigned int) AT91C_PA15_NPCS03 ) | + ((unsigned int) AT91C_PA17_MOSI0 ) | + ((unsigned int) AT91C_PA18_SPCK0 ) | + ((unsigned int) AT91C_PA14_NPCS02 ) | + ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A + ((unsigned int) AT91C_PA7_NPCS01 ) | + ((unsigned int) AT91C_PA9_NPCS03 ) | + ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ0 ) | + ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A + ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgPMC +//* \brief Enable Peripheral clock in PMC for AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_AES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_TWCK ) | + ((unsigned int) AT91C_PA10_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A + ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgPMC +//* \brief Enable Peripheral clock in PMC for TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TDES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB2_ETX0 ) | + ((unsigned int) AT91C_PB12_ETXER ) | + ((unsigned int) AT91C_PB16_ECOL ) | + ((unsigned int) AT91C_PB11_ETX3 ) | + ((unsigned int) AT91C_PB6_ERX1 ) | + ((unsigned int) AT91C_PB15_ERXDV ) | + ((unsigned int) AT91C_PB13_ERX2 ) | + ((unsigned int) AT91C_PB3_ETX1 ) | + ((unsigned int) AT91C_PB8_EMDC ) | + ((unsigned int) AT91C_PB5_ERX0 ) | + //((unsigned int) AT91C_PB18_EF100 ) | + ((unsigned int) AT91C_PB14_ERX3 ) | + ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | + ((unsigned int) AT91C_PB1_ETXEN ) | + ((unsigned int) AT91C_PB10_ETX2 ) | + ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | + ((unsigned int) AT91C_PB9_EMDIO ) | + ((unsigned int) AT91C_PB7_ERXER ) | + ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB23_TIOA0 ) | + ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A + ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB25_TIOA1 ) | + ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A + ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB28_TIOB2 ) | + ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPMC +//* \brief Enable Peripheral clock in PMC for CAN +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_CAN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPIO +//* \brief Configure PIO controllers to drive CAN signals +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA20_CANTX ) | + ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7X128_H
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h new file mode 100644 index 0000000..02ee900 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
@@ -0,0 +1,4558 @@ +//* ---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//* ---------------------------------------------------------------------------- +//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//* ---------------------------------------------------------------------------- +//* File Name : lib_AT91SAM7X256.h +//* Object : AT91SAM7X256 inlined functions +//* Generated : AT91 SW Application Group 05/20/2005 (16:22:29) +//* +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_pmc_SAM7X.h/1.1/Tue Feb 1 08:32:10 2005// +//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// +//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// +//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003// +//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// +//* CVS Reference : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005// +//* CVS Reference : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005// +//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// +//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// +//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// +//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005// +//* CVS Reference : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003// +//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// +//* ---------------------------------------------------------------------------- + +#ifndef lib_AT91SAM7X256_H +#define lib_AT91SAM7X256_H + +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +__inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +__inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkEnableReg +//* \brief Configure the System Clock Enable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkEnableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCER register + pPMC->PMC_SCER = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgSysClkDisableReg +//* \brief Configure the System Clock Disable Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgSysClkDisableReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + //* Write to the SCDR register + pPMC->PMC_SCDR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetSysClkStatusReg +//* \brief Return the System Clock Status Register of the PMC controller +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetSysClkStatusReg ( + AT91PS_PMC pPMC // pointer to a CAN controller + ) +{ + return pPMC->PMC_SCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Disable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetPeriphClock +//* \brief Get peripheral clock status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetPeriphClock ( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_PCSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscillatorReg ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int mode) +{ + pCKGR->CKGR_MOR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainOscillatorReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MOR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_EnableMainOscillator +//* \brief Enable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_EnableMainOscillator( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_DisableMainOscillator +//* \brief Disable the main oscillator +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_DisableMainOscillator ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_CfgMainOscStartUpTime +//* \brief Cfg MOR Register according to the main osc startup time +//*---------------------------------------------------------------------------- +__inline void AT91F_CKGR_CfgMainOscStartUpTime ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int startup_time, // \arg main osc startup time in microsecond (us) + unsigned int slowClock) // \arg slowClock in Hz +{ + pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; + pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClockFreqReg +//* \brief Cfg the main oscillator +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( + AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller +{ + return pCKGR->CKGR_MCFR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgMCKReg +//* \brief Cfg Master Clock Register +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgMCKReg ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int mode) +{ + pPMC->PMC_MCKR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMCKReg +//* \brief Return Master Clock Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetMCKReg( + AT91PS_PMC pPMC) // \arg pointer to PMC controller +{ + return pPMC->PMC_MCKR; +} + +//*------------------------------------------------------------------------------ +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz which correponds to processor clock for ARM7 +//*------------------------------------------------------------------------------ +__inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLR; + pllDivider = (reg & AT91C_CKGR_DIV); + pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int mode) +{ + pPMC->PMC_PCKR[pck] = mode; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnableIt +//* \brief Enable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_EnableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pPMC->PMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisableIt +//* \brief Disable PMC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_DisableIt ( + AT91PS_PMC pPMC, // pointer to a PMC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pPMC->PMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetStatus +//* \brief Return PMC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetInterruptMaskStatus +//* \brief Return PMC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status + AT91PS_PMC pPMC) // pointer to a PMC controller +{ + return pPMC->PMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsInterruptMasked +//* \brief Test if PMC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsInterruptMasked( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_IsStatusSet +//* \brief Test if PMC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PMC_IsStatusSet( + AT91PS_PMC pPMC, // \arg pointer to a PMC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PMC_GetStatus(pPMC) & flag); +}/* ***************************************************************************** + SOFTWARE API FOR RSTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSoftReset +//* \brief Start Software Reset +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSoftReset( + AT91PS_RSTC pRSTC, + unsigned int reset) +{ + pRSTC->RSTC_RCR = (0xA5000000 | reset); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTSetMode +//* \brief Set Reset Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTSetMode( + AT91PS_RSTC pRSTC, + unsigned int mode) +{ + pRSTC->RSTC_RMR = (0xA5000000 | mode); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetMode +//* \brief Get Reset Mode +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetMode( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTGetStatus +//* \brief Get Reset Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTGetStatus( + AT91PS_RSTC pRSTC) +{ + return (pRSTC->RSTC_RSR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTIsSoftRstActive +//* \brief Return !=0 if software reset is still not completed +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_RSTIsSoftRstActive( + AT91PS_RSTC pRSTC) +{ + return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); +} +/* ***************************************************************************** + SOFTWARE API FOR RTTC + ***************************************************************************** */ +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_SetRTT_TimeBase() +//* \brief Set the RTT prescaler according to the TimeBase in ms +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetTimeBase( + AT91PS_RTTC pRTTC, + unsigned int ms) +{ + if (ms > 2000) + return 1; // AT91C_TIME_OUT_OF_RANGE + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); + return 0; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTSetPrescaler() +//* \brief Set the new prescaler value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTSetPrescaler( + AT91PS_RTTC pRTTC, + unsigned int rtpres) +{ + pRTTC->RTTC_RTMR &= ~0xFFFF; + pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); + return (pRTTC->RTTC_RTMR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTRestart() +//* \brief Restart the RTT prescaler +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTRestart( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; +} + + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmINT() +//* \brief Enable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearAlarmINT() +//* \brief Disable RTT Alarm Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearAlarmINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetRttIncINT() +//* \brief Enable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ClearRttIncINT() +//* \brief Disable RTT INC Interrupt +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTClearRttIncINT( + AT91PS_RTTC pRTTC) +{ + pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_SetAlarmValue() +//* \brief Set RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline void AT91F_RTTSetAlarmValue( + AT91PS_RTTC pRTTC, unsigned int alarm) +{ + pRTTC->RTTC_RTAR = alarm; +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_GetAlarmValue() +//* \brief Get RTT Alarm Value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetAlarmValue( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTAR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTTGetStatus() +//* \brief Read the RTT status +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTGetStatus( + AT91PS_RTTC pRTTC) +{ + return(pRTTC->RTTC_RTSR); +} + +//*-------------------------------------------------------------------------------------- +//* \fn AT91F_RTT_ReadValue() +//* \brief Read the RTT value +//*-------------------------------------------------------------------------------------- +__inline unsigned int AT91F_RTTReadValue( + AT91PS_RTTC pRTTC) +{ + register volatile unsigned int val1,val2; + do + { + val1 = pRTTC->RTTC_RTVR; + val2 = pRTTC->RTTC_RTVR; + } + while(val1 != val2); + return(val1); +} +/* ***************************************************************************** + SOFTWARE API FOR PITC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITInit +//* \brief System timer init : period in µsecond, system clock freq in MHz +//*---------------------------------------------------------------------------- +__inline void AT91F_PITInit( + AT91PS_PITC pPITC, + unsigned int period, + unsigned int pit_frequency) +{ + pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 + pPITC->PITC_PIMR |= AT91C_PITC_PITEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITSetPIV +//* \brief Set the PIT Periodic Interval Value +//*---------------------------------------------------------------------------- +__inline void AT91F_PITSetPIV( + AT91PS_PITC pPITC, + unsigned int piv) +{ + pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITEnableInt +//* \brief Enable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITEnableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITDisableInt +//* \brief Disable PIT periodic interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PITDisableInt( + AT91PS_PITC pPITC) +{ + pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetMode +//* \brief Read PIT mode register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetMode( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIMR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetStatus +//* \brief Read PIT status register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetStatus( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PISR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIIR +//* \brief Read PIT CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIIR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIIR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITGetPIVR +//* \brief Read System timer CPIV and PICNT without ressetting the counters +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PITGetPIVR( + AT91PS_PITC pPITC) +{ + return(pPITC->PITC_PIVR); +} +/* ***************************************************************************** + SOFTWARE API FOR WDTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSetMode +//* \brief Set Watchdog Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTSetMode( + AT91PS_WDTC pWDTC, + unsigned int Mode) +{ + pWDTC->WDTC_WDMR = Mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTRestart +//* \brief Restart Watchdog +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTRestart( + AT91PS_WDTC pWDTC) +{ + pWDTC->WDTC_WDCR = 0xA5000001; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTSGettatus +//* \brief Get Watchdog Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTSGettatus( + AT91PS_WDTC pWDTC) +{ + return(pWDTC->WDTC_WDSR & 0x3); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTGetPeriod +//* \brief Translate ms into Watchdog Compatible value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) +{ + if ((ms < 4) || (ms > 16000)) + return 0; + return((ms << 8) / 1000); +} +/* ***************************************************************************** + SOFTWARE API FOR VREG + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Enable_LowPowerMode +//* \brief Enable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Enable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR |= AT91C_VREG_PSTDBY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_Disable_LowPowerMode +//* \brief Disable VREG Low Power Mode +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_Disable_LowPowerMode( + AT91PS_VREG pVREG) +{ + pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; +}/* ***************************************************************************** + SOFTWARE API FOR MC + ***************************************************************************** */ + +#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_Remap +//* \brief Make Remap +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_Remap (void) // +{ + AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; + + pMC->MC_RCR = AT91C_MC_RCB; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_CfgModeReg +//* \brief Configure the EFC Mode Register of the MC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_CfgModeReg ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int mode) // mode register +{ + // Write to the FMR register + pMC->MC_FMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetModeReg +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetModeReg( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_ComputeFMCN +//* \brief Return MC EFC Mode Regsiter +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_ComputeFMCN( + int master_clock) // master clock in Hz +{ + return (master_clock/1000000 +2); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_PerformCmd +//* \brief Perform EFC Command +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_EFC_PerformCmd ( + AT91PS_MC pMC, // pointer to a MC controller + unsigned int transfer_cmd) +{ + pMC->MC_FCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_GetStatus +//* \brief Return MC EFC Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_GetStatus( + AT91PS_MC pMC) // pointer to a MC controller +{ + return pMC->MC_FSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptMasked +//* \brief Test if EFC MC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptMasked( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetModeReg(pMC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_EFC_IsInterruptSet +//* \brief Test if EFC MC Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_MC_EFC_IsInterruptSet( + AT91PS_MC pMC, // \arg pointer to a MC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_MC_EFC_GetStatus(pMC) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgCs ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(pSPI->SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +__inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +__inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +__inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +__inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +__inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +__inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +__inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PWMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetStatus +//* \brief Return PWM Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status + AT91PS_PWMC pPWM) // pointer to a PWM controller +{ + return pPWM->PWMC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptEnable +//* \brief Enable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptEnable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be enabled +{ + pPwm->PWMC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_InterruptDisable +//* \brief Disable PWM Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_InterruptDisable( + AT91PS_PWMC pPwm, // \arg pointer to a PWM controller + unsigned int flag) // \arg PWM interrupt to be disabled +{ + pPwm->PWMC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_GetInterruptMaskStatus +//* \brief Return PWM Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status + AT91PS_PWMC pPwm) // \arg pointer to a PWM controller +{ + return pPwm->PWMC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsInterruptMasked +//* \brief Test if PWM Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsInterruptMasked( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_IsStatusSet +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_PWMC_IsStatusSet( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PWMC_GetStatus(pPWM) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_CfgChannel +//* \brief Test if PWM Interrupt is Set +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int mode, // \arg PWM mode + unsigned int period, // \arg PWM period + unsigned int duty) // \arg PWM duty cycle +{ + pPWM->PWMC_CH[channelId].PWMC_CMR = mode; + pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; + pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StartChannel +//* \brief Enable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StartChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_ENA = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_StopChannel +//* \brief Disable channel +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_StopChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int flag) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_DIS = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWM_UpdateChannel +//* \brief Update Period or Duty Cycle +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_UpdateChannel( + AT91PS_PWMC pPWM, // \arg pointer to a PWM controller + unsigned int channelId, // \arg PWM channel ID + unsigned int update) // \arg Channels IDs to be enabled +{ + pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; +} + +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; + pUDP->UDP_RSTEP = 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR CAN + ***************************************************************************** */ +#define STANDARD_FORMAT 0 +#define EXTENDED_FORMAT 1 + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitMailboxRegisters() +//* \brief Configure the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB CAN_Mailbox, + int mode_reg, + int acceptance_mask_reg, + int id_reg, + int data_low_reg, + int data_high_reg, + int control_reg) +{ + CAN_Mailbox->CAN_MB_MCR = 0x0; + CAN_Mailbox->CAN_MB_MMR = mode_reg; + CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; + CAN_Mailbox->CAN_MB_MID = id_reg; + CAN_Mailbox->CAN_MB_MDL = data_low_reg; + CAN_Mailbox->CAN_MB_MDH = data_high_reg; + CAN_Mailbox->CAN_MB_MCR = control_reg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EnableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_EnableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR |= AT91C_CAN_CANEN; + + // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver + while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DisableCAN() +//* \brief +//*---------------------------------------------------------------------------- +__inline void AT91F_DisableCAN( + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + pCAN->CAN_MR &= ~AT91C_CAN_CANEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_EnableIt +//* \brief Enable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_EnableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pCAN->CAN_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_DisableIt +//* \brief Disable CAN interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_DisableIt ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pCAN->CAN_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetStatus +//* \brief Return CAN Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInterruptMaskStatus +//* \brief Return CAN Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status + AT91PS_CAN pCAN) // pointer to a CAN controller +{ + return pCAN->CAN_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsInterruptMasked +//* \brief Test if CAN Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsInterruptMasked( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_IsStatusSet +//* \brief Test if CAN Interrupt is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_IsStatusSet( + AT91PS_CAN pCAN, // \arg pointer to a CAN controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_CAN_GetStatus(pCAN) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgModeReg +//* \brief Configure the Mode Register of the CAN controller +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgModeReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pCAN->CAN_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetModeReg +//* \brief Return the Mode Register of the CAN controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetModeReg ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgBaudrateReg +//* \brief Configure the Baudrate of the CAN controller for the network +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgBaudrateReg ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int baudrate_cfg) +{ + //* Write to the BR register + pCAN->CAN_BR = baudrate_cfg; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetBaudrate +//* \brief Return the Baudrate of the CAN controller for the network value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetBaudrate ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_BR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetInternalCounter +//* \brief Return CAN Timer Regsiter Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetInternalCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetTimestamp +//* \brief Return CAN Timestamp Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetTimestamp ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_TIMESTP; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetErrorCounter +//* \brief Return CAN Error Counter Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetErrorCounter ( + AT91PS_CAN pCAN // pointer to a CAN controller + ) +{ + return pCAN->CAN_ECR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitTransferRequest +//* \brief Request for a transfer on the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitTransferRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int transfer_cmd) +{ + pCAN->CAN_TCR = transfer_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_InitAbortRequest +//* \brief Abort the corresponding mailboxes +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_InitAbortRequest ( + AT91PS_CAN pCAN, // pointer to a CAN controller + unsigned int abort_cmd) +{ + pCAN->CAN_ACR = abort_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageModeReg +//* \brief Program the Message Mode Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mode) +{ + CAN_Mailbox->CAN_MB_MMR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageModeReg +//* \brief Return the Message Mode Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageModeReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageIDReg +//* \brief Program the Message ID Register +//* \brief Version == 0 for Standard messsage, Version == 1 for Extended +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int id, + unsigned char version) +{ + if(version==0) // IDvA Standard Format + CAN_Mailbox->CAN_MB_MID = id<<18; + else // IDvB Extended Format + CAN_Mailbox->CAN_MB_MID = id | (1<<29); // set MIDE bit +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageIDReg +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageIDReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg +//* \brief Program the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int mask) +{ + CAN_Mailbox->CAN_MB_MAM = mask; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg +//* \brief Return the Message Acceptance Mask Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MAM; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetFamilyID +//* \brief Return the Message ID Register +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetFamilyID ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MFID; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageCtrl +//* \brief Request and config for a transfer on the corresponding mailbox +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageCtrlReg ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int message_ctrl_cmd) +{ + CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageStatus +//* \brief Return CAN Mailbox Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageStatus ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataLow +//* \brief Program data low value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDL = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataLow +//* \brief Return data low value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataLow ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgMessageDataHigh +//* \brief Program data high value +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox + unsigned int data) +{ + CAN_Mailbox->CAN_MB_MDH = data; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_GetMessageDataHigh +//* \brief Return data high value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_GetMessageDataHigh ( + AT91PS_CAN_MB CAN_Mailbox) // pointer to a CAN Mailbox +{ + return CAN_Mailbox->CAN_MB_MDH; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_Open +//* \brief Open a CAN Port +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_CAN_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} +/* ***************************************************************************** + SOFTWARE API FOR ADC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableIt +//* \brief Enable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pADC->ADC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableIt +//* \brief Disable ADC interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableIt ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pADC->ADC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetStatus +//* \brief Return ADC Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_SR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetInterruptMaskStatus +//* \brief Return ADC Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status + AT91PS_ADC pADC) // pointer to a ADC controller +{ + return pADC->ADC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsInterruptMasked +//* \brief Test if ADC Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsInterruptMasked( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_IsStatusSet +//* \brief Test if ADC Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_IsStatusSet( + AT91PS_ADC pADC, // \arg pointer to a ADC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ADC_GetStatus(pADC) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgModeReg +//* \brief Configure the Mode Register of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgModeReg ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pADC->ADC_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetModeReg +//* \brief Return the Mode Register of the ADC controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetModeReg ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgTimings +//* \brief Configure the different necessary timings of the ADC controller +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgTimings ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int mck_clock, // in MHz + unsigned int adc_clock, // in MHz + unsigned int startup_time, // in us + unsigned int sample_and_hold_time) // in ns +{ + unsigned int prescal,startup,shtim; + + prescal = mck_clock/(2*adc_clock) - 1; + startup = adc_clock*startup_time/8 - 1; + shtim = adc_clock*sample_and_hold_time/1000 - 1; + + //* Write to the MR register + pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_EnableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_EnableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHER register + pADC->ADC_CHER = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_DisableChannel +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_DisableChannel ( + AT91PS_ADC pADC, // pointer to a ADC controller + unsigned int channel) // mode register +{ + //* Write to the CHDR register + pADC->ADC_CHDR = channel; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetChannelStatus +//* \brief Return ADC Timer Register Value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetChannelStatus ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CHSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_StartConversion +//* \brief Software request for a analog to digital conversion +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_StartConversion ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_SoftReset +//* \brief Software reset +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_SoftReset ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + pADC->ADC_CR = AT91C_ADC_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetLastConvertedData +//* \brief Return the Last Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetLastConvertedData ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_LCDR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH0 +//* \brief Return the Channel 0 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH1 +//* \brief Return the Channel 1 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR1; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH2 +//* \brief Return the Channel 2 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR2; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH3 +//* \brief Return the Channel 3 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR3; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH4 +//* \brief Return the Channel 4 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH5 +//* \brief Return the Channel 5 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR5; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH6 +//* \brief Return the Channel 6 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR6; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_GetConvertedDataCH7 +//* \brief Return the Channel 7 Converted Data +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( + AT91PS_ADC pADC // pointer to a ADC controller + ) +{ + return pADC->ADC_CDR7; +} + +/* ***************************************************************************** + SOFTWARE API FOR AES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_EnableIt +//* \brief Enable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_EnableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pAES->AES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_DisableIt +//* \brief Disable AES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_DisableIt ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pAES->AES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetStatus +//* \brief Return AES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetInterruptMaskStatus +//* \brief Return AES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status + AT91PS_AES pAES) // pointer to a AES controller +{ + return pAES->AES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsInterruptMasked +//* \brief Test if AES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsInterruptMasked( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_IsStatusSet +//* \brief Test if AES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_IsStatusSet( + AT91PS_AES pAES, // \arg pointer to a AES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_AES_GetStatus(pAES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgModeReg +//* \brief Configure the Mode Register of the AES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgModeReg ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pAES->AES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetModeReg +//* \brief Return the Mode Register of the AES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetModeReg ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + return pAES->AES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_StartProcessing ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SoftReset +//* \brief Reset AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SoftReset ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_LoadNewSeed +//* \brief Load New Seed in the random number generator +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_LoadNewSeed ( + AT91PS_AES pAES // pointer to a AES controller + ) +{ + pAES->AES_CR = AT91C_AES_LOADSEED; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetCryptoKey +//* \brief Set Cryptographic Key x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetCryptoKey ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int keyword + ) +{ + pAES->AES_KEYWxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_InputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int indata + ) +{ + pAES->AES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_AES_GetOutputData ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index + ) +{ + return pAES->AES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_SetInitializationVector +//* \brief Set Initialization Vector (or Counter) x +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_SetInitializationVector ( + AT91PS_AES pAES, // pointer to a AES controller + unsigned char index, + unsigned int initvector + ) +{ + pAES->AES_IVxR[index] = initvector; +} + +/* ***************************************************************************** + SOFTWARE API FOR TDES + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_EnableIt +//* \brief Enable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_EnableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pTDES->TDES_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_DisableIt +//* \brief Disable TDES interrupt +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_DisableIt ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pTDES->TDES_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetStatus +//* \brief Return TDES Interrupt Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetInterruptMaskStatus +//* \brief Return TDES Interrupt Mask Status +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status + AT91PS_TDES pTDES) // pointer to a TDES controller +{ + return pTDES->TDES_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsInterruptMasked +//* \brief Test if TDES Interrupt is Masked +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsInterruptMasked( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_IsStatusSet +//* \brief Test if TDES Status is Set +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_IsStatusSet( + AT91PS_TDES pTDES, // \arg pointer to a TDES controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TDES_GetStatus(pTDES) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgModeReg +//* \brief Configure the Mode Register of the TDES controller +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgModeReg ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned int mode) // mode register +{ + //* Write to the MR register + pTDES->TDES_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetModeReg +//* \brief Return the Mode Register of the TDES controller value +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetModeReg ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + return pTDES->TDES_MR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_StartProcessing +//* \brief Start Encryption or Decryption +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_StartProcessing ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_START; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SoftReset +//* \brief Reset TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SoftReset ( + AT91PS_TDES pTDES // pointer to a TDES controller + ) +{ + pTDES->TDES_CR = AT91C_TDES_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey1 +//* \brief Set Cryptographic Key 1 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey1 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY1WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey2 +//* \brief Set Cryptographic Key 2 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey2 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY2WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetCryptoKey3 +//* \brief Set Cryptographic Key 3 Word x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetCryptoKey3 ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int keyword + ) +{ + pTDES->TDES_KEY3WxR[index] = keyword; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_InputData +//* \brief Set Input Data x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_InputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int indata + ) +{ + pTDES->TDES_IDATAxR[index] = indata; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_GetOutputData +//* \brief Get Output Data x +//*---------------------------------------------------------------------------- +__inline unsigned int AT91F_TDES_GetOutputData ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index + ) +{ + return pTDES->TDES_ODATAxR[index]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_SetInitializationVector +//* \brief Set Initialization Vector x +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_SetInitializationVector ( + AT91PS_TDES pTDES, // pointer to a TDES controller + unsigned char index, + unsigned int initvector + ) +{ + pTDES->TDES_IVxR[index] = initvector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +__inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA27_DRXD ) | + ((unsigned int) AT91C_PA28_DTXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB30_PCK2 ) | + ((unsigned int) AT91C_PB29_PCK1 ), // Peripheral A + ((unsigned int) AT91C_PB20_PCK0 ) | + ((unsigned int) AT91C_PB0_PCK0 ) | + ((unsigned int) AT91C_PB22_PCK2 ) | + ((unsigned int) AT91C_PB21_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA30_PCK2 ) | + ((unsigned int) AT91C_PA13_PCK1 ) | + ((unsigned int) AT91C_PA27_PCK3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_VREG_CfgPMC +//* \brief Enable Peripheral clock in PMC for VREG +//*---------------------------------------------------------------------------- +__inline void AT91F_VREG_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RSTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RSTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RSTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_CfgPIO +//* \brief Configure PIO controllers to drive SSC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SSC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_RK ) | + ((unsigned int) AT91C_PA22_TK ) | + ((unsigned int) AT91C_PA21_TF ) | + ((unsigned int) AT91C_PA24_RD ) | + ((unsigned int) AT91C_PA26_RF ) | + ((unsigned int) AT91C_PA23_TD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_WDTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for WDTC +//*---------------------------------------------------------------------------- +__inline void AT91F_WDTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB26_RI1 ) | + ((unsigned int) AT91C_PB24_DSR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB25_DTR1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA7_SCK1 ) | + ((unsigned int) AT91C_PA8_RTS1 ) | + ((unsigned int) AT91C_PA6_TXD1 ) | + ((unsigned int) AT91C_PA5_RXD1 ) | + ((unsigned int) AT91C_PA9_CTS1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA0_RXD0 ) | + ((unsigned int) AT91C_PA4_CTS0 ) | + ((unsigned int) AT91C_PA3_RTS0 ) | + ((unsigned int) AT91C_PA2_SCK0 ) | + ((unsigned int) AT91C_PA1_TXD0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI1 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI1_CfgPIO +//* \brief Configure PIO controllers to drive SPI1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB16_NPCS13 ) | + ((unsigned int) AT91C_PB10_NPCS11 ) | + ((unsigned int) AT91C_PB11_NPCS12 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA4_NPCS13 ) | + ((unsigned int) AT91C_PA29_NPCS13 ) | + ((unsigned int) AT91C_PA21_NPCS10 ) | + ((unsigned int) AT91C_PA22_SPCK1 ) | + ((unsigned int) AT91C_PA25_NPCS11 ) | + ((unsigned int) AT91C_PA2_NPCS11 ) | + ((unsigned int) AT91C_PA24_MISO1 ) | + ((unsigned int) AT91C_PA3_NPCS12 ) | + ((unsigned int) AT91C_PA26_NPCS12 ) | + ((unsigned int) AT91C_PA23_MOSI1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI0 +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI0_CfgPIO +//* \brief Configure PIO controllers to drive SPI0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_SPI0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB13_NPCS01 ) | + ((unsigned int) AT91C_PB17_NPCS03 ) | + ((unsigned int) AT91C_PB14_NPCS02 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA16_MISO0 ) | + ((unsigned int) AT91C_PA13_NPCS01 ) | + ((unsigned int) AT91C_PA15_NPCS03 ) | + ((unsigned int) AT91C_PA17_MOSI0 ) | + ((unsigned int) AT91C_PA18_SPCK0 ) | + ((unsigned int) AT91C_PA14_NPCS02 ) | + ((unsigned int) AT91C_PA12_NPCS00 ), // Peripheral A + ((unsigned int) AT91C_PA7_NPCS01 ) | + ((unsigned int) AT91C_PA9_NPCS03 ) | + ((unsigned int) AT91C_PA8_NPCS02 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PITC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PITC +//*---------------------------------------------------------------------------- +__inline void AT91F_PITC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPIO +//* \brief Configure PIO controllers to drive AIC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_AIC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA30_IRQ0 ) | + ((unsigned int) AT91C_PA29_FIQ ), // Peripheral A + ((unsigned int) AT91C_PA14_IRQ1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AES_CfgPMC +//* \brief Enable Peripheral clock in PMC for AES +//*---------------------------------------------------------------------------- +__inline void AT91F_AES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_AES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA11_TWCK ) | + ((unsigned int) AT91C_PA10_TWD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPMC +//* \brief Enable Peripheral clock in PMC for ADC +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_ADC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ADC_CfgPIO +//* \brief Configure PIO controllers to drive ADC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_ADC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB18_ADTRG )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH3_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH3 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH3_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB22_PWM3 ), // Peripheral A + ((unsigned int) AT91C_PB30_PWM3 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH2_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_PWM2 ), // Peripheral A + ((unsigned int) AT91C_PB29_PWM2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH1_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB20_PWM1 ), // Peripheral A + ((unsigned int) AT91C_PB28_PWM1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CH0_CfgPIO +//* \brief Configure PIO controllers to drive PWMC_CH0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CH0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB19_PWM0 ), // Peripheral A + ((unsigned int) AT91C_PB27_PWM0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTTC +//*---------------------------------------------------------------------------- +__inline void AT91F_RTTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +__inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TDES_CfgPMC +//* \brief Enable Peripheral clock in PMC for TDES +//*---------------------------------------------------------------------------- +__inline void AT91F_TDES_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TDES)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +__inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB2_ETX0 ) | + ((unsigned int) AT91C_PB12_ETXER ) | + ((unsigned int) AT91C_PB16_ECOL ) | + ((unsigned int) AT91C_PB11_ETX3 ) | + ((unsigned int) AT91C_PB6_ERX1 ) | + ((unsigned int) AT91C_PB15_ERXDV ) | + ((unsigned int) AT91C_PB13_ERX2 ) | + ((unsigned int) AT91C_PB3_ETX1 ) | + ((unsigned int) AT91C_PB8_EMDC ) | + ((unsigned int) AT91C_PB5_ERX0 ) | + //((unsigned int) AT91C_PB18_EF100 ) | + ((unsigned int) AT91C_PB14_ERX3 ) | + ((unsigned int) AT91C_PB4_ECRS_ECRSDV) | + ((unsigned int) AT91C_PB1_ETXEN ) | + ((unsigned int) AT91C_PB10_ETX2 ) | + ((unsigned int) AT91C_PB0_ETXCK_EREFCK) | + ((unsigned int) AT91C_PB9_EMDIO ) | + ((unsigned int) AT91C_PB7_ERXER ) | + ((unsigned int) AT91C_PB17_ERXCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPIO +//* \brief Configure PIO controllers to drive TC0 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB23_TIOA0 ) | + ((unsigned int) AT91C_PB24_TIOB0 ), // Peripheral A + ((unsigned int) AT91C_PB12_TCLK0 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPIO +//* \brief Configure PIO controllers to drive TC1 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB25_TIOA1 ) | + ((unsigned int) AT91C_PB26_TIOB1 ), // Peripheral A + ((unsigned int) AT91C_PB19_TCLK1 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPIO +//* \brief Configure PIO controllers to drive TC2 signals +//*---------------------------------------------------------------------------- +__inline void AT91F_TC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB28_TIOB2 ) | + ((unsigned int) AT91C_PB27_TIOA2 ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA15_TCLK2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MC_CfgPMC +//* \brief Enable Peripheral clock in PMC for MC +//*---------------------------------------------------------------------------- +__inline void AT91F_MC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +__inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPMC +//* \brief Enable Peripheral clock in PMC for CAN +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_CAN)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CAN_CfgPIO +//* \brief Configure PIO controllers to drive CAN signals +//*---------------------------------------------------------------------------- +__inline void AT91F_CAN_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA20_CANTX ) | + ((unsigned int) AT91C_PA19_CANRX ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PWMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PWMC +//*---------------------------------------------------------------------------- +__inline void AT91F_PWMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PWMC)); +} + +#endif // lib_AT91SAM7X256_H
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c new file mode 100644 index 0000000..56842e4 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c
@@ -0,0 +1,259 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Atmel ARM7 port. + *----------------------------------------------------------*/ + + +/* Standard includes. */ +#include <stdlib.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + static __arm __irq void vPortNonPreemptiveTick( void ); + static __arm __irq void vPortNonPreemptiveTick( void ) + { + uint32_t ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + xTaskIncrementTick(); + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* End the interrupt in the AIC. */ + AT91C_BASE_AIC->AIC_EOICR = ulDummy; + } + +#else + + /* Currently the IAR port requires the preemptive tick function to be + defined in an asm file. */ + +#endif + +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +AT91PS_PITC pxPIT = AT91C_BASE_PITC; + + /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends + on whether the preemptive or cooperative scheduler is being used. */ + #if configUSE_PREEMPTION == 0 + + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick ); + + #else + + extern void ( vPortPreemptiveTick )( void ); + AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick ); + + #endif + + /* Configure the PIT period. */ + pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE; + + /* Enable the interrupt. Global interrupts are disables at this point so + this is safe. */ + AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS ); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79 new file mode 100644 index 0000000..9af364f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79
@@ -0,0 +1,88 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + + PUBLIC vPortYieldProcessor + PUBLIC vPortPreemptiveTick + PUBLIC vPortStartFirstTask + +#include "AT91SAM7S64_inc.h" +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get installed if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTick: + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =xTaskIncrementTick ; Increment the tick count - this may wake a task. + mov lr, pc + BX R0 + + CMP R0, #0 + BEQ SkipContextSwitch + LDR R0, =vTaskSwitchContext ; Select the next task to execute. + mov lr, pc + BX R0 +SkipContextSwitch + LDR R14, =AT91C_BASE_PITC ; Clear the PIT interrupt + LDR R0, [R14, #PITC_PIVR ] + + LDR R14, =AT91C_BASE_AIC ; Mark the End of Interrupt on the AIC + STR R14, [R14, #AIC_EOICR] + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h new file mode 100644 index 0000000..5fdf4f2 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h
@@ -0,0 +1,111 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h new file mode 100644 index 0000000..4a32f39 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h
@@ -0,0 +1,78 @@ + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c new file mode 100644 index 0000000..54361b9 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c
@@ -0,0 +1,256 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Atmel ARM7 port. + *----------------------------------------------------------*/ + + +/* Standard includes. */ +#include <stdlib.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware includes. */ +#include <board.h> +#include <pio/pio.h> +#include <pio/pio_it.h> +#include <pit/pit.h> +#include <aic/aic.h> +#include <tc/tc.h> +#include <utility/led.h> +#include <utility/trace.h> + +/*-----------------------------------------------------------*/ + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to setup the PIT. */ +#define port1MHz_IN_Hz ( 1000000ul ) +#define port1SECOND_IN_uS ( 1000000.0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* The PIT interrupt handler - the RTOS tick. */ +static void vPortTickISR( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + #ifdef THUMB_INTERWORK + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + #endif + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +static __arm void vPortTickISR( void ) +{ +volatile uint32_t ulDummy; + + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + if( xTaskIncrementTick() != pdFALSE ) + { + vTaskSwitchContext(); + } + + /* Clear the PIT interrupt. */ + ulDummy = AT91C_BASE_PITC->PITC_PIVR; + + /* To remove compiler warning. */ + ( void ) ulDummy; + + /* The AIC is cleared in the asm wrapper, outside of this function. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS; + + /* Setup the PIT for the required frequency. */ + PIT_Init( ulPeriodIn_uS, BOARD_MCK / port1MHz_IN_Hz ); + + /* Setup the PIT interrupt. */ + AIC_DisableIT( AT91C_ID_SYS ); + AIC_ConfigureIT( AT91C_ID_SYS, AT91C_AIC_PRIOR_LOWEST, vPortTickISR ); + AIC_EnableIT( AT91C_ID_SYS ); + PIT_EnableIT(); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_irq(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_irq(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79 new file mode 100644 index 0000000..d5ac7eb --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79
@@ -0,0 +1,34 @@ + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h new file mode 100644 index 0000000..7fe236d --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h
@@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include <intrinsics.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_irq() +#define portENABLE_INTERRUPTS() __enable_irq() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h new file mode 100644 index 0000000..18e0b3b --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h
@@ -0,0 +1,105 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/port.c new file mode 100644 index 0000000..371a74a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/port.c
@@ -0,0 +1,317 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the Philips ARM7 port. + *----------------------------------------------------------*/ + +/* + Changes from V3.2.2 + + + Bug fix - The prescale value for the timer setup is now written to T0PR + instead of T0PC. This bug would have had no effect unless a prescale + value was actually used. +*/ + +/* Standard includes. */ +#include <stdlib.h> +#include <intrinsics.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the tick ISR. */ +#define portENABLE_TIMER ( ( uint8_t ) 0x01 ) +#define portPRESCALE_VALUE 0x00 +#define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 ) +#define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 ) + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to setup the PIT. */ +#define portPIT_CLOCK_DIVISOR ( ( uint32_t ) 16 ) +#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS ) + +/* Constants required to handle interrupts. */ +#define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 ) +#define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + + +#define portINT_LEVEL_SENSITIVE 0 +#define portPIT_ENABLE ( ( uint16_t ) 0x1 << 24 ) +#define portPIT_INT_ENABLE ( ( uint16_t ) 0x1 << 25 ) + +/* Constants required to setup the VIC for the tick ISR. */ +#define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 ) +#define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 ) +#define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 ) + +/*-----------------------------------------------------------*/ + +/* Setup the PIT to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +#if configUSE_PREEMPTION == 0 + + /* The cooperative scheduler requires a normal IRQ service routine to + simply increment the system tick. */ + static __arm __irq void vPortNonPreemptiveTick( void ); + static __arm __irq void vPortNonPreemptiveTick( void ) + { + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + xTaskIncrementTick(); + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#else + + /* This function is called from an asm wrapper, so does not require the __irq + keyword. */ + void vPortPreemptiveTick( void ); + void vPortPreemptiveTick( void ) + { + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* The new tick value might unblock a task. Ensure the highest task that + is ready to execute is the task that will execute when the tick ISR + exits. */ + vTaskSwitchContext(); + } + + /* Ready for the next interrupt. */ + T0IR = portTIMER_MATCH_ISR_BIT; + VICVectAddr = portCLEAR_VIC_INTERRUPT; + } + +#endif + +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +uint32_t ulCompareMatch; + + /* A 1ms tick does not require the use of the timer prescale. This is + defaulted to zero but can be used if necessary. */ + T0PR = portPRESCALE_VALUE; + + /* Calculate the match value required for our wanted tick rate. */ + ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ; + + /* Protect against divide by zero. Using an if() statement still results + in a warning - hence the #if. */ + #if portPRESCALE_VALUE != 0 + { + ulCompareMatch /= ( portPRESCALE_VALUE + 1 ); + } + #endif + + T0MR0 = ulCompareMatch; + + /* Generate tick with timer 0 compare match. */ + T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH; + + /* Setup the VIC for the timer. */ + VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT ); + VICIntEnable |= portTIMER_VIC_CHANNEL_BIT; + + /* The ISR installed depends on whether the preemptive or cooperative + scheduler is being used. */ + #if configUSE_PREEMPTION == 1 + { + extern void ( vPortPreemptiveTickEntry )( void ); + + VICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry; + } + #else + { + extern void ( vNonPreemptiveTick )( void ); + + VICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick; + } + #endif + + VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE; + + /* Start the timer - interrupts are disabled when this function is called + so it is okay to do this here. */ + T0TCR = portENABLE_TIMER; +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79 new file mode 100644 index 0000000..6036e3e --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79
@@ -0,0 +1,76 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + EXTERN vPortPreemptiveTick + + PUBLIC vPortPreemptiveTickEntry + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get installed if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTickEntry: +#if configUSE_PREEMPTION == 1 + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vPortPreemptiveTick; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. +#endif + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h new file mode 100644 index 0000000..7ebcbe8 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h
@@ -0,0 +1,113 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include <intrinsics.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/port.c new file mode 100644 index 0000000..605c7c7 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/port.c
@@ -0,0 +1,173 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430 port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void vPortSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x3333; + pxTopOfStack--; + */ + + /* The msp430 automatically pushes the PC then SR onto the stack before + executing an ISR. We want the stack to look just as if this has happened + so place a pointer to the start of the task on the stack first - followed + by the flags we want the task to use when it starts up. */ + *pxTopOfStack = ( StackType_t ) pxCode; + pxTopOfStack--; + *pxTopOfStack = portFLAGS_INT_ENABLED; + pxTopOfStack--; + + /* Next the general purpose registers. */ + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x7777; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R15. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xffff; + pxTopOfStack--; + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses timer 0 + * but could alternatively use the watchdog timer or timer 1. + */ +void vPortSetupTimerInterrupt( void ) +{ + /* Ensure the timer is stopped. */ + TACTL = 0; + + /* Run the timer of the ACLK. */ + TACTL = TASSEL_1; + + /* Clear everything to start with. */ + TACTL |= TACLR; + + /* Set the compare match value according to the tick rate we want. */ + TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ; + + /* Enable the interrupts. */ + TACCTL0 = CCIE; + + /* Start up clean. */ + TACTL |= TACLR; + + /* Up mode. */ + TACTL |= MC_1; +} +/*-----------------------------------------------------------*/ + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/portasm.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/portasm.h new file mode 100644 index 0000000..bb5da67 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/portasm.h
@@ -0,0 +1,84 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTASM_H +#define PORTASM_H + +portSAVE_CONTEXT macro + + IMPORT pxCurrentTCB + IMPORT usCriticalNesting + + /* Save the remaining registers. */ + push r4 + push r5 + push r6 + push r7 + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + mov.w &usCriticalNesting, r14 + push r14 + mov.w &pxCurrentTCB, r12 + mov.w r1, 0(r12) + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + mov.w &pxCurrentTCB, r12 + mov.w @r12, r1 + pop r15 + mov.w r15, &usCriticalNesting + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop r7 + pop r6 + pop r5 + pop r4 + + /* The last thing on the stack will be the status register. + Ensure the power down bits are clear ready for the next + time this power down register is popped from the stack. */ + bic.w #0xf0,0(SP) + + reti + endm +/*-----------------------------------------------------------*/ + +#endif +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/portext.s43 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/portext.s43 new file mode 100644 index 0000000..ace7e5c --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/portext.s43
@@ -0,0 +1,106 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ +#include "FreeRTOSConfig.h" +#include "portasm.h" + + IMPORT xTaskIncrementTick + IMPORT vTaskSwitchContext + IMPORT vPortSetupTimerInterrupt + + EXPORT vTickISR + EXPORT vPortYield + EXPORT xPortStartScheduler + + RSEG CODE + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ +vTickISR: + portSAVE_CONTEXT + + call #xTaskIncrementTick + cmp.w #0x0, R12 + jeq SkipContextSwitch + call #vTaskSwitchContext +SkipContextSwitch: + + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Manual context switch called by the portYIELD() macro. + */ +vPortYield: + + /* Mimic an interrupt by pushing the SR. */ + push SR + + /* Now the SR is stacked we can disable interrupts. */ + dint + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Switch to the highest priority task that is ready to run. */ + call #vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ +xPortStartScheduler: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + call #vPortSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + + /* Install vTickISR as the timer A0 interrupt. */ + ASEG + ORG 0xFFE0 + TIMERA0_VECTOR + + _vTickISR_: DC16 vTickISR + + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h new file mode 100644 index 0000000..728c17d --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h
@@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); _NOP() +#define portENABLE_INTERRUPTS() _EINT(); _NOP() +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() +#define portPOINTER_SIZE_TYPE uint16_t +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#if configINTERRUPT_EXAMPLE_METHOD == 2 + +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext() + +#endif + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h new file mode 100644 index 0000000..e03a16b --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h
@@ -0,0 +1,63 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef DATA_MODEL_H +#define DATA_MODEL_H + +#if __DATA_MODEL__ == __DATA_MODEL_SMALL__ + #define pushm_x pushm.w + #define popm_x popm.w + #define push_x push.w + #define pop_x pop.w + #define mov_x mov.w + #define cmp_x cmp.w +#endif + +#if __DATA_MODEL__ == __DATA_MODEL_MEDIUM__ + #define pushm_x pushm.a + #define popm_x popm.a + #define push_x pushx.a + #define pop_x popx.a + #define mov_x mov.w + #define cmp_x cmp.w +#endif + +#if __DATA_MODEL__ == __DATA_MODEL_LARGE__ + #define pushm_x pushm.a + #define popm_x popm.a + #define push_x pushx.a + #define pop_x popx.a + #define mov_x movx.a + #define cmp_x cmpx.a +#endif + +#ifndef pushm_x + #error The assembler options must define one of the following symbols: __DATA_MODEL_SMALL__, __DATA_MODEL_MEDIUM__, or __DATA_MODEL_LARGE__ +#endif + +#endif /* DATA_MODEL_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/port.c new file mode 100644 index 0000000..c8d63da --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/port.c
@@ -0,0 +1,182 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the MSP430X port. + *----------------------------------------------------------*/ + +/* Constants required for hardware setup. The tick ISR runs off the ACLK, +not the MCLK. */ +#define portACLK_FREQUENCY_HZ ( ( TickType_t ) 32768 ) +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) +#define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x08 ) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each +time a critical section is entered the count is incremented. Each time a +critical section is exited the count is decremented - with interrupts only +being re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as this will cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + + +/* + * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but + * could have alternatively used the watchdog timer or timer 1. + */ +void vPortSetupTimerInterrupt( void ); +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint16_t *pusTopOfStack; +uint32_t *pulTopOfStack; + + /* + Place a few bytes of known values on the bottom of the stack. + This is just useful for debugging and can be included if required. + + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x3333; + */ + + /* StackType_t is either 16 bits or 32 bits depending on the data model. + Some stacked items do not change size depending on the data model so have + to be explicitly cast to the correct size so this function will work + whichever data model is being used. */ + if( sizeof( StackType_t ) == sizeof( uint16_t ) ) + { + /* Make room for a 20 bit value stored as a 32 bit value. */ + pusTopOfStack = ( uint16_t * ) pxTopOfStack; + pusTopOfStack--; + pulTopOfStack = ( uint32_t * ) pusTopOfStack; + } + else + { + pulTopOfStack = ( uint32_t * ) pxTopOfStack; + } + *pulTopOfStack = ( uint32_t ) pxCode; + + pusTopOfStack = ( uint16_t * ) pulTopOfStack; + pusTopOfStack--; + *pusTopOfStack = portFLAGS_INT_ENABLED; + pusTopOfStack -= ( sizeof( StackType_t ) / 2 ); + + /* From here on the size of stacked items depends on the memory model. */ + pxTopOfStack = ( StackType_t * ) pusTopOfStack; + + /* Next the general purpose registers. */ + #ifdef PRELOAD_REGISTER_VALUES + *pxTopOfStack = ( StackType_t ) 0xffff; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xeeee; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xdddd; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xbbbb; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xaaaa; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x9999; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x8888; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x6666; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x5555; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x4444; + pxTopOfStack--; + #else + pxTopOfStack -= 3; + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack -= 9; + #endif + + + /* A variable is used to keep track of the critical section nesting. + This variable has to be stored as part of the task context and is + initially set to zero. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack we have generated so this can + be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the MSP430 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. + */ +void vPortSetupTimerInterrupt( void ) +{ + vApplicationSetupTimerInterrupt(); +} +/*-----------------------------------------------------------*/ + +#pragma vector=configTICK_VECTOR +__interrupt __raw void vTickISREntry( void ) +{ +extern void vPortTickISR( void ); + + __bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF ); + vPortTickISR(); +} + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43 new file mode 100644 index 0000000..eef4454 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43
@@ -0,0 +1,138 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ +#include "msp430.h" +#include "FreeRTOSConfig.h" +#include "data_model.h" + + IMPORT xTaskIncrementTick + IMPORT vTaskSwitchContext + IMPORT vPortSetupTimerInterrupt + IMPORT pxCurrentTCB + IMPORT usCriticalNesting + + EXPORT vPortTickISR + EXPORT vPortYield + EXPORT xPortStartScheduler + +portSAVE_CONTEXT macro + + /* Save the remaining registers. */ + pushm_x #12, r15 + mov.w &usCriticalNesting, r14 + push_x r14 + mov_x &pxCurrentTCB, r12 + mov_x sp, 0( r12 ) + endm +/*-----------------------------------------------------------*/ + +portRESTORE_CONTEXT macro + + mov_x &pxCurrentTCB, r12 + mov_x @r12, sp + pop_x r15 + mov.w r15, &usCriticalNesting + popm_x #12, r15 + nop + pop.w sr + nop + reta + endm +/*-----------------------------------------------------------*/ + + +/* + * The RTOS tick ISR. + * + * If the cooperative scheduler is in use this simply increments the tick + * count. + * + * If the preemptive scheduler is in use a context switch can also occur. + */ + + RSEG CODE + EVEN + +vPortTickISR: + + /* The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs + to save it manually before it gets modified (interrupts get disabled). + Entering through this interrupt means the SR is already on the stack, but + this keeps the stack frames identical. */ + push.w sr + portSAVE_CONTEXT + + calla #xTaskIncrementTick + cmp.w #0x0, R12 + jeq SkipContextSwitch + calla #vTaskSwitchContext +SkipContextSwitch: + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + +/* + * Manual context switch called by the portYIELD() macro. + */ + EVEN + +vPortYield: + + /* The sr needs saving before it is modified. */ + push.w sr + + /* Now the SR is stacked interrupts can be disabled. */ + dint + nop + + /* Save the context of the current task. */ + portSAVE_CONTEXT + + /* Select the next task to run. */ + calla #vTaskSwitchContext + + /* Restore the context of the new task. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + +/* + * Start off the scheduler by initialising the RTOS tick timer, then restoring + * the context of the first task. + */ + EVEN + +xPortStartScheduler: + + /* Setup the hardware to generate the tick. Interrupts are disabled + when this function is called. */ + calla #vPortSetupTimerInterrupt + + /* Restore the context of the first task that is going to run. */ + portRESTORE_CONTEXT +/*-----------------------------------------------------------*/ + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h new file mode 100644 index 0000000..d5719fe --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h
@@ -0,0 +1,142 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Hardware includes. */ +#include "msp430.h" + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT int +#define portBASE_TYPE short + +/* The stack type changes depending on the data model. */ +#if( __DATA_MODEL__ == __DATA_MODEL_SMALL__ ) + #define portSTACK_TYPE uint16_t + #define portPOINTER_SIZE_TYPE uint16_t +#else + #define portSTACK_TYPE uint32_t +#endif + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif + +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() _DINT(); _NOP() +#define portENABLE_INTERRUPTS() _EINT(); _NOP() +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled usCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ + +/* + * Manual context switch called by portYIELD or taskYIELD. + */ +extern void vPortYield( void ); +#define portYIELD() vPortYield() +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#define portYIELD_FROM_ISR( x ) if( x ) vPortYield() + +void vApplicationSetupTimerInterrupt( void ); + +/* sizeof( int ) != sizeof( long ) so a full printf() library is required if +run time stats information is to be displayed. */ +#define portLU_PRINTF_SPECIFIER_REQUIRED + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h new file mode 100644 index 0000000..d9aeb95 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h
@@ -0,0 +1,83 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + +#include "FreeRTOSConfig.h" + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the general purpose registers, CS and ES (only in far +; memory mode) registers the usCriticalNesting Value and the Stack Pointer +; of the active Task onto the task stack +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO + + PUSH AX ; Save AX Register to stack. + PUSH HL + MOV A, CS ; Save CS register. + XCH A, X + MOV A, ES ; Save ES register. + PUSH AX + PUSH DE ; Save the remaining general purpose registers. + PUSH BC + MOVW AX, usCriticalNesting ; Save the usCriticalNesting value. + PUSH AX + MOVW AX, pxCurrentTCB ; Save the Stack pointer. + MOVW HL, AX + MOVW AX, SP + MOVW [HL], AX + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Restores the task Stack Pointer then use this to restore usCriticalNesting, +; general purpose registers and the CS and ES (only in far memory mode) +; of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVW AX, pxCurrentTCB ; Restore the Stack pointer. + MOVW HL, AX + MOVW AX, [HL] + MOVW SP, AX + POP AX ; Restore usCriticalNesting value. + MOVW usCriticalNesting, AX + POP BC ; Restore the necessary general purpose registers. + POP DE + POP AX ; Restore the ES register. + MOV ES, A + XCH A, X ; Restore the CS register. + MOV CS, A + POP HL ; Restore general purpose register HL. + POP AX ; Restore AX. + ENDM +;------------------------------------------------------------------------------
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/port.c new file mode 100644 index 0000000..84bfabd --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/port.c
@@ -0,0 +1,280 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* The critical nesting value is initialised to a non zero value to ensure +interrupts don't accidentally become enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING ( ( uint16_t ) 10 ) + +/* Initial PSW value allocated to a newly created task. + * 1100011000000000 + * ||||||||-------------- Fill byte + * |||||||--------------- Carry Flag cleared + * |||||----------------- In-service priority Flags set to low level + * ||||------------------ Register bank Select 0 Flag cleared + * |||------------------- Auxiliary Carry Flag cleared + * ||-------------------- Register bank Select 1 Flag cleared + * |--------------------- Zero Flag set + * ---------------------- Global Interrupt Flag set (enabled) + */ +#define portPSW ( 0xc6UL ) + +/* The address of the pxCurrentTCB variable, but don't know or need to know its +type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Each task maintains a count of the critical section nesting depth. Each time +a critical section is entered the count is incremented. Each time a critical +section is exited the count is decremented - with interrupts only being +re-enabled if the count is zero. + +usCriticalNesting will get set to zero when the scheduler starts, but must +not be initialised to zero as that could cause problems during the startup +sequence. */ +volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; + +/*-----------------------------------------------------------*/ + +/* + * Sets up the periodic ISR used for the RTOS tick using the interval timer. + * The application writer can define configSETUP_TICK_INTERRUPT() (in + * FreeRTOSConfig.h) such that their own tick interrupt configuration is used + * in place of prvSetupTimerInterrupt(). + */ +static void prvSetupTimerInterrupt( void ); +#ifndef configSETUP_TICK_INTERRUPT + /* The user has not provided their own tick interrupt configuration so use + the definition in this file (which uses the interval timer). */ + #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() +#endif /* configSETUP_TICK_INTERRUPT */ + +/* + * Defined in portasm.s87, this function starts the scheduler by loading the + * context of the first task to run. + */ +extern void vPortStartFirstTask( void ); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See the header file portable.h. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +uint32_t *pulLocal; + + /* With large code and large data sizeof( StackType_t ) == 2, and + sizeof( StackType_t * ) == 4. With small code and small data + sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */ + + #if __DATA_MODEL__ == __DATA_MODEL_FAR__ + { + /* Parameters are passed in on the stack, and written using a 32-bit value + hence a space is left for the second two bytes. */ + pxTopOfStack--; + + /* Write in the parameter value. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) pvParameters; + pxTopOfStack--; + + /* The return address, leaving space for the first two bytes of the + 32-bit value. See the comments above the prvTaskExitError() prototype + at the top of this file. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) prvTaskExitError; + pxTopOfStack--; + + /* The start address / PSW value is also written in as a 32-bit value, + so leave a space for the second two bytes. */ + pxTopOfStack--; + + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* An initial value for the AX register. */ + *pxTopOfStack = ( StackType_t ) 0x1111; + pxTopOfStack--; + } + #else + { + /* The return address, leaving space for the first two bytes of the + 32-bit value. See the comments above the prvTaskExitError() prototype + at the top of this file. */ + pxTopOfStack--; + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( uint32_t ) prvTaskExitError; + pxTopOfStack--; + + /* Task function. Again as it is written as a 32-bit value a space is + left on the stack for the second two bytes. */ + pxTopOfStack--; + + /* Task function start address combined with the PSW. */ + pulLocal = ( uint32_t * ) pxTopOfStack; + *pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) ); + pxTopOfStack--; + + /* The parameter is passed in AX. */ + *pxTopOfStack = ( StackType_t ) pvParameters; + pxTopOfStack--; + } + #endif + + /* An initial value for the HL register. */ + *pxTopOfStack = ( StackType_t ) 0x2222; + pxTopOfStack--; + + /* CS and ES registers. */ + *pxTopOfStack = ( StackType_t ) 0x0F00; + pxTopOfStack--; + + /* The remaining general purpose registers DE and BC */ + *pxTopOfStack = ( StackType_t ) 0xDEDE; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0xBCBC; + pxTopOfStack--; + + /* Finally the critical section nesting count is set to zero when the task + first starts. */ + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* Return a pointer to the top of the stack that has been generated so it + can be stored in the task control block for the task. */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError( void ) +{ + /* A function that implements a task must not exit or attempt to return to + its caller as there is nothing to return to. If a task wants to exit it + should instead call vTaskDelete( NULL ). + + Artificially force an assert() to be triggered if configASSERT() is + defined, then stop here so application writers can catch the error. */ + configASSERT( usCriticalNesting == ~0U ); + portDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + configSETUP_TICK_INTERRUPT(); + + /* Restore the context of the first task that is going to run. */ + vPortStartFirstTask(); + + /* Execution should not reach here as the tasks are now running! + prvSetupTimerInterrupt() is called here to prevent the compiler outputting + a warning about a statically declared function not being referenced in the + case that the application writer has provided their own tick interrupt + configuration routine (and defined configSETUP_TICK_INTERRUPT() such that + their own routine will be called in place of prvSetupTimerInterrupt()). */ + prvSetupTimerInterrupt(); + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the RL78 port will get stopped. */ +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +const uint16_t usClockHz = 15000UL; /* Internal clock. */ +const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL; + + /* Use the internal 15K clock. */ + OSMC = ( uint8_t ) 0x16; + + #ifdef RTCEN + { + /* Supply the interval timer clock. */ + RTCEN = ( uint8_t ) 1U; + + /* Disable INTIT interrupt. */ + ITMK = ( uint8_t ) 1; + + /* Disable ITMC operation. */ + ITMC = ( uint8_t ) 0x0000; + + /* Clear INIT interrupt. */ + ITIF = ( uint8_t ) 0; + + /* Set interval and enable interrupt operation. */ + ITMC = usCompareMatch | 0x8000U; + + /* Enable INTIT interrupt. */ + ITMK = ( uint8_t ) 0; + } + #endif + + #ifdef TMKAEN + { + /* Supply the interval timer clock. */ + TMKAEN = ( uint8_t ) 1U; + + /* Disable INTIT interrupt. */ + TMKAMK = ( uint8_t ) 1; + + /* Disable ITMC operation. */ + ITMC = ( uint8_t ) 0x0000; + + /* Clear INIT interrupt. */ + TMKAIF = ( uint8_t ) 0; + + /* Set interval and enable interrupt operation. */ + ITMC = usCompareMatch | 0x8000U; + + /* Enable INTIT interrupt. */ + TMKAMK = ( uint8_t ) 0; + } + #endif +} +/*-----------------------------------------------------------*/ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/portasm.s87 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/portasm.s87 new file mode 100644 index 0000000..8e30f01 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/portasm.s87
@@ -0,0 +1,83 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + +#include "ISR_Support.h" + +#define CS 0xFFFFC +#define ES 0xFFFFD + + PUBLIC vPortYield + PUBLIC vPortStartFirstTask + PUBLIC vPortTickISR + + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; FreeRTOS yield handler. This is installed as the BRK software interrupt +; handler. + RSEG CODE:CODE +vPortYield: + portSAVE_CONTEXT ; Save the context of the current task. + call vTaskSwitchContext ; Call the scheduler to select the next task. + portRESTORE_CONTEXT ; Restore the context of the next task to run. + retb + + +; Starts the scheduler by restoring the context of the task that will execute +; first. + RSEG CODE:CODE +vPortStartFirstTask: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + reti ; An interrupt stack frame is used so the task + ; is started using a RETI instruction. + +; FreeRTOS tick handler. This is installed as the interval timer interrupt +; handler. + RSEG CODE:CODE +vPortTickISR: + + portSAVE_CONTEXT ; Save the context of the current task. + call xTaskIncrementTick ; Call the timer tick function. + cmpw ax, #0x00 + skz + call vTaskSwitchContext ; Call the scheduler to select the next task. + portRESTORE_CONTEXT ; Restore the context of the next task to run. + reti + + +; Install the interrupt handlers + + COMMON INTVEC:CODE:ROOT(1) + ORG configTICK_VECTOR + DW vPortTickISR + + COMMON INTVEC:CODE:ROOT(1) + ORG 126 + DW vPortYield + + + END \ No newline at end of file
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/portmacro.h new file mode 100644 index 0000000..9261bad --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RL78/portmacro.h
@@ -0,0 +1,144 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__ + #warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model. +#endif + +#if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__ + #warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model. +#endif + +/* Type definitions. */ + +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint16_t +#define portBASE_TYPE short + +typedef portSTACK_TYPE StackType_t; +typedef short BaseType_t; +typedef unsigned short UBaseType_t; + + +#if __DATA_MODEL__ == __DATA_MODEL_FAR__ + #define portPOINTER_SIZE_TYPE uint32_t +#else + #define portPOINTER_SIZE_TYPE uint16_t +#endif + + +#if ( configUSE_16_BIT_TICKS == 1 ) + typedef unsigned int TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm ( "DI" ) +#define portENABLE_INTERRUPTS() __asm ( "EI" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( uint16_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile uint16_t usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portYIELD() __asm( "BRK" ) +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext() +#define portNOP() __asm( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 2 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX100/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX100/port.c new file mode 100644 index 0000000..f9e9dbc --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX100/port.c
@@ -0,0 +1,516 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Standard C includes. */ +#include "limits.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include "machine.h" + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) + +/* The peripheral clock is divided by this value before being supplying the +CMT. */ +#if ( configUSE_TICKLESS_IDLE == 0 ) + /* If tickless idle is not used then the divisor can be fixed. */ + #define portCLOCK_DIVISOR 8UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 ) + #define portCLOCK_DIVISOR 512UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 ) + #define portCLOCK_DIVISOR 128UL +#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 ) + #define portCLOCK_DIVISOR 32UL +#else + #define portCLOCK_DIVISOR 8UL +#endif + + +/* Keys required to lock and unlock access to certain system registers +respectively. */ +#define portUNLOCK_KEY 0xA50B +#define portLOCK_KEY 0xA500 + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +extern void prvStartFirstTask( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt static void prvTickISR( void ); + +/* + * Sets up the periodic ISR used for the RTOS tick using the CMT. + * The application writer can define configSETUP_TICK_INTERRUPT() (in + * FreeRTOSConfig.h) such that their own tick interrupt configuration is used + * in place of prvSetupTimerInterrupt(). + */ +static void prvSetupTimerInterrupt( void ); +#ifndef configSETUP_TICK_INTERRUPT + /* The user has not provided their own tick interrupt configuration so use + the definition in this file (which uses the interval timer). */ + #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt() +#endif /* configSETUP_TICK_INTERRUPT */ + +/* + * Called after the sleep mode registers have been configured, prvSleep() + * executes the pre and post sleep macros, and actually calls the wait + * instruction. + */ +#if configUSE_TICKLESS_IDLE == 1 + static void prvSleep( TickType_t xExpectedIdleTime ); +#endif /* configUSE_TICKLESS_IDLE */ + +/*-----------------------------------------------------------*/ + +extern void *pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* Calculate how many clock increments make up a single tick period. */ +static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + +#if configUSE_TICKLESS_IDLE == 1 + + /* Holds the maximum number of ticks that can be suppressed - which is + basically how far into the future an interrupt can be generated. Set + during initialisation. This is the maximum possible value that the + compare match register can hold divided by ulMatchValueForOneTick. */ + static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ ); + + /* Flag set from the tick interrupt to allow the sleep processing to know if + sleep mode was exited because of a tick interrupt, or an interrupt + generated by something else. */ + static volatile uint32_t ulTickFlag = pdFALSE; + + /* The CMT counter is stopped temporarily each time it is re-programmed. + The following constant offsets the CMT counter match value by the number of + CMT counts that would typically be missed while the counter was stopped to + compensate for the lost time. The large difference between the divided CMT + clock and the CPU clock means it is likely ulStoppedTimerCompensation will + equal zero - and be optimised away. */ + static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) ); + +#endif + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* Offset to end up on 8 byte boundary. */ + pxTopOfStack--; + + /* R0 is not included as it is the stack pointer. */ + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xaaaabbbb; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + /* Leave space for the registers that will get popped from the stack + when the task first starts executing. */ + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate + the tick interrupt. This way the application can decide which + peripheral to use. If tickless mode is used then the default + implementation defined in this file (which uses CMT0) should not be + overridden. */ + configSETUP_TICK_INTERRUPT(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Execution should not reach here as the tasks are now running! + prvSetupTimerInterrupt() is called here to prevent the compiler outputting + a warning about a statically declared function not being referenced in the + case that the application writer has provided their own tick interrupt + configuration routine (and defined configSETUP_TICK_INTERRUPT() such that + their own routine will be called in place of prvSetupTimerInterrupt()). */ + prvSetupTimerInterrupt(); + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma vector = configTICK_VECTOR +__interrupt static void prvTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); + + #if configUSE_TICKLESS_IDLE == 1 + { + /* The CPU woke because of a tick. */ + ulTickFlag = pdTRUE; + + /* If this is the first tick since exiting tickless mode then the CMT + compare match value needs resetting. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + } + #endif +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Unlock. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Enable CMT0. */ + MSTP( CMT0 ) = 0; + + /* Lock again. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; + + /* Divide the PCLK. */ + #if portCLOCK_DIVISOR == 512 + { + CMT0.CMCR.BIT.CKS = 3; + } + #elif portCLOCK_DIVISOR == 128 + { + CMT0.CMCR.BIT.CKS = 2; + } + #elif portCLOCK_DIVISOR == 32 + { + CMT0.CMCR.BIT.CKS = 1; + } + #elif portCLOCK_DIVISOR == 8 + { + CMT0.CMCR.BIT.CKS = 0; + } + #else + { + #error Invalid portCLOCK_DIVISOR setting + } + #endif + + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; +} +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + static void prvSleep( TickType_t xExpectedIdleTime ) + { + /* Allow the application to define some pre-sleep processing. */ + configPRE_SLEEP_PROCESSING( xExpectedIdleTime ); + + /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING() + means the application defined code has already executed the WAIT + instruction. */ + if( xExpectedIdleTime > 0 ) + { + __wait_for_interrupt(); + } + + /* Allow the application to define some post sleep processing. */ + configPOST_SLEEP_PROCESSING( xExpectedIdleTime ); + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if configUSE_TICKLESS_IDLE == 1 + + void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) + { + uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount; + eSleepModeStatus eSleepAction; + + /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* Make sure the CMT reload value does not overflow the counter. */ + if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks ) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Calculate the reload value required to wait xExpectedIdleTime tick + periods. */ + ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime; + if( ulMatchValue > ulStoppedTimerCompensation ) + { + /* Compensate for the fact that the CMT is going to be stopped + momentarily. */ + ulMatchValue -= ulStoppedTimerCompensation; + } + + /* Stop the CMT momentarily. The time the CMT is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + /* Critical section using the global interrupt bit as the i bit is + automatically reset by the WAIT instruction. */ + __disable_interrupt(); + + /* The tick flag is set to false before sleeping. If it is true when + sleep mode is exited then sleep mode was probably exited because the + tick was suppressed for the entire xExpectedIdleTime period. */ + ulTickFlag = pdFALSE; + + /* If a context switch is pending then abandon the low power entry as + the context switch might have been pended by an external interrupt that + requires processing. */ + eSleepAction = eTaskConfirmSleepModeStatus(); + if( eSleepAction == eAbortSleep ) + { + /* Restart tick. */ + CMT.CMSTR0.BIT.STR0 = 1; + __enable_interrupt(); + } + else if( eSleepAction == eNoTasksWaitingTimeout ) + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for software standby with all clocks stopped. */ + SYSTEM.SBYCR.BIT.SSBY = 1; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Sleep until something happens. Calling prvSleep() will + automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Restart the CMT. */ + CMT.CMSTR0.BIT.STR0 = 1; + } + else + { + /* Protection off. */ + SYSTEM.PRCR.WORD = portUNLOCK_KEY; + + /* Ready for deep sleep mode. */ + SYSTEM.MSTPCRC.BIT.DSLPE = 1; + SYSTEM.MSTPCRA.BIT.MSTPA28 = 1; + SYSTEM.SBYCR.BIT.SSBY = 0; + + /* Protection on. */ + SYSTEM.PRCR.WORD = portLOCK_KEY; + + /* Adjust the match value to take into account that the current + time slice is already partially complete. */ + ulMatchValue -= ( uint32_t ) CMT0.CMCNT; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* Restart the CMT to count up to the new match value. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Sleep until something happens. Calling prvSleep() will + automatically reset the i bit in the PSW. */ + prvSleep( xExpectedIdleTime ); + + /* Stop CMT. Again, the time the SysTick is stopped for is + accounted for as best it can be, but using the tickless mode will + inevitably result in some tiny drift of the time maintained by the + kernel with respect to calendar time. */ + CMT.CMSTR0.BIT.STR0 = 0; + while( CMT.CMSTR0.BIT.STR0 == 1 ) + { + /* Nothing to do here. */ + } + + ulCurrentCount = ( uint32_t ) CMT0.CMCNT; + + if( ulTickFlag != pdFALSE ) + { + /* The tick interrupt has already executed, although because + this function is called with the scheduler suspended the actual + tick processing will not occur until after this function has + exited. Reset the match value with whatever remains of this + tick period. */ + ulMatchValue = ulMatchValueForOneTick - ulCurrentCount; + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + + /* The tick interrupt handler will already have pended the tick + processing in the kernel. As the pending tick will be + processed as soon as this function exits, the tick value + maintained by the tick is stepped forward by one less than the + time spent sleeping. The actual stepping of the tick appears + later in this function. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + How many complete tick periods passed while the processor was + sleeping? */ + ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick; + + /* The match value is set to whatever fraction of a single tick + period remains. */ + ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick ); + CMT0.CMCOR = ( uint16_t ) ulMatchValue; + } + + /* Restart the CMT so it runs up to the match value. The match value + will get set to the value required to generate exactly one tick period + the next time the CMT interrupt executes. */ + CMT0.CMCNT = 0; + CMT.CMSTR0.BIT.STR0 = 1; + + /* Wind the tick forward by the number of tick periods that the CPU + remained in a low power state. */ + vTaskStepTick( ulCompleteTickPeriods ); + } + } + +#endif /* configUSE_TICKLESS_IDLE */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX100/port_asm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX100/port_asm.s new file mode 100644 index 0000000..69d3178 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX100/port_asm.s
@@ -0,0 +1,151 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include "PriorityDefinitions.h" + + PUBLIC _prvStartFirstTask + PUBLIC ___interrupt_27 + + EXTERN _pxCurrentTCB + EXTERN _vTaskSwitchContext + + RSEG CODE:CODE(4) + +_prvStartFirstTask: + + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15 + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + +/* The software interrupt - overwrite the default 'weak' definition. */ +___interrupt_27: + + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the accumulator. */ + MVFACHI R15 + PUSH.L R15 + + /* Middle word. */ + MVFACMI R15 + + /* Shifted left as it is restored to the low order word. */ + SHLL #16, R15 + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POPM R1-R15 + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX100/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX100/portmacro.h new file mode 100644 index 0000000..324e988 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX100/portmacro.h
@@ -0,0 +1,150 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include <intrinsics.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Hardware specifics. */ +#include "machine.h" + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +#define portYIELD() \ + __asm volatile \ + ( \ + "MOV.L #0x872E0, R15 \n" \ + "MOV.B #1, [R15] \n" \ + "MOV.L [R15], R15 \n" \ + ::: "R15" \ + ) + +#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) { portYIELD(); } + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/* Tickless idle/low power functionality. */ +#if configUSE_TICKLESS_IDLE == 1 + #ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) + #endif +#endif + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prevent warnings of undefined behaviour: the order of volatile accesses is +undefined - all warnings have been manually checked and are not an issue, and +the warnings cannot be prevent by code changes without undesirable effects. */ +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX600/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX600/port.c new file mode 100644 index 0000000..7f8f4cc --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX600/port.c
@@ -0,0 +1,193 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include <iorx62n.h> + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +extern void prvStartFirstTask( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +extern void *pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x12345678; /* Accumulator. */ + pxTopOfStack--; + *pxTopOfStack = 0x87654321; /* Accumulator. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma vector = configTICK_VECTOR +__interrupt void vTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX600/port_asm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX600/port_asm.s new file mode 100644 index 0000000..c66e99e --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX600/port_asm.s
@@ -0,0 +1,159 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include "PriorityDefinitions.h" + + PUBLIC _prvStartFirstTask + PUBLIC ___interrupt_27 + + EXTERN _pxCurrentTCB + EXTERN _vTaskSwitchContext + + RSEG CODE:CODE(4) + +_prvStartFirstTask: + + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15 + POP R15 + + /* Floating point status word. */ + MVTC R15, FPSW + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + +/* The software interrupt - overwrite the default 'weak' definition. */ +___interrupt_27: + + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulator. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACHI R15 + PUSH.L R15 + + /* Middle word. */ + MVFACMI R15 + + /* Shifted left as it is restored to the low order word. */ + SHLL #16, R15 + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + MVTACLO R15 + POP R15 + MVTACHI R15 + POP R15 + MVTC R15, FPSW + POPM R1-R15 + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX600/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX600/portmacro.h new file mode 100644 index 0000000..e869600 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RX600/portmacro.h
@@ -0,0 +1,139 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include <intrinsics.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" +where portITU_SWINTR is the location of the software interrupt register +(0x000872E0). Don't rely on the assembler to select a register, so instead +save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) portYIELD() + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RXv2/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RXv2/port.c new file mode 100644 index 0000000..484d71a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RXv2/port.c
@@ -0,0 +1,201 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#include <machine.h> + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +extern void prvStartFirstTask( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +extern void *pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 1. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma vector = configTICK_VECTOR +__interrupt void vTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s new file mode 100644 index 0000000..3c4ef17 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s
@@ -0,0 +1,200 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include "PriorityDefinitions.h" + + PUBLIC _prvStartFirstTask + PUBLIC ___interrupt_27 + + EXTERN _pxCurrentTCB + EXTERN _vTaskSwitchContext + + RSEG CODE:CODE(4) + +_prvStartFirstTask: + + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + + /* Floating point status word. */ + MVTC R15, FPSW + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + +/* The software interrupt - overwrite the default 'weak' definition. */ +___interrupt_27: + + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulator. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACGU #0, A1, R15 + PUSH.L R15 + MVFACHI #0, A1, R15 + PUSH.L R15 + /* Low order word. */ + MVFACLO #0, A1, R15 + PUSH.L R15 + MVFACGU #0, A0, R15 + PUSH.L R15 + MVFACHI #0, A0, R15 + PUSH.L R15 + /* Low order word. */ + MVFACLO #0, A0, R15 + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + MVTC R15, FPSW + POPM R1-R15 + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h new file mode 100644 index 0000000..f260ab4 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h
@@ -0,0 +1,144 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include <intrinsics.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" +where portITU_SWINTR is the location of the software interrupt register +(0x000872E0). Don't rely on the assembler to select a register, so instead +save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) portYIELD() + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prevent warnings of undefined behaviour: the order of volatile accesses is +undefined - all warnings have been manually checked and are not an issue, and +the warnings cannot be prevent by code changes without undesirable effects. */ +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h new file mode 100644 index 0000000..18e0b3b --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h
@@ -0,0 +1,105 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/port.c new file mode 100644 index 0000000..ed06217 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/port.c
@@ -0,0 +1,258 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR71x ARM7 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "wdg.h" +#include "eic.h" + +/* Standard includes. */ +#include <stdlib.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +#define portMICROS_PER_SECOND 1000000 + +/*-----------------------------------------------------------*/ + +/* Setup the watchdog to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/* Tick interrupt routines for cooperative and preemptive operation +respectively. The preemptive version is not defined as __irq as it is called +from an asm wrapper function. */ +__arm __irq void vPortNonPreemptiveTick( void ); +void vPortPreemptiveTick( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + + if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL ) + { + /* We want the task to start in thumb mode. */ + *pxTopOfStack |= portTHUMB_MODE_BIT; + } + + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* The cooperative scheduler requires a normal IRQ service routine to +simply increment the system tick. */ +__arm __irq void vPortNonPreemptiveTick( void ) +{ + /* Increment the tick count - which may wake some tasks but as the + preemptive scheduler is not being used any woken task is not given + processor time no matter what its priority. */ + xTaskIncrementTick(); + + /* Clear the interrupt in the watchdog and EIC. */ + WDG->SR = 0x0000; + portCLEAR_EIC(); +} +/*-----------------------------------------------------------*/ + +/* This function is called from an asm wrapper, so does not require the __irq +keyword. */ +void vPortPreemptiveTick( void ) +{ + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to execute. */ + vTaskSwitchContext(); + } + + /* Clear the interrupt in the watchdog and EIC. */ + WDG->SR = 0x0000; + portCLEAR_EIC(); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ + /* Set the watchdog up to generate a periodic tick. */ + WDG_ECITConfig( DISABLE ); + WDG_CntOnOffConfig( DISABLE ); + WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ ); + + /* Setup the tick interrupt in the EIC. */ + EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 ); + EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE ); + EIC_IRQConfig( ENABLE ); + WDG_ECITConfig( ENABLE ); + + /* Start the timer - interrupts are actually disabled at this point so + it is safe to do this here. */ + WDG_CntOnOffConfig( ENABLE ); +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79 new file mode 100644 index 0000000..59afb02 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79
@@ -0,0 +1,76 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vPortPreemptiveTick + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + PUBLIC vPortPreemptiveTickISR + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Preemptive context switch function. This will only ever get used if +; portUSE_PREEMPTION is set to 1 in portmacro.h. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortPreemptiveTickISR: + portSAVE_CONTEXT ; Save the context of the current task. + + LDR R0, =vPortPreemptiveTick ; Increment the tick count - this may wake a task. + MOV lr, pc + BX R0 + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h new file mode 100644 index 0000000..2cf720f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h
@@ -0,0 +1,121 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include <intrinsics.h> + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortDisableInterruptsFromThumb( void ); +__arm __interwork void vPortEnableInterruptsFromThumb( void ); +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + +/* EIC utilities. */ +#define portEIC_CICR_ADDR *( ( uint32_t * ) 0xFFFFF804 ) +#define portEIC_IPR_ADDR *( ( uint32_t * ) 0xFFFFF840 ) +#define portCLEAR_EIC() portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h new file mode 100644 index 0000000..18e0b3b --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h
@@ -0,0 +1,105 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/port.c new file mode 100644 index 0000000..0d68bcc --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/port.c
@@ -0,0 +1,237 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR75x ARM7 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "75x_tb.h" +#include "75x_eic.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Constants required to setup the initial stack. */ +#define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +/* Prescale used on the timer clock when calculating the tick period. */ +#define portPRESCALE 20 + + +/*-----------------------------------------------------------*/ + +/* Setup the TB to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/* Tick interrupt routines for preemptive operation. */ +__arm void vPortPreemptiveTick( void ); + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ +StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +__arm void vPortPreemptiveTick( void ) +{ + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to execute. */ + vTaskSwitchContext(); + } + + TB_ClearITPendingBit( TB_IT_Update ); +} +/*-----------------------------------------------------------*/ + +static void prvSetupTimerInterrupt( void ) +{ +EIC_IRQInitTypeDef EIC_IRQInitStructure; +TB_InitTypeDef TB_InitStructure; + + /* Setup the EIC for the TB. */ + EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE; + EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel; + EIC_IRQInitStructure.EIC_IRQChannelPriority = 1; + EIC_IRQInit(&EIC_IRQInitStructure); + + /* Setup the TB for the generation of the tick interrupt. */ + TB_InitStructure.TB_Mode = TB_Mode_Timing; + TB_InitStructure.TB_CounterMode = TB_CounterMode_Down; + TB_InitStructure.TB_Prescaler = portPRESCALE - 1; + TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ ); + TB_Init(&TB_InitStructure); + + /* Enable TB Update interrupt */ + TB_ITConfig(TB_IT_Update, ENABLE); + + /* Clear TB Update interrupt pending bit */ + TB_ClearITPendingBit(TB_IT_Update); + + /* Enable TB */ + TB_Cmd(ENABLE); +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + __disable_interrupt(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + __enable_interrupt(); + } + } +} +/*-----------------------------------------------------------*/ + + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79 new file mode 100644 index 0000000..eac9c4b --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79
@@ -0,0 +1,63 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vPortPreemptiveTick + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + mov lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h new file mode 100644 index 0000000..4a20cf1 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h
@@ -0,0 +1,112 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include <intrinsics.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h new file mode 100644 index 0000000..f9a6466 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h
@@ -0,0 +1,105 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + EXTERN pxCurrentTCB + EXTERN ulCriticalNesting + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + ; Push R0 as we are going to use the register. + STMDB SP!, {R0} + + ; Set R0 to point to the task stack pointer. + STMDB SP, {SP}^ + NOP + SUB SP, SP, #4 + LDMIA SP!, {R0} + + ; Push the return address onto the stack. + STMDB R0!, {LR} + + ; Now we have saved LR we can use it instead of R0. + MOV LR, R0 + + ; Pop R0 so we can save it onto the system mode stack. + LDMIA SP!, {R0} + + ; Push all the system mode registers onto the task stack. + STMDB LR, {R0-LR}^ + NOP + SUB LR, LR, #60 + + ; Push the SPSR onto the task stack. + MRS R0, SPSR + STMDB LR!, {R0} + + LDR R0, =ulCriticalNesting + LDR R0, [R0] + STMDB LR!, {R0} + + ; Store the new top of stack for the task. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + STR LR, [R0] + + ENDM + + +portRESTORE_CONTEXT MACRO + + ; Set the LR to the task stack. + LDR R1, =pxCurrentTCB + LDR R0, [R1] + LDR LR, [R0] + + ; The critical nesting depth is the first item on the stack. + ; Load it into the ulCriticalNesting variable. + LDR R0, =ulCriticalNesting + LDMFD LR!, {R1} + STR R1, [R0] + + ; Get the SPSR from the stack. + LDMFD LR!, {R0} + MSR SPSR_cxsf, R0 + + ; Restore all system mode registers for the task. + LDMFD LR, {R0-R14}^ + NOP + + ; Restore the return address. + LDR LR, [LR, #+60] + + ; And return - correcting the offset in the LR to obtain the + ; correct address. + SUBS PC, LR, #4 + + ENDM +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/port.c new file mode 100644 index 0000000..2a4c44e --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/port.c
@@ -0,0 +1,421 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the ST STR91x ARM9 + * port. + *----------------------------------------------------------*/ + +/* Library includes. */ +#include "91x_lib.h" + +/* Standard includes. */ +#include <stdlib.h> +#include <assert.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef configUSE_WATCHDOG_TICK + #error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively. +#endif + +/* Constants required to setup the initial stack. */ +#ifndef _RUN_TASK_IN_ARM_MODE_ + #define portINITIAL_SPSR ( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */ +#else + #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#endif + +#define portINSTRUCTION_SIZE ( ( StackType_t ) 4 ) + +/* Constants required to handle critical sections. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + +#ifndef abs + #define abs(x) ((x)>0 ? (x) : -(x)) +#endif + +/** + * Toggle a led using the following algorithm: + * if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) ) + * { + * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET ); + * } + * else + * { + * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET ); + * } + * + */ +#define TOGGLE_LED(port,pin) \ + if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) \ + { \ + (port)->DR[(pin) <<2] = 0x00; \ + } \ + else \ + { \ + (port)->DR[(pin) <<2] = (pin); \ + } + + +/*-----------------------------------------------------------*/ + +/* Setup the watchdog to generate the tick interrupts. */ +static void prvSetupTimerInterrupt( void ); + +/* ulCriticalNesting will get set to zero when the first task starts. It +cannot be initialised to 0 as this will cause interrupts to be enabled +during the kernel initialisation process. */ +uint32_t ulCriticalNesting = ( uint32_t ) 9999; + +/* Tick interrupt routines for cooperative and preemptive operation +respectively. The preemptive version is not defined as __irq as it is called +from an asm wrapper function. */ +void WDG_IRQHandler( void ); + +/* VIC interrupt default handler. */ +static void prvDefaultHandler( void ); + +#if configUSE_WATCHDOG_TICK == 0 + /* Used to update the OCR timer register */ + static u16 s_nPulseLength; +#endif + +/*-----------------------------------------------------------*/ + +/* + * Initialise the stack of a task to look exactly as if a call to + * portSAVE_CONTEXT had been called. + * + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + StackType_t *pxOriginalTOS; + + pxOriginalTOS = pxTopOfStack; + + /* To ensure asserts in tasks.c don't fail, although in this case the assert + is not really required. */ + pxTopOfStack--; + + /* Setup the initial stack of the task. The stack is set exactly as + expected by the portRESTORE_CONTEXT() macro. */ + + /* First on the stack is the return address - which in this case is the + start of the task. The offset is added to make the return address appear + as it would within an IRQ ISR. */ + *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; + pxTopOfStack--; + + *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + pxTopOfStack--; + + /* When the task starts is will expect to find the function parameter in + R0. */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + pxTopOfStack--; + + /* The status register is set for system mode, with interrupts enabled. */ + *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR; + pxTopOfStack--; + + /* Interrupt flags cannot always be stored on the stack and will + instead be stored in a variable, which is then saved as part of the + tasks context. */ + *pxTopOfStack = portNO_CRITICAL_NESTING; + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vPortStartFirstTask( void ); + + /* Start the timer that generates the tick ISR. Interrupts are disabled + here already. */ + prvSetupTimerInterrupt(); + + /* Start the first task. */ + vPortStartFirstTask(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the ARM port will require this function as there + is nothing to return to. */ +} +/*-----------------------------------------------------------*/ + +/* This function is called from an asm wrapper, so does not require the __irq +keyword. */ +#if configUSE_WATCHDOG_TICK == 1 + + static void prvFindFactors(u32 n, u16 *a, u32 *b) + { + /* This function is copied from the ST STR7 library and is + copyright STMicroelectronics. Reproduced with permission. */ + + u32 b0; + u16 a0; + int32_t err, err_min=n; + + *a = a0 = ((n-1)/65536ul) + 1; + *b = b0 = n / *a; + + for (; *a <= 256; (*a)++) + { + *b = n / *a; + err = (int32_t)*a * (int32_t)*b - (int32_t)n; + if (abs(err) > (*a / 2)) + { + (*b)++; + err = (int32_t)*a * (int32_t)*b - (int32_t)n; + } + if (abs(err) < abs(err_min)) + { + err_min = err; + a0 = *a; + b0 = *b; + if (err == 0) break; + } + } + + *a = a0; + *b = b0; + } + /*-----------------------------------------------------------*/ + + static void prvSetupTimerInterrupt( void ) + { + WDG_InitTypeDef xWdg; + uint16_t a; + uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b; + + /* Configure the watchdog as a free running timer that generates a + periodic interrupt. */ + + SCU_APBPeriphClockConfig( __WDG, ENABLE ); + WDG_DeInit(); + WDG_StructInit(&xWdg); + prvFindFactors( n, &a, &b ); + xWdg.WDG_Prescaler = a - 1; + xWdg.WDG_Preload = b - 1; + WDG_Init( &xWdg ); + WDG_ITConfig(ENABLE); + + /* Configure the VIC for the WDG interrupt. */ + VIC_Config( WDG_ITLine, VIC_IRQ, 10 ); + VIC_ITCmd( WDG_ITLine, ENABLE ); + + /* Install the default handlers for both VIC's. */ + VIC0->DVAR = ( uint32_t ) prvDefaultHandler; + VIC1->DVAR = ( uint32_t ) prvDefaultHandler; + + WDG_Cmd(ENABLE); + } + /*-----------------------------------------------------------*/ + + void WDG_IRQHandler( void ) + { + { + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to execute. */ + vTaskSwitchContext(); + } + + /* Clear the interrupt in the watchdog. */ + WDG->SR &= ~0x0001; + } + } + +#else + + static void prvFindFactors(u32 n, u8 *a, u16 *b) + { + /* This function is copied from the ST STR7 library and is + copyright STMicroelectronics. Reproduced with permission. */ + + u16 b0; + u8 a0; + int32_t err, err_min=n; + + + *a = a0 = ((n-1)/256) + 1; + *b = b0 = n / *a; + + for (; *a <= 256; (*a)++) + { + *b = n / *a; + err = (int32_t)*a * (int32_t)*b - (int32_t)n; + if (abs(err) > (*a / 2)) + { + (*b)++; + err = (int32_t)*a * (int32_t)*b - (int32_t)n; + } + if (abs(err) < abs(err_min)) + { + err_min = err; + a0 = *a; + b0 = *b; + if (err == 0) break; + } + } + + *a = a0; + *b = b0; + } + /*-----------------------------------------------------------*/ + + static void prvSetupTimerInterrupt( void ) + { + uint8_t a; + uint16_t b; + uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ; + + TIM_InitTypeDef timer; + + SCU_APBPeriphClockConfig( __TIM23, ENABLE ); + TIM_DeInit(TIM2); + TIM_StructInit(&timer); + prvFindFactors( n, &a, &b ); + + timer.TIM_Mode = TIM_OCM_CHANNEL_1; + timer.TIM_OC1_Modes = TIM_TIMING; + timer.TIM_Clock_Source = TIM_CLK_APB; + timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING; + timer.TIM_Prescaler = a-1; + timer.TIM_Pulse_Level_1 = TIM_HIGH; + timer.TIM_Pulse_Length_1 = s_nPulseLength = b-1; + + TIM_Init (TIM2, &timer); + TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE); + /* Configure the VIC for the WDG interrupt. */ + VIC_Config( TIM2_ITLine, VIC_IRQ, 10 ); + VIC_ITCmd( TIM2_ITLine, ENABLE ); + + /* Install the default handlers for both VIC's. */ + VIC0->DVAR = ( uint32_t ) prvDefaultHandler; + VIC1->DVAR = ( uint32_t ) prvDefaultHandler; + + TIM_CounterCmd(TIM2, TIM_CLEAR); + TIM_CounterCmd(TIM2, TIM_START); + } + /*-----------------------------------------------------------*/ + + void TIM2_IRQHandler( void ) + { + /* Reset the timer counter to avioid overflow. */ + TIM2->OC1R += s_nPulseLength; + + /* Increment the tick counter. */ + if( xTaskIncrementTick() != pdFALSE ) + { + /* Select a new task to run. */ + vTaskSwitchContext(); + } + + /* Clear the interrupt in the watchdog. */ + TIM2->SR &= ~TIM_FLAG_OC1; + } + +#endif /* USE_WATCHDOG_TICK */ + +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortEnterCritical( void ) +{ + /* Disable interrupts first! */ + portDISABLE_INTERRUPTS(); + + /* Now interrupts are disabled ulCriticalNesting can be accessed + directly. Increment ulCriticalNesting to keep a count of how many times + portENTER_CRITICAL() has been called. */ + ulCriticalNesting++; +} +/*-----------------------------------------------------------*/ + +__arm __interwork void vPortExitCritical( void ) +{ + if( ulCriticalNesting > portNO_CRITICAL_NESTING ) + { + /* Decrement the nesting count as we are leaving a critical section. */ + ulCriticalNesting--; + + /* If the nesting level has reached zero then interrupts should be + re-enabled. */ + if( ulCriticalNesting == portNO_CRITICAL_NESTING ) + { + portENABLE_INTERRUPTS(); + } + } +} +/*-----------------------------------------------------------*/ + +static void prvDefaultHandler( void ) +{ +} + + + + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79 new file mode 100644 index 0000000..8ee30f7 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79
@@ -0,0 +1,60 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + RSEG ICODE:CODE + CODE32 + + EXTERN vTaskSwitchContext + + PUBLIC vPortYieldProcessor + PUBLIC vPortStartFirstTask + +#include "ISR_Support.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Starting the first task is just a matter of restoring the context that +; was created by pxPortInitialiseStack(). +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortStartFirstTask: + portRESTORE_CONTEXT + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Manual context switch function. This is the SWI hander. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +vPortYieldProcessor: + ADD LR, LR, #4 ; Add 4 to the LR to make the LR appear exactly + ; as if the context was saved during and IRQ + ; handler. + + portSAVE_CONTEXT ; Save the context of the current task... + LDR R0, =vTaskSwitchContext ; before selecting the next task to execute. + MOV lr, pc + BX R0 + portRESTORE_CONTEXT ; Restore the context of the selected task. + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h new file mode 100644 index 0000000..ba63916 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h
@@ -0,0 +1,114 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +#include <intrinsics.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portYIELD() asm ( "SWI 0" ) +#define portNOP() asm ( "NOP" ) +/*-----------------------------------------------------------*/ + +/* Critical section handling. */ +__arm __interwork void vPortEnterCritical( void ); +__arm __interwork void vPortExitCritical( void ); +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +#define portDISABLE_INTERRUPTS() __disable_interrupt() +#define portENABLE_INTERRUPTS() __enable_interrupt() + + +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ +{ \ +extern void vTaskSwitchContext( void ); \ + \ + if( xSwitchRequired ) \ + { \ + vTaskSwitchContext(); \ + } \ +} +/*-----------------------------------------------------------*/ + + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h new file mode 100644 index 0000000..8ee843a --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h
@@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +#include "FreeRTOSConfig.h" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Context save and restore macro definitions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +portSAVE_CONTEXT MACRO + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack +#if configDATA_MODE == 1 ; Using the Tiny data model + prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers + sst.w r19,72[ep] + sst.w r18,68[ep] + sst.w r17,64[ep] + sst.w r16,60[ep] + sst.w r15,56[ep] + sst.w r14,52[ep] + sst.w r13,48[ep] + sst.w r12,44[ep] + sst.w r11,40[ep] + sst.w r10,36[ep] + sst.w r9,32[ep] + sst.w r8,28[ep] + sst.w r7,24[ep] + sst.w r6,20[ep] + sst.w r5,16[ep] + sst.w r4,12[ep] +#else ; Using the Small/Large data model + prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers + sst.w r19,68[ep] + sst.w r18,64[ep] + sst.w r17,60[ep] + sst.w r16,56[ep] + sst.w r15,52[ep] + sst.w r14,48[ep] + sst.w r13,44[ep] + sst.w r12,40[ep] + sst.w r11,36[ep] + sst.w r10,32[ep] + sst.w r9,28[ep] + sst.w r8,24[ep] + sst.w r7,20[ep] + sst.w r6,16[ep] + sst.w r5,12[ep] +#endif /* configDATA_MODE */ + sst.w r2,8[ep] + sst.w r1,4[ep] + MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack + ld.w lw1(usCriticalNesting)[r1],r2 + sst.w r2,0[ep] + MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB + ld.w lw1(pxCurrentTCB)[r1],r2 + st.w sp,0[r2] + ENDM + + +portRESTORE_CONTEXT MACRO + + MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address + ld.w lw1(pxCurrentTCB)[r1],sp + MOV sp,r1 + ld.w 0[r1],sp ; load stackpointer + MOV sp,ep ; set stack pointer to element pointer + sld.w 0[ep],r1 ; load usCriticalNesting value from stack + MOVHI hi1(usCriticalNesting),r0,r2 + st.w r1,lw1(usCriticalNesting)[r2] + sld.w 4[ep],r1 ; restore general purpose registers + sld.w 8[ep],r2 +#if configDATA_MODE == 1 ; Using Tiny data model + sld.w 12[ep],r4 + sld.w 16[ep],r5 + sld.w 20[ep],r6 + sld.w 24[ep],r7 + sld.w 28[ep],r8 + sld.w 32[ep],r9 + sld.w 36[ep],r10 + sld.w 40[ep],r11 + sld.w 44[ep],r12 + sld.w 48[ep],r13 + sld.w 52[ep],r14 + sld.w 56[ep],r15 + sld.w 60[ep],r16 + sld.w 64[ep],r17 + sld.w 68[ep],r18 + sld.w 72[ep],r19 + dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} +#else ; Using Small/Large data model + sld.w 12[ep],r5 + sld.w 16[ep],r6 + sld.w 20[ep],r7 + sld.w 24[ep],r8 + sld.w 28[ep],r9 + sld.w 32[ep],r10 + sld.w 36[ep],r11 + sld.w 40[ep],r12 + sld.w 44[ep],r13 + sld.w 48[ep],r14 + sld.w 52[ep],r15 + sld.w 56[ep],r16 + sld.w 60[ep],r17 + sld.w 64[ep],r18 + sld.w 68[ep],r19 + dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +#endif /* configDATA_MODE */ + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI + + ENDM
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/port.c b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/port.c new file mode 100644 index 0000000..b6e7580 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/port.c
@@ -0,0 +1,183 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include <stdlib.h> + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Critical nesting should be initialised to a non zero value so interrupts don't +accidentally get enabled before the scheduler is started. */ +#define portINITIAL_CRITICAL_NESTING (( StackType_t ) 10) + +/* The PSW value assigned to tasks when they start to run for the first time. */ +#define portPSW (( StackType_t ) 0x00000000) + +/* We require the address of the pxCurrentTCB variable, but don't want to know +any details of its type. */ +typedef void TCB_t; +extern volatile TCB_t * volatile pxCurrentTCB; + +/* Keeps track of the nesting level of critical sections. */ +volatile StackType_t usCriticalNesting = portINITIAL_CRITICAL_NESTING; +/*-----------------------------------------------------------*/ + +/* Sets up the timer to generate the tick interrupt. */ +static void prvSetupTimerInterrupt( void ); + +/*-----------------------------------------------------------*/ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */ + pxTopOfStack--; + *pxTopOfStack = portPSW; /* Initial PSW value */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x20202020; /* Initial Value of R20 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x21212121; /* Initial Value of R21 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R22 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x23232323; /* Initial Value of R23 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x24242424; /* Initial Value of R24 */ + pxTopOfStack--; +#if (__DATA_MODEL__ == 0) || (__DATA_MODEL__ == 1) + *pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 */ + pxTopOfStack--; +#endif /* configDATA_MODE */ + *pxTopOfStack = ( StackType_t ) 0x26262626; /* Initial Value of R26 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x27272727; /* Initial Value of R27 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x28282828; /* Initial Value of R28 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x29292929; /* Initial Value of R29 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x30303030; /* Initial Value of R30 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x19191919; /* Initial Value of R19 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x18181818; /* Initial Value of R18 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x17171717; /* Initial Value of R17 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x16161616; /* Initial Value of R16 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x15151515; /* Initial Value of R15 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x14141414; /* Initial Value of R14 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x13131313; /* Initial Value of R13 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x12121212; /* Initial Value of R12 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x11111111; /* Initial Value of R11 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x10101010; /* Initial Value of R10 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x99999999; /* Initial Value of R09 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x88888888; /* Initial Value of R08 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x77777777; /* Initial Value of R07 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x66666666; /* Initial Value of R06 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) 0x55555555; /* Initial Value of R05 */ + pxTopOfStack--; +#if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1 + *pxTopOfStack = ( StackType_t ) 0x44444444; /* Initial Value of R04 */ + pxTopOfStack--; +#endif /* configDATA_MODE */ + *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R02 */ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 is expected to hold the function parameter*/ + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING; + + /* + * Return a pointer to the top of the stack we have generated so this can + * be stored in the task control block for the task. + */ + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ + /* Setup the hardware to generate the tick. Interrupts are disabled when + this function is called. */ + prvSetupTimerInterrupt(); + + /* Restore the context of the first task that is going to run. */ + vPortStart(); + + /* Should not get here as the tasks are now running! */ + return pdTRUE; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* It is unlikely that the V850ES/Fx3 port will get stopped. If required simply + disable the tick interrupt here. */ +} +/*-----------------------------------------------------------*/ + +/* + * Hardware initialisation to generate the RTOS tick. This uses + */ +static void prvSetupTimerInterrupt( void ) +{ + TM0CE = 0; /* TMM0 operation disable */ + TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */ + TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */ + + #ifdef __IAR_V850ES_Fx3__ + { + TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */ + } + #else + { + TM0CMP0 = (configCPU_CLOCK_HZ / configTICK_RATE_HZ); + } + #endif + + TM0EQIC0 &= 0xF8; + TM0CTL0 = 0x00; + TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */ + TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */ + TM0CE = 1; /* TMM0 operation enable */ +} +/*-----------------------------------------------------------*/ + +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85 new file mode 100644 index 0000000..f1393b3 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85
@@ -0,0 +1,315 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ +; Note: Select the correct include files for the device used by the application. +#include "FreeRTOSConfig.h" +;------------------------------------------------------------------------------ + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Security ID definition +;------------------------------------------------------------------------------ +#define CG_SECURITY0 0FFH +#define CG_SECURITY1 0FFH +#define CG_SECURITY2 0FFH +#define CG_SECURITY3 0FFH +#define CG_SECURITY4 0FFH +#define CG_SECURITY5 0FFH +#define CG_SECURITY6 0FFH +#define CG_SECURITY7 0FFH +#define CG_SECURITY8 0FFH +#define CG_SECURITY9 0FFH + +; Tick ISR Prototype +;------------------------------------------------------------------------------ + PUBWEAK `??MD_INTTM0EQ0??INTVEC 640` + PUBLIC MD_INTTM0EQ0 + +MD_INTTM0EQ0 SYMBOL "MD_INTTM0EQ0" +`??MD_INTTM0EQ0??INTVEC 640` SYMBOL "??INTVEC 640", MD_INTTM0EQ0 + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the remaining general purpose registers +; and the usCriticalNesting Value of the active Task onto the task stack +; saves stack pointer to the TCB +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO +#if configDATA_MODE == 1 ; Using the Tiny data model + prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers + sst.w r19,72[ep] + sst.w r18,68[ep] + sst.w r17,64[ep] + sst.w r16,60[ep] + sst.w r15,56[ep] + sst.w r14,52[ep] + sst.w r13,48[ep] + sst.w r12,44[ep] + sst.w r11,40[ep] + sst.w r10,36[ep] + sst.w r9,32[ep] + sst.w r8,28[ep] + sst.w r7,24[ep] + sst.w r6,20[ep] + sst.w r5,16[ep] + sst.w r4,12[ep] +#else ; Using the Small/Large data model + prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers + sst.w r19,68[ep] + sst.w r18,64[ep] + sst.w r17,60[ep] + sst.w r16,56[ep] + sst.w r15,52[ep] + sst.w r14,48[ep] + sst.w r13,44[ep] + sst.w r12,40[ep] + sst.w r11,36[ep] + sst.w r10,32[ep] + sst.w r9,28[ep] + sst.w r8,24[ep] + sst.w r7,20[ep] + sst.w r6,16[ep] + sst.w r5,12[ep] +#endif /* configDATA_MODE */ + sst.w r2,8[ep] + sst.w r1,4[ep] + MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack + ld.w lw1(usCriticalNesting)[r1],r2 + sst.w r2,0[ep] + MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB + ld.w lw1(pxCurrentTCB)[r1],r2 + st.w sp,0[r2] + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Gets stack pointer from the current TCB +; Restores the context of the usCriticalNesting value and general purpose +; registers of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address + ld.w lw1(pxCurrentTCB)[r1],sp + MOV sp,r1 + ld.w 0[r1],sp ; load stackpointer + MOV sp,ep ; set stack pointer to element pointer + sld.w 0[ep],r1 ; load usCriticalNesting value from stack + MOVHI hi1(usCriticalNesting),r0,r2 + st.w r1,lw1(usCriticalNesting)[r2] + sld.w 4[ep],r1 ; restore general purpose registers + sld.w 8[ep],r2 +#if configDATA_MODE == 1 ; Using Tiny data model + sld.w 12[ep],r4 + sld.w 16[ep],r5 + sld.w 20[ep],r6 + sld.w 24[ep],r7 + sld.w 28[ep],r8 + sld.w 32[ep],r9 + sld.w 36[ep],r10 + sld.w 40[ep],r11 + sld.w 44[ep],r12 + sld.w 48[ep],r13 + sld.w 52[ep],r14 + sld.w 56[ep],r15 + sld.w 60[ep],r16 + sld.w 64[ep],r17 + sld.w 68[ep],r18 + sld.w 72[ep],r19 + dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} +#else ; Using Small/Large data model + sld.w 12[ep],r5 + sld.w 16[ep],r6 + sld.w 20[ep],r7 + sld.w 24[ep],r8 + sld.w 28[ep],r9 + sld.w 32[ep],r10 + sld.w 36[ep],r11 + sld.w 40[ep],r12 + sld.w 44[ep],r13 + sld.w 48[ep],r14 + sld.w 52[ep],r15 + sld.w 56[ep],r16 + sld.w 60[ep],r17 + sld.w 64[ep],r18 + sld.w 68[ep],r19 + dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +#endif /* configDATA_MODE */ + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ld.w 0[sp],lp + ldsr lp,5 ; restore PSW + DI + ld.w 4[sp],lp ; restore LP + ld.w 8[sp],lp ; restore LP + ADD 0x0C,sp ; set SP to right position + EI + jmp [lp] +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Port Yield function to check for a Task switch in the cooperative and +; preemptive mode +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +;------------------------------------------------------------------------------ + + RSEG CODE:CODE +vPortYield: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +;------------------------------------------------------------------------------ +#if configUSE_PREEMPTION == 1 ; use preemptive kernel mode + +MD_INTTM0EQ0: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl xTaskIncrementTick,lp ; Call the timer tick function. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI +;------------------------------------------------------------------------------ +#else ; use cooperative kernel mode + +MD_INTTM0EQ0: + prepare {lp,ep},8,sp + sst.w r1,4[ep] + sst.w r5,0[ep] + jarl xTaskIncrementTick,lp ; Call the timer tick function. + sld.w 0[ep],r5 + sld.w 4[ep],r1 + dispose 8,{lp,ep} + RETI +#endif /* configUSE_PREEMPTION */ + +;------------------------------------------------------------------------------ + COMMON INTVEC:CODE:ROOT(2) + ORG 640 +`??MD_INTTM0EQ0??INTVEC 640`: + JR MD_INTTM0EQ0 + + RSEG NEAR_ID:CONST:SORT:NOROOT(2) +`?<Initializer for usCriticalNesting>`: + DW 10 + + COMMON INTVEC:CODE:ROOT(2) + ORG 40H +`??vPortYield??INTVEC 40`: + JR vPortYield + +;------------------------------------------------------------------------------ +; set microcontroller security ID + + COMMON INTVEC:CODE:ROOT(2) + ORG 70H +`SECUID`: + DB CG_SECURITY0 + DB CG_SECURITY1 + DB CG_SECURITY2 + DB CG_SECURITY3 + DB CG_SECURITY4 + DB CG_SECURITY5 + DB CG_SECURITY6 + DB CG_SECURITY7 + DB CG_SECURITY8 + DB CG_SECURITY9 + + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85 new file mode 100644 index 0000000..62cf09f --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85
@@ -0,0 +1,335 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ +; Note: Select the correct include files for the device used by the application. +#include "FreeRTOSConfig.h" +;------------------------------------------------------------------------------ + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Security ID definition +;------------------------------------------------------------------------------ +#define CG_SECURITY0 0FFH +#define CG_SECURITY1 0FFH +#define CG_SECURITY2 0FFH +#define CG_SECURITY3 0FFH +#define CG_SECURITY4 0FFH +#define CG_SECURITY5 0FFH +#define CG_SECURITY6 0FFH +#define CG_SECURITY7 0FFH +#define CG_SECURITY8 0FFH +#define CG_SECURITY9 0FFH + +; Option Byte definitions +;------------------------------------------------------------------------------ +#define CG_OPTION7A 0x00 +#define CG_OPTION7B 0x04 +#define OPT7C 0x00 +#define OPT7D 0x00 +#define OPT7E 0x00 +#define OPT7F 0x00 + +; Tick ISR Prototype +;------------------------------------------------------------------------------ + PUBWEAK `??MD_INTTM0EQ0??INTVEC 608` + PUBLIC MD_INTTM0EQ0 + +MD_INTTM0EQ0 SYMBOL "MD_INTTM0EQ0" +`??MD_INTTM0EQ0??INTVEC 608` SYMBOL "??INTVEC 608", MD_INTTM0EQ0 + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the remaining general purpose registers +; and the usCriticalNesting Value of the active Task onto the task stack +; saves stack pointer to the TCB +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO +#if configDATA_MODE == 1 ; Using the Tiny data model + prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers + sst.w r19,72[ep] + sst.w r18,68[ep] + sst.w r17,64[ep] + sst.w r16,60[ep] + sst.w r15,56[ep] + sst.w r14,52[ep] + sst.w r13,48[ep] + sst.w r12,44[ep] + sst.w r11,40[ep] + sst.w r10,36[ep] + sst.w r9,32[ep] + sst.w r8,28[ep] + sst.w r7,24[ep] + sst.w r6,20[ep] + sst.w r5,16[ep] + sst.w r4,12[ep] +#else ; Using the Small/Large data model + prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers + sst.w r19,68[ep] + sst.w r18,64[ep] + sst.w r17,60[ep] + sst.w r16,56[ep] + sst.w r15,52[ep] + sst.w r14,48[ep] + sst.w r13,44[ep] + sst.w r12,40[ep] + sst.w r11,36[ep] + sst.w r10,32[ep] + sst.w r9,28[ep] + sst.w r8,24[ep] + sst.w r7,20[ep] + sst.w r6,16[ep] + sst.w r5,12[ep] +#endif /* configDATA_MODE */ + sst.w r2,8[ep] + sst.w r1,4[ep] + MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack + ld.w lw1(usCriticalNesting)[r1],r2 + sst.w r2,0[ep] + MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB + ld.w lw1(pxCurrentTCB)[r1],r2 + st.w sp,0[r2] + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Gets stack pointer from the current TCB +; Restores the context of the usCriticalNesting value and general purpose +; registers of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address + ld.w lw1(pxCurrentTCB)[r1],sp + MOV sp,r1 + ld.w 0[r1],sp ; load stackpointer + MOV sp,ep ; set stack pointer to element pointer + sld.w 0[ep],r1 ; load usCriticalNesting value from stack + MOVHI hi1(usCriticalNesting),r0,r2 + st.w r1,lw1(usCriticalNesting)[r2] + sld.w 4[ep],r1 ; restore general purpose registers + sld.w 8[ep],r2 +#if configDATA_MODE == 1 ; Using Tiny data model + sld.w 12[ep],r4 + sld.w 16[ep],r5 + sld.w 20[ep],r6 + sld.w 24[ep],r7 + sld.w 28[ep],r8 + sld.w 32[ep],r9 + sld.w 36[ep],r10 + sld.w 40[ep],r11 + sld.w 44[ep],r12 + sld.w 48[ep],r13 + sld.w 52[ep],r14 + sld.w 56[ep],r15 + sld.w 60[ep],r16 + sld.w 64[ep],r17 + sld.w 68[ep],r18 + sld.w 72[ep],r19 + dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} +#else ; Using Small/Large data model + sld.w 12[ep],r5 + sld.w 16[ep],r6 + sld.w 20[ep],r7 + sld.w 24[ep],r8 + sld.w 28[ep],r9 + sld.w 32[ep],r10 + sld.w 36[ep],r11 + sld.w 40[ep],r12 + sld.w 44[ep],r13 + sld.w 48[ep],r14 + sld.w 52[ep],r15 + sld.w 56[ep],r16 + sld.w 60[ep],r17 + sld.w 64[ep],r18 + sld.w 68[ep],r19 + dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +#endif /* configDATA_MODE */ + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ld.w 0[sp],lp + ldsr lp,5 ; restore PSW + DI + ld.w 4[sp],lp ; restore LP + ld.w 8[sp],lp ; restore LP + ADD 0x0C,sp ; set SP to right position + EI + jmp [lp] +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Port Yield function to check for a Task switch in the cooperative and +; preemptive mode +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +;------------------------------------------------------------------------------ + + RSEG CODE:CODE +vPortYield: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +;------------------------------------------------------------------------------ +#if configUSE_PREEMPTION == 1 ; use preemptive kernel mode + +MD_INTTM0EQ0: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl xTaskIncrementTick,lp ; Call the timer tick function. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI +;------------------------------------------------------------------------------ +#else ; use cooperative kernel mode + +MD_INTTM0EQ0: + prepare {lp,ep},8,sp + sst.w r1,4[ep] + sst.w r5,0[ep] + jarl xTaskIncrementTick,lp ; Call the timer tick function. + sld.w 0[ep],r5 + sld.w 4[ep],r1 + dispose 8,{lp,ep} + RETI +#endif /* configUSE_PREEMPTION */ + +;------------------------------------------------------------------------------ + COMMON INTVEC:CODE:ROOT(2) + ORG 608 +`??MD_INTTM0EQ0??INTVEC 608`: + JR MD_INTTM0EQ0 + + RSEG NEAR_ID:CONST:SORT:NOROOT(2) +`?<Initializer for usCriticalNesting>`: + DW 10 + + COMMON INTVEC:CODE:ROOT(2) + ORG 40H +`??vPortYield??INTVEC 40`: + JR vPortYield + +;------------------------------------------------------------------------------ +; set microcontroller security ID + + COMMON INTVEC:CODE:ROOT(2) + ORG 70H +`SECUID`: + DB CG_SECURITY0 + DB CG_SECURITY1 + DB CG_SECURITY2 + DB CG_SECURITY3 + DB CG_SECURITY4 + DB CG_SECURITY5 + DB CG_SECURITY6 + DB CG_SECURITY7 + DB CG_SECURITY8 + DB CG_SECURITY9 + +;------------------------------------------------------------------------------ +; set microcontroller option bytes + + COMMON INTVEC:CODE:ROOT(2) + ORG 7AH +`OPTBYTES`: + DB CG_OPTION7A + DB CG_OPTION7B + DB OPT7C + DB OPT7D + DB OPT7E + DB OPT7F + + END \ No newline at end of file
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85 b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85 new file mode 100644 index 0000000..4be6fb3 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85
@@ -0,0 +1,350 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ +; Note: Select the correct include files for the device used by the application. +#include "FreeRTOSConfig.h" +;------------------------------------------------------------------------------ + +; Functions used by scheduler +;------------------------------------------------------------------------------ + EXTERN vTaskSwitchContext + EXTERN xTaskIncrementTick + +; Variables used by scheduler +;------------------------------------------------------------------------------ + EXTERN pxCurrentTCB + EXTERN usCriticalNesting + +; Functions implemented in this file +;------------------------------------------------------------------------------ + PUBLIC vPortYield + PUBLIC vPortStart + +; Security ID definition +;------------------------------------------------------------------------------ +#define CG_SECURITY0 0FFH +#define CG_SECURITY1 0FFH +#define CG_SECURITY2 0FFH +#define CG_SECURITY3 0FFH +#define CG_SECURITY4 0FFH +#define CG_SECURITY5 0FFH +#define CG_SECURITY6 0FFH +#define CG_SECURITY7 0FFH +#define CG_SECURITY8 0FFH +#define CG_SECURITY9 0FFH + +; Tick ISR Prototype +;------------------------------------------------------------------------------ + PUBWEAK `??MD_INTTM0EQ0??INTVEC 544` + PUBLIC MD_INTTM0EQ0 + +MD_INTTM0EQ0 SYMBOL "MD_INTTM0EQ0" +`??MD_INTTM0EQ0??INTVEC 544` SYMBOL "??INTVEC 544", MD_INTTM0EQ0 + +;------------------------------------------------------------------------------ +; portSAVE_CONTEXT MACRO +; Saves the context of the remaining general purpose registers +; and the usCriticalNesting Value of the active Task onto the task stack +; saves stack pointer to the TCB +;------------------------------------------------------------------------------ +portSAVE_CONTEXT MACRO +#if configDATA_MODE == 1 ; Using the Tiny data model + prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers + sst.w r19,72[ep] + sst.w r18,68[ep] + sst.w r17,64[ep] + sst.w r16,60[ep] + sst.w r15,56[ep] + sst.w r14,52[ep] + sst.w r13,48[ep] + sst.w r12,44[ep] + sst.w r11,40[ep] + sst.w r10,36[ep] + sst.w r9,32[ep] + sst.w r8,28[ep] + sst.w r7,24[ep] + sst.w r6,20[ep] + sst.w r5,16[ep] + sst.w r4,12[ep] +#else ; Using the Small/Large data model + prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp ; save general purpose registers + sst.w r19,68[ep] + sst.w r18,64[ep] + sst.w r17,60[ep] + sst.w r16,56[ep] + sst.w r15,52[ep] + sst.w r14,48[ep] + sst.w r13,44[ep] + sst.w r12,40[ep] + sst.w r11,36[ep] + sst.w r10,32[ep] + sst.w r9,28[ep] + sst.w r8,24[ep] + sst.w r7,20[ep] + sst.w r6,16[ep] + sst.w r5,12[ep] +#endif /* configDATA_MODE */ + sst.w r2,8[ep] + sst.w r1,4[ep] + MOVHI hi1(usCriticalNesting),r0,r1 ; save usCriticalNesting value to stack + ld.w lw1(usCriticalNesting)[r1],r2 + sst.w r2,0[ep] + MOVHI hi1(pxCurrentTCB),r0,r1 ; save SP to top of current TCB + ld.w lw1(pxCurrentTCB)[r1],r2 + st.w sp,0[r2] + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; portRESTORE_CONTEXT MACRO +; Gets stack pointer from the current TCB +; Restores the context of the usCriticalNesting value and general purpose +; registers of the selected task from the task stack +;------------------------------------------------------------------------------ +portRESTORE_CONTEXT MACRO + MOVHI hi1(pxCurrentTCB),r0,r1 ; get Stackpointer address + ld.w lw1(pxCurrentTCB)[r1],sp + MOV sp,r1 + ld.w 0[r1],sp ; load stackpointer + MOV sp,ep ; set stack pointer to element pointer + sld.w 0[ep],r1 ; load usCriticalNesting value from stack + MOVHI hi1(usCriticalNesting),r0,r2 + st.w r1,lw1(usCriticalNesting)[r2] + sld.w 4[ep],r1 ; restore general purpose registers + sld.w 8[ep],r2 +#if configDATA_MODE == 1 ; Using Tiny data model + sld.w 12[ep],r4 + sld.w 16[ep],r5 + sld.w 20[ep],r6 + sld.w 24[ep],r7 + sld.w 28[ep],r8 + sld.w 32[ep],r9 + sld.w 36[ep],r10 + sld.w 40[ep],r11 + sld.w 44[ep],r12 + sld.w 48[ep],r13 + sld.w 52[ep],r14 + sld.w 56[ep],r15 + sld.w 60[ep],r16 + sld.w 64[ep],r17 + sld.w 68[ep],r18 + sld.w 72[ep],r19 + dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30} +#else ; Using Small/Large data model + sld.w 12[ep],r5 + sld.w 16[ep],r6 + sld.w 20[ep],r7 + sld.w 24[ep],r8 + sld.w 28[ep],r9 + sld.w 32[ep],r10 + sld.w 36[ep],r11 + sld.w 40[ep],r12 + sld.w 44[ep],r13 + sld.w 48[ep],r14 + sld.w 52[ep],r15 + sld.w 56[ep],r16 + sld.w 60[ep],r17 + sld.w 64[ep],r18 + sld.w 68[ep],r19 + dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30} +#endif /* configDATA_MODE */ + ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Restore the context of the first task that is going to run. +; +; Input: NONE +; +; Call: CALL vPortStart +; +; Output: NONE +;------------------------------------------------------------------------------ + RSEG CODE:CODE +vPortStart: + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ld.w 0[sp],lp + ldsr lp,5 ; restore PSW + DI + ld.w 4[sp],lp ; restore LP + ld.w 8[sp],lp ; restore LP + ADD 0x0C,sp ; set SP to right position + EI + jmp [lp] +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Port Yield function to check for a Task switch in the cooperative and +; preemptive mode +; +; Input: NONE +; +; Call: CALL vPortYield +; +; Output: NONE +;------------------------------------------------------------------------------ + + RSEG CODE:CODE +vPortYield: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Perform the necessary steps of the Tick Count Increment and Task Switch +; depending on the chosen kernel configuration +; +; Input: NONE +; +; Call: ISR +; +; Output: NONE +;------------------------------------------------------------------------------ +#if configUSE_PREEMPTION == 1 ; use preemptive kernel mode + +MD_INTTM0EQ0: + + add -0x0C,sp ; prepare stack to save necessary values + st.w lp,8[sp] ; store LP to stack + stsr 0,r31 + st.w lp,4[sp] ; store EIPC to stack + stsr 1,lp + st.w lp,0[sp] ; store EIPSW to stack + portSAVE_CONTEXT ; Save the context of the current task. + jarl xTaskIncrementTick,lp ; Call the timer tick function. + jarl vTaskSwitchContext,lp ; Call the scheduler. + portRESTORE_CONTEXT ; Restore the context of whichever task the ... + ; ... scheduler decided should run. + ld.w 0[sp],lp ; restore EIPSW from stack + ldsr lp,1 + ld.w 4[sp],lp ; restore EIPC from stack + ldsr lp,0 + ld.w 8[sp],lp ; restore LP from stack + add 0x0C,sp ; set SP to right position + + RETI +;------------------------------------------------------------------------------ +#else ; use cooperative kernel mode + +MD_INTTM0EQ0: + prepare {lp,ep},8,sp + sst.w r1,4[ep] + sst.w r5,0[ep] + jarl xTaskIncrementTick,lp ; Call the timer tick function. + sld.w 0[ep],r5 + sld.w 4[ep],r1 + dispose 8,{lp,ep} + RETI +#endif /* configUSE_PREEMPTION */ + +;------------------------------------------------------------------------------ + COMMON INTVEC:CODE:ROOT(2) + ORG 544 +`??MD_INTTM0EQ0??INTVEC 544`: + JR MD_INTTM0EQ0 + + RSEG NEAR_ID:CONST:SORT:NOROOT(2) +`?<Initializer for usCriticalNesting>`: + DW 10 + + COMMON INTVEC:CODE:ROOT(2) + ORG 40H +`??vPortYield??INTVEC 40`: + JR vPortYield + +;------------------------------------------------------------------------------ +; set microcontroller security ID + + COMMON INTVEC:CODE:ROOT(2) + ORG 70H +`SECUID`: + DB CG_SECURITY0 + DB CG_SECURITY1 + DB CG_SECURITY2 + DB CG_SECURITY3 + DB CG_SECURITY4 + DB CG_SECURITY5 + DB CG_SECURITY6 + DB CG_SECURITY7 + DB CG_SECURITY8 + DB CG_SECURITY9 + + +; set microcontroller Option bytes + + COMMON INTVEC:CODE:ROOT(2) + ORG 122 +`OPTBYTES`: + DB 0xFD + DB 0xFF + DB 0xFF + DB 0xFF + DB 0xFF + DB 0xFF + +#if configOCD_USAGE == 1 + + COMMON INTVEC:CODE:ROOT(4) + ORG 0x230 + PUBLIC ROM_INT2 +ROM_INT2: + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + + + COMMON INTVEC:CODE:ROOT(4) + ORG 0x60 + PUBLIC ROM_INT +ROM_INT: + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + DB 0xff, 0xff, 0xff, 0xff + +#endif /* configOCD_USAGE */ + + END +
diff --git a/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h new file mode 100644 index 0000000..5a97624 --- /dev/null +++ b/190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h
@@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE unsigned int +#define portBASE_TYPE int + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if (configUSE_16_BIT_TICKS==1) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#endif +/*-----------------------------------------------------------*/ + +/* Interrupt control macros. */ +#define portDISABLE_INTERRUPTS() __asm ( "DI" ) +#define portENABLE_INTERRUPTS() __asm ( "EI" ) +/*-----------------------------------------------------------*/ + +/* Critical section control macros. */ +#define portNO_CRITICAL_SECTION_NESTING ( ( UBaseType_t ) 0 ) + +#define portENTER_CRITICAL() \ +{ \ +extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \ + \ + portDISABLE_INTERRUPTS(); \ + \ + /* Now interrupts are disabled ulCriticalNesting can be accessed */ \ + /* directly. Increment ulCriticalNesting to keep a count of how many */ \ + /* times portENTER_CRITICAL() has been called. */ \ + usCriticalNesting++; \ +} + +#define portEXIT_CRITICAL() \ +{ \ +extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting; \ + \ + if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING ) \ + { \ + /* Decrement the nesting count as we are leaving a critical section. */ \ + usCriticalNesting--; \ + \ + /* If the nesting level has reached zero then interrupts should be */ \ + /* re-enabled. */ \ + if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING ) \ + { \ + portENABLE_INTERRUPTS(); \ + } \ + } \ +} +/*-----------------------------------------------------------*/ + +/* Task utilities. */ +extern void vPortYield( void ); +extern void vPortStart( void ); +extern void portSAVE_CONTEXT( void ); +extern void portRESTORE_CONTEXT( void ); +#define portYIELD() __asm ( "trap 0" ) +#define portNOP() __asm ( "NOP" ) +extern void vTaskSwitchContext( void ); +#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext() + +/*-----------------------------------------------------------*/ + +/* Hardwware specifics. */ +#define portBYTE_ALIGNMENT 4 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ +