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  1. ae448fc Add Cortex M23 GCC and IAR ports. Add demo projects for Nuvoton NuMaker-PFM-2351. by Gaurav Aggarwal · 5 years ago
  2. 079d081 Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit. by Richard Barry · 5 years ago
  3. 27ca5c8 Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM Cortex-M33 ports to assist with link time optimisation. by Richard Barry · 5 years ago
  4. 8437744 Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation. by Richard Barry · 5 years ago
  5. 6068454 Fix potential memory leak in the Win32 FreeRTOS+TCP network interface initialisation sequence. by Richard Barry · 5 years ago
  6. dd9a971 Export port architecture name for COrtex-M33. This can be used by debuggers to find the port in-use to be able to correctly decode the context stored on the stack. by Gaurav Aggarwal · 5 years ago
  7. ba39a95 Fix spelling of priority in comments. by Gaurav Aggarwal · 5 years ago
  8. 12fb75b Fix warning portHAS_STACK_OVERFLOW_CHECKING not defined by Gaurav Aggarwal · 5 years ago
  9. 2265d70 Correcting spelling mistakes in comments only. by Richard Barry · 5 years ago
  10. 06596c3 Prepare the RISC-V port layer for addition of 64-bit port. by Richard Barry · 5 years ago
  11. 50e67a8 Update version number in +TCP code. by Richard Barry · 5 years ago
  12. 5fe8465 Change type of usStackDepth to configSTACK_DEPTH_TYPE. by Gaurav Aggarwal · 5 years ago
  13. 5623c69 Fix Build and Links failure in MPU projects. Minor cosmetic changes in some V8M files. by Gaurav Aggarwal · 5 years ago
  14. 8b6ab5f Add instructions on building the Cortex-M33 secure and non secure projects into the comments of that project and into a readme.txt file. by Richard Barry · 5 years ago
  15. ceeff14 Set default value of configRUN_FREERTOS_SECURE_ONLY to 0. by Gaurav Aggarwal · 5 years ago
  16. 5849459 Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change spaces to tabs. by Gaurav Aggarwal · 5 years ago
  17. c3c9c12 Update the common demo death.c to use the updated macro name to give it a secure context. by Richard Barry · 5 years ago
  18. ce576f3 First Official Release of ARMV8M Support. This release removes Pre-Release from all the ARMv8M files licensees. by Gaurav Aggarwal · 5 years ago
  19. 58ba10e Update version number in readiness for V10.2.0 release. by Richard Barry · 5 years ago
  20. 55ad386 Sync the Renesas port to AFR Git Repo by Gaurav Aggarwal · 5 years ago
  21. 0de2a27 Fix definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE by Gaurav Aggarwal · 5 years ago
  22. 2c88fb7 Fix build failure when dynamic allocation is not enabled. by Gaurav Aggarwal · 5 years ago
  23. 6844bef Replace the pdf RISC-V documentation with links to the documentation web pages. by Richard Barry · 5 years ago
  24. b2b1b09 Fix bug in core_cm3.c atomic macros. by Richard Barry · 5 years ago
  25. 3153131 Add Dornerworks attribution to makefiles that build the Freedom Studio RISC-V project. by Richard Barry · 5 years ago
  26. 7e08fd6 Add makefiles that build the FreedomStudio project (provided by Dornerworks - thanks). by Richard Barry · 5 years ago
  27. fb73829 Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState(). by Richard Barry · 5 years ago
  28. df5952f Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations. by Richard Barry · 5 years ago
  29. 817783d Copyright updates from Cadence. by Gaurav Aggarwal · 5 years ago
  30. a4941ac Update main.c() for the WIN32-MingW project so the trace recorder is initialized even when the simple blinky demo is used - otherwise the trace recorder causes an exception as it is used without first being initialized. by Richard Barry · 5 years ago
  31. 80df5cd Update the pin mux setup on the Vega board demo to enable the LED. by Richard Barry · 5 years ago
  32. 11d9c44 Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason). by Richard Barry · 5 years ago
  33. e2af102 Re-org of RISC-V file structure and naming step 2. by Richard Barry · 5 years ago
  34. 818eecc Re-org of RISC-V file structure and naming step 1. by Richard Barry · 5 years ago
  35. 3474e75 Create folder to hold RISC-V chip specific extensions. by Richard Barry · 5 years ago
  36. db750d0 Update RSIC-V port layer after testing saving and receiving of chip specific registers. by Richard Barry · 5 years ago
  37. 60b133b Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack. by Richard Barry · 5 years ago
  38. 911a1de Correct accidental deletion in GenQTest.c. by Richard Barry · 5 years ago
  39. d369110 Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings. by Richard Barry · 5 years ago
  40. 178fe4f Update the Freedom Studio RISC-V project so the gdbinit options are now specified on the command line. by Richard Barry · 5 years ago
  41. e5daf23 Update Freedom Studio RISC-V demo for the latest GCC RISC-V port - not yet tested. by Richard Barry · 5 years ago
  42. 80f6f3e Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running. by Richard Barry · 5 years ago
  43. ce36928 Rename directories in the RISC-V port. by Richard Barry · 5 years ago
  44. 2181c03 Backup Microsemi Renode project before adding a build configuration for the target hardware. by Richard Barry · 6 years ago
  45. 8d213b4 Add vTimerSetReloadMode() calls to the code coverage tests. by Richard Barry · 6 years ago
  46. 6edabbe Update the the MPU simulator project to exercise the timer API. by Richard Barry · 6 years ago
  47. 148f588 Remove "FromISR' functions from the list of functions that switch to a privileged mode as IRQs are privileged already. by Richard Barry · 6 years ago
  48. 8285ca6 Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode. by Richard Barry · 6 years ago
  49. 1018069 Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT. by Richard Barry · 6 years ago
  50. 7cc42b2 Save changes to the RISC-V port layer before making changes necessary to support pulpino too: by Richard Barry · 6 years ago
  51. 866635d Microsemi RISC-V project: by Richard Barry · 6 years ago
  52. 6b37800 Backup checkin of MiFive demo running in ReNode emulator. by Richard Barry · 6 years ago
  53. 9a136a5 Backup check in of the Microsemi IGLOO2 Creative Board RISC-V demo - still a work in progress. by Richard Barry · 6 years ago
  54. 4b9dd38 Backup checking of the Freedom Studio RISC-V project - still a work in progress. by Richard Barry · 6 years ago
  55. 65f7a2d Update RISC-V port to use a separate interrupt stack. by Richard Barry · 6 years ago
  56. e85ea96 Some efficiency improvements in Risc-V port. by Richard Barry · 6 years ago
  57. dc99300 First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo. by Richard Barry · 6 years ago
  58. d0ef322 Add kernel code to the RISC-V-Qemu-sifive_e-FreedomStudio demo. by Richard Barry · 6 years ago
  59. f7102f2 Add a starting point for a Freedom Studio Risc V project. by Richard Barry · 6 years ago
  60. db64297 Provide each Risc V task with an initial mstatus register value. by Richard Barry · 6 years ago
  61. 8cef339 Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress. by Richard Barry · 6 years ago
  62. baee711 Continue work on Risc V port. by Richard Barry · 6 years ago
  63. 74d0d16 Update xTaskRemoveFromEventList() so when tickless idle is used prvResetNextTaskUnblockTime() only gets called if the scheduler is not locked, as it would get called when the scheduler is unlocked in any case. by Richard Barry · 6 years ago
  64. 55ff893 Update the method used to detect if a timer is active. Previously the timer was deemed to be inactive if it was not referenced from a list. However, when a timer is updated it is temporarily removed from, then re-added to a list, so now the timer's active status is stored separately. by Richard Barry · 6 years ago
  65. 6fab2b9 Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom(). by Richard Barry · 6 years ago
  66. 1af8085 Fix Xtensa project file and some documentation improvements. by Gaurav Aggarwal · 6 years ago
  67. c6de000 Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type. by Richard Barry · 6 years ago
  68. e3dc5e9 RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet. by Richard Barry · 6 years ago
  69. 2bcb1ab Add trap handler to RISC-V port so there is no dependency on third party code. by Richard Barry · 6 years ago
  70. 32f35e9 RISC-V: by Richard Barry · 6 years ago
  71. b11eb3a RISC-V work in progress: by Richard Barry · 6 years ago
  72. 0c0f0d0 Minor synching - no functional changes. by Richard Barry · 6 years ago
  73. ab49c6a Very minor formatting changes, and remove legacy link to V8 upgrade information. by Richard Barry · 6 years ago
  74. 92ae8e7 Update version numbers ready for release. by Richard Barry · 6 years ago
  75. 1a235ef Update trace configuration files for the updated trace recorder code. by Richard Barry · 6 years ago
  76. be9c073 Update trace recorder code to the latest. by Richard Barry · 6 years ago
  77. 21a8ff3 Two minor updates in the comments to fix html formatting that was preventing doxygen creating documents correctly. by Richard Barry · 6 years ago
  78. 97a686b Fix mixed tabs and spaces in the latest TCP patches. by Richard Barry · 6 years ago
  79. e2750cd Case unused return values for memset and memcpy to void in stream_buffer.c to avoid compiler warnings when the warning level is turned up. by Richard Barry · 6 years ago
  80. 0d6e3df Minor updates to fix issues with the Segger kernel aware plug since V10.1.0. by Richard Barry · 6 years ago
  81. 9bda04b Fix build issues in the FreeRTOS_Plus_TCP_Minimal_Windows_Simulator project: by Richard Barry · 6 years ago
  82. 893db45 Changes required for the IAR StateViewer plug-in to work with FreeRTOS V10.1.0. by Richard Barry · 6 years ago
  83. b0ce1f6 Move some variables from function scope back to being file scope for the benefit of some kernel aware debuggers that were left working in a non-functioning mode after the V10.1.0 release - not last change for this purpose. by Richard Barry · 6 years ago
  84. a11b1a4 FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, by Richard Barry · 6 years ago
  85. 3a1631f Update copyright date ready for tagging V10.1.0. by Richard Barry · 6 years ago
  86. bdb088e Fix some build issues in older kernel demo projects. by Richard Barry · 6 years ago
  87. fb9de58 Update version numbers in preparation for a new release. by Richard Barry · 6 years ago
  88. 722ca8f Update demo project for Tensilita - work in progres.. by Richard Barry · 6 years ago
  89. 78d20e2 Only include the static definition of freertos_tasks_c_additions_init if FREERTOS_TASKS_C_ADDITIONS_INIT is defined, matching the guide used to include the function's prototype. by Richard Barry · 6 years ago
  90. 56dc0dd Merge bug fixes from Cadence by Gaurav Aggarwal · 6 years ago
  91. f6cbf20 Update RISC-V project to used official port stubs in place of third party port. by Richard Barry · 6 years ago
  92. 3bfc32d Add stubs for official RISC-V RV32 port. by Richard Barry · 6 years ago
  93. d525d50 Update trace recorder code. by Richard Barry · 6 years ago
  94. f7fc215 Update stream buffer tests to try resetting a statically allocated stream buffer before deleting it (tests fix in code). by Richard Barry · 6 years ago
  95. 0887713 Fix issues whereby vStreamBufferReset() clobbered the flag that indicated the stream buffer was statically allocated. by Richard Barry · 6 years ago
  96. 9119e1e Add starting point for IGLOO2 RISV-V demo project. by Richard Barry · 6 years ago
  97. 483f4a8 Small change to the directory name in which the RISC-V port is stored. by Richard Barry · 6 years ago
  98. 3d8d2f3 Add RISCV port layer. by Richard Barry · 6 years ago
  99. 10eea4a Remove period from the URL that links to the web page that describes the FreeRTOSConfig.h parameters. by Richard Barry · 6 years ago
  100. c4b1afc Add Xtensa port by Gaurav Aggarwal · 6 years ago