Target i2c2 for init

* Move "for now" target to BUS 2 instead of BUS 0 in the server
* Add init step for I2C2 to evb entry

services/i2c/server/src/main.rs

diff --git a/services/i2c/server/src/main.rs b/services/i2c/server/src/main.rs
index 43ef4c5..7c113f6 100644
--- a/services/i2c/server/src/main.rs
+++ b/services/i2c/server/src/main.rs
@@ -68,8 +68,8 @@
 
     // Per-controller hardware init (I2CC00, timing, interrupts).
     // Platform init (entry.rs) already ran init_i2c_global() + pinmux.
-    // TODO: Initialize all buses this server owns. For now, just bus 0 (I2C1).
-    backend.init_bus(0).map_err(|_| pw_status::Error::Internal)?;
+    // TODO: Initialize all buses this server owns. For now, just bus 2 (I2C1 in hardware).
+    backend.init_bus(2).map_err(|_| pw_status::Error::Internal)?;
 
     // Per-bus notification state (set/cleared via EnableSlaveNotification IPC).
     let mut notification_enabled = [false; 14];

target/ast1060-evb/entry.rs

diff --git a/target/ast1060-evb/entry.rs b/target/ast1060-evb/entry.rs
index 31dc911..ea9dee9 100644
--- a/target/ast1060-evb/entry.rs
+++ b/target/ast1060-evb/entry.rs
@@ -88,7 +88,7 @@
 /// Initialize I2C subsystem
 ///
 /// This must be called once before any I2C controller is used.
-/// Sets up global I2C registers and pin muxing for I2C1.
+/// Sets up global I2C registers and pin muxing for I2C1 and I2C2.
 fn i2c_init() {
     // 1. Initialize I2C global registers (reset, clock dividers)
     //    - Asserts/de-asserts I2C reset via SCU050/SCU054
@@ -96,8 +96,9 @@
     //    - Sets I2CG10 base clock dividers for all speed modes
     aspeed_ddk::i2c_core::init_i2c_global();
 
-    // 2. Configure I2C1 pin muxing via SCU414 bits 30-31
+    // 2. Configure I2C pin muxing
     aspeed_ddk::pinctrl::Pinctrl::apply_pinctrl_group(aspeed_ddk::pinctrl::PINCTRL_I2C1);
+    aspeed_ddk::pinctrl::Pinctrl::apply_pinctrl_group(aspeed_ddk::pinctrl::PINCTRL_I2C2);
 }
 
 #[cortex_m_rt::entry]