now spi1 master controller read and read dma works
diff --git a/target/ast10x0/tests/smc/read/target.rs b/target/ast10x0/tests/smc/read/target.rs index 09b2065..5bf0507 100644 --- a/target/ast10x0/tests/smc/read/target.rs +++ b/target/ast10x0/tests/smc/read/target.rs
@@ -110,9 +110,9 @@ pw_log::info!("=== read dma test==="); // --- 4. DMA --- - let tempbuf = unsafe { core::slice::from_raw_parts(0x41000 as *mut u8, 256) }; + let tempbuf = unsafe { core::slice::from_raw_parts(0x41500 as *mut u8, 256) }; - let _ = match controller.dma_read(ChipSelect::Cs0, 0x400, 0x41000 as usize, 256) { + let _ = match controller.dma_read(ChipSelect::Cs0, 0x400, 0x41500 as usize, 256) { Err(SmcError::InvalidCapacity) => Ok(()), Err(other) => Err(other), Ok(()) => Err(SmcError::HardwareError),
diff --git a/target/ast10x0/tests/smc/read/target_spi1.rs b/target/ast10x0/tests/smc/read/target_spi1.rs index 4da9be0..04d23f7 100644 --- a/target/ast10x0/tests/smc/read/target_spi1.rs +++ b/target/ast10x0/tests/smc/read/target_spi1.rs
@@ -11,8 +11,8 @@ ScuExtMuxSelect, ScuRegisters, SpiMonitorInstance, SpiMonitorPassthrough, SpiMonitorSource, }; use ast10x0_peripherals::smc::{ - ChipSelect, FlashConfig, SmcConfig, SmcController, SmcError, SmcTopology, SpiTransaction, - SpiUninit, + ChipSelect, FlashConfig, SmcConfig, SmcController, SmcError, SmcTopology, SpiNorFlash, + SpiNorFlashDevice, SpiTransaction, SpiUninit, }; use console_backend::console_backend_write_all; use target_common::{declare_target, TargetInterface}; @@ -20,7 +20,6 @@ #[path = "../target_debug.rs"] mod target_debug; -use core::ptr::write_volatile; use target_debug::{dump_smc_read, dump_smc_register}; const SPI_FLASH_CONFIG: FlashConfig = FlashConfig { @@ -68,6 +67,17 @@ return Err(SmcError::HardwareError); } + let jedec = { + let flash = SpiNorFlash::from_spi_cs(&mut spi, SPI_FLASH_CONFIG, ChipSelect::Cs0)?; + flash.jedec_id()? + }; + pw_log::info!( + "SPI1 CS0 JEDEC ID: {:02x} {:02x} {:02x}", + jedec[0] as u32, + jedec[1] as u32, + jedec[2] as u32 + ); + pw_log::info!("=== SPI1 controller register ==="); dump_smc_register(0x7E63_0000, 16); dump_smc_register(0x7E63_0080, 16); @@ -76,21 +86,13 @@ pw_log::info!("=== SPI1 controller/window ==="); dump_smc_register(0x9000_0000, 16); - unsafe { - write_volatile(0x7E63_0080 as *mut u32, 0x0); - write_volatile(0x7E63_0084 as *mut u32, 0x04220000); - write_volatile(0x7E63_0088 as *mut u32, 0x800b3640); - write_volatile(0x7E63_008c as *mut u32, 0x0); - write_volatile(0x7E63_0094 as *mut u32, 0x00790000); - } - pw_log::info!("=== SPI1 read ==="); let mut buf = [0u8; 64]; let n = SpiTransaction::read_with_spim( &mut spi, SpiMonitorInstance::Spim0, ChipSelect::Cs0, - 0x100000, + 0x0, &mut buf, )?; if n != buf.len() { @@ -98,14 +100,14 @@ } dump_smc_read(&buf, buf.len() as u32); - pw_log::info!("=== SPI1 DMA read @ 0x00100000 ==="); - let dma_buf = unsafe { core::slice::from_raw_parts_mut(0x41000 as *mut u8, 256) }; + pw_log::info!("=== SPI1 DMA read @ 0x00000000 ==="); + let dma_buf = unsafe { core::slice::from_raw_parts_mut(0x41500 as *mut u8, 256) }; let mut dma_txn = SpiTransaction::dma_read_with_spim( &mut spi, SpiMonitorInstance::Spim0, ChipSelect::Cs0, - 0x100000, - 0x41000usize, + 0x0, + 0x41500usize, dma_buf.len() as u32, )?;
diff --git a/target/ast10x0/tests/smc/read/target_spi2.rs b/target/ast10x0/tests/smc/read/target_spi2.rs index d1485dc..4f2e2e3 100644 --- a/target/ast10x0/tests/smc/read/target_spi2.rs +++ b/target/ast10x0/tests/smc/read/target_spi2.rs
@@ -11,8 +11,8 @@ ScuExtMuxSelect, ScuRegisters, SpiMonitorInstance, SpiMonitorPassthrough, SpiMonitorSource, }; use ast10x0_peripherals::smc::{ - ChipSelect, FlashConfig, SmcConfig, SmcController, SmcError, SmcTopology, SpiTransaction, - SpiUninit, + ChipSelect, FlashConfig, SmcConfig, SmcController, SmcError, SmcTopology, SpiNorFlash, + SpiNorFlashDevice, SpiTransaction, SpiUninit, }; use console_backend::console_backend_write_all; use target_common::{declare_target, TargetInterface}; @@ -20,7 +20,6 @@ #[path = "../target_debug.rs"] mod target_debug; -//use core::ptr::write_volatile; use target_debug::{dump_smc_read, dump_smc_register}; const SPI_FLASH_CONFIG: FlashConfig = FlashConfig { @@ -33,6 +32,25 @@ pub struct Target {} +//TODO: need to port this in GPIO peripherals. +//GPIOL2 and L3 should must be pull high before SPI2 Controller accessing flash. +//GPIOL2/L3 is controlling the power for level shifter, SPI2 data path may going +// through level shifter, so the pmic enabling is required. +fn gpio_flash_power() { + /* + let peripherals = unsafe { Peripherals::steal() }; + let gpio = peripherals.gpio; + let gpiol = gpiol::GPIOL::new(gpio).split(); + + pinctrl::Pinctrl::apply_pinctrl_group(pinctrl::PINCTRL_GPIOL2); + pinctrl::Pinctrl::apply_pinctrl_group(pinctrl::PINCTRL_GPIOL3); + let mut pl2 = gpiol.pl2.into_push_pull_output(); + pl2.set_high().unwrap(); + + let mut pl3 = gpiol.pl3.into_push_pull_output(); + pl3.set_high().unwrap();*/ +} + fn config_spi2_master_controller() -> Result<(), SmcError> { let scu = unsafe { ScuRegisters::new_global_unlocked() }; scu.apply_pinctrl_group(PINCTRL_SPIM3_DEFAULT); @@ -48,6 +66,7 @@ } fn run_spi2_read_test() -> Result<(), SmcError> { + gpio_flash_power(); config_spi2_master_controller()?; let config = SmcConfig { @@ -68,6 +87,17 @@ return Err(SmcError::HardwareError); } + let jedec = { + let flash = SpiNorFlash::from_spi_cs(&mut spi, SPI_FLASH_CONFIG, ChipSelect::Cs0)?; + flash.jedec_id()? + }; + pw_log::info!( + "SPI2 CS0 JEDEC ID: {:02x} {:02x} {:02x}", + jedec[0] as u32, + jedec[1] as u32, + jedec[2] as u32 + ); + pw_log::info!("=== SPI2 controller register ==="); dump_smc_register(0x7E64_0000, 16); dump_smc_register(0x7E64_0080, 16); @@ -75,22 +105,14 @@ dump_smc_register(0x7E6E_20F0, 4); pw_log::info!("=== SPI2 controller/window ==="); dump_smc_register(0xB000_0000, 16); -/* - unsafe { - write_volatile(0x7E64_0080 as *mut u32, 0x0); - write_volatile(0x7E64_0084 as *mut u32, 0x04220000); - write_volatile(0x7E64_0088 as *mut u32, 0x800b3640); - write_volatile(0x7E64_008c as *mut u32, 0x0); - write_volatile(0x7E64_0094 as *mut u32, 0x00790000); - } -*/ + pw_log::info!("=== SPI2 read ==="); let mut buf = [0u8; 64]; let n = SpiTransaction::read_with_spim( &mut spi, SpiMonitorInstance::Spim2, ChipSelect::Cs0, - 0x100000, + 0x0, &mut buf, )?; if n != buf.len() { @@ -98,14 +120,14 @@ } dump_smc_read(&buf, buf.len() as u32); - pw_log::info!("=== SPI2 DMA read @ 0x00100000 ==="); - let dma_buf = unsafe { core::slice::from_raw_parts_mut(0x41000 as *mut u8, 256) }; + pw_log::info!("=== SPI2 DMA read @ 0x00000000 ==="); + let dma_buf = unsafe { core::slice::from_raw_parts_mut(0x41500 as *mut u8, 256) }; let mut dma_txn = SpiTransaction::dma_read_with_spim( &mut spi, SpiMonitorInstance::Spim2, ChipSelect::Cs0, - 0x100000, - 0x41000usize, + 0x0, + 0x41500usize, dma_buf.len() as u32, )?;