earlgrey: update clock domains Signed-off-by: Chris Frantz <cfrantz@google.com>
diff --git a/target/earlgrey/BUILD.bazel b/target/earlgrey/BUILD.bazel index 43cafb5..217318c 100644 --- a/target/earlgrey/BUILD.bazel +++ b/target/earlgrey/BUILD.bazel
@@ -139,6 +139,22 @@ ) rust_library( + name = "clock_domain", + srcs = ["clock_domain.rs"], + crate_features = select({ + ":fpga": ["fpga"], + ":qemu": ["qemu"], + ":silicon": ["silicon"], + ":verilator": ["verilator"], + "//conditions:default": [], + }), + crate_name = "earlgrey_clock_domain", + edition = "2024", + target_compatible_with = TARGET_COMPATIBLE_WITH, + visibility = ["//visibility:public"], +) + +rust_library( name = "config", srcs = ["config.rs"], crate_features = select({ @@ -153,6 +169,7 @@ target_compatible_with = TARGET_COMPATIBLE_WITH, visibility = [":__subpackages__"], deps = [ + ":clock_domain", "@pigweed//pw_kernel/config:kernel_config_interface", "@pigweed//pw_kernel/lib/memory_config", ],
diff --git a/target/earlgrey/clock_domain.rs b/target/earlgrey/clock_domain.rs new file mode 100644 index 0000000..cdbdc35 --- /dev/null +++ b/target/earlgrey/clock_domain.rs
@@ -0,0 +1,39 @@ +// Licensed under the Apache-2.0 license +// SPDX-License-Identifier: Apache-2.0 +#![no_std] + +#[cfg(feature = "silicon")] +pub const SYSTEM_CLOCK_HZ: u64 = 100_000_000; +#[cfg(feature = "silicon")] +pub const PERIPHERAL_CLOCK_HZ: u64 = 24_000_000; +#[cfg(feature = "silicon")] +pub const HI_SPEED_PERIPHERAL_CLOCK_HZ: u64 = 96_000_000; +#[cfg(feature = "silicon")] +pub const AON_CLOCK_HZ: u64 = 200_000; + +#[cfg(feature = "fpga")] +pub const SYSTEM_CLOCK_HZ: u64 = 6_000_000; +#[cfg(feature = "fpga")] +pub const PERIPHERAL_CLOCK_HZ: u64 = 6_000_000; +#[cfg(feature = "fpga")] +pub const HI_SPEED_PERIPHERAL_CLOCK_HZ: u64 = 24_000_000; +#[cfg(feature = "fpga")] +pub const AON_CLOCK_HZ: u64 = 250_000; + +#[cfg(feature = "verilator")] +pub const SYSTEM_CLOCK_HZ: u64 = 125_000; +#[cfg(feature = "verilator")] +pub const PERIPHERAL_CLOCK_HZ: u64 = 125_000; +#[cfg(feature = "verilator")] +pub const HI_SPEED_PERIPHERAL_CLOCK_HZ: u64 = 500_000; +#[cfg(feature = "verilator")] +pub const AON_CLOCK_HZ: u64 = 125_000; + +#[cfg(feature = "qemu")] +pub const SYSTEM_CLOCK_HZ: u64 = 24_000_000; +#[cfg(feature = "qemu")] +pub const PERIPHERAL_CLOCK_HZ: u64 = 24_000_000; +#[cfg(feature = "qemu")] +pub const HI_SPEED_PERIPHERAL_CLOCK_HZ: u64 = 24_000_000; +#[cfg(feature = "qemu")] +pub const AON_CLOCK_HZ: u64 = 250_000;
diff --git a/target/earlgrey/config.rs b/target/earlgrey/config.rs index 80f9944..4155302 100644 --- a/target/earlgrey/config.rs +++ b/target/earlgrey/config.rs
@@ -27,14 +27,7 @@ pub struct KernelConfig; impl KernelConfigInterface for KernelConfig { - #[cfg(feature = "silicon")] - const SYSTEM_CLOCK_HZ: u64 = 100_000_000; - #[cfg(feature = "fpga")] - const SYSTEM_CLOCK_HZ: u64 = 6_000_000; - #[cfg(feature = "verilator")] - const SYSTEM_CLOCK_HZ: u64 = 125_000; - #[cfg(feature = "qemu")] - const SYSTEM_CLOCK_HZ: u64 = 24_000_000; + const SYSTEM_CLOCK_HZ: u64 = earlgrey_clock_domain::SYSTEM_CLOCK_HZ; } impl RiscVKernelConfigInterface for KernelConfig {
diff --git a/target/earlgrey/syscall_latency/BUILD.bazel b/target/earlgrey/syscall_latency/BUILD.bazel index 1db2c52..4c655d2 100644 --- a/target/earlgrey/syscall_latency/BUILD.bazel +++ b/target/earlgrey/syscall_latency/BUILD.bazel
@@ -28,6 +28,7 @@ system_config = "@pigweed//pw_kernel/target:system_config_file", target_compatible_with = TARGET_COMPATIBLE_WITH, deps = [ + "//target/earlgrey:clock_domain", "//target/earlgrey:config", "//target/earlgrey/registers", "@pigweed//pw_base64/rust:pw_base64",
diff --git a/target/earlgrey/syscall_latency/main.rs b/target/earlgrey/syscall_latency/main.rs index f96026d..5d2c7b9 100644 --- a/target/earlgrey/syscall_latency/main.rs +++ b/target/earlgrey/syscall_latency/main.rs
@@ -8,14 +8,7 @@ use registers::rv_timer::RvTimer; use userspace::{entry, syscall}; -#[cfg(feature = "silicon")] -const IO_CLOCK_HZ: u64 = 24_000_000; -#[cfg(feature = "fpga")] -const IO_CLOCK_HZ: u64 = 6_000_000; -#[cfg(feature = "verilator")] -const IO_CLOCK_HZ: u64 = 125_000; -#[cfg(feature = "qemu")] -const IO_CLOCK_HZ: u64 = 24_000_000; +const PERIPHERAL_CLOCK_HZ: u64 = earlgrey_clock_domain::PERIPHERAL_CLOCK_HZ; #[inline(always)] fn rv_timer_value(rv_timer: &RvTimer) -> u64 { @@ -46,7 +39,7 @@ let average = total / (n as u64); pw_log::info!("Average latency: {} rv_timer ticks", average as u64); - let cpu_clocks = average * KernelConfig::SYSTEM_CLOCK_HZ / IO_CLOCK_HZ; + let cpu_clocks = average * KernelConfig::SYSTEM_CLOCK_HZ / PERIPHERAL_CLOCK_HZ; pw_log::info!("Average latency: {} cpu clocks", cpu_clocks as u64); Ok(()) }
diff --git a/target/earlgrey/syscall_latency/system.json5 b/target/earlgrey/syscall_latency/system.json5 index b5eabb1..2ba8ae8 100644 --- a/target/earlgrey/syscall_latency/system.json5 +++ b/target/earlgrey/syscall_latency/system.json5
@@ -30,14 +30,14 @@ }, ], objects: [ - { - type: "thread", - name: "syscall_latency", + { + name: "syscall_latency_thread", kernel_stack_size_bytes: 4096, + type: "thread", }, ], }, ], }, ], -} \ No newline at end of file +}