tooling: run the formatter on all files Signed-off-by: Chris Frantz <cfrantz@google.com>

diff --git a/drivers/usart/client/src/lib.rs b/drivers/usart/client/src/lib.rs
index b94b025..8d78ef8 100644
--- a/drivers/usart/client/src/lib.rs
+++ b/drivers/usart/client/src/lib.rs

@@ -3,9 +3,7 @@
 
 #![no_std]
 
-use usart_api::{
-    UsartError, UsartOp, UsartRequestHeader, UsartResponseHeader, MAX_PAYLOAD_SIZE,
-};
+use usart_api::{UsartError, UsartOp, UsartRequestHeader, UsartResponseHeader, MAX_PAYLOAD_SIZE};
 use userspace::syscall;
 use userspace::time::Instant;
 

diff --git a/drivers/usart/server/src/runtime.rs b/drivers/usart/server/src/runtime.rs
index c7b42da..102c2d4 100644
--- a/drivers/usart/server/src/runtime.rs
+++ b/drivers/usart/server/src/runtime.rs

@@ -2,11 +2,11 @@
 // SPDX-License-Identifier: Apache-2.0
 
 use usart_api::backend::{IrqMask, UsartBackend};
-use usart_api::{UsartResponseHeader};
+use usart_api::UsartResponseHeader;
 use userspace::syscall::{self, Signals};
 use userspace::time::Instant;
 
-use crate::{DispatchOutcome, MAX_REQUEST_SIZE, MAX_RESPONSE_SIZE, dispatch_request};
+use crate::{dispatch_request, DispatchOutcome, MAX_REQUEST_SIZE, MAX_RESPONSE_SIZE};
 
 /// Holds at most one in-flight `TryRead` request that is waiting for the RX
 /// interrupt to fire before it can be completed.
@@ -83,8 +83,7 @@
             continue;
         };
 
-        if wait_return.user_data as u32 == irq
-            && wait_return.pending_signals.contains(irq_signals)
+        if wait_return.user_data as u32 == irq && wait_return.pending_signals.contains(irq_signals)
         {
             let acked = wait_return.pending_signals & irq_signals;
             let _ = syscall::interrupt_ack(irq, acked);
@@ -99,9 +98,9 @@
                 // try_read also finds no data (unlikely at this point).
                 let _ = backend.disable_interrupts(IrqMask::RX_DATA_AVAILABLE);
 
-                let resp_len = match backend.try_read(
-                    &mut response_buf[payload_offset..payload_offset + read_buf_len],
-                ) {
+                let resp_len = match backend
+                    .try_read(&mut response_buf[payload_offset..payload_offset + read_buf_len])
+                {
                     Ok(n) => {
                         let hdr = UsartResponseHeader::success(n as u16);
                         response_buf[..UsartResponseHeader::SIZE]

diff --git a/services/mctp/api/src/error.rs b/services/mctp/api/src/error.rs
index 29af55e..17e65d0 100644
--- a/services/mctp/api/src/error.rs
+++ b/services/mctp/api/src/error.rs

@@ -148,7 +148,10 @@
         assert_eq!(ResponseCode::AddrInUse.to_string(), "address in use");
         assert_eq!(ResponseCode::TimedOut.to_string(), "timed out");
         assert_eq!(ResponseCode::BadArgument.to_string(), "bad argument");
-        assert_eq!(ResponseCode::ServerRestarted.to_string(), "server restarted");
+        assert_eq!(
+            ResponseCode::ServerRestarted.to_string(),
+            "server restarted"
+        );
     }
 
     #[test]

diff --git a/services/mctp/api/src/stack.rs b/services/mctp/api/src/stack.rs
index 89adbe5..fead571 100644
--- a/services/mctp/api/src/stack.rs
+++ b/services/mctp/api/src/stack.rs

@@ -29,8 +29,8 @@
 //! let (meta, response) = req.recv(&mut buf).unwrap();
 //! ```
 
-use crate::{Handle, MctpClient, MctpError, RecvMetadata, ResponseCode};
 use crate::traits::{MctpListener, MctpReqChannel, MctpRespChannel};
+use crate::{Handle, MctpClient, MctpError, RecvMetadata, ResponseCode};
 
 // ============================================================================
 // Stack
@@ -65,11 +65,7 @@
     /// Open an outbound request channel to `eid`.
     ///
     /// `timeout_millis` of 0 means no timeout (block indefinitely).
-    pub fn req(
-        &self,
-        eid: u8,
-        timeout_millis: u32,
-    ) -> Result<StackReqChannel<'_, C>, MctpError> {
+    pub fn req(&self, eid: u8, timeout_millis: u32) -> Result<StackReqChannel<'_, C>, MctpError> {
         let handle = self.client.req(eid)?;
         Ok(StackReqChannel {
             stack: self,
@@ -118,22 +114,15 @@
         if self.sent_tag.is_some() {
             return Err(MctpError::from_code(ResponseCode::BadArgument));
         }
-        let tag = self.stack.client.send(
-            Some(self.handle),
-            msg_type,
-            None,
-            None,
-            false,
-            buf,
-        )?;
+        let tag = self
+            .stack
+            .client
+            .send(Some(self.handle), msg_type, None, None, false, buf)?;
         self.sent_tag = Some(tag);
         Ok(())
     }
 
-    fn recv<'f>(
-        &mut self,
-        buf: &'f mut [u8],
-    ) -> Result<(RecvMetadata, &'f mut [u8]), MctpError> {
+    fn recv<'f>(&mut self, buf: &'f mut [u8]) -> Result<(RecvMetadata, &'f mut [u8]), MctpError> {
         if self.sent_tag.is_none() {
             return Err(MctpError::from_code(ResponseCode::BadArgument));
         }
@@ -214,7 +203,14 @@
         // responses by the presence or absence of a handle.
         self.stack
             .client
-            .send(None, self.msg_type, Some(self.eid), Some(self.tag), false, buf)
+            .send(
+                None,
+                self.msg_type,
+                Some(self.eid),
+                Some(self.tag),
+                false,
+                buf,
+            )
             .map(|_| ())
     }
 

diff --git a/services/mctp/api/src/traits.rs b/services/mctp/api/src/traits.rs
index 4750be9..f4d0c03 100644
--- a/services/mctp/api/src/traits.rs
+++ b/services/mctp/api/src/traits.rs

@@ -75,10 +75,7 @@
     fn send(&mut self, msg_type: u8, buf: &[u8]) -> Result<(), MctpError>;
 
     /// Receive the response to a previously sent request.
-    fn recv<'f>(
-        &mut self,
-        buf: &'f mut [u8],
-    ) -> Result<(RecvMetadata, &'f mut [u8]), MctpError>;
+    fn recv<'f>(&mut self, buf: &'f mut [u8]) -> Result<(RecvMetadata, &'f mut [u8]), MctpError>;
 
     /// The remote endpoint ID this channel targets.
     fn remote_eid(&self) -> u8;

diff --git a/services/mctp/api/src/wire.rs b/services/mctp/api/src/wire.rs
index 8be7ca5..a5d5c8a 100644
--- a/services/mctp/api/src/wire.rs
+++ b/services/mctp/api/src/wire.rs

@@ -133,9 +133,14 @@
             self.flags,
             self.msg_type,
             self.eid,
-            h[0], h[1], h[2], h[3],
+            h[0],
+            h[1],
+            h[2],
+            h[3],
             self.tag,
-            0, 0, 0, // reserved
+            0,
+            0,
+            0, // reserved
         ]
     }
 
@@ -232,8 +237,12 @@
             self.flags,
             self.msg_type,
             self.eid,
-            h[0], h[1], h[2], h[3],
-            pl[0], pl[1],
+            h[0],
+            h[1],
+            h[2],
+            h[3],
+            pl[0],
+            pl[1],
             self.tag,
             0, // reserved
         ]
@@ -520,7 +529,10 @@
 }
 
 /// Get response payload data (after header).
-pub fn get_response_payload<'a>(buf: &'a [u8], header: &MctpResponseHeader) -> Result<&'a [u8], WireError> {
+pub fn get_response_payload<'a>(
+    buf: &'a [u8],
+    header: &MctpResponseHeader,
+) -> Result<&'a [u8], WireError> {
     let end = MctpResponseHeader::SIZE + header.payload_len as usize;
     if buf.len() < end {
         return Err(WireError::Truncated);

diff --git a/services/mctp/echo/src/lib.rs b/services/mctp/echo/src/lib.rs
index 3f5704f..6fde1bf 100644
--- a/services/mctp/echo/src/lib.rs
+++ b/services/mctp/echo/src/lib.rs

@@ -22,7 +22,9 @@
 pub const ECHO_EID: u8 = 8;
 
 /// Prepare a stack for echoing by setting the local EID and opening a listener.
-pub fn prepare_listener<C: MctpClient>(stack: &Stack<C>) -> Result<StackListener<'_, C>, MctpError> {
+pub fn prepare_listener<C: MctpClient>(
+    stack: &Stack<C>,
+) -> Result<StackListener<'_, C>, MctpError> {
     stack.set_eid(ECHO_EID)?;
     stack.listener(ECHO_MSG_TYPE, 0)
 }
@@ -47,4 +49,3 @@
     let (_meta, msg, mut resp) = listener.recv(buf)?;
     resp.send(msg)
 }
-

diff --git a/services/mctp/echo/tests/echo_host.rs b/services/mctp/echo/tests/echo_host.rs
index b3b939e..33e1288 100644
--- a/services/mctp/echo/tests/echo_host.rs
+++ b/services/mctp/echo/tests/echo_host.rs

@@ -41,10 +41,7 @@
     }
 }
 
-fn transfer<S: Sender, const N: usize>(
-    packets: &RefCell<Vec<Vec<u8>>>,
-    dest: &mut Server<S, N>,
-) {
+fn transfer<S: Sender, const N: usize>(packets: &RefCell<Vec<Vec<u8>>>, dest: &mut Server<S, N>) {
     let pkts = packets.borrow();
     for pkt in pkts.iter() {
         dest.inbound(pkt).expect("inbound should accept packet");
@@ -87,7 +84,9 @@
         self.server
             .borrow_mut()
             .try_recv(handle, buf)
-            .ok_or(MctpError::from_code(openprot_mctp_api::ResponseCode::TimedOut))
+            .ok_or(MctpError::from_code(
+                openprot_mctp_api::ResponseCode::TimedOut,
+            ))
     }
 
     fn send(
@@ -129,7 +128,8 @@
 
     let mut req_b = stack_b.req(8, 0).expect("request channel should open");
     let payload = b"echo from host test";
-    req_b.send(ECHO_MSG_TYPE, payload)
+    req_b
+        .send(ECHO_MSG_TYPE, payload)
         .expect("request send should succeed");
 
     // Deliver request packets from B -> A, run one echo step, then A -> B.

diff --git a/services/mctp/server/src/dispatch.rs b/services/mctp/server/src/dispatch.rs
index 2f6f90c..6ea91a6 100644
--- a/services/mctp/server/src/dispatch.rs
+++ b/services/mctp/server/src/dispatch.rs

@@ -6,9 +6,7 @@
 //! Decodes wire-protocol requests and dispatches them to the [`Server`].
 //! This is the server-side counterpart of `openprot-mctp-client`.
 
-use openprot_mctp_api::wire::{
-    self, flags, MctpOp, MctpRequestHeader,
-};
+use openprot_mctp_api::wire::{self, flags, MctpOp, MctpRequestHeader};
 use openprot_mctp_api::{Handle, ResponseCode};
 
 use crate::{RecvResult, Sender, Server};

diff --git a/services/mctp/server/src/server.rs b/services/mctp/server/src/server.rs
index ab4c6c0..c58a713 100644
--- a/services/mctp/server/src/server.rs
+++ b/services/mctp/server/src/server.rs

@@ -103,11 +103,7 @@
     /// If a message is available, returns the metadata and copies the
     /// payload into `buf`. Otherwise returns `None` and the caller
     /// should register a pending recv via [`register_recv`](Self::register_recv).
-    pub fn try_recv(
-        &mut self,
-        handle: Handle,
-        buf: &mut [u8],
-    ) -> Option<RecvMetadata> {
+    pub fn try_recv(&mut self, handle: Handle, buf: &mut [u8]) -> Option<RecvMetadata> {
         let cookie = AppCookie(handle.0 as usize);
         let msg = self.stack.recv(cookie)?;
 
@@ -182,14 +178,9 @@
         // Responses need no handle, use 255 as dummy
         let cookie = AppCookie(handle.unwrap_or(Handle(255)).0 as usize);
 
-        let result = self.stack.send(
-            eid.map(Eid),
-            MsgType(typ),
-            tag,
-            MsgIC(ic),
-            cookie,
-            buf,
-        );
+        let result = self
+            .stack
+            .send(eid.map(Eid), MsgType(typ), tag, MsgIC(ic), cookie, buf);
 
         match result {
             Ok(tag) => Ok(tag.tag().0),
@@ -208,10 +199,7 @@
         recv_buf: &mut [u8],
     ) -> (u32, heapless::Vec<(Handle, RecvResult), OUTSTANDING>) {
         // Update the mctp-stack; get the next timeout interval
-        let stack_timeout = self
-            .stack
-            .update(now_millis)
-            .unwrap_or(60_000) as u32;
+        let stack_timeout = self.stack.update(now_millis).unwrap_or(60_000) as u32;
 
         let mut ready: heapless::Vec<(Handle, RecvResult), OUTSTANDING> = heapless::Vec::new();
 
@@ -264,9 +252,7 @@
     /// binding. The packet should be a raw MCTP packet without transport
     /// headers (the transport binding strips those).
     pub fn inbound(&mut self, pkt: &[u8]) -> Result<(), MctpError> {
-        self.stack
-            .inbound(pkt)
-            .map_err(mctp_error_to_server_error)
+        self.stack.inbound(pkt).map_err(mctp_error_to_server_error)
     }
 }
 

diff --git a/services/mctp/server/tests/common/mod.rs b/services/mctp/server/tests/common/mod.rs
index 5a747ba..992eb1a 100644
--- a/services/mctp/server/tests/common/mod.rs
+++ b/services/mctp/server/tests/common/mod.rs

@@ -264,7 +264,10 @@
 }
 
 impl<'a, S: Sender, const N: usize> MctpListener for DirectListener<'a, S, N> {
-    type RespChannel<'r> = DirectRespChannel<'a, S, N> where Self: 'r;
+    type RespChannel<'r>
+        = DirectRespChannel<'a, S, N>
+    where
+        Self: 'r;
 
     fn recv<'f>(
         &mut self,
@@ -325,10 +328,7 @@
             .map(|_| ())
     }
 
-    fn recv<'f>(
-        &mut self,
-        buf: &'f mut [u8],
-    ) -> Result<(RecvMetadata, &'f mut [u8]), MctpError> {
+    fn recv<'f>(&mut self, buf: &'f mut [u8]) -> Result<(RecvMetadata, &'f mut [u8]), MctpError> {
         let meta = self
             .client
             .server
@@ -349,9 +349,6 @@
 // ---------------------------------------------------------------------------
 
 /// Construct a `Server` + its outbound packet buffer, for two-endpoint tests.
-pub fn make_server(
-    eid: u8,
-    packets: &RefCell<Vec<Vec<u8>>>,
-) -> Server<BufferSender<'_>, 16> {
+pub fn make_server(eid: u8, packets: &RefCell<Vec<Vec<u8>>>) -> Server<BufferSender<'_>, 16> {
     Server::new(Eid(eid), 0, BufferSender { packets })
 }

diff --git a/services/mctp/server/tests/dispatch.rs b/services/mctp/server/tests/dispatch.rs
index 523f0b5..25cd198 100644
--- a/services/mctp/server/tests/dispatch.rs
+++ b/services/mctp/server/tests/dispatch.rs

@@ -13,7 +13,10 @@
 
 use mctp::Eid;
 use openprot_mctp_api::{wire, Handle};
-use openprot_mctp_server::{dispatch::{dispatch_mctp_op, drive_pending, DispatchOutcome}, Server};
+use openprot_mctp_server::{
+    dispatch::{dispatch_mctp_op, drive_pending, DispatchOutcome},
+    Server,
+};
 
 use common::{transfer, BufferSender};
 
@@ -94,16 +97,8 @@
 
     // B sends a message via dispatch
     let payload = b"dispatch echo!";
-    let req_len = wire::encode_send(
-        &mut req,
-        Some(req_handle),
-        1,
-        None,
-        None,
-        false,
-        payload,
-    )
-    .unwrap();
+    let req_len =
+        wire::encode_send(&mut req, Some(req_handle), 1, None, None, false, payload).unwrap();
     let resp_len = dispatch_reply(&req[..req_len], &mut resp, &mut server_b, &mut recv_buf);
     let header = wire::decode_response_header(&resp[..resp_len]).unwrap();
     assert!(header.is_success());

diff --git a/services/mctp/server/tests/echo.rs b/services/mctp/server/tests/echo.rs
index 8c13f71..f9dbd8d 100644
--- a/services/mctp/server/tests/echo.rs
+++ b/services/mctp/server/tests/echo.rs

@@ -23,7 +23,6 @@
 
 use common::{transfer, BufferSender, DirectClient};
 
-
 // ---------------------------------------------------------------------------
 // Echo application logic (client side)
 // ---------------------------------------------------------------------------
@@ -69,13 +68,11 @@
     // -- Server side: set up two MCTP server instances with mock transport --
     let buf_a = RefCell::new(Vec::new());
     let sender_a = BufferSender { packets: &buf_a };
-    let server_a: RefCell<Server<_, 16>> =
-        RefCell::new(Server::new(Eid(8), 0, sender_a));
+    let server_a: RefCell<Server<_, 16>> = RefCell::new(Server::new(Eid(8), 0, sender_a));
 
     let buf_b = RefCell::new(Vec::new());
     let sender_b = BufferSender { packets: &buf_b };
-    let server_b: RefCell<Server<_, 16>> =
-        RefCell::new(Server::new(Eid(42), 0, sender_b));
+    let server_b: RefCell<Server<_, 16>> = RefCell::new(Server::new(Eid(42), 0, sender_b));
 
     // -- Client side: wrap servers in DirectClient to use MctpClient trait --
     let client_a = DirectClient::new(&server_a);
@@ -109,7 +106,10 @@
         .expect("Client B should have received the echo response");
 
     let response = &resp_buf[..resp_meta.payload_size];
-    assert_eq!(response, payload, "Echo response should match original payload");
+    assert_eq!(
+        response, payload,
+        "Echo response should match original payload"
+    );
     assert_eq!(resp_meta.msg_type, 1);
     assert_eq!(resp_meta.remote_eid, 8);
 
@@ -123,13 +123,11 @@
 fn mctp_echo_multiple() {
     let buf_a = RefCell::new(Vec::new());
     let sender_a = BufferSender { packets: &buf_a };
-    let server_a: RefCell<Server<_, 16>> =
-        RefCell::new(Server::new(Eid(8), 0, sender_a));
+    let server_a: RefCell<Server<_, 16>> = RefCell::new(Server::new(Eid(8), 0, sender_a));
 
     let buf_b = RefCell::new(Vec::new());
     let sender_b = BufferSender { packets: &buf_b };
-    let server_b: RefCell<Server<_, 16>> =
-        RefCell::new(Server::new(Eid(42), 0, sender_b));
+    let server_b: RefCell<Server<_, 16>> = RefCell::new(Server::new(Eid(42), 0, sender_b));
 
     let client_a = DirectClient::new(&server_a);
     let client_b = DirectClient::new(&server_b);

diff --git a/services/mctp/server/tests/integration.rs b/services/mctp/server/tests/integration.rs
index cfe1a54..61ab5eb 100644
--- a/services/mctp/server/tests/integration.rs
+++ b/services/mctp/server/tests/integration.rs

@@ -22,7 +22,9 @@
 use openprot_mctp_server::Server;
 use openprot_mctp_server::ServerConfig;
 
-use common::{transfer, BufferSender, DirectClient, DirectListener, DirectReqChannel, SmallMtuBufferSender};
+use common::{
+    transfer, BufferSender, DirectClient, DirectListener, DirectReqChannel, SmallMtuBufferSender,
+};
 
 // ---------------------------------------------------------------------------
 // Multi-fragment roundtrip
@@ -215,9 +217,7 @@
 
     // A echoes manually (through MctpClient)
     let mut echo_buf = [0u8; 255];
-    let meta = client_a
-        .recv(listener_handle, 0, &mut echo_buf)
-        .unwrap();
+    let meta = client_a.recv(listener_handle, 0, &mut echo_buf).unwrap();
     client_a
         .send(
             None,
@@ -448,7 +448,9 @@
 
     let mut req = stack.req(42, 0).expect("req alloc");
     let mut resp_buf = [0u8; 255];
-    let err = req.recv(&mut resp_buf).expect_err("recv before send must fail");
+    let err = req
+        .recv(&mut resp_buf)
+        .expect_err("recv before send must fail");
     assert_eq!(err.code, openprot_mctp_api::ResponseCode::BadArgument);
 }
 
@@ -545,4 +547,3 @@
     stack.set_eid(99).expect("set_eid should succeed");
     assert_eq!(stack.get_eid(), 99);
 }
-

diff --git a/services/mctp/server/tests/server_unit.rs b/services/mctp/server/tests/server_unit.rs
index 165d472..e3fb375 100644
--- a/services/mctp/server/tests/server_unit.rs
+++ b/services/mctp/server/tests/server_unit.rs

@@ -12,10 +12,10 @@
 use std::cell::RefCell;
 
 use mctp::Eid;
-use openprot_mctp_api::{ResponseCode};
+use openprot_mctp_api::ResponseCode;
 use openprot_mctp_server::{RecvResult, Server, ServerConfig};
 
-use common::{BufferSender, DroppingBufferSender, transfer};
+use common::{transfer, BufferSender, DroppingBufferSender};
 
 // ---------------------------------------------------------------------------
 // Helpers
@@ -95,7 +95,9 @@
     let sender = DroppingBufferSender;
     let mut server: Server<_, 16> = Server::new(Eid(8), 0, sender);
     server.listener(1).expect("first listener should succeed");
-    let err = server.listener(1).expect_err("duplicate listener should fail");
+    let err = server
+        .listener(1)
+        .expect_err("duplicate listener should fail");
     assert_eq!(err.code, ResponseCode::AddrInUse);
 }
 

diff --git a/target/ast10x0/board/src/lib.rs b/target/ast10x0/board/src/lib.rs
index b921388..eb4f4db 100644
--- a/target/ast10x0/board/src/lib.rs
+++ b/target/ast10x0/board/src/lib.rs

@@ -2,7 +2,6 @@
 // SPDX-License-Identifier: Apache-2.0
 
 #![no_std]
-
 #![deny(
     clippy::unwrap_used,
     clippy::expect_used,
@@ -12,8 +11,8 @@
     clippy::unimplemented
 )]
 
-use ast10x0_peripherals::scu::{PinctrlPin, ScuRegisters};
 use ast10x0_peripherals::scu::{ClockRegisterHalf, ScuRegisterHalf};
+use ast10x0_peripherals::scu::{PinctrlPin, ScuRegisters};
 
 /// Board descriptor metadata for AST10x0 board initialization.
 #[derive(Clone, Debug)]
@@ -85,4 +84,4 @@
     for _ in 0..(micros * 16) {
         core::hint::spin_loop();
     }
-}
\ No newline at end of file
+}

diff --git a/target/ast10x0/config.rs b/target/ast10x0/config.rs
index 7cef221..d3ac165 100644
--- a/target/ast10x0/config.rs
+++ b/target/ast10x0/config.rs

@@ -10,9 +10,7 @@
 //! the production AST10x0 hardware datasheet.
 #![no_std]
 
-pub use kernel_config::{
-    CortexMKernelConfigInterface, KernelConfigInterface, NvicConfigInterface,
-};
+pub use kernel_config::{CortexMKernelConfigInterface, KernelConfigInterface, NvicConfigInterface};
 
 pub struct KernelConfig;
 

diff --git a/target/ast10x0/console_backend.rs b/target/ast10x0/console_backend.rs
index 121a3fb..7f70753 100644
--- a/target/ast10x0/console_backend.rs
+++ b/target/ast10x0/console_backend.rs

@@ -7,8 +7,8 @@
 
 #![no_std]
 
-use ast10x0_peripherals::uart::Usart;
 use ast1060_pac as device;
+use ast10x0_peripherals::uart::Usart;
 use embedded_io::Write;
 use kernel::sync::spinlock::SpinLock;
 use pw_status::{Error, Result};

diff --git a/target/ast10x0/entry.rs b/target/ast10x0/entry.rs
index f9fd412..a668bce 100644
--- a/target/ast10x0/entry.rs
+++ b/target/ast10x0/entry.rs

@@ -87,8 +87,6 @@
     unsafe { init_cache() };
 }
 
-
-
 #[unsafe(no_mangle)]
 #[allow(non_snake_case)]
 pub extern "C" fn pw_assert_HandleFailure() -> ! {
@@ -113,14 +111,9 @@
 
 // Default stub handlers for peripherals not yet implemented
 default_handler!(
-    fmc, gpio, hace,
-    i2c, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8, i2c9, i2c10, i2c11, i2c12, i2c13,
-    i2cfilter,
-    i3c, i3c1, i3c2, i3c3,
-    scu, sgpiom,
-    spi, spi1, spipf1, spipf2, spipf3,
-    timer1, timer2, timer3, timer4, timer5, timer6, timer7,
-    uart, uartdma, wdt
+    fmc, gpio, hace, i2c, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8, i2c9, i2c10, i2c11,
+    i2c12, i2c13, i2cfilter, i3c, i3c1, i3c2, i3c3, scu, sgpiom, spi, spi1, spipf1, spipf2, spipf3,
+    timer1, timer2, timer3, timer4, timer5, timer6, timer7, uart, uartdma, wdt
 );
 
 mod console_backend {

diff --git a/target/ast10x0/peripherals/i2c/controller.rs b/target/ast10x0/peripherals/i2c/controller.rs
index dbff8d9..555fc5b 100644
--- a/target/ast10x0/peripherals/i2c/controller.rs
+++ b/target/ast10x0/peripherals/i2c/controller.rs

@@ -286,4 +286,3 @@
         }
     }
 }
-

diff --git a/target/ast10x0/peripherals/i2c/master.rs b/target/ast10x0/peripherals/i2c/master.rs
index b286fd9..f8a01f9 100644
--- a/target/ast10x0/peripherals/i2c/master.rs
+++ b/target/ast10x0/peripherals/i2c/master.rs

@@ -211,7 +211,9 @@
 
         while offset < total_len {
             let chunk_len = core::cmp::min(constants::BUFFER_MODE_SIZE, total_len - offset);
-            let chunk = bytes.get(offset..offset + chunk_len).ok_or(I2cError::Invalid)?;
+            let chunk = bytes
+                .get(offset..offset + chunk_len)
+                .ok_or(I2cError::Invalid)?;
             let is_first = offset == 0;
             let is_last = offset + chunk_len >= total_len;
 
@@ -336,7 +338,9 @@
             }
 
             // Copy from hardware buffer AFTER successful transfer
-            let chunk = buffer.get_mut(offset..offset + chunk_len).ok_or(I2cError::Invalid)?;
+            let chunk = buffer
+                .get_mut(offset..offset + chunk_len)
+                .ok_or(I2cError::Invalid)?;
             self.copy_from_buffer(chunk)?;
 
             #[allow(clippy::cast_possible_truncation)]
@@ -442,7 +446,9 @@
 
         while offset < total_len {
             let chunk_len = core::cmp::min(constants::DMA_MODE_MAX_SIZE, total_len - offset);
-            let chunk = bytes.get(offset..offset + chunk_len).ok_or(I2cError::Invalid)?;
+            let chunk = bytes
+                .get(offset..offset + chunk_len)
+                .ok_or(I2cError::Invalid)?;
             let is_first = offset == 0;
             let is_last = offset + chunk_len >= total_len;
 
@@ -584,7 +590,10 @@
             // Copy from DMA buffer into caller's buffer
             {
                 let dma_buf = self.dma_buf.as_deref().ok_or(I2cError::Invalid)?;
-                buffer.get_mut(offset..offset + chunk_len).ok_or(I2cError::Invalid)?.copy_from_slice(dma_buf.get(..chunk_len).ok_or(I2cError::Invalid)?);
+                buffer
+                    .get_mut(offset..offset + chunk_len)
+                    .ok_or(I2cError::Invalid)?
+                    .copy_from_slice(dma_buf.get(..chunk_len).ok_or(I2cError::Invalid)?);
             }
 
             #[allow(clippy::cast_possible_truncation)]

diff --git a/target/ast10x0/peripherals/i2c/target_adapter.rs b/target/ast10x0/peripherals/i2c/target_adapter.rs
index 847d852..bc6d840 100644
--- a/target/ast10x0/peripherals/i2c/target_adapter.rs
+++ b/target/ast10x0/peripherals/i2c/target_adapter.rs

@@ -272,4 +272,3 @@
     /// Called when a stop condition is received.
     fn on_stop(&mut self);
 }
-

diff --git a/target/ast10x0/peripherals/scu/clock.rs b/target/ast10x0/peripherals/scu/clock.rs
index b1e21db..e258112 100644
--- a/target/ast10x0/peripherals/scu/clock.rs
+++ b/target/ast10x0/peripherals/scu/clock.rs

@@ -43,4 +43,4 @@
             ClockRegisterHalf::Upper => self.regs().scu090().read().bits(),
         }
     }
-}
\ No newline at end of file
+}

diff --git a/target/ast10x0/peripherals/scu/mod.rs b/target/ast10x0/peripherals/scu/mod.rs
index fc6468a..fdcd40c 100644
--- a/target/ast10x0/peripherals/scu/mod.rs
+++ b/target/ast10x0/peripherals/scu/mod.rs

@@ -3,13 +3,13 @@
 
 //! AST10x0 System Control Unit (SCU) module.
 
-pub mod registers;
-pub mod types;
-pub mod reset;
 pub mod clock;
-pub mod status;
 pub mod pinctrl;
+pub mod registers;
+pub mod reset;
+pub mod status;
+pub mod types;
 
-pub use registers::ScuRegisters;
 pub use pinctrl::PinctrlPin;
-pub use types::{ClockRegisterHalf, ScuRegisterHalf};
\ No newline at end of file
+pub use registers::ScuRegisters;
+pub use types::{ClockRegisterHalf, ScuRegisterHalf};

diff --git a/target/ast10x0/peripherals/scu/registers.rs b/target/ast10x0/peripherals/scu/registers.rs
index 255f735..9414ce9 100644
--- a/target/ast10x0/peripherals/scu/registers.rs
+++ b/target/ast10x0/peripherals/scu/registers.rs

@@ -69,4 +69,4 @@
             .scu000()
             .write(|w| unsafe { w.bits(SCU_UNLOCK_KEY) });
     }
-}
\ No newline at end of file
+}

diff --git a/target/ast10x0/peripherals/scu/reset.rs b/target/ast10x0/peripherals/scu/reset.rs
index 76f7ece..73dc09a 100644
--- a/target/ast10x0/peripherals/scu/reset.rs
+++ b/target/ast10x0/peripherals/scu/reset.rs

@@ -43,4 +43,4 @@
             ScuRegisterHalf::Upper => self.regs().scu050().read().bits(),
         }
     }
-}
\ No newline at end of file
+}

diff --git a/target/ast10x0/peripherals/scu/status.rs b/target/ast10x0/peripherals/scu/status.rs
index 0fb276b..28206ae 100644
--- a/target/ast10x0/peripherals/scu/status.rs
+++ b/target/ast10x0/peripherals/scu/status.rs

@@ -29,4 +29,4 @@
     pub fn multi_func_694_raw(&self) -> u32 {
         self.regs().scu694().read().bits()
     }
-}
\ No newline at end of file
+}

diff --git a/target/ast10x0/peripherals/scu/types.rs b/target/ast10x0/peripherals/scu/types.rs
index cf0314b..0a2d8c1 100644
--- a/target/ast10x0/peripherals/scu/types.rs
+++ b/target/ast10x0/peripherals/scu/types.rs

@@ -15,4 +15,4 @@
 pub enum ClockRegisterHalf {
     Lower,
     Upper,
-}
\ No newline at end of file
+}

diff --git a/target/ast10x0/peripherals/smc/controller.rs b/target/ast10x0/peripherals/smc/controller.rs
index c3e5823..1ae7248 100644
--- a/target/ast10x0/peripherals/smc/controller.rs
+++ b/target/ast10x0/peripherals/smc/controller.rs

@@ -46,7 +46,8 @@
 // ownership, so this scratch buffer is not accessed concurrently.
 unsafe impl Sync for CalibrationScratch {}
 
-static CALIBRATION_SCRATCH: CalibrationScratch = CalibrationScratch(UnsafeCell::new([0; SPI_CALIB_LEN]));
+static CALIBRATION_SCRATCH: CalibrationScratch =
+    CalibrationScratch(UnsafeCell::new([0; SPI_CALIB_LEN]));
 
 const fn spi_nor_qread_cmd_for_capacity(capacity_bytes: usize) -> u32 {
     if capacity_bytes > SPI_NOR_4B_READ_THRESHOLD_BYTES {

diff --git a/target/ast10x0/peripherals/smc/device/block_device.rs b/target/ast10x0/peripherals/smc/device/block_device.rs
index fbfbfff..e9112c2 100644
--- a/target/ast10x0/peripherals/smc/device/block_device.rs
+++ b/target/ast10x0/peripherals/smc/device/block_device.rs

@@ -23,10 +23,7 @@
 
 impl<'a, 'b> SpiNorBlockDevice<'a, 'b> {
     /// Build a block facade from an existing `SpiNorFlash` plus known config.
-    pub fn from_flash(
-        flash: &'a mut SpiNorFlash<'b>,
-        cfg: FlashConfig,
-    ) -> Result<Self, SmcError> {
+    pub fn from_flash(flash: &'a mut SpiNorFlash<'b>, cfg: FlashConfig) -> Result<Self, SmcError> {
         let expected = cfg_capacity_bytes(cfg)?;
         let actual = SpiNorFlashDevice::capacity_bytes(flash)?;
         if expected != actual {
@@ -39,10 +36,7 @@
     }
 
     /// Build a block facade by mapping a JEDEC ID to a known flash profile.
-    pub fn from_jedec_id(
-        flash: &'a mut SpiNorFlash<'b>,
-        jedec: JedecId,
-    ) -> Result<Self, SmcError> {
+    pub fn from_jedec_id(flash: &'a mut SpiNorFlash<'b>, jedec: JedecId) -> Result<Self, SmcError> {
         let cfg = cfg_from_jedec(jedec)?;
         Self::from_flash(flash, cfg)
     }
@@ -111,4 +105,4 @@
         (0xEF, 0x40, 0x19) => Ok(FlashConfig::winbond_w25q256()),
         _ => Err(SmcError::DeviceNotSupported),
     }
-}
\ No newline at end of file
+}

diff --git a/target/ast10x0/peripherals/smc/device/flash.rs b/target/ast10x0/peripherals/smc/device/flash.rs
index 7aa2e5e..70992a5 100644
--- a/target/ast10x0/peripherals/smc/device/flash.rs
+++ b/target/ast10x0/peripherals/smc/device/flash.rs

@@ -225,7 +225,11 @@
     }
 
     /// Build a flash facade from an initialized FMC controller wrapper with explicit CS.
-    pub fn from_fmc_cs(fmc: &'a mut FmcReady, cfg: FlashConfig, cs: ChipSelect) -> Result<Self, SmcError> {
+    pub fn from_fmc_cs(
+        fmc: &'a mut FmcReady,
+        cfg: FlashConfig,
+        cs: ChipSelect,
+    ) -> Result<Self, SmcError> {
         let addressing_policy = Self::default_addressing_for_cfg(cfg);
         Self::validate_capacity_cfg(cfg, fmc.cs_config(cs)?)?;
         Ok(Self {
@@ -244,7 +248,11 @@
     }
 
     /// Build a flash facade from an initialized SPI1/SPI2 controller wrapper with explicit CS.
-    pub fn from_spi_cs(spi: &'a mut SpiReady, cfg: FlashConfig, cs: ChipSelect) -> Result<Self, SmcError> {
+    pub fn from_spi_cs(
+        spi: &'a mut SpiReady,
+        cfg: FlashConfig,
+        cs: ChipSelect,
+    ) -> Result<Self, SmcError> {
         let addressing_policy = Self::default_addressing_for_cfg(cfg);
         Self::validate_capacity_cfg(cfg, spi.cs_config(cs)?)?;
         Ok(Self {
@@ -388,7 +396,6 @@
         self.command_profile
     }
 
-
     /// Validate a device-local offset before handing it to the controller.
     ///
     /// `FmcReady::read` / `SpiReady::read` already select the per-CS AHB
@@ -444,12 +451,8 @@
         let opcode = self.command_profile().read_status;
         let mut status = [0u8; 1];
         match &self.backend {
-            FlashBackend::Fmc(fmc) => {
-                fmc.transceive_user(cs, &[opcode], &[], &mut status, mode)?
-            }
-            FlashBackend::Spi(spi) => {
-                spi.transceive_user(cs, &[opcode], &[], &mut status, mode)?
-            }
+            FlashBackend::Fmc(fmc) => fmc.transceive_user(cs, &[opcode], &[], &mut status, mode)?,
+            FlashBackend::Spi(spi) => spi.transceive_user(cs, &[opcode], &[], &mut status, mode)?,
         }
         Ok(status[0])
     }
@@ -651,10 +654,12 @@
     #[test]
     fn compare_chunked_propagates_read_error() {
         let expected = fixture_1kb();
-        let read = |_offset: u32, _dst: &mut [u8]| -> Result<usize, SmcError> {
+        let read =
+            |_offset: u32, _dst: &mut [u8]| -> Result<usize, SmcError> { Err(SmcError::Timeout) };
+        assert_eq!(
+            compare_chunked(read, 0, &expected, 256),
             Err(SmcError::Timeout)
-        };
-        assert_eq!(compare_chunked(read, 0, &expected, 256), Err(SmcError::Timeout));
+        );
     }
 
     #[test]
@@ -667,6 +672,9 @@
     fn expect_jedec_match_rejects_mismatch() {
         let expected = JedecId::from_bytes([0xEF, 0x40, 0x18]);
         let actual = JedecId::from_bytes([0xC2, 0x20, 0x19]);
-        assert_eq!(expect_jedec_match(actual, expected), Err(SmcError::HardwareError));
+        assert_eq!(
+            expect_jedec_match(actual, expected),
+            Err(SmcError::HardwareError)
+        );
     }
 }

diff --git a/target/ast10x0/peripherals/smc/device/mod.rs b/target/ast10x0/peripherals/smc/device/mod.rs
index f7fba1f..16c3b58 100644
--- a/target/ast10x0/peripherals/smc/device/mod.rs
+++ b/target/ast10x0/peripherals/smc/device/mod.rs

@@ -3,8 +3,10 @@
 
 //! Flash device abstractions layered on top of SMC wrappers.
 
-mod flash;
 mod block_device;
+mod flash;
 
-pub use flash::{FlashAddressingPolicy, FlashCommandProfile, SpiNorFlashDevice, JedecId, SpiNorFlash};
 pub use block_device::{BlockDeviceInfo, SpiNorBlockDevice};
+pub use flash::{
+    FlashAddressingPolicy, FlashCommandProfile, JedecId, SpiNorFlash, SpiNorFlashDevice,
+};

diff --git a/target/ast10x0/peripherals/smc/interrupts.rs b/target/ast10x0/peripherals/smc/interrupts.rs
index fae72cb..ceca6db 100644
--- a/target/ast10x0/peripherals/smc/interrupts.rs
+++ b/target/ast10x0/peripherals/smc/interrupts.rs

@@ -88,7 +88,10 @@
     #[test]
     fn decode_emits_dma_error_on_abort_by_default() {
         let intr_ctrl = 1 << 10;
-        assert_eq!(SmcInterruptDecoder::decode(intr_ctrl), SmcInterrupt::DmaError);
+        assert_eq!(
+            SmcInterruptDecoder::decode(intr_ctrl),
+            SmcInterrupt::DmaError
+        );
     }
 
     #[test]

diff --git a/target/ast10x0/peripherals/smc/mod.rs b/target/ast10x0/peripherals/smc/mod.rs
index 4f2bc8c..8ef133d 100644
--- a/target/ast10x0/peripherals/smc/mod.rs
+++ b/target/ast10x0/peripherals/smc/mod.rs

@@ -6,23 +6,26 @@
 //! Provides safe abstractions over the FMC (Firmware Memory Controller)
 //! and SPI1/SPI2 flash controllers.
 
-pub mod registers;
-pub mod types;
-mod helpers;
 pub mod controller;
-pub mod fmc;
-pub mod spi;
-pub mod interrupts;
 pub mod device;
+pub mod fmc;
+mod helpers;
+pub mod interrupts;
+pub mod registers;
+pub mod spi;
+pub mod types;
 
-pub use types::{SmcError, SmcController, ChipSelect, FlashConfig, SmcConfig, SmcRetryable, TransferMode, AddressWidth, SmcTopology};
 pub use controller::{Ready, ReadySmc, Smc, UninitSmc, Uninitialized};
-pub use fmc::{FmcReady, FmcUninit};
-pub use spi::{SpiReady, SpiUninit};
-pub use interrupts::{SmcInterrupt, SmcInterruptDecoder};
 pub use device::{
-	BlockDeviceInfo, FlashAddressingPolicy, FlashCommandProfile, JedecId, SpiNorBlockDevice,
-	SpiNorFlash, SpiNorFlashDevice,
+    BlockDeviceInfo, FlashAddressingPolicy, FlashCommandProfile, JedecId, SpiNorBlockDevice,
+    SpiNorFlash, SpiNorFlashDevice,
+};
+pub use fmc::{FmcReady, FmcUninit};
+pub use interrupts::{SmcInterrupt, SmcInterruptDecoder};
+pub use spi::{SpiReady, SpiUninit};
+pub use types::{
+    AddressWidth, ChipSelect, FlashConfig, SmcConfig, SmcController, SmcError, SmcRetryable,
+    SmcTopology, TransferMode,
 };
 
 /// Result type for SMC operations

diff --git a/target/ast10x0/peripherals/smc/registers.rs b/target/ast10x0/peripherals/smc/registers.rs
index 4328f5f..f629249 100644
--- a/target/ast10x0/peripherals/smc/registers.rs
+++ b/target/ast10x0/peripherals/smc/registers.rs

@@ -9,7 +9,7 @@
 //! # Phase 5: Topology Logic Boundary
 //!
 //! **This trait is pure register abstraction. No topology logic belongs here.**
-//! 
+//!
 //! All decisions about when to call these operations, how to interpret results
 //! based on controller role, and topology-gated behaviors (decode-range sizing,
 //! calibration skip, control register programming per role) live in the
@@ -19,8 +19,8 @@
 //! The controller layer answers "what to do with the data based on the topology."
 
 use ast1060_pac as device;
-use core::marker::PhantomData;
 use core::cell::UnsafeCell;
+use core::marker::PhantomData;
 
 use crate::smc::helpers::{
     SPI_DMA_DISCARD_REQ_MAGIC, SPI_DMA_GET_REQ_MAGIC, SPI_DMA_GRANT, SPI_DMA_REQUEST,
@@ -104,7 +104,9 @@
 
     /// FMC008: Clear DMA status bits (write-1-to-clear).
     pub fn clear_dma_status(&self, clear_mask: u32) {
-        self.regs().fmc008().write(|w| unsafe { w.bits(clear_mask) });
+        self.regs()
+            .fmc008()
+            .write(|w| unsafe { w.bits(clear_mask) });
     }
 
     /// FMC008: Enable DMA interrupt (bit 3, `dmaintenbl`).
@@ -118,7 +120,9 @@
     ///
     /// Call at the top of the IRQ handler before processing status bits.
     pub fn disable_dma_irq(&self) {
-        self.regs().fmc008().modify(|_, w| w.dmaintenbl().clear_bit());
+        self.regs()
+            .fmc008()
+            .modify(|_, w| w.dmaintenbl().clear_bit());
     }
 
     /// FMC010: CS0 control register
@@ -310,13 +314,9 @@
 
     pub fn already_calibrated(&self, cs: crate::smc::types::ChipSelect) -> bool {
         match cs {
-            crate::smc::types::ChipSelect::Cs0 => {
-                self.read_cs0_timing_compensation() != 0
-            }
+            crate::smc::types::ChipSelect::Cs0 => self.read_cs0_timing_compensation() != 0,
 
-            crate::smc::types::ChipSelect::Cs1 => {
-                self.read_cs1_timing_compensation() != 0
-            }
+            crate::smc::types::ChipSelect::Cs1 => self.read_cs1_timing_compensation() != 0,
         }
     }
 }

diff --git a/target/ast10x0/peripherals/uart/mod.rs b/target/ast10x0/peripherals/uart/mod.rs
index e8d039e..7a07df4 100644
--- a/target/ast10x0/peripherals/uart/mod.rs
+++ b/target/ast10x0/peripherals/uart/mod.rs

@@ -8,468 +8,461 @@
 
 #[derive(Clone, Copy, Eq, PartialEq, Debug)]
 pub enum Error {
-	Frame,
-	Parity,
-	Noise,
-	BufFull,
+    Frame,
+    Parity,
+    Noise,
+    BufFull,
 }
 
 #[derive(Debug)]
 pub enum InterruptDecoding {
-	ModemStatusChange = 0,
-	TxEmpty = 1,
-	RxDataAvailable = 2,
-	LineStatusChange = 3,
-	CharacterTimeout = 6,
-	Unknown = -1,
+    ModemStatusChange = 0,
+    TxEmpty = 1,
+    RxDataAvailable = 2,
+    LineStatusChange = 3,
+    CharacterTimeout = 6,
+    Unknown = -1,
 }
 
 impl TryFrom<u8> for InterruptDecoding {
-	type Error = ();
+    type Error = ();
 
-	fn try_from(value: u8) -> Result<Self, Self::Error> {
-		match value & 0x07 {
-			0 => Ok(InterruptDecoding::ModemStatusChange),
-			1 => Ok(InterruptDecoding::TxEmpty),
-			2 => Ok(InterruptDecoding::RxDataAvailable),
-			3 => Ok(InterruptDecoding::LineStatusChange),
-			6 => Ok(InterruptDecoding::CharacterTimeout),
-			_ => Err(()),
-		}
-	}
+    fn try_from(value: u8) -> Result<Self, Self::Error> {
+        match value & 0x07 {
+            0 => Ok(InterruptDecoding::ModemStatusChange),
+            1 => Ok(InterruptDecoding::TxEmpty),
+            2 => Ok(InterruptDecoding::RxDataAvailable),
+            3 => Ok(InterruptDecoding::LineStatusChange),
+            6 => Ok(InterruptDecoding::CharacterTimeout),
+            _ => Err(()),
+        }
+    }
 }
 
 /// Receiver FIFO Interrupt trigger level
 #[derive(Debug)]
 #[repr(u8)]
 pub enum FifoTriggerLevel {
-	// 1 byte trigger level
-	OneByte = 0b00,
-	// 4 byte trigger level
-	FourByte = 0b01,
-	// 8 byte trigger level
-	EightByte = 0b10,
-	// 14 byte trigger level
-	FourteenByte = 0b11,
+    // 1 byte trigger level
+    OneByte = 0b00,
+    // 4 byte trigger level
+    FourByte = 0b01,
+    // 8 byte trigger level
+    EightByte = 0b10,
+    // 14 byte trigger level
+    FourteenByte = 0b11,
 }
 
 bitflags! {
-	#[derive(Debug)]
-	pub struct LineStatus: u8 {
-		/// here is at least one parity error, framing error, or break indication in the FIFO.
-		///
-		/// This bit is only active when FIFOs are enabled.
-		/// This bit is cleared when the `UART_LSR` is read.
-		const ErrorInReceiverFifo = 0x80;
-		/// Transmitter empty
-		///
-		/// When FIFO enabled, the Transmitter Shift Register and FIFO are both empty.
-		/// When FIFO disabled, the Transmitter Shift Register and UART_THR are both empty.
-		const TransmitterEmpty = 0x40;
-		/// Transmitter Holding Register Empty
-		///
-		/// This bit is set whenever data is transferred from UART_THR
-		/// or TX FIFO to the transmitter shift register
-		/// and no new data has been written to the UART THR or TX FIFO.
-		/// This also causes a THRE Interrupt to occur, if THRE Interrupt is enabled
-		const TransmitterHoldingRegisterEmpty = 0x20;
-		/// Break interrupt
-		///
-		/// The serial input is held in a logic `0` state for longer
-		/// than the sum of start time + data bits + parity + stop bits.
-		/// A break condition on serial input causes one and only one character,
-		/// consisting of all zeros, to be received by the UART
-		const BreakInterrupt = 0x10;
-		/// Framing error
-		///
-		/// A received character did not have a valid stop bit.
-		const FramingError = 0x08;
-		/// Parity error
-		///
-		/// Receive parity error while parity enable was set.
-		const ParityError = 0x04;
-		/// Overrun error
-		///
-		/// Character was received while the receiver or FIFO was full.
-		const OverrunError = 0x02;
-		/// Data ready
-		///
-		/// The receiver contains at least one character.
-		const DataReady = 0x01;
-	}
+    #[derive(Debug)]
+    pub struct LineStatus: u8 {
+        /// here is at least one parity error, framing error, or break indication in the FIFO.
+        ///
+        /// This bit is only active when FIFOs are enabled.
+        /// This bit is cleared when the `UART_LSR` is read.
+        const ErrorInReceiverFifo = 0x80;
+        /// Transmitter empty
+        ///
+        /// When FIFO enabled, the Transmitter Shift Register and FIFO are both empty.
+        /// When FIFO disabled, the Transmitter Shift Register and UART_THR are both empty.
+        const TransmitterEmpty = 0x40;
+        /// Transmitter Holding Register Empty
+        ///
+        /// This bit is set whenever data is transferred from UART_THR
+        /// or TX FIFO to the transmitter shift register
+        /// and no new data has been written to the UART THR or TX FIFO.
+        /// This also causes a THRE Interrupt to occur, if THRE Interrupt is enabled
+        const TransmitterHoldingRegisterEmpty = 0x20;
+        /// Break interrupt
+        ///
+        /// The serial input is held in a logic `0` state for longer
+        /// than the sum of start time + data bits + parity + stop bits.
+        /// A break condition on serial input causes one and only one character,
+        /// consisting of all zeros, to be received by the UART
+        const BreakInterrupt = 0x10;
+        /// Framing error
+        ///
+        /// A received character did not have a valid stop bit.
+        const FramingError = 0x08;
+        /// Parity error
+        ///
+        /// Receive parity error while parity enable was set.
+        const ParityError = 0x04;
+        /// Overrun error
+        ///
+        /// Character was received while the receiver or FIFO was full.
+        const OverrunError = 0x02;
+        /// Data ready
+        ///
+        /// The receiver contains at least one character.
+        const DataReady = 0x01;
+    }
 }
 pub struct Usart {
-	usart: *const device::uart::RegisterBlock,
+    usart: *const device::uart::RegisterBlock,
 }
 
 impl embedded_io::ErrorType for Usart {
-	type Error = Error;
+    type Error = Error;
 }
 
 impl embedded_io::Error for Error {
-	fn kind(&self) -> embedded_io::ErrorKind {
-		embedded_io::ErrorKind::Other
-	}
+    fn kind(&self) -> embedded_io::ErrorKind {
+        embedded_io::ErrorKind::Other
+    }
 }
 
 impl serial_nb::Error for Error {
-	fn kind(&self) -> serial_nb::ErrorKind {
-		match self {
-			Error::Frame => serial_nb::ErrorKind::FrameFormat,
-			Error::Parity => serial_nb::ErrorKind::Parity,
-			Error::Noise => serial_nb::ErrorKind::Noise,
-			Error::BufFull => serial_nb::ErrorKind::Overrun,
-		}
-	}
+    fn kind(&self) -> serial_nb::ErrorKind {
+        match self {
+            Error::Frame => serial_nb::ErrorKind::FrameFormat,
+            Error::Parity => serial_nb::ErrorKind::Parity,
+            Error::Noise => serial_nb::ErrorKind::Noise,
+            Error::BufFull => serial_nb::ErrorKind::Overrun,
+        }
+    }
 }
 
 impl serial_nb::ErrorType for Usart {
-	type Error = Error;
+    type Error = Error;
 }
 
 impl Write for Usart {
-	fn flush(&mut self) -> Result<(), Error> {
-		while !self.is_tx_idle() {}
-		Ok(())
-	}
+    fn flush(&mut self) -> Result<(), Error> {
+        while !self.is_tx_idle() {}
+        Ok(())
+    }
 
-	#[inline(always)]
-	fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
-		let mut written = 0;
-		for byte in buf.iter() {
-			if !self.is_tx_full() {
-				// This is unsafe because we can transmit 7, 8 or 9 bits but the
-				// interface can't know what it's been configured for.
-				self.regs()
-					.uartthr()
-					.write(|w| unsafe { w.bits(*byte as u32) });
-				written += 1;
-			} else {
-				if written == 0 {
-					// spec demands to block until at least one byte has been written.
-					// `continue` would skip to the next byte rather than retrying
-					// this one, so we busy-wait inline instead.
-					while self.is_tx_full() {}
-					self.regs()
-						.uartthr()
-						.write(|w| unsafe { w.bits(*byte as u32) });
-					written += 1;
-				} else {
-					break;
-				}
-			}
-		}
-		// Two invariants hold that LLVM cannot prove through value range analysis
-		// due to the busy-wait inner loop and early break:
-		//
-		// 1. n <= buf.len(): `written` is incremented at most once per element of
-		//    `buf.iter()`. Without this, `write_all`'s `buf = &buf[n..]` retains
-		//    a bounds-check panic. The `min` makes the assert mathematically sound.
-		//
-		// 2. n > 0 when buf is non-empty: the busy-wait guarantees at least one
-		//    byte is written before returning. Without this, `write_all`'s
-		//    `Ok(0) => panic!` branch is retained even though it is unreachable.
-		let n = written.min(buf.len());
-		unsafe {
-			core::hint::assert_unchecked(n <= buf.len());
-			core::hint::assert_unchecked(n > 0 || buf.is_empty());
-		}
-		Ok(n)
-	}
+    #[inline(always)]
+    fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
+        let mut written = 0;
+        for byte in buf.iter() {
+            if !self.is_tx_full() {
+                // This is unsafe because we can transmit 7, 8 or 9 bits but the
+                // interface can't know what it's been configured for.
+                self.regs()
+                    .uartthr()
+                    .write(|w| unsafe { w.bits(*byte as u32) });
+                written += 1;
+            } else {
+                if written == 0 {
+                    // spec demands to block until at least one byte has been written.
+                    // `continue` would skip to the next byte rather than retrying
+                    // this one, so we busy-wait inline instead.
+                    while self.is_tx_full() {}
+                    self.regs()
+                        .uartthr()
+                        .write(|w| unsafe { w.bits(*byte as u32) });
+                    written += 1;
+                } else {
+                    break;
+                }
+            }
+        }
+        // Two invariants hold that LLVM cannot prove through value range analysis
+        // due to the busy-wait inner loop and early break:
+        //
+        // 1. n <= buf.len(): `written` is incremented at most once per element of
+        //    `buf.iter()`. Without this, `write_all`'s `buf = &buf[n..]` retains
+        //    a bounds-check panic. The `min` makes the assert mathematically sound.
+        //
+        // 2. n > 0 when buf is non-empty: the busy-wait guarantees at least one
+        //    byte is written before returning. Without this, `write_all`'s
+        //    `Ok(0) => panic!` branch is retained even though it is unreachable.
+        let n = written.min(buf.len());
+        unsafe {
+            core::hint::assert_unchecked(n <= buf.len());
+            core::hint::assert_unchecked(n > 0 || buf.is_empty());
+        }
+        Ok(n)
+    }
 }
 
 impl Read for Usart {
-	fn read(&mut self, out: &mut [u8]) -> Result<usize, Self::Error> {
-		if out.is_empty() {
-			return Ok(0);
-		}
+    fn read(&mut self, out: &mut [u8]) -> Result<usize, Self::Error> {
+        if out.is_empty() {
+            return Ok(0);
+        }
 
-		let mut count = 0;
-		// Block until at least one byte is available, then drain what is immediately readable.
-		while count == 0 {
-			match self.try_read_byte() {
-				Ok(byte) => {
-					out[count] = byte;
-					count += 1;
-				}
-				Err(nb::Error::WouldBlock) => continue,
-				Err(nb::Error::Other(e)) => return Err(e),
-			}
-		}
+        let mut count = 0;
+        // Block until at least one byte is available, then drain what is immediately readable.
+        while count == 0 {
+            match self.try_read_byte() {
+                Ok(byte) => {
+                    out[count] = byte;
+                    count += 1;
+                }
+                Err(nb::Error::WouldBlock) => continue,
+                Err(nb::Error::Other(e)) => return Err(e),
+            }
+        }
 
-		while count < out.len() {
-			match self.try_read_byte() {
-				Ok(byte) => {
-					out[count] = byte;
-					count += 1;
-				}
-				Err(nb::Error::WouldBlock) => break,
-				Err(nb::Error::Other(e)) => return Err(e),
-			}
-		}
+        while count < out.len() {
+            match self.try_read_byte() {
+                Ok(byte) => {
+                    out[count] = byte;
+                    count += 1;
+                }
+                Err(nb::Error::WouldBlock) => break,
+                Err(nb::Error::Other(e)) => return Err(e),
+            }
+        }
 
-		Ok(count)
-	}
+        Ok(count)
+    }
 }
 
 impl serial_nb::Write<u8> for Usart {
-	fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
-		if !self.is_tx_full() {
-			// This is unsafe because we can transmit 7, 8 or 9 bits but the
-			// interface can't know what it's been configured for.
-			self.regs()
-				.uartthr()
-				.write(|w| unsafe { w.bits(word as u32) });
-			Ok(())
-		} else {
-			Err(nb::Error::WouldBlock)
-		}
-	}
+    fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
+        if !self.is_tx_full() {
+            // This is unsafe because we can transmit 7, 8 or 9 bits but the
+            // interface can't know what it's been configured for.
+            self.regs()
+                .uartthr()
+                .write(|w| unsafe { w.bits(word as u32) });
+            Ok(())
+        } else {
+            Err(nb::Error::WouldBlock)
+        }
+    }
 
-	fn flush(&mut self) -> nb::Result<(), Self::Error> {
-		if self.is_tx_idle() {
-			Ok(())
-		} else {
-			Err(nb::Error::WouldBlock)
-		}
-	}
+    fn flush(&mut self) -> nb::Result<(), Self::Error> {
+        if self.is_tx_idle() {
+            Ok(())
+        } else {
+            Err(nb::Error::WouldBlock)
+        }
+    }
 }
 
 impl serial_nb::Read<u8> for Usart {
-	fn read(&mut self) -> nb::Result<u8, Self::Error> {
-		self.try_read_byte()
-	}
+    fn read(&mut self) -> nb::Result<u8, Self::Error> {
+        self.try_read_byte()
+    }
 }
 pub enum Rate {
-	Baud9600,
-	Baud19200,
-	MBaud1_5,
+    Baud9600,
+    Baud19200,
+    MBaud1_5,
 }
 
 impl Usart {
-	#[inline]
-	fn try_read_byte(&self) -> nb::Result<u8, Error> {
-		// Read LSR exactly once per byte so error bits and DR correspond to the same FIFO state.
-		let lsr = self.regs().uartlsr().read();
-		if !lsr.dr().bit() {
-			return Err(nb::Error::WouldBlock);
-		}
+    #[inline]
+    fn try_read_byte(&self) -> nb::Result<u8, Error> {
+        // Read LSR exactly once per byte so error bits and DR correspond to the same FIFO state.
+        let lsr = self.regs().uartlsr().read();
+        if !lsr.dr().bit() {
+            return Err(nb::Error::WouldBlock);
+        }
 
-		let byte = self.regs().uartrbr().read().bits() as u8;
-		if lsr.fe().bit_is_set() {
-			Err(nb::Error::Other(Error::Frame))
-		} else if lsr.pe().bit_is_set() {
-			Err(nb::Error::Other(Error::Parity))
-		} else if self.is_rx_noise_err() {
-			Err(nb::Error::Other(Error::Noise))
-		} else {
-			Ok(byte)
-		}
-	}
+        let byte = self.regs().uartrbr().read().bits() as u8;
+        if lsr.fe().bit_is_set() {
+            Err(nb::Error::Other(Error::Frame))
+        } else if lsr.pe().bit_is_set() {
+            Err(nb::Error::Other(Error::Parity))
+        } else if self.is_rx_noise_err() {
+            Err(nb::Error::Other(Error::Noise))
+        } else {
+            Ok(byte)
+        }
+    }
 
-	/// Create an uninitialized USART instance without writing to registers.
-	///
-	/// This const function creates a Usart struct pointing to the register block
-	/// but does not perform any hardware initialization. Use this for static
-	/// initializers and call `new()` or follow with hardware initialization.
-	///
-	/// # Safety
-	///
-	/// - `usart` must be a valid, non-null pointer to the AST1060 UART register block.
-	/// - The pointed register block must remain valid for the lifetime of this `Usart`.
-	pub const unsafe fn new_uninit(usart: *const device::uart::RegisterBlock) -> Self {
-		Self { usart }
-	}
+    /// Create an uninitialized USART instance without writing to registers.
+    ///
+    /// This const function creates a Usart struct pointing to the register block
+    /// but does not perform any hardware initialization. Use this for static
+    /// initializers and call `new()` or follow with hardware initialization.
+    ///
+    /// # Safety
+    ///
+    /// - `usart` must be a valid, non-null pointer to the AST1060 UART register block.
+    /// - The pointed register block must remain valid for the lifetime of this `Usart`.
+    pub const unsafe fn new_uninit(usart: *const device::uart::RegisterBlock) -> Self {
+        Self { usart }
+    }
 
-	/// Create a new USART instance from a raw register-block pointer.
-	///
-	/// Configures RX/TX FIFO, 8 byte RX trigger level, 1.5MBaud, 8n1, and
-	/// enables all interrupts.
-	///
-	/// # Safety
-	///
-	/// - `usart` must be a valid, non-null pointer to the AST1060 UART register block.
-	/// - The pointed register block must remain valid for the lifetime of this `Usart`.
-	/// - Caller must enforce global ownership/coordination so concurrent mutable access
-	///   does not occur through other code paths.
-	pub unsafe fn new(usart: *const device::uart::RegisterBlock) -> Self {
-		let this = Self {
-			usart,
-		};
+    /// Create a new USART instance from a raw register-block pointer.
+    ///
+    /// Configures RX/TX FIFO, 8 byte RX trigger level, 1.5MBaud, 8n1, and
+    /// enables all interrupts.
+    ///
+    /// # Safety
+    ///
+    /// - `usart` must be a valid, non-null pointer to the AST1060 UART register block.
+    /// - The pointed register block must remain valid for the lifetime of this `Usart`.
+    /// - Caller must enforce global ownership/coordination so concurrent mutable access
+    ///   does not occur through other code paths.
+    pub unsafe fn new(usart: *const device::uart::RegisterBlock) -> Self {
+        let this = Self { usart };
 
-		unsafe {
-			this.regs().uartfcr().write(|w| {
-				w.enbl_uartfifo().set_bit();
-				w.rx_fiforst().set_bit();
-				w.tx_fiforst().set_bit();
-				w.define_the_rxr_fifointtrigger_level().bits(0b10)
-			});
-		}
+        unsafe {
+            this.regs().uartfcr().write(|w| {
+                w.enbl_uartfifo().set_bit();
+                w.rx_fiforst().set_bit();
+                w.tx_fiforst().set_bit();
+                w.define_the_rxr_fifointtrigger_level().bits(0b10)
+            });
+        }
 
-		this
-			.set_rate(Rate::MBaud1_5)
-			.set_8n1()
-			.interrupt_enable()
-	}
+        this.set_rate(Rate::MBaud1_5).set_8n1().interrupt_enable()
+    }
 
-	#[inline]
-	fn regs(&self) -> &device::uart::RegisterBlock {
-		// SAFETY: `Usart` construction is `unsafe`, so caller upholds pointer validity,
-		// non-nullness, and aliasing/ownership requirements.
-		unsafe { &*self.usart }
-	}
+    #[inline]
+    fn regs(&self) -> &device::uart::RegisterBlock {
+        // SAFETY: `Usart` construction is `unsafe`, so caller upholds pointer validity,
+        // non-nullness, and aliasing/ownership requirements.
+        unsafe { &*self.usart }
+    }
 
-	/// Set the baud rate
-	///
-	/// These baud rates assume that the uart clock is set to 24Mhz.
-	pub fn set_rate(self, rate: Rate) -> Self {
-		// These baud rates assume that the uart clock is set to 24Mhz.
+    /// Set the baud rate
+    ///
+    /// These baud rates assume that the uart clock is set to 24Mhz.
+    pub fn set_rate(self, rate: Rate) -> Self {
+        // These baud rates assume that the uart clock is set to 24Mhz.
 
-		// Enable DLAB to access divisor latch registers
-		self.regs().uartlcr().modify(|_, w| w.dlab().set_bit());
+        // Enable DLAB to access divisor latch registers
+        self.regs().uartlcr().modify(|_, w| w.dlab().set_bit());
 
-		// Divisor = 24M / (13 * 16 * Baud Rate)
-		match rate {
-			Rate::Baud9600 => {
-				self.regs().uartdlh().write(|w| unsafe { w.bits(0) });
-				self.regs().uartdll().write(|w| unsafe { w.bits(12) });
-			}
-			Rate::Baud19200 => {
-				self.regs().uartdlh().write(|w| unsafe { w.bits(0) });
-				self.regs().uartdll().write(|w| unsafe { w.bits(6) });
-			}
-			Rate::MBaud1_5 => {
-				self.regs().uartdlh().write(|w| unsafe { w.bits(0) });
-				self.regs().uartdll().write(|w| unsafe { w.bits(1) });
-			}
-		}
-		// Disable DLAB to access other registers
-		self.regs().uartlcr().modify(|_, w| w.dlab().clear_bit());
+        // Divisor = 24M / (13 * 16 * Baud Rate)
+        match rate {
+            Rate::Baud9600 => {
+                self.regs().uartdlh().write(|w| unsafe { w.bits(0) });
+                self.regs().uartdll().write(|w| unsafe { w.bits(12) });
+            }
+            Rate::Baud19200 => {
+                self.regs().uartdlh().write(|w| unsafe { w.bits(0) });
+                self.regs().uartdll().write(|w| unsafe { w.bits(6) });
+            }
+            Rate::MBaud1_5 => {
+                self.regs().uartdlh().write(|w| unsafe { w.bits(0) });
+                self.regs().uartdll().write(|w| unsafe { w.bits(1) });
+            }
+        }
+        // Disable DLAB to access other registers
+        self.regs().uartlcr().modify(|_, w| w.dlab().clear_bit());
 
-		self
-	}
+        self
+    }
 
-	/// Enable all interrupts
-	///
-	/// - Modem Status Interrupt
-	/// - Receiver Line Status Interrupt
-	/// - Transmitter Holding Register Empty Interrupt
-	/// - Received Data Available Interrupt
-	pub fn interrupt_enable(self) -> Self {
-		self.regs().uartier().write(|w| {
-			w.erbfi().set_bit(); // Enable Received Data Available Interrupt
-			w.etbei().set_bit(); // Enable Transmitter Holding Register Empty Interrupt
-			w.elsi().set_bit(); // Enable Receiver Line Status Interrupt
-			w.edssi().set_bit(); // Enable Modem Status Interrupt
-			w
-		});
+    /// Enable all interrupts
+    ///
+    /// - Modem Status Interrupt
+    /// - Receiver Line Status Interrupt
+    /// - Transmitter Holding Register Empty Interrupt
+    /// - Received Data Available Interrupt
+    pub fn interrupt_enable(self) -> Self {
+        self.regs().uartier().write(|w| {
+            w.erbfi().set_bit(); // Enable Received Data Available Interrupt
+            w.etbei().set_bit(); // Enable Transmitter Holding Register Empty Interrupt
+            w.elsi().set_bit(); // Enable Receiver Line Status Interrupt
+            w.edssi().set_bit(); // Enable Modem Status Interrupt
+            w
+        });
 
-		self
-	}
+        self
+    }
 
-	/// Set the Receiver FIFO Interrupt trigger level
-	pub fn set_rx_fifo_trigger_level(&self, level: FifoTriggerLevel) {
-		unsafe {
-			self.regs().uartfcr().modify(|_, w| {
-				w.define_the_rxr_fifointtrigger_level().bits(level as u8)
-			});
-		}
-	}
+    /// Set the Receiver FIFO Interrupt trigger level
+    pub fn set_rx_fifo_trigger_level(&self, level: FifoTriggerLevel) {
+        unsafe {
+            self.regs()
+                .uartfcr()
+                .modify(|_, w| w.define_the_rxr_fifointtrigger_level().bits(level as u8));
+        }
+    }
 
-	pub fn set_8n1(self) -> Self {
-		self
-	}
+    pub fn set_8n1(self) -> Self {
+        self
+    }
 
-	pub fn is_tx_full(&self) -> bool {
-		!self.regs().uartlsr().read().thre().bit()
-	}
+    pub fn is_tx_full(&self) -> bool {
+        !self.regs().uartlsr().read().thre().bit()
+    }
 
-	pub fn is_rx_empty(&self) -> bool {
-		!self.regs().uartlsr().read().dr().bit()
-	}
+    pub fn is_rx_empty(&self) -> bool {
+        !self.regs().uartlsr().read().dr().bit()
+    }
 
-	pub fn is_rx_frame_err(&self) -> bool {
-		self.regs().uartlsr().read().fe().bit_is_set()
-	}
+    pub fn is_rx_frame_err(&self) -> bool {
+        self.regs().uartlsr().read().fe().bit_is_set()
+    }
 
-	pub fn is_rx_parity_err(&self) -> bool {
-		self.regs().uartlsr().read().pe().bit_is_set()
-	}
+    pub fn is_rx_parity_err(&self) -> bool {
+        self.regs().uartlsr().read().pe().bit_is_set()
+    }
 
-	pub fn is_rx_noise_err(&self) -> bool {
-		// self.usart.uartlsr().read().rxnoise().bit()
-		false
-	}
+    pub fn is_rx_noise_err(&self) -> bool {
+        // self.usart.uartlsr().read().rxnoise().bit()
+        false
+    }
 
-	pub fn read_interrupt_status(&self) -> InterruptDecoding {
-		InterruptDecoding::try_from(
-			self.regs().uartiir().read().intdecoding_table().bits() & 0x07,
-		)
-		.unwrap_or(InterruptDecoding::Unknown)
-	}
+    pub fn read_interrupt_status(&self) -> InterruptDecoding {
+        InterruptDecoding::try_from(self.regs().uartiir().read().intdecoding_table().bits() & 0x07)
+            .unwrap_or(InterruptDecoding::Unknown)
+    }
 
-	pub fn read_line_status(&self) -> LineStatus {
-		let status = self.regs().uartlsr().read().bits() as u8;
-		LineStatus::from_bits_truncate(status)
-	}
+    pub fn read_line_status(&self) -> LineStatus {
+        let status = self.regs().uartlsr().read().bits() as u8;
+        LineStatus::from_bits_truncate(status)
+    }
 
-	/// Non-blocking drain of the RX FIFO into `out`.
-	///
-	/// Copies as many bytes as are immediately available (up to `out.len()`)
-	/// and returns the count.  Returns `0` if the FIFO is empty; the caller
-	/// should arm the `RX_DATA_AVAILABLE` interrupt and retry.
-	pub fn try_read_available(&self, out: &mut [u8]) -> usize {
-		let mut count = 0;
-		while count < out.len() {
-			match self.try_read_byte() {
-				Ok(byte) => {
-					out[count] = byte;
-					count += 1;
-				}
-				Err(nb::Error::WouldBlock) => break,
-				Err(nb::Error::Other(_)) => break,
-			}
-		}
-		count
-	}
+    /// Non-blocking drain of the RX FIFO into `out`.
+    ///
+    /// Copies as many bytes as are immediately available (up to `out.len()`)
+    /// and returns the count.  Returns `0` if the FIFO is empty; the caller
+    /// should arm the `RX_DATA_AVAILABLE` interrupt and retry.
+    pub fn try_read_available(&self, out: &mut [u8]) -> usize {
+        let mut count = 0;
+        while count < out.len() {
+            match self.try_read_byte() {
+                Ok(byte) => {
+                    out[count] = byte;
+                    count += 1;
+                }
+                Err(nb::Error::WouldBlock) => break,
+                Err(nb::Error::Other(_)) => break,
+            }
+        }
+        count
+    }
 
-	pub fn read_modem_status(&self) -> u8 {
-		self.regs().uartmsr().read().bits() as u8
-	}
+    pub fn read_modem_status(&self) -> u8 {
+        self.regs().uartmsr().read().bits() as u8
+    }
 
-	pub fn is_tx_idle(&self) -> bool {
-		self.regs().uartlsr().read().txter_empty().bit_is_set()
-	}
+    pub fn is_tx_idle(&self) -> bool {
+        self.regs().uartlsr().read().txter_empty().bit_is_set()
+    }
 
-	/// Enables the TX idle interrupt (ETBEI)
-	pub fn set_tx_idle_interrupt(&self) {
-		self.regs().uartier().modify(|_, w| w.etbei().set_bit());
-	}
+    /// Enables the TX idle interrupt (ETBEI)
+    pub fn set_tx_idle_interrupt(&self) {
+        self.regs().uartier().modify(|_, w| w.etbei().set_bit());
+    }
 
-	/// Disables the TX idle interrupt (ETBEI)
-	pub fn clear_tx_idle_interrupt(&self) {
-		// self.regs().uartier().write(|w| w.etbei().clear_bit());
-		self.regs().uartier().modify(|_, w| w.etbei().clear_bit());
-	}
+    /// Disables the TX idle interrupt (ETBEI)
+    pub fn clear_tx_idle_interrupt(&self) {
+        // self.regs().uartier().write(|w| w.etbei().clear_bit());
+        self.regs().uartier().modify(|_, w| w.etbei().clear_bit());
+    }
 
-	/// Enables the RX idle interrupt (ERBFI)
-	pub fn set_rx_data_available_interrupt(&self) {
-		self.regs().uartier().modify(|_, w| w.erbfi().set_bit());
-	}
+    /// Enables the RX idle interrupt (ERBFI)
+    pub fn set_rx_data_available_interrupt(&self) {
+        self.regs().uartier().modify(|_, w| w.erbfi().set_bit());
+    }
 
-	/// Disables the RX idle interrupt (ERBFI)
-	pub fn clear_rx_data_available_interrupt(&self) {
-		self.regs().uartier().modify(|_, w| w.erbfi().clear_bit());
-	}
+    /// Disables the RX idle interrupt (ERBFI)
+    pub fn clear_rx_data_available_interrupt(&self) {
+        self.regs().uartier().modify(|_, w| w.erbfi().clear_bit());
+    }
 
-	/// Disables all four IER interrupt sources at once.
-	pub fn disable_all_interrupts(&self) {
-		self.regs().uartier().write(|w| w);
-	}
+    /// Disables all four IER interrupt sources at once.
+    pub fn disable_all_interrupts(&self) {
+        self.regs().uartier().write(|w| w);
+    }
 
-	/// Reads and discards MSR to clear the delta bits (DCTS/DDSR/TERI/DDCD)
-	/// that would otherwise keep retriggering EDSSI after enable.
-	pub fn drain_modem_status(&self) {
-		let _ = self.regs().uartmsr().read().bits();
-	}
+    /// Reads and discards MSR to clear the delta bits (DCTS/DDSR/TERI/DDCD)
+    /// that would otherwise keep retriggering EDSSI after enable.
+    pub fn drain_modem_status(&self) {
+        let _ = self.regs().uartmsr().read().bits();
+    }
 }

diff --git a/target/ast10x0/tests/interrupts/kernel/target.rs b/target/ast10x0/tests/interrupts/kernel/target.rs
index 0616415..d7b6a3a 100644
--- a/target/ast10x0/tests/interrupts/kernel/target.rs
+++ b/target/ast10x0/tests/interrupts/kernel/target.rs

@@ -8,7 +8,7 @@
 use codegen as _;
 use console_backend::console_backend_write_all;
 use entry as _;
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 
 pub struct Target {}
 

diff --git a/target/ast10x0/tests/interrupts/user/target.rs b/target/ast10x0/tests/interrupts/user/target.rs
index 92cb3fc..ebf027e 100644
--- a/target/ast10x0/tests/interrupts/user/target.rs
+++ b/target/ast10x0/tests/interrupts/user/target.rs

@@ -6,7 +6,7 @@
 
 use console_backend::console_backend_write_all;
 use entry as _;
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 
 pub struct Target {}
 
@@ -21,7 +21,11 @@
 
     fn shutdown(code: u32) -> ! {
         pw_log::info!("Shutting down with code {}", code as u32);
-        let sentinel: &[u8] = if code == 0 { b"TEST_RESULT:PASS\n" } else { b"TEST_RESULT:FAIL\n" };
+        let sentinel: &[u8] = if code == 0 {
+            b"TEST_RESULT:PASS\n"
+        } else {
+            b"TEST_RESULT:FAIL\n"
+        };
         let _ = console_backend_write_all(sentinel);
         #[expect(clippy::empty_loop)]
         loop {}

diff --git a/target/ast10x0/tests/ipc/user/target.rs b/target/ast10x0/tests/ipc/user/target.rs
index d386f54..68b9571 100644
--- a/target/ast10x0/tests/ipc/user/target.rs
+++ b/target/ast10x0/tests/ipc/user/target.rs

@@ -5,8 +5,8 @@
 #![no_main]
 
 use console_backend::console_backend_write_all;
-use target_common::{TargetInterface, declare_target};
 use entry as _;
+use target_common::{declare_target, TargetInterface};
 
 pub struct Target {}
 
@@ -21,7 +21,11 @@
 
     fn shutdown(code: u32) -> ! {
         pw_log::info!("Shutting down with code {}", code as u32);
-        let sentinel: &[u8] = if code == 0 { b"TEST_RESULT:PASS\n" } else { b"TEST_RESULT:FAIL\n" };
+        let sentinel: &[u8] = if code == 0 {
+            b"TEST_RESULT:PASS\n"
+        } else {
+            b"TEST_RESULT:FAIL\n"
+        };
         let _ = console_backend_write_all(sentinel);
         #[expect(clippy::empty_loop)]
         loop {}

diff --git a/target/ast10x0/tests/peripherals/i2c/i2c_init/target.rs b/target/ast10x0/tests/peripherals/i2c/i2c_init/target.rs
index 27d6d44..6b819be 100644
--- a/target/ast10x0/tests/peripherals/i2c/i2c_init/target.rs
+++ b/target/ast10x0/tests/peripherals/i2c/i2c_init/target.rs

@@ -12,7 +12,7 @@
 use codegen as _;
 use console_backend::console_backend_write_all;
 use entry as _;
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 
 pub struct Target {}
 
@@ -391,11 +391,7 @@
         }
         Err(error) => {
             let error_name = i2c_error_str(error);
-            pw_log::error!(
-                "{} mode init failed: {}",
-                name as &str,
-                error_name as &str
-            );
+            pw_log::error!("{} mode init failed: {}", name as &str, error_name as &str);
             dump_i2c1_registers(name, &config);
             Err(ERR_INIT_FAILED)
         }
@@ -430,11 +426,7 @@
         }
         Err(error) => {
             let error_name = i2c_error_str(error);
-            pw_log::error!(
-                "{} mode init failed: {}",
-                name as &str,
-                error_name as &str
-            );
+            pw_log::error!("{} mode init failed: {}", name as &str, error_name as &str);
             dump_i2c1_registers(name, &config);
             Err(ERR_INIT_FAILED)
         }

diff --git a/target/ast10x0/tests/peripherals/i2c/i2c_irq/slave_target.rs b/target/ast10x0/tests/peripherals/i2c/i2c_irq/slave_target.rs
index c187718..2ee63a1 100644
--- a/target/ast10x0/tests/peripherals/i2c/i2c_irq/slave_target.rs
+++ b/target/ast10x0/tests/peripherals/i2c/i2c_irq/slave_target.rs

@@ -21,7 +21,7 @@
 use codegen as _;
 use console_backend::console_backend_write_all;
 use entry as _;
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 
 pub struct Target {}
 
@@ -41,10 +41,7 @@
 }
 
 /// Poll handle_slave_interrupt until an event arrives or the budget runs out.
-fn wait_event<Y: FnMut(u32)>(
-    slave: &mut Ast1060I2c<'_, Y>,
-    max_polls: u32,
-) -> Option<SlaveEvent> {
+fn wait_event<Y: FnMut(u32)>(slave: &mut Ast1060I2c<'_, Y>, max_polls: u32) -> Option<SlaveEvent> {
     for _ in 0..max_polls {
         if let Some(ev) = slave.handle_slave_interrupt() {
             return Some(ev);
@@ -56,7 +53,10 @@
 
 fn run_slave() -> Result<(), &'static str> {
     pw_log::info!("=== I2C slave IRQ test: SLAVE (device B) ===");
-    pw_log::info!("Listening at addr 0x{:02x}. Start master (device A) now.", SLAVE_ADDR as u32);
+    pw_log::info!(
+        "Listening at addr 0x{:02x}. Start master (device A) now.",
+        SLAVE_ADDR as u32
+    );
 
     let board = Ast10x0Board::new(Ast10x0BoardDescriptor {
         pinctrl_groups: &[pinctrl::PINCTRL_I2C2],
@@ -87,11 +87,17 @@
     match wait_event(&mut slave, 50_000_000) {
         Some(SlaveEvent::DataReceived { len }) => {
             if len != EXPECTED_WRITE.len() {
-                pw_log::error!("test 1: DataReceived len={} expected={}", len as u32, EXPECTED_WRITE.len() as u32);
+                pw_log::error!(
+                    "test 1: DataReceived len={} expected={}",
+                    len as u32,
+                    EXPECTED_WRITE.len() as u32
+                );
                 return Err("test 1: DataReceived len mismatch");
             }
             let mut buf = [0u8; EXPECTED_WRITE.len()];
-            slave.slave_read(&mut buf).map_err(|_| "test 1: slave_read failed")?;
+            slave
+                .slave_read(&mut buf)
+                .map_err(|_| "test 1: slave_read failed")?;
             if buf != *EXPECTED_WRITE {
                 return Err("test 1: DataReceived payload mismatch");
             }

diff --git a/target/ast10x0/tests/peripherals/i2c/i2c_irq/target.rs b/target/ast10x0/tests/peripherals/i2c/i2c_irq/target.rs
index 238fb56..33439ed 100644
--- a/target/ast10x0/tests/peripherals/i2c/i2c_irq/target.rs
+++ b/target/ast10x0/tests/peripherals/i2c/i2c_irq/target.rs

@@ -25,7 +25,7 @@
 use codegen as _;
 use console_backend::console_backend_write_all;
 use entry as _;
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 
 pub struct Target {}
 
@@ -68,9 +68,9 @@
     // Test 1: master write → slave DataReceived
     // ------------------------------------------------------------------
     pw_log::info!("Test 1: master write");
-    master
-        .write(SLAVE_ADDR, WRITE_PAYLOAD)
-        .map_err(|_| "test 1: master write failed (slave not responding — check J15 and slave firmware)")?;
+    master.write(SLAVE_ADDR, WRITE_PAYLOAD).map_err(|_| {
+        "test 1: master write failed (slave not responding — check J15 and slave firmware)"
+    })?;
     pw_log::info!("Test 1 passed");
 
     // ------------------------------------------------------------------

diff --git a/target/ast10x0/tests/smc/dma_irq/target.rs b/target/ast10x0/tests/smc/dma_irq/target.rs
index 6828cb1..0f311f3 100644
--- a/target/ast10x0/tests/smc/dma_irq/target.rs
+++ b/target/ast10x0/tests/smc/dma_irq/target.rs

@@ -22,8 +22,8 @@
 use core::task::Poll;
 
 use arch_arm_cortex_m::Arch;
-use ast10x0_peripherals::scu::ScuRegisters;
 use ast10x0_peripherals::scu::pinctrl::PINCTRL_FMC_QUAD;
+use ast10x0_peripherals::scu::ScuRegisters;
 use ast10x0_peripherals::smc::{
     ChipSelect, FlashConfig, SmcConfig, SmcController, SmcError, SmcInterrupt, SmcTopology,
     UninitSmc,
@@ -32,7 +32,7 @@
 use console_backend::console_backend_write_all;
 use kernel::Arch as KernelArch;
 use kernel::Kernel;
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 use {console_backend as _, entry as _};
 
 #[path = "../target_debug.rs"]

diff --git a/target/ast10x0/tests/stress/ipc/user/target.rs b/target/ast10x0/tests/stress/ipc/user/target.rs
index c5a38b9..fd56688 100644
--- a/target/ast10x0/tests/stress/ipc/user/target.rs
+++ b/target/ast10x0/tests/stress/ipc/user/target.rs

@@ -6,7 +6,7 @@
 
 use console_backend::console_backend_write_all;
 use entry as _;
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 
 pub struct Target {}
 

diff --git a/target/ast10x0/tests/stress/mutex/kernel/target.rs b/target/ast10x0/tests/stress/mutex/kernel/target.rs
index 1d84fb9..d8b334f 100644
--- a/target/ast10x0/tests/stress/mutex/kernel/target.rs
+++ b/target/ast10x0/tests/stress/mutex/kernel/target.rs

@@ -7,7 +7,7 @@
 use arch_arm_cortex_m::Arch;
 use console_backend::console_backend_write_all;
 use entry as _;
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 
 pub struct Target {}
 

diff --git a/target/ast10x0/tests/stress/process_termination/user/target.rs b/target/ast10x0/tests/stress/process_termination/user/target.rs
index 43af741..66657f1 100644
--- a/target/ast10x0/tests/stress/process_termination/user/target.rs
+++ b/target/ast10x0/tests/stress/process_termination/user/target.rs

@@ -6,7 +6,7 @@
 
 use console_backend::console_backend_write_all;
 use entry as _;
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 
 pub struct Target {}
 

diff --git a/target/ast10x0/tests/threads/kernel/target.rs b/target/ast10x0/tests/threads/kernel/target.rs
index d9376d9..b90e8a9 100644
--- a/target/ast10x0/tests/threads/kernel/target.rs
+++ b/target/ast10x0/tests/threads/kernel/target.rs

@@ -8,8 +8,8 @@
 
 use arch_arm_cortex_m::Arch;
 use console_backend::console_backend_write_all;
-use target_common::{TargetInterface, declare_target};
 use entry as _;
+use target_common::{declare_target, TargetInterface};
 
 pub struct Target {}
 

diff --git a/target/ast10x0/tests/unittest_runner/target.rs b/target/ast10x0/tests/unittest_runner/target.rs
index 176eeca..dfe8fee 100644
--- a/target/ast10x0/tests/unittest_runner/target.rs
+++ b/target/ast10x0/tests/unittest_runner/target.rs

@@ -5,7 +5,7 @@
 #![no_main]
 
 use console_backend::console_backend_write_all;
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 use unittest_core::TestsResult;
 use {entry as _, integration_tests as _};
 

diff --git a/target/ast10x0/tests/usart/target.rs b/target/ast10x0/tests/usart/target.rs
index 485021f..2ab9dc6 100644
--- a/target/ast10x0/tests/usart/target.rs
+++ b/target/ast10x0/tests/usart/target.rs

@@ -9,8 +9,8 @@
 #![no_std]
 #![no_main]
 
-use cortex_m_semihosting::debug::{EXIT_FAILURE, EXIT_SUCCESS, exit};
-use target_common::{TargetInterface, declare_target};
+use cortex_m_semihosting::debug::{exit, EXIT_FAILURE, EXIT_SUCCESS};
+use target_common::{declare_target, TargetInterface};
 use {console_backend as _, entry as _};
 
 pub struct Target {}
@@ -25,7 +25,11 @@
     }
 
     fn shutdown(code: u32) -> ! {
-        let status = if code == 0 { EXIT_SUCCESS } else { EXIT_FAILURE };
+        let status = if code == 0 {
+            EXIT_SUCCESS
+        } else {
+            EXIT_FAILURE
+        };
         exit(status);
         #[expect(clippy::empty_loop)]
         loop {}

diff --git a/target/earlgrey/drivers/gpio.rs b/target/earlgrey/drivers/gpio.rs
index 568052d..2c9c4c3 100644
--- a/target/earlgrey/drivers/gpio.rs
+++ b/target/earlgrey/drivers/gpio.rs

@@ -3,8 +3,8 @@
 
 #![no_std]
 
-use earlgrey_pinmux::{EarlGreyPinmux, Pad, PadConfig, Pull};
 use core::fmt::Debug;
+use earlgrey_pinmux::{EarlGreyPinmux, Pad, PadConfig, Pull};
 use openprot_hal_blocking::gpio_port::{
     EdgeSensitivity, GpioError, GpioErrorKind, GpioErrorType, GpioInterrupt, GpioPort,
     InterruptOperation, PinMask,
@@ -34,9 +34,9 @@
 
 impl EarlGreyGpio {
     /// Create a new instance of the EarlGrey GPIO driver using real MMIO.
-    /// 
+    ///
     /// # Safety
-    /// 
+    ///
     /// The caller must ensure that they have exclusive access to the GPIO and Pinmux peripherals.
     pub unsafe fn new() -> Self {
         Self {
@@ -46,7 +46,7 @@
     }
 
     /// Read current state of output pins.
-    /// 
+    ///
     /// This is a target-specific extension not yet in the core HAL.
     pub fn read_output(&self) -> Result<GpioMask, EarlGreyGpioError> {
         Ok(GpioMask(self.registers.direct_out().read()))
@@ -97,10 +97,38 @@
 
 #[derive(Debug, Copy, Clone, Eq, PartialEq)]
 pub enum GpioPin {
-    Pin0 = 0, Pin1 = 1, Pin2 = 2, Pin3 = 3, Pin4 = 4, Pin5 = 5, Pin6 = 6, Pin7 = 7,
-    Pin8 = 8, Pin9 = 9, Pin10 = 10, Pin11 = 11, Pin12 = 12, Pin13 = 13, Pin14 = 14, Pin15 = 15,
-    Pin16 = 16, Pin17 = 17, Pin18 = 18, Pin19 = 19, Pin20 = 20, Pin21 = 21, Pin22 = 22, Pin23 = 23,
-    Pin24 = 24, Pin25 = 25, Pin26 = 26, Pin27 = 27, Pin28 = 28, Pin29 = 29, Pin30 = 30, Pin31 = 31,
+    Pin0 = 0,
+    Pin1 = 1,
+    Pin2 = 2,
+    Pin3 = 3,
+    Pin4 = 4,
+    Pin5 = 5,
+    Pin6 = 6,
+    Pin7 = 7,
+    Pin8 = 8,
+    Pin9 = 9,
+    Pin10 = 10,
+    Pin11 = 11,
+    Pin12 = 12,
+    Pin13 = 13,
+    Pin14 = 14,
+    Pin15 = 15,
+    Pin16 = 16,
+    Pin17 = 17,
+    Pin18 = 18,
+    Pin19 = 19,
+    Pin20 = 20,
+    Pin21 = 21,
+    Pin22 = 22,
+    Pin23 = 23,
+    Pin24 = 24,
+    Pin25 = 25,
+    Pin26 = 26,
+    Pin27 = 27,
+    Pin28 = 28,
+    Pin29 = 29,
+    Pin30 = 30,
+    Pin31 = 31,
 }
 
 impl From<GpioPin> for GpioMask {
@@ -116,7 +144,7 @@
     pub is_output: bool,
     /// Whether to enable the 16-cycle input filter.
     pub input_filter: bool,
-    /// Optional pad to connect these pins to. 
+    /// Optional pad to connect these pins to.
     /// If multiple pins are specified in the mask, this should be None.
     pub pad: Option<Pad>,
     /// Pull-up/down configuration for the pad.
@@ -175,8 +203,8 @@
         // Handle Pinmux and Pad attributes
         if let Some(pad) = config.pad {
             let pin_idx = pins.0.trailing_zeros() as usize;
-            
-            // DIO pads are dedicated and don't require routing, 
+
+            // DIO pads are dedicated and don't require routing,
             // only attribute configuration.
             if !pad.is_dio() {
                 if config.is_input {
@@ -187,10 +215,13 @@
                 }
             }
 
-            self.pinmux.configure_pad(pad, &PadConfig {
-                pull: config.pull,
-                ..Default::default()
-            });
+            self.pinmux.configure_pad(
+                pad,
+                &PadConfig {
+                    pull: config.pull,
+                    ..Default::default()
+                },
+            );
         }
 
         Ok(())
@@ -207,9 +238,9 @@
         let lower_mask = set_lower | reset_lower;
 
         if lower_mask != 0 {
-            self.registers.masked_out_lower().write(|w| {
-                w.mask(lower_mask).data(set_lower)
-            });
+            self.registers
+                .masked_out_lower()
+                .write(|w| w.mask(lower_mask).data(set_lower));
         }
 
         // Process upper 16 bits
@@ -218,9 +249,9 @@
         let upper_mask = set_upper | reset_upper;
 
         if upper_mask != 0 {
-            self.registers.masked_out_upper().write(|w| {
-                w.mask(upper_mask).data(set_upper)
-            });
+            self.registers
+                .masked_out_upper()
+                .write(|w| w.mask(upper_mask).data(set_upper));
         }
 
         Ok(())
@@ -248,8 +279,12 @@
     ) -> Result<(), Self::Error> {
         // Clear all sensitivity settings for these pins first
         self.registers.intr_ctrl_en_rising().modify(|w| w & !mask.0);
-        self.registers.intr_ctrl_en_falling().modify(|w| w & !mask.0);
-        self.registers.intr_ctrl_en_lvlhigh().modify(|w| w & !mask.0);
+        self.registers
+            .intr_ctrl_en_falling()
+            .modify(|w| w & !mask.0);
+        self.registers
+            .intr_ctrl_en_lvlhigh()
+            .modify(|w| w & !mask.0);
         self.registers.intr_ctrl_en_lvllow().modify(|w| w & !mask.0);
 
         // Apply new sensitivity

diff --git a/target/earlgrey/drivers/pinmux.rs b/target/earlgrey/drivers/pinmux.rs
index 0bbe89a..be9fe7a 100644
--- a/target/earlgrey/drivers/pinmux.rs
+++ b/target/earlgrey/drivers/pinmux.rs

@@ -9,16 +9,70 @@
 #[repr(u32)]
 pub enum Pad {
     // MIO Pads (0-46)
-    IOA0 = 0, IOA1 = 1, IOA2 = 2, IOA3 = 3, IOA4 = 4, IOA5 = 5, IOA6 = 6, IOA7 = 7, IOA8 = 8,
-    IOB0 = 9, IOB1 = 10, IOB2 = 11, IOB3 = 12, IOB4 = 13, IOB5 = 14, IOB6 = 15, IOB7 = 16, IOB8 = 17,
-    IOB9 = 18, IOB10 = 19, IOB11 = 20, IOB12 = 21,
-    IOC0 = 22, IOC1 = 23, IOC2 = 24, IOC3 = 25, IOC4 = 26, IOC5 = 27, IOC6 = 28, IOC7 = 29, IOC8 = 30,
-    IOC9 = 31, IOC10 = 32, IOC11 = 33, IOC12 = 34,
-    IOR0 = 35, IOR1 = 36, IOR2 = 37, IOR3 = 38, IOR4 = 39, IOR5 = 40, IOR6 = 41, IOR7 = 42,
-    IOR10 = 43, IOR11 = 44, IOR12 = 45, IOR13 = 46,
+    IOA0 = 0,
+    IOA1 = 1,
+    IOA2 = 2,
+    IOA3 = 3,
+    IOA4 = 4,
+    IOA5 = 5,
+    IOA6 = 6,
+    IOA7 = 7,
+    IOA8 = 8,
+    IOB0 = 9,
+    IOB1 = 10,
+    IOB2 = 11,
+    IOB3 = 12,
+    IOB4 = 13,
+    IOB5 = 14,
+    IOB6 = 15,
+    IOB7 = 16,
+    IOB8 = 17,
+    IOB9 = 18,
+    IOB10 = 19,
+    IOB11 = 20,
+    IOB12 = 21,
+    IOC0 = 22,
+    IOC1 = 23,
+    IOC2 = 24,
+    IOC3 = 25,
+    IOC4 = 26,
+    IOC5 = 27,
+    IOC6 = 28,
+    IOC7 = 29,
+    IOC8 = 30,
+    IOC9 = 31,
+    IOC10 = 32,
+    IOC11 = 33,
+    IOC12 = 34,
+    IOR0 = 35,
+    IOR1 = 36,
+    IOR2 = 37,
+    IOR3 = 38,
+    IOR4 = 39,
+    IOR5 = 40,
+    IOR6 = 41,
+    IOR7 = 42,
+    IOR10 = 43,
+    IOR11 = 44,
+    IOR12 = 45,
+    IOR13 = 46,
     // DIO Pads (47-62)
-    DIO0 = 47, DIO1 = 48, DIO2 = 49, DIO3 = 50, DIO4 = 51, DIO5 = 52, DIO6 = 53, DIO7 = 54,
-    DIO8 = 55, DIO9 = 56, DIO10 = 57, DIO11 = 58, DIO12 = 59, DIO13 = 60, DIO14 = 61, DIO15 = 62,
+    DIO0 = 47,
+    DIO1 = 48,
+    DIO2 = 49,
+    DIO3 = 50,
+    DIO4 = 51,
+    DIO5 = 52,
+    DIO6 = 53,
+    DIO7 = 54,
+    DIO8 = 55,
+    DIO9 = 56,
+    DIO10 = 57,
+    DIO11 = 58,
+    DIO12 = 59,
+    DIO13 = 60,
+    DIO14 = 61,
+    DIO15 = 62,
 }
 
 impl Pad {
@@ -65,9 +119,9 @@
 
 impl EarlGreyPinmux {
     /// Create a new instance of the EarlGrey Pinmux driver.
-    /// 
+    ///
     /// # Safety
-    /// 
+    ///
     /// The caller must ensure that they have exclusive access to the Pinmux peripheral.
     pub unsafe fn new() -> Self {
         Self {
@@ -79,7 +133,8 @@
     pub fn connect_input(&mut self, periph_input_idx: usize, pad: Pad) {
         // MIO pads start at index 2 in periph_insel (0=Low, 1=High)
         let periph_source = 2 + (pad as u32);
-        self.registers.mio_periph_insel()
+        self.registers
+            .mio_periph_insel()
             .at(periph_input_idx)
             .write(|w| w.in_(periph_source));
     }
@@ -88,42 +143,39 @@
     pub fn connect_output(&mut self, pad: Pad, periph_output_idx: usize) {
         // Peripheral outputs start at index 3 in outsel (0=Low, 1=High, 2=HighZ)
         let pad_source = 3 + (periph_output_idx as u32);
-        self.registers.mio_outsel()
+        self.registers
+            .mio_outsel()
             .at(pad as usize)
             .write(|w| w.out(pad_source));
     }
 
     pub fn configure_pad(&mut self, pad: Pad, config: &PadConfig) {
         if let Some(dio_idx) = pad.dio_index() {
-            self.registers.dio_pad_attr()
-                .at(dio_idx)
-                .modify(|w| {
-                    w.pull_en(config.pull != Pull::None)
-                        .pull_select(|w| {
-                            if config.pull == Pull::Up {
-                                w.pull_up()
-                            } else {
-                                w.pull_down()
-                            }
-                        })
-                        .od_en(config.open_drain)
-                        .invert(config.invert)
-                });
+            self.registers.dio_pad_attr().at(dio_idx).modify(|w| {
+                w.pull_en(config.pull != Pull::None)
+                    .pull_select(|w| {
+                        if config.pull == Pull::Up {
+                            w.pull_up()
+                        } else {
+                            w.pull_down()
+                        }
+                    })
+                    .od_en(config.open_drain)
+                    .invert(config.invert)
+            });
         } else {
-            self.registers.mio_pad_attr()
-                .at(pad as usize)
-                .modify(|w| {
-                    w.pull_en(config.pull != Pull::None)
-                        .pull_select(|w| {
-                            if config.pull == Pull::Up {
-                                w.pull_up()
-                            } else {
-                                w.pull_down()
-                            }
-                        })
-                        .od_en(config.open_drain)
-                        .invert(config.invert)
-                });
+            self.registers.mio_pad_attr().at(pad as usize).modify(|w| {
+                w.pull_en(config.pull != Pull::None)
+                    .pull_select(|w| {
+                        if config.pull == Pull::Up {
+                            w.pull_up()
+                        } else {
+                            w.pull_down()
+                        }
+                    })
+                    .od_en(config.open_drain)
+                    .invert(config.invert)
+            });
         }
     }
 }

diff --git a/target/earlgrey/tests/drivers/gpio/target.rs b/target/earlgrey/tests/drivers/gpio/target.rs
index 146669a..36a559e 100644
--- a/target/earlgrey/tests/drivers/gpio/target.rs
+++ b/target/earlgrey/tests/drivers/gpio/target.rs

@@ -3,7 +3,7 @@
 
 #![no_std]
 #![no_main]
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 use {console_backend as _, entry as _};
 
 pub struct Target {}

diff --git a/target/earlgrey/tests/ipc/user/target.rs b/target/earlgrey/tests/ipc/user/target.rs
index d0532f2..44a1825 100644
--- a/target/earlgrey/tests/ipc/user/target.rs
+++ b/target/earlgrey/tests/ipc/user/target.rs

@@ -3,7 +3,7 @@
 
 #![no_std]
 #![no_main]
-use target_common::{TargetInterface, declare_target};
+use target_common::{declare_target, TargetInterface};
 use {console_backend as _, entry as _};
 
 pub struct Target {}
@@ -27,4 +27,3 @@
 }
 
 declare_target!(Target);
-

diff --git a/target/earlgrey/tests/uart/test_uart.rs b/target/earlgrey/tests/uart/test_uart.rs
index 2333700..eeef483 100644
--- a/target/earlgrey/tests/uart/test_uart.rs
+++ b/target/earlgrey/tests/uart/test_uart.rs

@@ -3,8 +3,8 @@
 
 #![no_std]
 #![no_main]
-use test_uart_codegen::handle;
 use pw_status::{Error, Result, StatusCode};
+use test_uart_codegen::handle;
 use userspace::syscall::Signals;
 use userspace::time::Instant;
 use userspace::{entry, syscall};

diff --git a/target/earlgrey/tests/uart/test_uart_listener.rs b/target/earlgrey/tests/uart/test_uart_listener.rs
index a013c7b..a94f3e5 100644
--- a/target/earlgrey/tests/uart/test_uart_listener.rs
+++ b/target/earlgrey/tests/uart/test_uart_listener.rs

@@ -3,8 +3,8 @@
 
 #![no_std]
 #![no_main]
-use test_uart_listener_codegen::{handle, signals};
 use pw_status::{Error, Result};
+use test_uart_listener_codegen::{handle, signals};
 use userspace::syscall::Signals;
 use userspace::time::Instant;
 use userspace::{entry, syscall};

diff --git a/third_party/caliptra/caliptra-mcu-sw/src/signer_main.rs b/third_party/caliptra/caliptra-mcu-sw/src/signer_main.rs
index f82184f..53954c9 100644
--- a/third_party/caliptra/caliptra-mcu-sw/src/signer_main.rs
+++ b/third_party/caliptra/caliptra-mcu-sw/src/signer_main.rs

@@ -82,7 +82,14 @@
     } else {
         0
     };
-    Ok((path, load_addr, staging_addr, image_id, exec_bit, component_id))
+    Ok((
+        path,
+        load_addr,
+        staging_addr,
+        image_id,
+        exec_bit,
+        component_id,
+    ))
 }
 
 fn parse_addr(s: &str) -> Result<u64> {
@@ -129,9 +136,7 @@
     })
 }
 
-fn create_auth_manifest(
-    image_metadata_list: Vec<AuthManifestImageMetadata>,
-) -> Result<Vec<u8>> {
+fn create_auth_manifest(image_metadata_list: Vec<AuthManifestImageMetadata>) -> Result<Vec<u8>> {
     let vendor_fw_key_info = AuthManifestGeneratorKeyConfig {
         pub_keys: AuthManifestPubKeysConfig {
             ecc_pub_key: VENDOR_ECC_KEY_0_PUBLIC,
@@ -207,9 +212,7 @@
         Commands::Experimental(cmd) => firmware_bundler::execute(cmd),
         Commands::AuthManifest { subcommand } => match subcommand {
             AuthManifestCommands::Create {
-                mcu_image,
-                output,
-                ..
+                mcu_image, output, ..
             } => {
                 let (path, load_addr, staging_addr, image_id, exec_bit, component_id) =
                     parse_image_cfg(&mcu_image)?;

diff --git a/third_party/caliptra/caliptra-sw/src/caliptra_firmware_bundler.rs b/third_party/caliptra/caliptra-sw/src/caliptra_firmware_bundler.rs
index 495a330..b66c3e6 100644
--- a/third_party/caliptra/caliptra-sw/src/caliptra_firmware_bundler.rs
+++ b/third_party/caliptra/caliptra-sw/src/caliptra_firmware_bundler.rs

@@ -37,9 +37,7 @@
 use anyhow::{anyhow, bail, Context, Result};
 use caliptra_image_crypto::RustCrypto as Crypto;
 use caliptra_image_fake_keys::{OWNER_CONFIG, VENDOR_CONFIG_KEY_0};
-use caliptra_image_gen::{
-    ImageGenerator, ImageGeneratorConfig, ImageGeneratorExecutable,
-};
+use caliptra_image_gen::{ImageGenerator, ImageGeneratorConfig, ImageGeneratorExecutable};
 use caliptra_image_types::{FwVerificationPqcKeyType, ImageRevision};
 use elf::endian::AnyEndian;
 use elf::ElfBytes;
@@ -84,9 +82,7 @@
             }
             let seg_addr = segment.p_paddr as u32;
             if seg_addr < load_addr {
-                bail!(
-                    "segment at 0x{seg_addr:08x} below base 0x{load_addr:08x}"
-                );
+                bail!("segment at 0x{seg_addr:08x} below base 0x{load_addr:08x}");
             }
             let offset = (seg_addr - load_addr) as usize;
             let end = offset + data.len();
@@ -166,15 +162,14 @@
     // rev-parse anyway.
     let rev: ImageRevision = *b"~~~~~NO_GIT_REVISION";
 
-    let fmc_bytes = fs::read(&args.fmc)
-        .with_context(|| format!("failed to read FMC ELF {:?}", args.fmc))?;
+    let fmc_bytes =
+        fs::read(&args.fmc).with_context(|| format!("failed to read FMC ELF {:?}", args.fmc))?;
     let runtime_bytes = fs::read(&args.runtime)
         .with_context(|| format!("failed to read Runtime ELF {:?}", args.runtime))?;
 
-    let fmc = ElfExecutable::from_bytes(&fmc_bytes, 0, rev)
-        .context("failed to pack FMC ELF")?;
-    let runtime = ElfExecutable::from_bytes(&runtime_bytes, 0, rev)
-        .context("failed to pack Runtime ELF")?;
+    let fmc = ElfExecutable::from_bytes(&fmc_bytes, 0, rev).context("failed to pack FMC ELF")?;
+    let runtime =
+        ElfExecutable::from_bytes(&runtime_bytes, 0, rev).context("failed to pack Runtime ELF")?;
 
     let cfg = ImageGeneratorConfig {
         pqc_key_type: FwVerificationPqcKeyType::LMS,

diff --git a/third_party/caliptra/caliptra-sw/src/caliptra_rom_packager.rs b/third_party/caliptra/caliptra-sw/src/caliptra_rom_packager.rs
index 4aa625e..02306d5 100644
--- a/third_party/caliptra/caliptra-sw/src/caliptra_rom_packager.rs
+++ b/third_party/caliptra/caliptra-sw/src/caliptra_rom_packager.rs

@@ -105,13 +105,15 @@
         let src = elf_bytes
             .get(file_offset..file_offset + len)
             .ok_or_else(|| anyhow!("segment at file offset 0x{file_offset:x} out of bounds"))?;
-        let dst = result.get_mut(mem_offset..mem_offset + len).ok_or_else(|| {
-            anyhow!(
-                "segment at 0x{mem_offset:x}..0x{:x} exceeds ROM region 0x0..0x{:x}",
-                mem_offset + len,
-                ROM_SIZE
-            )
-        })?;
+        let dst = result
+            .get_mut(mem_offset..mem_offset + len)
+            .ok_or_else(|| {
+                anyhow!(
+                    "segment at 0x{mem_offset:x}..0x{:x} exceeds ROM region 0x0..0x{:x}",
+                    mem_offset + len,
+                    ROM_SIZE
+                )
+            })?;
         dst.copy_from_slice(src);
     }
 
@@ -161,7 +163,9 @@
     if args.len() != 3 {
         bail!(
             "usage: {} <input_elf> <output_bin>",
-            args.first().map(String::as_str).unwrap_or("caliptra_rom_packager")
+            args.first()
+                .map(String::as_str)
+                .unwrap_or("caliptra_rom_packager")
         );
     }
     let input_path = &args[1];