Move I3C register operations into the I3cRegisters facade

Complete the SmcRegisters alignment: instead of only confining the
pointer derefs, every register operation now goes through an
intent-named method on I3cRegisters (enable_controller_primary,
assert_all_queue_resets, dat_program_addr, ...), so hardware.rs is pure
protocol logic with zero PAC register types and zero MMIO unsafe. Its
remaining unsafe is non-MMIO only: the IRQ-registry critical-section
leaves, the forwarded constructor gate, the curr_xfer handoff cast, and
the transfer buffer re-slicing.

The per-bus I3C-global reg0/reg1 dispatch and the eight-slot DAT
dispatch move into private macros inside the facade (the bus index
already lives there), deleting the macro layer from hardware.rs along
with its unreachable fallback arms. The FIFO word loops sink into the
facade as tx_fifo_write/rx_fifo_read/rx_fifo_drain/ibi_fifo_*, which
also retires the closure-taking rd_fifo/drain_fifo trait methods.