Add i3c module with pointer-based architecture and minimal coupling Integrate i3c controller from aspeed-rust into peripherals crate with: - Raw pointer architecture: Replace generic Instance trait with direct *const pointers to i3c and i3cglobal register blocks - Yield closure pattern: Use Y: FnMut(u32) for cooperative polling instead of blocking DelayNs trait calls - No SCU coupling: Remove all SCU reset/clock operations; caller responsible for pre-initialization - No Logger coupling: Remove Logger trait; provide no-op stubs in common.rs - Aligned with i2c module design: Minimal hardware abstraction layer with safe helper methods for register access Complete build with all tests passing. Co-Authored-By: Claude Haiku 4.5 <noreply@anthropic.com>
diff --git a/target/ast10x0/peripherals/BUILD.bazel b/target/ast10x0/peripherals/BUILD.bazel index 5da2edc..2831dac 100644 --- a/target/ast10x0/peripherals/BUILD.bazel +++ b/target/ast10x0/peripherals/BUILD.bazel
@@ -9,6 +9,7 @@ rust_library( name = "peripherals", srcs = [ + "common.rs", "i2c/constants.rs", "i2c/controller.rs", "i2c/error.rs", @@ -22,6 +23,16 @@ "i2c/timing.rs", "i2c/transfer.rs", "i2c/types.rs", + "i3c/ccc.rs", + "i3c/config.rs", + "i3c/constants.rs", + "i3c/controller.rs", + "i3c/error.rs", + "i3c/hal_impl.rs", + "i3c/hardware.rs", + "i3c/ibi.rs", + "i3c/mod.rs", + "i3c/types.rs", "lib.rs", "scu/clock.rs", "scu/mod.rs", @@ -54,10 +65,14 @@ "@ast1060_pac", "@pigweed//pw_log/rust:pw_log", "@rust_crates//:bitflags", + "@rust_crates//:cortex-m", + "@rust_crates//:critical-section", "@rust_crates//:embedded-hal", "@rust_crates//:embedded-hal-nb", "@rust_crates//:embedded-io", "@rust_crates//:embedded-storage", + "@rust_crates//:heapless", "@rust_crates//:nb", + "@rust_crates//:proposed-traits", ], )
diff --git a/target/ast10x0/peripherals/common.rs b/target/ast10x0/peripherals/common.rs new file mode 100644 index 0000000..4e9b828 --- /dev/null +++ b/target/ast10x0/peripherals/common.rs
@@ -0,0 +1,23 @@ +// Licensed under the Apache-2.0 license +// SPDX-License-Identifier: Apache-2.0 + +pub struct DummyDelay; + +impl embedded_hal::delay::DelayNs for DummyDelay { + fn delay_ns(&mut self, ns: u32) { + for _ in 0..(ns / 100) { + cortex_m::asm::nop(); + } + } +} + +pub trait Logger { + fn debug(&mut self, msg: &str); + fn error(&mut self, msg: &str); +} + +pub struct NoOpLogger; +impl Logger for NoOpLogger { + fn debug(&mut self, _msg: &str) {} + fn error(&mut self, _msg: &str) {} +}
diff --git a/target/ast10x0/peripherals/i3c/ccc.rs b/target/ast10x0/peripherals/i3c/ccc.rs new file mode 100644 index 0000000..bd93e4f --- /dev/null +++ b/target/ast10x0/peripherals/i3c/ccc.rs
@@ -0,0 +1,450 @@ +// Licensed under the Apache-2.0 license + +//! I3C Common Command Codes (CCC) +//! +//! Functions and types for executing I3C CCCs. + +use super::config::I3cConfig; +use super::constants::{ + I3C_CCC_GETBCR, I3C_CCC_GETPID, I3C_CCC_GETSTATUS, I3C_CCC_RSTDAA, I3C_CCC_SETNEWDA, +}; +use super::error::{CccErrorKind, I3cError}; +use super::hardware::HardwareInterface; + +// ============================================================================= +// CCC Types +// ============================================================================= + +/// CCC target payload for direct CCCs +#[derive(Debug)] +pub struct CccTargetPayload<'a> { + /// Target 7-bit dynamic address + pub addr: u8, + /// `false` = write, `true` = read + pub rnw: bool, + /// Data buffer for write (source) or read (destination) + pub data: Option<&'a mut [u8]>, + /// Actual bytes transferred (driver fills on return) + pub num_xfer: usize, +} + +/// CCC descriptor +#[derive(Debug)] +pub struct Ccc<'a> { + /// CCC ID (command code) + pub id: u8, + /// Optional CCC data immediately following the CCC byte + pub data: Option<&'a mut [u8]>, + /// Actual bytes transferred (driver fills on return) + pub num_xfer: usize, +} + +/// Complete CCC transaction description +#[derive(Debug)] +pub struct CccPayload<'a, 'b> { + /// The CCC command + pub ccc: Option<Ccc<'a>>, + /// Optional list of direct-CCC target payloads + pub targets: Option<&'b mut [CccTargetPayload<'a>]>, +} + +// ============================================================================= +// CCC Reset Action +// ============================================================================= + +/// RSTACT defining byte values +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum CccRstActDefByte { + /// No reset + NoReset = 0x0, + /// Reset peripheral only + PeriphralOnly = 0x1, + /// Reset whole target + ResetWholeTarget = 0x2, + /// Debug network adapter + DebugNetworkAdapter = 0x3, + /// Virtual target detect + VirtualTargetDetect = 0x4, +} + +impl CccRstActDefByte { + #[inline] + fn as_byte(self) -> u8 { + self as u8 + } +} + +// ============================================================================= +// GETSTATUS Types +// ============================================================================= + +/// GETSTATUS format selection +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GetStatusFormat { + /// Format 1 (no defining byte) + Fmt1, + /// Format 2 (with defining byte) + Fmt2(GetStatusDefByte), +} + +/// GETSTATUS defining byte values +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GetStatusDefByte { + /// 0x00 - TGTSTAT + TgtStat, + /// 0x91 - PRECR + Precr, +} + +impl GetStatusDefByte { + #[inline] + fn as_byte(self) -> u8 { + match self { + Self::TgtStat => 0x00, + Self::Precr => 0x91, + } + } +} + +/// GETSTATUS response +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GetStatusResp { + /// Format 1 response + Fmt1 { status: u16 }, + /// Format 2 response + Fmt2 { + kind: GetStatusDefByte, + raw_u16: u16, + }, +} + +// ============================================================================= +// CCC Helper Functions +// ============================================================================= + +const fn ccc_enec(broadcast: bool) -> u8 { + if broadcast { + 0x00 + } else { + 0x80 + } +} + +const fn ccc_disec(broadcast: bool) -> u8 { + if broadcast { + 0x01 + } else { + 0x81 + } +} + +const fn ccc_rstact(broadcast: bool) -> u8 { + if broadcast { + 0x2a + } else { + 0x9a + } +} + +// ============================================================================= +// CCC Operations +// ============================================================================= + +/// Enable/disable events for all devices (broadcast) +pub fn ccc_events_all_set<H>( + hw: &mut H, + config: &mut I3cConfig, + enable: bool, + events: u8, +) -> Result<(), I3cError> +where + H: HardwareInterface, +{ + let id = if enable { + ccc_enec(true) + } else { + ccc_disec(true) + }; + + hw.do_ccc( + config, + &mut CccPayload { + ccc: Some(Ccc { + id, + data: Some(&mut [events]), + num_xfer: 0, + }), + targets: None, + }, + ) + .map_err(|_| I3cError::CccError(CccErrorKind::Invalid)) +} + +/// Enable/disable events for a specific device (direct) +pub fn ccc_events_set<H>( + hw: &mut H, + config: &mut I3cConfig, + da: u8, + enable: bool, + events: u8, +) -> Result<(), I3cError> +where + H: HardwareInterface, +{ + if da == 0 { + return Err(I3cError::CccError(CccErrorKind::InvalidParam)); + } + + let mut ev_buf = [events]; + let tgt = CccTargetPayload { + addr: da, + rnw: false, + data: Some(&mut ev_buf[..]), + num_xfer: 0, + }; + + let mut tgts = [tgt]; + let ccc_id = if enable { + ccc_enec(false) + } else { + ccc_disec(false) + }; + let ccc = Ccc { + id: ccc_id, + data: None, + num_xfer: 0, + }; + + let mut payload = CccPayload { + ccc: Some(ccc), + targets: Some(&mut tgts[..]), + }; + + hw.do_ccc(config, &mut payload) + .map_err(|_| I3cError::CccError(CccErrorKind::Invalid)) +} + +/// Execute RSTACT (Reset Action) broadcast +pub fn ccc_rstact_all<H>( + hw: &mut H, + config: &mut I3cConfig, + action: CccRstActDefByte, +) -> Result<(), I3cError> +where + H: HardwareInterface, +{ + let mut db = [action.as_byte()]; + let ccc = Ccc { + id: ccc_rstact(true), + data: Some(&mut db[..]), + num_xfer: 0, + }; + let mut payload = CccPayload { + ccc: Some(ccc), + targets: None, + }; + + hw.do_ccc(config, &mut payload) + .map_err(|_| I3cError::CccError(CccErrorKind::Invalid)) +} + +/// Get BCR (Bus Characteristics Register) from a device +pub fn ccc_getbcr<H>(hw: &mut H, config: &mut I3cConfig, dyn_addr: u8) -> Result<u8, I3cError> +where + H: HardwareInterface, +{ + if dyn_addr == 0 { + return Err(I3cError::CccError(CccErrorKind::InvalidParam)); + } + + let mut bcr_buf = [0u8; 1]; + + let tgt = CccTargetPayload { + addr: dyn_addr, + rnw: true, + data: Some(&mut bcr_buf[..]), + num_xfer: 0, + }; + let mut tgts = [tgt]; + + let ccc = Ccc { + id: I3C_CCC_GETBCR, + data: None, + num_xfer: 0, + }; + let mut payload = CccPayload { + ccc: Some(ccc), + targets: Some(&mut tgts[..]), + }; + + hw.do_ccc(config, &mut payload) + .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))?; + + Ok(bcr_buf[0]) +} + +/// Set new dynamic address for a device +pub fn ccc_setnewda<H>( + hw: &mut H, + config: &mut I3cConfig, + curr_da: u8, + new_da: u8, +) -> Result<(), I3cError> +where + H: HardwareInterface, +{ + if curr_da == 0 || new_da == 0 { + return Err(I3cError::CccError(CccErrorKind::InvalidParam)); + } + + let pos = config.attached.pos_of_addr(curr_da); + if pos.is_none() { + return Err(I3cError::CccError(CccErrorKind::NotFound)); + } + + if !config.addrbook.is_free(new_da) { + return Err(I3cError::CccError(CccErrorKind::NoFreeSlot)); + } + + let mut new_dyn_addr = (new_da & 0x7F) << 1; + let tgt = CccTargetPayload { + addr: curr_da, + rnw: false, + data: Some(core::slice::from_mut(&mut new_dyn_addr)), + num_xfer: 0, + }; + let mut tgts = [tgt]; + let ccc = Ccc { + id: I3C_CCC_SETNEWDA, + data: None, + num_xfer: 0, + }; + let mut payload = CccPayload { + ccc: Some(ccc), + targets: Some(&mut tgts[..]), + }; + + hw.do_ccc(config, &mut payload) + .map_err(|_| I3cError::CccError(CccErrorKind::Invalid)) +} + +fn bytes_to_pid(bytes: &[u8]) -> u64 { + bytes + .iter() + .take(6) + .fold(0u64, |acc, &b| (acc << 8) | u64::from(b)) +} + +/// Get PID (Provisional ID) from a device +pub fn ccc_getpid<H>(hw: &mut H, config: &mut I3cConfig, dyn_addr: u8) -> Result<u64, I3cError> +where + H: HardwareInterface, +{ + let mut pid_buf = [0u8; 6]; + + let tgt = CccTargetPayload { + addr: dyn_addr, + rnw: true, + data: Some(&mut pid_buf[..]), + num_xfer: 0, + }; + let mut tgts = [tgt]; + + let ccc = Ccc { + id: I3C_CCC_GETPID, + data: None, + num_xfer: 0, + }; + let mut payload = CccPayload { + ccc: Some(ccc), + targets: Some(&mut tgts[..]), + }; + + hw.do_ccc(config, &mut payload) + .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))?; + + Ok(bytes_to_pid(&pid_buf)) +} + +/// Get status from a device +pub fn ccc_getstatus<H>( + hw: &mut H, + config: &mut I3cConfig, + da: u8, + fmt: GetStatusFormat, +) -> Result<GetStatusResp, I3cError> +where + H: HardwareInterface, +{ + let mut data_buf = [0u8; 2]; + let mut defbyte_buf = [0u8; 1]; + + let tgt = CccTargetPayload { + addr: da, + rnw: true, + data: Some(&mut data_buf[..]), + num_xfer: 0, + }; + + let mut ccc = Ccc { + id: I3C_CCC_GETSTATUS, + data: None, + num_xfer: 0, + }; + + let kind_opt = match fmt { + GetStatusFormat::Fmt1 => None, + GetStatusFormat::Fmt2(kind) => { + defbyte_buf[0] = kind.as_byte(); + ccc.data = Some(&mut defbyte_buf[..]); + Some(kind) + } + }; + + let mut targets_arr = [tgt]; + let mut payload = CccPayload { + ccc: Some(ccc), + targets: Some(&mut targets_arr[..]), + }; + + hw.do_ccc(config, &mut payload) + .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))?; + + let val = u16::from_be_bytes(data_buf); + + let resp = match kind_opt { + None => GetStatusResp::Fmt1 { status: val }, + Some(kind) => GetStatusResp::Fmt2 { kind, raw_u16: val }, + }; + Ok(resp) +} + +/// Get status (Format 1) from a device +pub fn ccc_getstatus_fmt1<H>(hw: &mut H, config: &mut I3cConfig, da: u8) -> Result<u16, I3cError> +where + H: HardwareInterface, +{ + match ccc_getstatus(hw, config, da, GetStatusFormat::Fmt1) { + Ok(GetStatusResp::Fmt1 { status }) => Ok(status), + _ => Err(I3cError::CccError(CccErrorKind::Invalid)), + } +} + +/// Reset dynamic address assignment for all devices (broadcast) +pub fn ccc_rstdaa_all<H>(hw: &mut H, config: &mut I3cConfig) -> Result<(), I3cError> +where + H: HardwareInterface, +{ + hw.do_ccc( + config, + &mut CccPayload { + ccc: Some(Ccc { + id: I3C_CCC_RSTDAA, + data: None, + num_xfer: 0, + }), + targets: None, + }, + ) + .map_err(|_| I3cError::CccError(CccErrorKind::Invalid)) +}
diff --git a/target/ast10x0/peripherals/i3c/config.rs b/target/ast10x0/peripherals/i3c/config.rs new file mode 100644 index 0000000..380f601 --- /dev/null +++ b/target/ast10x0/peripherals/i3c/config.rs
@@ -0,0 +1,666 @@ +// Licensed under the Apache-2.0 license + +//! I3C configuration types +//! +//! Configuration structures for I3C controller and devices. + +use core::marker::PhantomData; +use core::sync::atomic::AtomicPtr; +use heapless::Vec; + +use super::error::I3cError; +use super::types::{Completion, DevKind}; + +// ============================================================================= +// Target Configuration +// ============================================================================= + +/// Configuration for I3C target mode +pub struct I3cTargetConfig { + /// Target flags + pub flags: u8, + /// Dynamic address (assigned by controller) + pub addr: Option<u8>, + /// Mandatory Data Byte for IBI + pub mdb: u8, +} + +impl I3cTargetConfig { + /// Create a new target configuration + #[must_use] + pub const fn new(flags: u8, addr: Option<u8>, mdb: u8) -> Self { + Self { flags, addr, mdb } + } +} + +// ============================================================================= +// Address Book +// ============================================================================= + +/// Address allocation and tracking for I3C bus +pub struct AddrBook { + /// Addresses currently in use + pub in_use: [bool; 128], + /// Reserved addresses (not available for allocation) + pub reserved: [bool; 128], +} + +impl Default for AddrBook { + fn default() -> Self { + Self::new() + } +} + +impl AddrBook { + /// Create a new empty address book + #[must_use] + pub const fn new() -> Self { + Self { + in_use: [false; 128], + reserved: [false; 128], + } + } + + /// Check if an address is free (not in use and not reserved) + #[inline] + #[must_use] + pub fn is_free(&self, addr: u8) -> bool { + !self.in_use[addr as usize] && !self.reserved[addr as usize] + } + + /// Reserve default I3C addresses per specification + /// + /// Reserves addresses 0-7, 0x7E (broadcast), and addresses that + /// differ from 0x7E by a single bit. + pub fn reserve_defaults(&mut self) { + // Reserve addresses 0-7 + for a in 0usize..=7 { + self.reserved[a] = true; + } + // Reserve broadcast address + self.reserved[0x7E_usize] = true; + // Reserve addresses differing from 0x7E by single bit + for i in 0..=7 { + let alt = 0x7E ^ (1u8 << i); + if alt <= 0x7E { + self.reserved[alt as usize] = true; + } + } + } + + /// Allocate an address starting from the given value + /// + /// Returns `Some(addr)` if an address was found, `None` if exhausted. + pub fn alloc_from(&mut self, start: u8) -> Option<u8> { + let mut addr = start.max(8); + while addr < 0x7F { + if self.is_free(addr) { + return Some(addr); + } + addr += 1; + } + None + } + + /// Mark an address as used or free + #[inline] + pub fn mark_use(&mut self, addr: u8, used: bool) { + if addr != 0 { + self.in_use[addr as usize] = used; + } + } +} + +// ============================================================================= +// Device Entry +// ============================================================================= + +/// Entry for a device attached to the I3C bus +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct DeviceEntry { + /// Device type (I3C or I2C) + pub kind: DevKind, + /// Provisional ID (for I3C devices) + pub pid: Option<u64>, + /// Static address (for I2C or SETDASA) + pub static_addr: u8, + /// Current dynamic address + pub dyn_addr: u8, + /// Desired dynamic address + pub desired_da: u8, + /// Bus Characteristics Register + pub bcr: u8, + /// Device Characteristics Register + pub dcr: u8, + /// Maximum read speed + pub maxrd: u8, + /// Maximum write speed + pub maxwr: u8, + /// Maximum read length + pub mrl: u16, + /// Maximum write length + pub mwl: u16, + /// Maximum IBI payload size + pub max_ibi: u8, + /// IBI enabled flag + pub ibi_en: bool, + /// Position in DAT (Device Address Table) + pub pos: Option<u8>, +} + +impl DeviceEntry { + /// Create a new I3C device entry + #[must_use] + pub const fn new_i3c(pid: u64, desired_da: u8) -> Self { + Self { + kind: DevKind::I3c, + pid: Some(pid), + static_addr: 0, + dyn_addr: desired_da, + desired_da, + bcr: 0, + dcr: 0, + maxrd: 0, + maxwr: 0, + mrl: 0, + mwl: 0, + max_ibi: 0, + ibi_en: false, + pos: None, + } + } + + /// Create a new I2C device entry + #[must_use] + pub const fn new_i2c(static_addr: u8) -> Self { + Self { + kind: DevKind::I2c, + pid: None, + static_addr, + dyn_addr: static_addr, + desired_da: static_addr, + bcr: 0, + dcr: 0, + maxrd: 0, + maxwr: 0, + mrl: 0, + mwl: 0, + max_ibi: 0, + ibi_en: false, + pos: None, + } + } +} + +// ============================================================================= +// Attached Devices +// ============================================================================= + +/// Collection of devices attached to the I3C bus +pub struct Attached { + /// Device entries (max 8 devices) + pub devices: Vec<DeviceEntry, 8>, + /// Position-to-index mapping + pub by_pos: [Option<u8>; 8], +} + +impl Default for Attached { + fn default() -> Self { + Self::new() + } +} + +impl Attached { + /// Create a new empty attached devices collection + #[must_use] + pub const fn new() -> Self { + Self { + devices: Vec::new(), + by_pos: [None; 8], + } + } + + /// Attach a device to the bus + /// + /// Returns the device index on success. + pub fn attach(&mut self, dev: DeviceEntry) -> Result<usize, I3cError> { + let idx = self.devices.len(); + self.devices.push(dev).map_err(|_| I3cError::NoFreeSlot)?; + Ok(idx) + } + + /// Detach a device by its index + pub fn detach(&mut self, dev_idx: usize) { + if dev_idx >= self.devices.len() { + return; + } + + // Clear position mapping if device had one + if let Some(pos) = self.devices[dev_idx].pos { + if let Some(p) = self.by_pos.get_mut(pos as usize) { + *p = None; + } + } + + // Remove device and update position mappings + self.devices.remove(dev_idx); + for bp in &mut self.by_pos { + if let Some(idx) = bp { + let idx_usize = *idx as usize; + if idx_usize > dev_idx && idx_usize > 0 { + // SAFETY: Saturating subtract to prevent panic on underflow + *bp = Some(idx.saturating_sub(1)); + } + } + } + } + + /// Detach a device by its DAT position + pub fn detach_by_pos(&mut self, pos: usize) { + if let Some(Some(dev_idx)) = self.by_pos.get(pos) { + self.detach(*dev_idx as usize); + } + } + + /// Get the DAT position of a device by its index + #[must_use] + pub fn pos_of(&self, dev_idx: usize) -> Option<u8> { + let dev_idx_u8 = u8::try_from(dev_idx).ok()?; + self.by_pos + .iter() + .enumerate() + .find_map(|(pos, &v)| (v == Some(dev_idx_u8)).then_some(pos)) + .and_then(|p| u8::try_from(p).ok()) + } + + /// Find device index by dynamic address + #[must_use] + pub fn find_dev_idx_by_addr(&self, da: u8) -> Option<usize> { + self.devices.iter().position(|d| d.dyn_addr == da) + } + + /// Get DAT position by dynamic address + #[must_use] + pub fn pos_of_addr(&self, da: u8) -> Option<u8> { + let dev_idx = self.devices.iter().position(|d| d.dyn_addr == da)?; + self.pos_of(dev_idx) + } + + /// Get DAT position by PID + #[must_use] + pub fn pos_of_pid(&self, pid: u64) -> Option<u8> { + let dev_idx = self.devices.iter().position(|d| d.pid == Some(pid))?; + self.pos_of(dev_idx) + } + + /// Map a DAT position to a device index + #[inline] + pub fn map_pos(&mut self, pos: u8, idx: u8) -> bool { + if let Some(slot) = self.by_pos.get_mut(pos as usize) { + *slot = Some(idx); + return true; + } + false + } + + /// Unmap a DAT position + #[inline] + pub fn unmap_pos(&mut self, pos: u8) { + self.by_pos[pos as usize] = None; + } +} + +// ============================================================================= +// Common State +// ============================================================================= + +/// Common state shared across configurations (placeholder) +#[derive(Default)] +pub struct CommonState { + _phantom: PhantomData<()>, +} + +/// Common configuration (placeholder) +#[derive(Default)] +pub struct CommonCfg { + _phantom: PhantomData<()>, +} + +// ============================================================================= +// Reset Specification +// ============================================================================= + +/// Reset line specification +#[derive(Clone, Copy)] +pub struct ResetSpec { + /// Reset line ID + pub id: u32, + /// Whether reset is active high + pub active_high: bool, +} + +// ============================================================================= +// Main Configuration +// ============================================================================= + +/// Main I3C bus configuration +pub struct I3cConfig { + /// Common higher-level state + pub common: CommonState, + /// Target mode configuration (if operating as target) + pub target_config: Option<I3cTargetConfig>, + /// Address book for dynamic address management + pub addrbook: AddrBook, + /// Collection of attached devices + pub attached: Attached, + + // Concurrency + /// Pointer to current transfer in progress + pub curr_xfer: AtomicPtr<()>, + + // Clock configuration + /// Core clock frequency in Hz (injected by platform) + /// + /// If `None`, hardware implementation may auto-detect or use a default. + /// Providing this value decouples I3C from SCU/clock tree access. + pub core_clk_hz: Option<u32>, + + // Timing/PHY parameters (nanoseconds, computed from core_clk_hz) + /// Core clock period in ns (computed during init) + pub core_period: u32, + /// I2C SCL frequency in Hz + pub i2c_scl_hz: u32, + /// I3C SCL frequency in Hz + pub i3c_scl_hz: u32, + /// I3C push-pull SCL high period in ns + pub i3c_pp_scl_hi_period_ns: u32, + /// I3C push-pull SCL low period in ns + pub i3c_pp_scl_lo_period_ns: u32, + /// I3C open-drain SCL high period in ns + pub i3c_od_scl_hi_period_ns: u32, + /// I3C open-drain SCL low period in ns + pub i3c_od_scl_lo_period_ns: u32, + /// SDA TX hold time in ns + pub sda_tx_hold_ns: u32, + /// Whether this controller is secondary + pub is_secondary: bool, + + // Tables/indices + /// Maximum number of devices + pub maxdevs: u16, + /// Bitmap of free DAT positions + pub free_pos: u32, + /// Bitmap of devices needing dynamic address + pub need_da: u32, + /// Address array for DAT + pub addrs: [u8; 8], + /// DCR value + pub dcr: u32, + + // Target-mode data + /// Whether SIR (Slave Interrupt Request) is allowed by software + pub sir_allowed_by_sw: bool, + /// Completion for target IBI + pub target_ibi_done: Completion, + /// Completion for target data transfer + pub target_data_done: Completion, +} + +impl Default for I3cConfig { + fn default() -> Self { + Self::new() + } +} + +impl I3cConfig { + /// Create a new configuration with default values + #[must_use] + pub fn new() -> Self { + Self { + common: CommonState::default(), + target_config: None, + addrbook: AddrBook::new(), + attached: Attached::new(), + curr_xfer: AtomicPtr::new(core::ptr::null_mut()), + core_clk_hz: None, + core_period: 0, + i2c_scl_hz: 0, + i3c_scl_hz: 0, + i3c_pp_scl_hi_period_ns: 0, + i3c_pp_scl_lo_period_ns: 0, + i3c_od_scl_hi_period_ns: 0, + i3c_od_scl_lo_period_ns: 0, + sda_tx_hold_ns: 0, + is_secondary: false, + maxdevs: 8, + free_pos: 0, + need_da: 0, + addrs: [0; 8], + dcr: 0, + sir_allowed_by_sw: false, + target_ibi_done: Completion::new(), + target_data_done: Completion::new(), + } + } + + /// Initialize runtime fields (address book and attached devices) + pub fn init_runtime_fields(&mut self) { + self.addrbook = AddrBook::new(); + self.addrbook.reserve_defaults(); + self.attached = Attached::new(); + } + + /// Pick an initial dynamic address for a device + /// + /// Tries `desired` first, then `static_addr`, then allocates from pool. + pub fn pick_initial_da(&mut self, static_addr: u8, desired: u8) -> Option<u8> { + if desired != 0 && self.addrbook.is_free(desired) { + self.addrbook.mark_use(desired, true); + return Some(desired); + } + if static_addr != 0 && self.addrbook.is_free(static_addr) { + self.addrbook.mark_use(static_addr, true); + return Some(static_addr); + } + self.addrbook.alloc_from(8) + } + + /// Reassign a device's dynamic address + pub fn reassign_da(&mut self, from: u8, to: u8) -> Result<(), I3cError> { + if from == to { + return Ok(()); + } + if !self.addrbook.is_free(to) { + return Err(I3cError::AddrInUse); + } + + self.addrbook.mark_use(from, false); + self.addrbook.mark_use(to, true); + + if let Some((i, mut e)) = self + .attached + .devices + .iter() + .enumerate() + .find_map(|(i, d)| (d.dyn_addr == from).then_some((i, *d))) + { + e.dyn_addr = to; + self.attached.devices[i] = e; + Ok(()) + } else { + Err(I3cError::DevNotFound) + } + } +} + +// ============================================================================= +// Builder Pattern for I3cConfig +// ============================================================================= + +impl I3cConfig { + /// Set core clock frequency in Hz + /// + /// This decouples the I3C driver from SCU/clock tree access. + /// The platform layer should provide the actual clock rate. + /// + /// # I3C Timing Requirements (MIPI I3C Spec v1.1) + /// + /// | Mode | Min Clock | Typical | Notes | + /// |------|-----------|---------|-------| + /// | SDR | 12.5 `MHz` | 100-200 `MHz` | For 12.5 `MHz` SCL | + /// | HDR | 25 `MHz` | 100-200 `MHz` | For 25 `MHz` SCL | + /// + /// # Example + /// + /// ```rust,ignore + /// let config = I3cConfig::new() + /// .core_clk_hz(200_000_000) // 200 MHz from platform + /// .i3c_scl_hz(12_500_000); // 12.5 MHz SCL + /// ``` + #[must_use] + pub fn core_clk_hz(mut self, hz: u32) -> Self { + self.core_clk_hz = Some(hz); + self + } + + /// Set I2C SCL frequency + #[must_use] + pub fn i2c_scl_hz(mut self, hz: u32) -> Self { + self.i2c_scl_hz = hz; + self + } + + /// Set I3C SCL frequency + #[must_use] + pub fn i3c_scl_hz(mut self, hz: u32) -> Self { + self.i3c_scl_hz = hz; + self + } + + /// Set as secondary controller + #[must_use] + pub fn secondary(mut self, is_secondary: bool) -> Self { + self.is_secondary = is_secondary; + self + } + + /// Set DCR (Device Characteristics Register) + #[must_use] + pub fn dcr(mut self, dcr: u8) -> Self { + self.dcr = u32::from(dcr); + self + } + + /// Set target configuration + #[must_use] + pub fn target_config(mut self, config: I3cTargetConfig) -> Self { + self.target_config = Some(config); + self + } + + /// Set I3C Push-Pull SCL high period in ns + #[must_use] + pub fn i3c_pp_scl_hi_period_ns(mut self, ns: u32) -> Self { + self.i3c_pp_scl_hi_period_ns = ns; + self + } + + /// Set I3C Push-Pull SCL low period in ns + #[must_use] + pub fn i3c_pp_scl_lo_period_ns(mut self, ns: u32) -> Self { + self.i3c_pp_scl_lo_period_ns = ns; + self + } + + /// Set I3C Open-Drain SCL high period in ns + #[must_use] + pub fn i3c_od_scl_hi_period_ns(mut self, ns: u32) -> Self { + self.i3c_od_scl_hi_period_ns = ns; + self + } + + /// Set I3C Open-Drain SCL low period in ns + #[must_use] + pub fn i3c_od_scl_lo_period_ns(mut self, ns: u32) -> Self { + self.i3c_od_scl_lo_period_ns = ns; + self + } + + /// Set SDA TX hold time in ns + #[must_use] + pub fn sda_tx_hold_ns(mut self, ns: u32) -> Self { + self.sda_tx_hold_ns = ns; + self + } +} + +// ============================================================================= +// Clock Validation +// ============================================================================= + +/// Minimum core clock for I3C SDR mode (Hz) +/// Required to achieve 12.5 `MHz` SCL with proper timing margins +pub const I3C_MIN_CORE_CLK_SDR: u32 = 12_500_000; + +/// Minimum core clock for I3C HDR mode (Hz) +/// Required to achieve 25 `MHz` SCL with proper timing margins +pub const I3C_MIN_CORE_CLK_HDR: u32 = 25_000_000; + +/// Maximum supported core clock (Hz) +pub const I3C_MAX_CORE_CLK: u32 = 400_000_000; + +impl I3cConfig { + /// Validate clock configuration + /// + /// Checks that the configured clock frequencies are achievable per + /// MIPI I3C specification timing requirements. + /// + /// # Timing Requirements (MIPI I3C Basic Spec v1.1.1) + /// + /// | Parameter | SDR Mode | HDR-DDR Mode | Unit | + /// |-----------|----------|--------------|------| + /// | fSCL max | 12.5 | 12.5 | `MHz` | + /// | tLOW min | 32 | 32 | ns | + /// | tHIGH min | 32 | 32 | ns | + /// + /// For reliable operation, core clock should be at least 4x the SCL frequency + /// to allow proper timing register resolution. + /// + /// # Returns + /// + /// - `Ok(())` if configuration is valid + /// - `Err(I3cError::InvalidParam)` if configuration is invalid + /// + /// # Example + /// + /// ```rust,ignore + /// let config = I3cConfig::new() + /// .core_clk_hz(200_000_000) + /// .i3c_scl_hz(12_500_000); + /// + /// config.validate_clock()?; + /// ``` + pub fn validate_clock(&self) -> Result<(), I3cError> { + if let Some(core_hz) = self.core_clk_hz { + // Check core clock range + if core_hz < I3C_MIN_CORE_CLK_SDR { + return Err(I3cError::InvalidParam); + } + if core_hz > I3C_MAX_CORE_CLK { + return Err(I3cError::InvalidParam); + } + + // Check I3C SCL achievability (need ~4x core clock for timing resolution) + if self.i3c_scl_hz > 0 && core_hz < self.i3c_scl_hz * 4 { + return Err(I3cError::InvalidParam); + } + + // Check I2C SCL achievability + if self.i2c_scl_hz > 0 && core_hz < self.i2c_scl_hz * 4 { + return Err(I3cError::InvalidParam); + } + } + + Ok(()) + } +}
diff --git a/target/ast10x0/peripherals/i3c/constants.rs b/target/ast10x0/peripherals/i3c/constants.rs new file mode 100644 index 0000000..76d2905 --- /dev/null +++ b/target/ast10x0/peripherals/i3c/constants.rs
@@ -0,0 +1,316 @@ +// Licensed under the Apache-2.0 license + +//! I3C hardware constants and register definitions +//! +//! # Register Map +//! | Offset | Register | Description | +//! |--------|-----------------------|--------------------------------| +//! | 0x0C | COMMAND_QUEUE_PORT | Command queue port | +//! | 0x10 | RESPONSE_QUEUE_PORT | Response queue port | +//! | 0x18 | IBI_QUEUE_STATUS | IBI queue status | +//! | 0x3C | INTR_STATUS | Interrupt status | +//! | 0x40 | INTR_STATUS_EN | Interrupt status enable | +//! | 0x44 | INTR_SIGNAL_EN | Interrupt signal enable | + +// ============================================================================= +// Message Flags +// ============================================================================= + +/// I3C message write flag +pub const I3C_MSG_WRITE: u8 = 0x0; +/// I3C message read flag +pub const I3C_MSG_READ: u8 = 0x1; +/// I3C message stop flag +pub const I3C_MSG_STOP: u8 = 0x2; + +// ============================================================================= +// I2C Timing Constants (nanoseconds) +// ============================================================================= + +// Standard mode (100 kHz) +pub const I3C_BUS_I2C_STD_TLOW_MIN_NS: u32 = 4_700; +pub const I3C_BUS_I2C_STD_THIGH_MIN_NS: u32 = 4_000; +pub const I3C_BUS_I2C_STD_TR_MAX_NS: u32 = 1_000; +pub const I3C_BUS_I2C_STD_TF_MAX_NS: u32 = 300; + +// Fast mode (400 kHz) +pub const I3C_BUS_I2C_FM_TLOW_MIN_NS: u32 = 1_300; +pub const I3C_BUS_I2C_FM_THIGH_MIN_NS: u32 = 600; +pub const I3C_BUS_I2C_FM_TR_MAX_NS: u32 = 300; +pub const I3C_BUS_I2C_FM_TF_MAX_NS: u32 = 300; + +// Fast mode plus (1 MHz) +pub const I3C_BUS_I2C_FMP_TLOW_MIN_NS: u32 = 500; +pub const I3C_BUS_I2C_FMP_THIGH_MIN_NS: u32 = 260; +pub const I3C_BUS_I2C_FMP_TR_MAX_NS: u32 = 120; +pub const I3C_BUS_I2C_FMP_TF_MAX_NS: u32 = 120; + +// I3C timing +pub const I3C_BUS_THIGH_MAX_NS: u32 = 41; + +/// Nanoseconds per second +pub const NSEC_PER_SEC: u32 = 1_000_000_000; + +// ============================================================================= +// SDA TX Hold Configuration +// ============================================================================= + +pub const SDA_TX_HOLD_MIN: u32 = 0b001; +pub const SDA_TX_HOLD_MAX: u32 = 0b111; +pub const SDA_TX_HOLD_MASK: u32 = 0x0007_0000; // bits 18:16 + +// ============================================================================= +// Slave Configuration +// ============================================================================= + +pub const SLV_DCR_MASK: u32 = 0x0000_ff00; +pub const SLV_EVENT_CTRL: u32 = 0x38; +pub const SLV_EVENT_CTRL_MWL_UPD: u32 = bit(7); +pub const SLV_EVENT_CTRL_MRL_UPD: u32 = bit(6); +pub const SLV_EVENT_CTRL_HJ_REQ: u32 = bit(3); +pub const SLV_EVENT_CTRL_SIR_EN: u32 = bit(0); + +// ============================================================================= +// I3C Global Register Bits +// ============================================================================= + +pub const I3CG_REG1_SCL_IN_SW_MODE_VAL: u32 = bit(23); +pub const I3CG_REG1_SDA_IN_SW_MODE_VAL: u32 = bit(27); +pub const I3CG_REG1_SCL_IN_SW_MODE_EN: u32 = bit(28); +pub const I3CG_REG1_SDA_IN_SW_MODE_EN: u32 = bit(29); + +// ============================================================================= +// Transfer Status +// ============================================================================= + +pub const CM_TFR_STS_MASTER_HALT: u8 = 0xf; +pub const CM_TFR_STS_TARGET_HALT: u8 = 0x6; + +// ============================================================================= +// Command Queue Port (0x0C) +// ============================================================================= + +pub const COMMAND_QUEUE_PORT: u32 = 0x0c; + +// Command port bit flags +pub const COMMAND_PORT_PEC: u32 = bit(31); +pub const COMMAND_PORT_TOC: u32 = bit(30); +pub const COMMAND_PORT_READ_TRANSFER: u32 = bit(28); +pub const COMMAND_PORT_SDAP: u32 = bit(27); +pub const COMMAND_PORT_ROC: u32 = bit(26); +pub const COMMAND_PORT_DBP: u32 = bit(25); +pub const COMMAND_PORT_CP: u32 = bit(15); + +// Command port field masks +pub const COMMAND_PORT_SPEED: u32 = bits(23, 21); +pub const COMMAND_PORT_DEV_INDEX: u32 = bits(20, 16); +pub const COMMAND_PORT_CMD: u32 = bits(14, 7); +pub const COMMAND_PORT_TID: u32 = bits(6, 3); +pub const COMMAND_PORT_ARG_DB: u32 = bits(15, 8); +pub const COMMAND_PORT_ARG_DATA_LEN: u32 = bits(31, 16); +pub const COMMAND_PORT_ATTR: u32 = bits(2, 0); +pub const COMMAND_PORT_DEV_COUNT: u32 = bits(25, 21); + +// ============================================================================= +// Transaction IDs +// ============================================================================= + +pub const TID_TARGET_IBI: u32 = 0x1; +pub const TID_TARGET_RD_DATA: u32 = 0x2; +pub const TID_TARGET_MASTER_WR: u32 = 0x8; +pub const TID_TARGET_MASTER_DEF: u32 = 0xf; + +// ============================================================================= +// Command Attributes +// ============================================================================= + +pub const COMMAND_ATTR_XFER_CMD: u32 = 0; +pub const COMMAND_ATTR_XFER_ARG: u32 = 1; +pub const COMMAND_ATTR_SHORT_ARG: u32 = 2; +pub const COMMAND_ATTR_ADDR_ASSGN_CMD: u32 = 3; +pub const COMMAND_ATTR_SLAVE_DATA_CMD: u32 = 0; + +// ============================================================================= +// Device Address Table +// ============================================================================= + +pub const DEV_ADDR_TABLE_LEGACY_I2C_DEV: u32 = bit(31); +pub const DEV_ADDR_TABLE_DYNAMIC_ADDR: u32 = bits(23, 16); +pub const DEV_ADDR_TABLE_MR_REJECT: u32 = bit(14); +pub const DEV_ADDR_TABLE_SIR_REJECT: u32 = bit(13); +pub const DEV_ADDR_TABLE_IBI_MDB: u32 = bit(12); +pub const DEV_ADDR_TABLE_IBI_PEC: u32 = bit(11); +pub const DEV_ADDR_TABLE_STATIC_ADDR: u32 = bits(6, 0); + +// ============================================================================= +// IBI Queue Status (0x18) +// ============================================================================= + +pub const IBI_QUEUE_STATUS: u32 = 0x18; +pub const IBIQ_STATUS_IBI_ID: u32 = bits(15, 8); +pub const IBIQ_STATUS_IBI_ID_SHIFT: u32 = 8; +pub const IBIQ_STATUS_IBI_DATA_LEN: u32 = bits(7, 0); +pub const IBIQ_STATUS_IBI_DATA_LEN_SHIFT: u32 = 0; + +// ============================================================================= +// Reset Control +// ============================================================================= + +pub const RESET_CTRL_IBI_QUEUE: u32 = bit(5); +pub const RESET_CTRL_RX_FIFO: u32 = bit(4); +pub const RESET_CTRL_TX_FIFO: u32 = bit(3); +pub const RESET_CTRL_RESP_QUEUE: u32 = bit(2); +pub const RESET_CTRL_CMD_QUEUE: u32 = bit(1); +pub const RESET_CTRL_SOFT: u32 = bit(0); + +pub const RESET_CTRL_ALL: u32 = RESET_CTRL_IBI_QUEUE + | RESET_CTRL_RX_FIFO + | RESET_CTRL_TX_FIFO + | RESET_CTRL_RESP_QUEUE + | RESET_CTRL_CMD_QUEUE + | RESET_CTRL_SOFT; + +pub const RESET_CTRL_QUEUES: u32 = RESET_CTRL_IBI_QUEUE + | RESET_CTRL_RX_FIFO + | RESET_CTRL_TX_FIFO + | RESET_CTRL_RESP_QUEUE + | RESET_CTRL_CMD_QUEUE; + +pub const RESET_CTRL_XFER_QUEUES: u32 = + RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO | RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE; + +// ============================================================================= +// Response Queue Port (0x10) +// ============================================================================= + +pub const RESPONSE_QUEUE_PORT: u32 = 0x10; +pub const RESPONSE_PORT_ERR_STATUS_SHIFT: u32 = 28; +pub const RESPONSE_PORT_ERR_STATUS_MASK: u32 = genmask(31, 28); +pub const RESPONSE_PORT_TID_SHIFT: u32 = 24; +pub const RESPONSE_PORT_TID_MASK: u32 = genmask(27, 24); +pub const RESPONSE_PORT_DATA_LEN_SHIFT: u32 = 0; +pub const RESPONSE_PORT_DATA_LEN_MASK: u32 = genmask(15, 0); + +// Response error codes +pub const RESPONSE_NO_ERROR: u32 = 0; +pub const RESPONSE_ERROR_CRC: u32 = 1; +pub const RESPONSE_ERROR_PARITY: u32 = 2; +pub const RESPONSE_ERROR_FRAME: u32 = 3; +pub const RESPONSE_ERROR_IBA_NACK: u32 = 4; +pub const RESPONSE_ERROR_ADDRESS_NACK: u32 = 5; +pub const RESPONSE_ERROR_OVER_UNDER_FLOW: u32 = 6; +pub const RESPONSE_ERROR_TRANSF_ABORT: u32 = 8; +pub const RESPONSE_ERROR_I2C_W_NACK_ERR: u32 = 9; +pub const RESPONSE_ERROR_EARLY_TERMINATE: u32 = 10; +pub const RESPONSE_ERROR_PEC_ERR: u32 = 12; + +// ============================================================================= +// Interrupt Registers (0x3C - 0x48) +// ============================================================================= + +pub const INTR_STATUS: u32 = 0x3c; +pub const INTR_STATUS_EN: u32 = 0x40; +pub const INTR_SIGNAL_EN: u32 = 0x44; +pub const INTR_FORCE: u32 = 0x48; + +// Interrupt status bits +pub const INTR_BUSOWNER_UPDATE_STAT: u32 = bit(13); +pub const INTR_IBI_UPDATED_STAT: u32 = bit(12); +pub const INTR_READ_REQ_RECV_STAT: u32 = bit(11); +pub const INTR_DEFSLV_STAT: u32 = bit(10); +pub const INTR_TRANSFER_ERR_STAT: u32 = bit(9); +pub const INTR_DYN_ADDR_ASSGN_STAT: u32 = bit(8); +pub const INTR_CCC_UPDATED_STAT: u32 = bit(6); +pub const INTR_TRANSFER_ABORT_STAT: u32 = bit(5); +pub const INTR_RESP_READY_STAT: u32 = bit(4); +pub const INTR_CMD_QUEUE_READY_STAT: u32 = bit(3); +pub const INTR_IBI_THLD_STAT: u32 = bit(2); +pub const INTR_RX_THLD_STAT: u32 = bit(1); +pub const INTR_TX_THLD_STAT: u32 = bit(0); + +// BCR bits +pub const I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE: u32 = bit(2); + +// ============================================================================= +// Address Constants +// ============================================================================= + +/// I3C broadcast address +pub const I3C_BROADCAST_ADDR: u8 = 0x7E; +/// Maximum I3C address +pub const I3C_MAX_ADDR: u8 = 0x7F; + +// ============================================================================= +// Hardware Limits +// ============================================================================= + +/// Maximum number of commands in a single transfer +pub const MAX_CMDS: usize = 32; +/// Maximum number of I3C buses supported +pub const MAX_BUSES: usize = 4; +/// Maximum devices per bus +pub const MAX_DEVICES_PER_BUS: usize = 8; + +// ============================================================================= +// CCC (Common Command Code) Constants +// ============================================================================= + +pub const I3C_CCC_RSTDAA: u8 = 0x06; +pub const I3C_CCC_ENTDAA: u8 = 0x07; +pub const I3C_CCC_SETHID: u8 = 0x61; +pub const I3C_CCC_DEVCTRL: u8 = 0x62; +pub const I3C_CCC_SETDASA: u8 = 0x87; +pub const I3C_CCC_SETNEWDA: u8 = 0x88; +pub const I3C_CCC_GETPID: u8 = 0x8D; +pub const I3C_CCC_GETBCR: u8 = 0x8E; +pub const I3C_CCC_GETSTATUS: u8 = 0x90; + +// CCC event bits +pub const I3C_CCC_EVT_INTR: u8 = 1 << 0; +pub const I3C_CCC_EVT_CR: u8 = 1 << 1; +pub const I3C_CCC_EVT_HJ: u8 = 1 << 3; +pub const I3C_CCC_EVT_ALL: u8 = I3C_CCC_EVT_INTR | I3C_CCC_EVT_CR | I3C_CCC_EVT_HJ; + +// ============================================================================= +// Helper Functions +// ============================================================================= + +/// Create a single bit mask at position `n` +#[inline] +#[must_use] +pub const fn bit(n: u32) -> u32 { + 1 << n +} + +/// Create a bit mask from bit `l` to bit `h` (inclusive) +#[inline] +#[must_use] +pub const fn bits(h: u32, l: u32) -> u32 { + ((1u32 << (h - l + 1)) - 1) << l +} + +/// Prepare a value for a masked field +#[inline] +#[must_use] +pub const fn field_prep(mask: u32, val: u32) -> u32 { + (val << mask.trailing_zeros()) & mask +} + +/// Extract a value from a masked field +#[inline] +#[must_use] +pub const fn field_get(val: u32, mask: u32, shift: u32) -> u32 { + (val & mask) >> shift +} + +/// Generate a mask from MSB to LSB +#[inline] +#[must_use] +pub const fn genmask(msb: u32, lsb: u32) -> u32 { + let width = msb - lsb + 1; + if width >= 32 { + u32::MAX + } else { + ((1u32 << width) - 1) << lsb + } +}
diff --git a/target/ast10x0/peripherals/i3c/controller.rs b/target/ast10x0/peripherals/i3c/controller.rs new file mode 100644 index 0000000..3ffbc60 --- /dev/null +++ b/target/ast10x0/peripherals/i3c/controller.rs
@@ -0,0 +1,302 @@ +// Licensed under the Apache-2.0 license + +//! I3C Controller +//! +//! Main hardware abstraction for I3C bus controller. +//! +//! # Construction Patterns +//! +//! Two construction paths are provided: +//! +//! | Constructor | Purpose | Performance | Use Case | +//! |-------------|---------|-------------|----------| +//! | [`new()`](I3cController::new) | Full hardware init | Slower (register writes) | First-time setup, reset | +//! | [`from_initialized()`](I3cController::from_initialized) | Wrap pre-configured HW | Fast (no I/O) | Per-operation, hot path | +//! +//! # Example +//! +//! ```rust,ignore +//! // === BOOT/INIT CODE (runs once) === +//! // Platform init first (clocks, resets - not part of i3c_core) +//! scu.enable_i3c_clock(bus); +//! scu.deassert_i3c_reset(bus); +//! +//! // Full hardware init +//! let mut ctrl = I3cController::new(hw, config)?; +//! +//! // === HOT PATH (hardware already configured) === +//! let ctrl = I3cController::from_initialized(hw, config); +//! ctrl.do_transfer(...); +//! ``` + +use super::config::{DeviceEntry, I3cConfig}; +use super::constants::I3C_BROADCAST_ADDR; +use super::error::I3cError; +use super::hardware::HardwareInterface; +use super::types::DevKind; + +/// I3C controller wrapping hardware interface +pub struct I3cController<H: HardwareInterface> { + /// Hardware interface implementation + pub hw: H, + /// Bus configuration + pub config: I3cConfig, +} + +impl<H: HardwareInterface> I3cController<H> { + // ========================================================================= + // Construction + // ========================================================================= + + /// Create and initialize I3C controller (full init) + /// + /// Performs complete hardware initialization: + /// - Registers IRQ handler + /// - Enables interrupts + /// - Initializes hardware registers + /// + /// Use [`from_initialized`](Self::from_initialized) if hardware is already + /// configured. + /// + /// # Preconditions + /// + /// Platform initialization must be done before calling this: + /// - Clocks enabled (via SCU) + /// - Reset deasserted (via SCU) + /// - Pin mux configured + /// + /// # Returns + /// + /// Initialized controller ready for use. + pub fn new(hw: H, config: I3cConfig) -> Self { + Self::from_initialized(hw, config) + } + + /// Wrap pre-initialized hardware (lightweight, no I/O) + /// + /// Creates instance without touching hardware registers. + /// + /// # When to Use + /// + /// - Hardware was initialized at boot before kernel/RTOS start + /// - Creating temporary instances for single operations + /// - Avoiding redundant re-initialization overhead + /// - Hot path where performance matters + /// + /// # Preconditions + /// + /// Caller must ensure hardware is already configured: + /// - [`new()`](Self::new) was called previously, OR + /// - Hardware initialized by bootloader/firmware + /// + /// # Performance + /// + /// No register writes - significantly faster than `new()`. + #[must_use] + pub fn from_initialized(hw: H, config: I3cConfig) -> Self { + Self { hw, config } + } + + /// Initialize/reinitialize hardware registers + /// + /// Registers the IRQ handler and configures the hardware. + /// Called automatically by [`new()`](Self::new), but can be called + /// explicitly to reinitialize after error recovery. + /// + /// # Safety Invariant + /// + /// After calling this method, the caller must ensure that no `&mut self` + /// methods are called while interrupts are enabled, as the IRQ handler + /// also takes `&mut self`. Violation causes undefined behavior. + pub fn init_hardware(&mut self) { + let ctx = core::ptr::from_mut::<Self>(self) as usize; + let bus = self.hw.bus_num() as usize; + super::hardware::register_i3c_irq_handler(bus, Self::irq_trampoline, ctx); + + // IMPORTANT: init() must complete before enable_irq() to prevent + // IRQ firing on partially-initialized hardware + self.hw.init(&mut self.config); + + // Memory barrier to ensure init writes are visible before IRQ enable + cortex_m::asm::dmb(); + + self.hw.enable_irq(); + } + + /// IRQ trampoline function + fn irq_trampoline(ctx: usize) { + // SAFETY: `ctx` was created from `&mut Self` in `init_hardware()`. + // Aliasing safety relies on caller not holding `&mut self` when IRQs enabled. + let ctrl: &mut Self = unsafe { &mut *(ctx as *mut Self) }; + ctrl.hw.i3c_aspeed_isr(&mut ctrl.config); + } + + // ========================================================================= + // Device Management + // ========================================================================= + + /// Attach an I3C device to the bus + /// + /// # Arguments + /// * `pid` - Provisional ID of the device + /// * `desired_da` - Desired dynamic address + /// * `slot` - DAT slot to use + pub fn attach_i3c_dev(&mut self, pid: u64, desired_da: u8, slot: u8) -> Result<(), I3cError> { + if desired_da == 0 || desired_da >= I3C_BROADCAST_ADDR { + return Err(I3cError::InvalidArgs); + } + + let dev = DeviceEntry { + kind: DevKind::I3c, + pid: Some(pid), + static_addr: 0, + dyn_addr: desired_da, + desired_da, + bcr: 0, + dcr: 0, + maxrd: 0, + maxwr: 0, + mrl: 0, + mwl: 0, + max_ibi: 0, + ibi_en: false, + pos: Some(slot), + }; + + let idx = self + .config + .attached + .attach(dev) + .map_err(|_| I3cError::AddrInUse)?; + self.config + .attached + .map_pos(slot, u8::try_from(idx).map_err(|_| I3cError::InvalidArgs)?); + self.config.addrbook.mark_use(desired_da, true); + + self.hw + .attach_i3c_dev(slot.into(), desired_da) + .map_err(|_| I3cError::AddrInUse) + } + + /// Detach an I3C device by DAT position + pub fn detach_i3c_dev(&mut self, pos: usize) { + self.config.attached.detach_by_pos(pos); + self.hw.detach_i3c_dev(pos); + } + + /// Detach an I3C device by device index + pub fn detach_i3c_dev_by_idx(&mut self, dev_idx: usize) { + let dev = &self.config.attached.devices[dev_idx]; + + if dev.dyn_addr != 0 { + self.config.addrbook.mark_use(dev.dyn_addr, false); + } + + if let Some(pos) = dev.pos { + self.hw.detach_i3c_dev(pos.into()); + } + + self.config.attached.detach(dev_idx); + } + + // ========================================================================= + // Bus Recovery + // ========================================================================= + + /// Recover the I3C bus from a stuck state + /// + /// Performs bus recovery sequence: + /// 1. Enter software (bit-bang) mode + /// 2. Toggle SCL to clear stuck slaves + /// 3. Generate STOP condition + /// 4. Exit software mode + /// + /// # Arguments + /// * `scl_toggles` - Number of SCL toggles (typically 9 to clear a stuck byte) + /// + /// # When to Use + /// + /// - Bus appears hung (transfers timing out) + /// - Device not responding after partial transfer + /// - After detecting SDA stuck low + /// + /// # Example + /// + /// ```rust,ignore + /// // Standard recovery with 9 SCL clocks + /// ctrl.recover_bus(9); + /// + /// // More aggressive recovery + /// ctrl.recover_bus(18); + /// ``` + pub fn recover_bus(&mut self, scl_toggles: u32) { + self.hw.enter_sw_mode(); + self.hw.i3c_toggle_scl_in(scl_toggles); + self.hw.gen_internal_stop(); + self.hw.exit_sw_mode(); + } + + /// Perform full bus recovery with controller reset + /// + /// More aggressive recovery that also resets controller FIFOs: + /// 1. Bus recovery (SCL toggle + STOP) + /// 2. Reset TX/RX FIFOs + /// 3. Reset command queue + /// + /// # Arguments + /// * `reset_mask` - Controller components to reset (use `RESET_CTRL_*` constants) + /// + /// # Example + /// + /// ```rust,ignore + /// use aspeed_rust::i3c_core::{RESET_CTRL_RX_FIFO, RESET_CTRL_TX_FIFO, RESET_CTRL_CMD_QUEUE}; + /// + /// // Full recovery with FIFO reset + /// let reset = RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO | RESET_CTRL_CMD_QUEUE; + /// ctrl.recover_bus_full(reset); + /// ``` + pub fn recover_bus_full(&mut self, reset_mask: u32) { + self.recover_bus(8); + self.hw.reset_ctrl(reset_mask); + } + + // Accessors + // ========================================================================= + + /// Get a reference to the hardware interface + #[inline] + pub fn hw(&self) -> &H { + &self.hw + } + + /// Get a mutable reference to the hardware interface + #[inline] + pub fn hw_mut(&mut self) -> &mut H { + &mut self.hw + } + + /// Get a reference to the configuration + #[inline] + pub fn config(&self) -> &I3cConfig { + &self.config + } + + /// Get a mutable reference to the configuration + #[inline] + pub fn config_mut(&mut self) -> &mut I3cConfig { + &mut self.config + } +} + +// ============================================================================= +// Conversions +// ============================================================================= + +impl<H: HardwareInterface> From<(H, I3cConfig)> for I3cController<H> { + /// Lightweight conversion (no hardware I/O) + /// + /// Equivalent to [`from_initialized`](I3cController::from_initialized). + fn from((hw, config): (H, I3cConfig)) -> Self { + Self::from_initialized(hw, config) + } +}
diff --git a/target/ast10x0/peripherals/i3c/error.rs b/target/ast10x0/peripherals/i3c/error.rs new file mode 100644 index 0000000..8fe681c --- /dev/null +++ b/target/ast10x0/peripherals/i3c/error.rs
@@ -0,0 +1,122 @@ +// Licensed under the Apache-2.0 license + +//! I3C error types +//! +//! Consolidated error types for the I3C subsystem. + +use core::fmt; + +/// Primary error type for I3C operations +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum I3cError { + /// No DAT (Device Address Table) position available + NoDatPos, + /// No messages provided for transfer + NoMsgs, + /// Too many messages for single transfer + TooManyMsgs, + /// Invalid arguments provided + InvalidArgs, + /// Operation timed out + Timeout, + /// Device not found + NoSuchDev, + /// Access denied or not permitted + Access, + /// Generic I/O error + IoError, + /// Invalid operation or state + Invalid, + /// Address already in use + AddrInUse, + /// Address space exhausted + AddrExhausted, + /// No free slot available + NoFreeSlot, + /// Device not found in attached list + DevNotFound, + /// Device already attached + DevAlreadyAttached, + /// Invalid parameter + InvalidParam, + /// CCC (Common Command Code) error + CccError(CccErrorKind), + /// Other unspecified error + Other, +} + +impl fmt::Display for I3cError { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::NoDatPos => write!(f, "no DAT position available"), + Self::NoMsgs => write!(f, "no messages provided"), + Self::TooManyMsgs => write!(f, "too many messages"), + Self::InvalidArgs => write!(f, "invalid arguments"), + Self::Timeout => write!(f, "operation timed out"), + Self::NoSuchDev | Self::DevNotFound => write!(f, "device not found"), + Self::Access => write!(f, "access denied"), + Self::IoError => write!(f, "I/O error"), + Self::Invalid => write!(f, "invalid operation"), + Self::AddrInUse => write!(f, "address in use"), + Self::AddrExhausted => write!(f, "address space exhausted"), + Self::NoFreeSlot => write!(f, "no free slot"), + Self::DevAlreadyAttached => write!(f, "device already attached"), + Self::InvalidParam => write!(f, "invalid parameter"), + Self::CccError(kind) => write!(f, "CCC error: {kind:?}"), + Self::Other => write!(f, "other error"), + } + } +} + +/// CCC-specific error kinds +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub enum CccErrorKind { + /// Invalid parameter for CCC + InvalidParam, + /// Target not found + NotFound, + /// No free slot for CCC operation + NoFreeSlot, + /// Invalid CCC response or operation + Invalid, +} + +/// Convenience Result type for I3C operations +pub type Result<T> = core::result::Result<T, I3cError>; + +// Conversion from legacy error types for backwards compatibility + +impl From<CccErrorKind> for I3cError { + #[inline] + fn from(kind: CccErrorKind) -> Self { + Self::CccError(kind) + } +} + +/// Implement embedded-hal I2C error trait for interoperability +impl embedded_hal::i2c::Error for I3cError { + fn kind(&self) -> embedded_hal::i2c::ErrorKind { + match self { + Self::Timeout => embedded_hal::i2c::ErrorKind::NoAcknowledge( + embedded_hal::i2c::NoAcknowledgeSource::Unknown, + ), + Self::NoSuchDev | Self::DevNotFound => embedded_hal::i2c::ErrorKind::NoAcknowledge( + embedded_hal::i2c::NoAcknowledgeSource::Address, + ), + Self::IoError | Self::Access => embedded_hal::i2c::ErrorKind::Bus, + _ => embedded_hal::i2c::ErrorKind::Other, + } + } +} + +/// Implement proposed I3C master error trait +impl proposed_traits::i3c_master::Error for I3cError { + #[inline] + fn kind(&self) -> proposed_traits::i3c_master::ErrorKind { + match self { + Self::AddrInUse => proposed_traits::i3c_master::ErrorKind::DynamicAddressConflict, + Self::CccError(_) | Self::Invalid => proposed_traits::i3c_master::ErrorKind::InvalidCcc, + _ => proposed_traits::i3c_master::ErrorKind::Other, + } + } +}
diff --git a/target/ast10x0/peripherals/i3c/hal_impl.rs b/target/ast10x0/peripherals/i3c/hal_impl.rs new file mode 100644 index 0000000..647d09c --- /dev/null +++ b/target/ast10x0/peripherals/i3c/hal_impl.rs
@@ -0,0 +1,254 @@ +// Licensed under the Apache-2.0 license + +//! HAL trait implementations for I3C +//! +//! Implementations of external traits from `embedded-hal`, `proposed-traits`, etc. + +use core::convert::Infallible; + +use embedded_hal::i2c::SevenBitAddress; +use proposed_traits::i2c_target::I2CCoreTarget; +use proposed_traits::i3c_master::{ErrorKind, ErrorType, I3c, I3cSpeed}; +use proposed_traits::i3c_target::{DynamicAddressable, I3CCoreTarget, IBICapable}; + +use super::ccc; +use super::config::I3cTargetConfig; +use super::controller::I3cController; +use super::error::I3cError; +use super::hardware::HardwareInterface; +use super::types::{I3cIbi, I3cIbiType}; + +// ============================================================================= +// Error Type Implementation +// ============================================================================= + +impl<H: HardwareInterface> ErrorType for I3cController<H> { + type Error = I3cError; +} + +// ============================================================================= +// I3C Master Trait Implementation +// ============================================================================= + +impl<H: HardwareInterface> I3c for I3cController<H> { + fn assign_dynamic_address( + &mut self, + static_address: SevenBitAddress, + ) -> Result<SevenBitAddress, Self::Error> { + let slot = self + .config + .attached + .pos_of_addr(static_address) + .ok_or(I3cError::from(ErrorKind::DynamicAddressConflict))?; + + self.hw + .do_entdaa(&mut self.config, slot.into()) + .map_err(|_| I3cError::from(ErrorKind::DynamicAddressConflict))?; + + let pid = ccc::ccc_getpid(&mut self.hw, &mut self.config, static_address) + .map_err(|_| I3cError::from(ErrorKind::InvalidCcc))?; + + let dev_idx = self + .config + .attached + .find_dev_idx_by_addr(static_address) + .ok_or(I3cError::Other)?; + + let old_pid = self + .config + .attached + .devices + .get(dev_idx) + .ok_or(I3cError::Other)? + .pid; + + if let Some(op) = old_pid { + if pid != op { + return Err(I3cError::Other); + } + } + + let bcr = ccc::ccc_getbcr(&mut self.hw, &mut self.config, static_address) + .map_err(|_| I3cError::from(ErrorKind::InvalidCcc))?; + + { + let dev = self + .config + .attached + .devices + .get_mut(dev_idx) + .ok_or(I3cError::Other)?; + + dev.pid = Some(pid); + dev.bcr = bcr; + } + + let dyn_addr: SevenBitAddress = self + .config + .attached + .devices + .get(dev_idx) + .ok_or(I3cError::Other)? + .dyn_addr; + + self.hw + .ibi_enable(&mut self.config, dyn_addr) + .map_err(|_| I3cError::Other)?; + + Ok(dyn_addr) + } + + fn acknowledge_ibi(&mut self, address: SevenBitAddress) -> Result<(), Self::Error> { + let dev_idx = self + .config + .attached + .find_dev_idx_by_addr(address) + .ok_or(I3cError::Other)?; + + if self.config.attached.devices[dev_idx].pid.is_none() { + return Err(I3cError::Other); + } + + Ok(()) + } + + fn handle_hot_join(&mut self) -> Result<(), Self::Error> { + // Only need to call assign_dynamic_address after receiving hot-join IBI + Ok(()) + } + + fn set_bus_speed(&mut self, _speed: I3cSpeed) -> Result<(), Self::Error> { + // AST1060 I3C driver doesn't support changing bus speed dynamically + Ok(()) + } + + fn request_mastership(&mut self) -> Result<(), Self::Error> { + // AST1060 controller doesn't support multi-master + Ok(()) + } +} + +// ============================================================================= +// I2C Error Type Implementation +// ============================================================================= + +impl<H: HardwareInterface> embedded_hal::i2c::ErrorType for I3cController<H> { + type Error = Infallible; +} + +// ============================================================================= +// I2C Target Trait Implementation +// ============================================================================= + +impl<H: HardwareInterface> I2CCoreTarget for I3cController<H> { + #[inline] + fn init(&mut self, own_addr: u8) -> Result<(), Self::Error> { + if let Some(t) = self.config.target_config.as_mut() { + if t.addr.is_none() { + t.addr = Some(own_addr); + } + } else { + self.config.target_config = + Some(I3cTargetConfig::new(0, Some(own_addr), /* mdb */ 0xae)); + } + Ok(()) + } + + #[inline] + fn on_address_match(&mut self, addr: u8) -> bool { + self.config.target_config.as_ref().and_then(|t| t.addr) == Some(addr) + } + + #[inline] + fn on_transaction_start(&mut self, _is_read: bool) {} + + #[inline] + fn on_stop(&mut self) {} +} + +// ============================================================================= +// I3C Target Trait Implementation +// ============================================================================= + +impl<H: HardwareInterface> I3CCoreTarget for I3cController<H> {} + +impl<H: HardwareInterface> DynamicAddressable for I3cController<H> { + fn on_dynamic_address_assigned(&mut self, _new_address: u8) { + self.config.sir_allowed_by_sw = true; + } +} + +impl<H: HardwareInterface> IBICapable for I3cController<H> { + fn wants_ibi(&self) -> bool { + true + } + + fn get_ibi_payload(&mut self, buffer: &mut [u8]) -> Result<usize, Self::Error> { + let (da, mdb) = match self.config.target_config.as_ref() { + Some(t) => ( + match t.addr { + Some(da) => da, + None => return Ok(0), + }, + t.mdb, + ), + None => return Ok(0), + }; + + let addr_rnw = (da << 1) | 0x1; + let mut crc = crc8_ccitt(0, &[addr_rnw]); + crc = crc8_ccitt(crc, &[mdb]); + + let payload = [mdb, crc]; + let mut ibi = I3cIbi { + ibi_type: I3cIbiType::TargetIntr, + payload: Some(&payload), + }; + let rc = self + .hw + .target_pending_read_notify(&mut self.config, buffer, &mut ibi); + + match rc { + Ok(()) => Ok(buffer.len() + payload.len()), + _ => Ok(0), + } + } + + fn on_ibi_acknowledged(&mut self) {} +} + +// ============================================================================= +// Helper Functions +// ============================================================================= + +/// CRC-8 CCITT calculation +#[inline] +fn crc8_ccitt(mut crc: u8, data: &[u8]) -> u8 { + for &b in data { + let mut x = crc ^ b; + for _ in 0..8 { + x = if (x & 0x80) != 0 { + (x << 1) ^ 0x07 + } else { + x << 1 + }; + } + crc = x; + } + crc +} + +// ============================================================================= +// Error Conversions +// ============================================================================= + +impl From<ErrorKind> for I3cError { + #[inline] + fn from(kind: ErrorKind) -> Self { + match kind { + ErrorKind::DynamicAddressConflict => Self::AddrInUse, + ErrorKind::InvalidCcc => Self::Invalid, + _ => Self::Other, + } + } +}
diff --git a/target/ast10x0/peripherals/i3c/hardware.rs b/target/ast10x0/peripherals/i3c/hardware.rs new file mode 100644 index 0000000..3427233 --- /dev/null +++ b/target/ast10x0/peripherals/i3c/hardware.rs
@@ -0,0 +1,1900 @@ +// Licensed under the Apache-2.0 license + +//! I3C Hardware Interface +//! +//! Defines the hardware abstraction traits and IRQ handling infrastructure. +//! +//! # Trait Hierarchy +//! +//! The hardware interface is split into focused sub-traits: +//! +//! ```text +//! HardwareInterface (supertrait) +//! ├── HardwareCore - Init, IRQ, enable/disable +//! ├── HardwareClock - Clock configuration +//! ├── HardwareFifo - FIFO operations +//! ├── HardwareTransfer - Transfers, CCC, device management +//! ├── HardwareRecovery - SW mode, bus recovery +//! └── HardwareTarget - Target mode operations +//! ``` +//! +//! # Platform Initialization +//! +//! SCU operations (clock enable, reset control) are **not** part of these traits. +//! They should be performed by the platform/board layer before creating the +//! I3C controller. + +use core::cell::RefCell; +use critical_section::Mutex; + +use super::ccc::{ccc_events_set, CccPayload}; +use super::config::I3cConfig; +use super::constants::{ + bit, field_get, field_prep, CM_TFR_STS_MASTER_HALT, CM_TFR_STS_TARGET_HALT, + COMMAND_ATTR_ADDR_ASSGN_CMD, COMMAND_ATTR_SLAVE_DATA_CMD, COMMAND_ATTR_XFER_ARG, + COMMAND_ATTR_XFER_CMD, COMMAND_PORT_ARG_DATA_LEN, COMMAND_PORT_ARG_DB, COMMAND_PORT_ATTR, + COMMAND_PORT_CMD, COMMAND_PORT_CP, COMMAND_PORT_DBP, COMMAND_PORT_DEV_COUNT, + COMMAND_PORT_DEV_INDEX, COMMAND_PORT_READ_TRANSFER, COMMAND_PORT_ROC, COMMAND_PORT_SPEED, + COMMAND_PORT_TID, COMMAND_PORT_TOC, DEV_ADDR_TABLE_IBI_MDB, DEV_ADDR_TABLE_IBI_PEC, + DEV_ADDR_TABLE_SIR_REJECT, I3CG_REG1_SCL_IN_SW_MODE_EN, I3CG_REG1_SCL_IN_SW_MODE_VAL, + I3CG_REG1_SDA_IN_SW_MODE_EN, I3CG_REG1_SDA_IN_SW_MODE_VAL, I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE, + I3C_BUS_I2C_FMP_TF_MAX_NS, I3C_BUS_I2C_FMP_THIGH_MIN_NS, I3C_BUS_I2C_FMP_TLOW_MIN_NS, + I3C_BUS_I2C_FMP_TR_MAX_NS, I3C_BUS_I2C_FM_TF_MAX_NS, I3C_BUS_I2C_FM_THIGH_MIN_NS, + I3C_BUS_I2C_FM_TLOW_MIN_NS, I3C_BUS_I2C_FM_TR_MAX_NS, I3C_BUS_I2C_STD_TF_MAX_NS, + I3C_BUS_I2C_STD_THIGH_MIN_NS, I3C_BUS_I2C_STD_TLOW_MIN_NS, I3C_BUS_I2C_STD_TR_MAX_NS, + I3C_BUS_THIGH_MAX_NS, I3C_CCC_DEVCTRL, I3C_CCC_ENTDAA, I3C_CCC_EVT_INTR, I3C_CCC_SETHID, + I3C_MSG_READ, IBIQ_STATUS_IBI_DATA_LEN, IBIQ_STATUS_IBI_DATA_LEN_SHIFT, IBIQ_STATUS_IBI_ID, + IBIQ_STATUS_IBI_ID_SHIFT, INTR_CCC_UPDATED_STAT, INTR_DYN_ADDR_ASSGN_STAT, INTR_IBI_THLD_STAT, + INTR_RESP_READY_STAT, INTR_TRANSFER_ABORT_STAT, INTR_TRANSFER_ERR_STAT, MAX_CMDS, NSEC_PER_SEC, + RESET_CTRL_ALL, RESET_CTRL_QUEUES, RESET_CTRL_XFER_QUEUES, RESPONSE_ERROR_IBA_NACK, + RESPONSE_PORT_DATA_LEN_MASK, RESPONSE_PORT_DATA_LEN_SHIFT, RESPONSE_PORT_ERR_STATUS_MASK, + RESPONSE_PORT_ERR_STATUS_SHIFT, RESPONSE_PORT_TID_MASK, RESPONSE_PORT_TID_SHIFT, + SDA_TX_HOLD_MASK, SDA_TX_HOLD_MAX, SDA_TX_HOLD_MIN, SLV_DCR_MASK, SLV_EVENT_CTRL_SIR_EN, +}; +use super::error::I3cError as I3cDrvError; +use super::error::I3cError; +use super::ibi as ibi_workq; +use super::types::{I3cCmd, I3cIbi, I3cMsg, I3cXfer, SpeedI3c, Tid}; + +use core::marker::PhantomData; +use core::sync::atomic::Ordering; +use cortex_m::peripheral::NVIC; + +// ============================================================================= +// IRQ Handler Infrastructure +// ============================================================================= + +#[derive(Clone, Copy)] +struct Handler { + func: fn(usize), + ctx: usize, +} + +static BUS_HANDLERS: [Mutex<RefCell<Option<Handler>>>; 4] = [ + Mutex::new(RefCell::new(None)), + Mutex::new(RefCell::new(None)), + Mutex::new(RefCell::new(None)), + Mutex::new(RefCell::new(None)), +]; + +/// Register an IRQ handler for an I3C bus +/// +/// # Arguments +/// * `bus` - Bus index (0-3) +/// * `func` - Handler function +/// * `ctx` - Context value passed to handler +/// +/// # Panics +/// Panics if `bus >= 4`. +pub fn register_i3c_irq_handler(bus: usize, func: fn(usize), ctx: usize) { + assert!(bus < 4); + critical_section::with(|cs| { + *BUS_HANDLERS[bus].borrow(cs).borrow_mut() = Some(Handler { func, ctx }); + }); +} + +/// Dispatch IRQ for a specific bus +/// +/// Called by the actual IRQ entry points (defined elsewhere to avoid symbol conflicts). +#[inline] +pub fn dispatch_i3c_irq(bus: usize) { + // Copy handler out of critical section to avoid blocking IRQs during handler + let handler = + critical_section::with(|cs| BUS_HANDLERS.get(bus).and_then(|m| *m.borrow(cs).borrow())); + if let Some(h) = handler { + (h.func)(h.ctx); + } +} + +// IRQ entry points - defined in src/i3c/ module to avoid symbol conflicts. +// Use register_i3c_irq_handler() to register handlers that will be called +// from those entry points. + +// ============================================================================= +// Sub-trait: Core Operations +// ============================================================================= + +/// Core hardware operations: init, IRQ, enable/disable +pub trait HardwareCore { + /// Initialize the I3C controller hardware + fn init(&mut self, config: &mut I3cConfig); + + /// Get the bus number for this instance + fn bus_num(&self) -> u8; + + /// Enable interrupts + fn enable_irq(&mut self); + + /// Disable interrupts + fn disable_irq(&mut self); + + /// Enable the I3C controller + fn i3c_enable(&mut self, config: &I3cConfig); + + /// Disable the I3C controller + fn i3c_disable(&mut self, is_secondary: bool); + + /// Set the controller role (primary/secondary) + fn set_role(&mut self, is_secondary: bool); + + /// Main ISR handler + fn i3c_aspeed_isr(&mut self, config: &mut I3cConfig); +} + +// ============================================================================= +// Sub-trait: Clock Configuration +// ============================================================================= + +/// Clock and timing configuration +pub trait HardwareClock { + /// Initialize clock timing parameters + /// + /// Implementations should use `config.core_clk_hz` if set, falling back + /// to [`get_clock_rate()`](Self::get_clock_rate) for auto-detection. + fn init_clock(&mut self, config: &mut I3cConfig); + + /// Calculate I2C clock dividers for given SCL frequency + fn calc_i2c_clk(&mut self, fscl_hz: u32) -> (u32, u32); + + /// Initialize the PID (Provisional ID) for this controller + fn init_pid(&mut self, config: &mut I3cConfig); +} + +// ============================================================================= +// Sub-trait: FIFO Operations +// ============================================================================= + +/// FIFO read/write operations +pub trait HardwareFifo { + /// Write to TX FIFO + fn wr_tx_fifo(&mut self, bytes: &[u8]); + + /// Read from FIFO using provided read function + fn rd_fifo<F>(&mut self, read_word: F, out: &mut [u8]) + where + F: FnMut() -> u32; + + /// Drain FIFO without storing data + fn drain_fifo<F>(&mut self, read_word: F, len: usize) + where + F: FnMut() -> u32; + + /// Read from RX FIFO + fn rd_rx_fifo(&mut self, out: &mut [u8]); + + /// Read from IBI FIFO + fn rd_ibi_fifo(&mut self, out: &mut [u8]); +} + +// ============================================================================= +// Sub-trait: Transfer Operations +// ============================================================================= + +/// Transfer, CCC, and device management operations +pub trait HardwareTransfer { + /// Set the IBI Mandatory Data Byte + fn set_ibi_mdb(&mut self, mdb: u8); + + /// Exit halt state + fn exit_halt(&mut self, config: &mut I3cConfig); + + /// Enter halt state + fn enter_halt(&mut self, by_sw: bool, config: &mut I3cConfig); + + /// Reset controller components (FIFOs, queues, etc.) + fn reset_ctrl(&mut self, reset: u32); + + /// Enable IBI for a device + fn ibi_enable(&mut self, config: &mut I3cConfig, addr: u8) -> Result<(), I3cError>; + + /// Start a transfer + fn start_xfer(&mut self, config: &mut I3cConfig, xfer: &mut I3cXfer); + + /// End a transfer + fn end_xfer(&mut self, config: &mut I3cConfig); + + /// Get DAT position for an address + fn get_addr_pos(&mut self, config: &I3cConfig, addr: u8) -> Option<u8>; + + /// Detach a device by DAT position + fn detach_i3c_dev(&mut self, pos: usize); + + /// Attach a device to a DAT position + fn attach_i3c_dev(&mut self, pos: usize, addr: u8) -> Result<(), I3cError>; + + /// Execute a CCC + fn do_ccc(&mut self, config: &mut I3cConfig, ccc: &mut CccPayload) -> Result<(), I3cError>; + + /// Execute ENTDAA (Enter Dynamic Address Assignment) + fn do_entdaa(&mut self, config: &mut I3cConfig, index: u32) -> Result<(), I3cError>; + + /// Build commands for private transfer + fn priv_xfer_build_cmds<'a>( + &mut self, + cmds: &mut [I3cCmd<'a>], + msgs: &mut [I3cMsg<'a>], + pos: u8, + ) -> Result<(), I3cError>; + + /// Execute a private transfer + fn priv_xfer( + &mut self, + config: &mut I3cConfig, + pid: u64, + msgs: &mut [I3cMsg], + ) -> Result<(), I3cError>; + + /// Handle IBI SIR (Slave Interrupt Request) + fn handle_ibi_sir(&mut self, config: &mut I3cConfig, addr: u8, len: usize); + + /// Handle all pending IBIs + fn handle_ibis(&mut self, config: &mut I3cConfig); +} + +// ============================================================================= +// Sub-trait: Recovery / Software Mode +// ============================================================================= + +/// Software mode and bus recovery operations +pub trait HardwareRecovery { + /// Enter software mode for manual bus control + fn enter_sw_mode(&mut self); + + /// Exit software mode + fn exit_sw_mode(&mut self); + + /// Toggle SCL line in software mode + fn i3c_toggle_scl_in(&mut self, count: u32); + + /// Generate an internal STOP condition + fn gen_internal_stop(&mut self); + + /// Calculate even parity for a byte + fn even_parity(byte: u8) -> bool; +} + +// ============================================================================= +// Sub-trait: Target Mode Operations +// ============================================================================= + +/// Target (secondary) mode operations +pub trait HardwareTarget { + /// Write data to target TX buffer + fn target_tx_write(&mut self, buf: &[u8]); + + /// Raise a Hot-Join IBI (target mode) + fn target_ibi_raise_hj(&self, config: &mut I3cConfig) -> Result<(), I3cError>; + + /// Handle response ready in target mode + fn target_handle_response_ready(&mut self, config: &mut I3cConfig); + + /// Notify pending read in target mode + fn target_pending_read_notify( + &mut self, + config: &mut I3cConfig, + buf: &[u8], + notifier: &mut I3cIbi, + ) -> Result<(), I3cError>; + + /// Handle CCC update in target mode + fn target_handle_ccc_update(&mut self, config: &mut I3cConfig); +} + +// ============================================================================= +// Supertrait: Full Hardware Interface +// ============================================================================= + +/// Complete hardware abstraction for I3C controllers +/// +/// This is a supertrait combining all sub-traits. Implementors must provide +/// all operations. +/// +/// # Sub-traits +/// +/// - [`HardwareCore`] - Init, IRQ, enable/disable +/// - [`HardwareClock`] - Clock configuration +/// - [`HardwareFifo`] - FIFO operations +/// - [`HardwareTransfer`] - Transfers, CCC, device management +/// - [`HardwareRecovery`] - SW mode, bus recovery +/// - [`HardwareTarget`] - Target mode operations +pub trait HardwareInterface: + HardwareCore + HardwareClock + HardwareFifo + HardwareTransfer + HardwareRecovery + HardwareTarget +{ +} + +// Blanket implementation: any type implementing all sub-traits implements HardwareInterface +impl<T> HardwareInterface for T where + T: HardwareCore + + HardwareClock + + HardwareFifo + + HardwareTransfer + + HardwareRecovery + + HardwareTarget +{ +} + +/// I3C bus 0 interrupt handler - call this from your ISR +#[inline] +pub fn i3c_irq_handler() { + dispatch_i3c_irq(0); +} + +/// I3C bus 1 interrupt handler - call this from your ISR +#[inline] +pub fn i3c1_irq_handler() { + dispatch_i3c_irq(1); +} + +/// I3C bus 2 interrupt handler - call this from your ISR +#[inline] +pub fn i3c2_irq_handler() { + dispatch_i3c_irq(2); +} + +/// I3C bus 3 interrupt handler - call this from your ISR +#[inline] +pub fn i3c3_irq_handler() { + dispatch_i3c_irq(3); +} + +// ISR exports - only when isr-handlers feature is enabled +// For kernel integration, disable this feature and define ISRs in target code +#[cfg(feature = "isr-handlers")] +#[no_mangle] +pub extern "C" fn i3c() { + i3c_irq_handler(); +} + +#[cfg(feature = "isr-handlers")] +#[no_mangle] +pub extern "C" fn i3c1() { + i3c1_irq_handler(); +} + +#[cfg(feature = "isr-handlers")] +#[no_mangle] +pub extern "C" fn i3c2() { + i3c2_irq_handler(); +} + +#[cfg(feature = "isr-handlers")] +#[no_mangle] +pub extern "C" fn i3c3() { + i3c3_irq_handler(); +} + +/// I3C controller wrapping hardware register pointers. +/// +/// Provides low-level hardware abstraction for I3C controllers. +/// Platform/board layer is responsible for: +/// - Clock enable (SCU) +/// - Reset deassert (SCU) +/// - Pin mux configuration +/// +/// All of these must be done BEFORE constructing this instance. +pub struct Ast1060I3c<'a, Y: FnMut(u32)> { + i3c: *const ast1060_pac::i3c::RegisterBlock, + i3cg: *const ast1060_pac::i3cglobal::RegisterBlock, + pub bus_num: u8, + pub yield_ns: Y, + _lifetime: PhantomData<&'a ()>, +} + +impl<'a, Y: FnMut(u32)> Ast1060I3c<'a, Y> { + /// Create a new I3C instance from hardware pointers. + /// + /// # Safety + /// + /// - `i3c` and `i3cg` must be valid, non-null pointers to the respective register blocks + /// - Both must point to the **same** I3C controller instance + /// - `bus_num` must be 0-3 (one of the four I3C bus instances) + /// - Pointers must remain valid for the lifetime of this instance + /// - Caller must ensure exclusive ownership (no concurrent mutable access) + /// - Platform must have already handled SCU setup (clock, reset) + pub unsafe fn new( + i3c: *const ast1060_pac::i3c::RegisterBlock, + i3cg: *const ast1060_pac::i3cglobal::RegisterBlock, + bus_num: u8, + yield_ns: Y, + ) -> Self { + assert!(bus_num < 4, "I3C bus number must be 0-3, got {}", bus_num); + Self { + i3c, + i3cg, + bus_num, + yield_ns, + _lifetime: PhantomData, + } + } + + /// Create instance from pre-initialized hardware (no I/O). + /// + /// Lightweight constructor when hardware is already configured. + /// Use after [`new`] on the same controller, or when boot firmware + /// already initialized the I3C hardware. + #[must_use] + pub unsafe fn from_initialized( + i3c: *const ast1060_pac::i3c::RegisterBlock, + i3cg: *const ast1060_pac::i3cglobal::RegisterBlock, + bus_num: u8, + yield_ns: Y, + ) -> Self { + unsafe { Self::new(i3c, i3cg, bus_num, yield_ns) } + } + + /// Safe access to I3C registers + #[inline] + fn i3c(&self) -> &ast1060_pac::i3c::RegisterBlock { + unsafe { &*self.i3c } + } + + /// Safe access to I3C global registers + #[inline] + fn i3cg(&self) -> &ast1060_pac::i3cglobal::RegisterBlock { + unsafe { &*self.i3cg } + } +} + +// ----------------------------------------------------------------------------- +// Register Helper Macros +// ----------------------------------------------------------------------------- + +#[allow(unused_macros)] +macro_rules! read_i3cg_reg1 { + ($self:expr, $bus:expr) => {{ + match $bus { + 0 => $self.i3cg().i3c014().read().bits(), + 1 => $self.i3cg().i3c024().read().bits(), + 2 => $self.i3cg().i3c034().read().bits(), + 3 => $self.i3cg().i3c044().read().bits(), + _ => panic!("invalid I3C bus index: {}", $bus), + } + }}; +} + +#[allow(unused_macros)] +macro_rules! write_i3cg_reg0 { + ($self:expr, $bus:expr, |$w:ident| $body:expr) => {{ + match $bus { + 0 => $self.i3cg().i3c010().write(|$w| $body), + 1 => $self.i3cg().i3c020().write(|$w| $body), + 2 => $self.i3cg().i3c030().write(|$w| $body), + 3 => $self.i3cg().i3c040().write(|$w| $body), + _ => panic!("invalid I3C bus index: {}", $bus), + } + }}; +} + +#[allow(unused_macros)] +macro_rules! read_i3cg_reg0 { + ($self:expr, $bus:expr) => {{ + match $bus { + 0 => $self.i3cg().i3c010().read().bits(), + 1 => $self.i3cg().i3c020().read().bits(), + 2 => $self.i3cg().i3c030().read().bits(), + 3 => $self.i3cg().i3c040().read().bits(), + _ => panic!("invalid I3C bus index: {}", $bus), + } + }}; +} + +#[allow(unused_macros)] +macro_rules! write_i3cg_reg1 { + ($self:expr, $bus:expr, |$w:ident| $body:expr) => {{ + match $bus { + 0 => $self.i3cg().i3c014().write(|$w| $body), + 1 => $self.i3cg().i3c024().write(|$w| $body), + 2 => $self.i3cg().i3c034().write(|$w| $body), + 3 => $self.i3cg().i3c044().write(|$w| $body), + _ => panic!("invalid I3C bus index: {}", $bus), + } + }}; +} + +macro_rules! modify_i3cg_reg1 { + ($self:expr, $bus:expr, |$r:ident, $w:ident| $body:expr) => {{ + match $bus { + 0 => $self.i3cg().i3c014().modify(|$r, $w| $body), + 1 => $self.i3cg().i3c024().modify(|$r, $w| $body), + 2 => $self.i3cg().i3c034().modify(|$r, $w| $body), + 3 => $self.i3cg().i3c044().modify(|$r, $w| $body), + _ => panic!("invalid I3C bus index: {}", $bus), + } + }}; +} + +macro_rules! i3c_dat_read { + ($self:expr, $pos:expr) => {{ + match ($pos) { + 0 => $self.i3c().i3cd280().read().bits(), + 1 => $self.i3c().i3cd284().read().bits(), + 2 => $self.i3c().i3cd288().read().bits(), + 3 => $self.i3c().i3cd28c().read().bits(), + 4 => $self.i3c().i3cd290().read().bits(), + 5 => $self.i3c().i3cd294().read().bits(), + 6 => $self.i3c().i3cd298().read().bits(), + 7 => $self.i3c().i3cd29c().read().bits(), + _ => 0, + } + }}; +} + +macro_rules! i3c_dat_write { + ($self:expr, $pos:expr, |$w:ident| $body:expr) => {{ + match ($pos) { + 0 => { + $self.i3c().i3cd280().write(|$w| $body); + } + 1 => { + $self.i3c().i3cd284().write(|$w| $body); + } + 2 => { + $self.i3c().i3cd288().write(|$w| $body); + } + 3 => { + $self.i3c().i3cd28c().write(|$w| $body); + } + 4 => { + $self.i3c().i3cd290().write(|$w| $body); + } + 5 => { + $self.i3c().i3cd294().write(|$w| $body); + } + 6 => { + $self.i3c().i3cd298().write(|$w| $body); + } + 7 => { + $self.i3c().i3cd29c().write(|$w| $body); + } + _ => { /* ignore */ } + } + }}; +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum PollError { + Timeout, +} + +pub fn poll_with_timeout<F, C, Y>( + mut read_reg: F, + mut condition: C, + yield_ns: &mut Y, + delay_ns: u32, + max_iters: u32, +) -> Result<u32, PollError> +where + F: FnMut() -> u32, + C: FnMut(u32) -> bool, + Y: FnMut(u32), +{ + for _ in 0..max_iters { + let val = read_reg(); + if condition(val) { + return Ok(val); + } + yield_ns(delay_ns); + } + Err(PollError::Timeout) +} + +impl<'a, Y: FnMut(u32)> Ast1060I3c<'a, Y> { + fn toggle_scl_in(&mut self, count: u32) { + let bus = self.bus_num; + for _ in 0..count { + modify_i3cg_reg1!(self, bus, |r, w| unsafe { + w.bits(r.bits() & !I3CG_REG1_SCL_IN_SW_MODE_VAL) + }); + modify_i3cg_reg1!(self, bus, |r, w| unsafe { + w.bits(r.bits() | I3CG_REG1_SCL_IN_SW_MODE_VAL) + }); + } + } + + fn gen_internal_stop(&mut self) { + let bus = self.bus_num; + modify_i3cg_reg1!(self, bus, |r, w| unsafe { + w.bits(r.bits() & !I3CG_REG1_SCL_IN_SW_MODE_VAL) + }); + modify_i3cg_reg1!(self, bus, |r, w| unsafe { + w.bits(r.bits() & !I3CG_REG1_SDA_IN_SW_MODE_VAL) + }); + modify_i3cg_reg1!(self, bus, |r, w| unsafe { + w.bits(r.bits() | I3CG_REG1_SCL_IN_SW_MODE_VAL) + }); + modify_i3cg_reg1!(self, bus, |r, w| unsafe { + w.bits(r.bits() | I3CG_REG1_SDA_IN_SW_MODE_VAL) + }); + } + + fn enter_sw_mode(&mut self) { + let bus = self.bus_num; + let mut reg = read_i3cg_reg1!(self, bus); + reg |= I3CG_REG1_SCL_IN_SW_MODE_VAL | I3CG_REG1_SDA_IN_SW_MODE_VAL; + modify_i3cg_reg1!(self, bus, |_r, w| unsafe { w.bits(reg) }); + reg |= I3CG_REG1_SCL_IN_SW_MODE_EN | I3CG_REG1_SDA_IN_SW_MODE_EN; + modify_i3cg_reg1!(self, bus, |_r, w| unsafe { w.bits(reg) }); + } + + fn exit_sw_mode(&mut self) { + let bus = self.bus_num; + let mut reg = read_i3cg_reg1!(self, bus); + reg &= !(I3CG_REG1_SCL_IN_SW_MODE_EN | I3CG_REG1_SDA_IN_SW_MODE_EN); + modify_i3cg_reg1!(self, bus, |_r, w| unsafe { w.bits(reg) }); + } + +} + +impl<'a, Y: FnMut(u32)> HardwareCore for Ast1060I3c<'a, Y> { + #[allow(clippy::too_many_lines)] + fn init(&mut self, config: &mut I3cConfig) { + // PRECONDITION: Platform must have handled: + // - SCU clock enable for this I3C controller + // - SCU reset deassert + // - Pin mux configuration + + self.i3c_disable(config.is_secondary); + + self.i3c().i3cd034().write(|w| { + w.ibiqueue_sw_rst() + .set_bit() + .rx_buffer_sw_rst() + .set_bit() + .tx_buffer_sw_rst() + .set_bit() + .response_queue_sw_rst() + .set_bit() + .cmd_queue_sw_rst() + .set_bit() + .core_sw_rst() + .set_bit() + }); + + let ptr = self.i3c; + let _ = poll_with_timeout( + move || unsafe { (*ptr).i3cd034().read().bits() }, + |val| val == 0, + &mut self.yield_ns, + 100_000, + 1_000_000, + ); + + self.set_role(config.is_secondary); + self.init_clock(config); + + self.i3c().i3cd03c().write(|w| unsafe { w.bits(0xffff_ffff) }); + if config.is_secondary { + self.i3c().i3cd040().write(|w| { + w.transfererrstaten() + .set_bit() + .respreadystatintren() + .set_bit() + .cccupdatedstaten() + .set_bit() + .dynaddrassgnstaten() + .set_bit() + .ibiupdatedstaten() + .set_bit() + .readreqrecvstaten() + .set_bit() + }); + + self.i3c().i3cd044().write(|w| { + w.transfererrsignalen() + .set_bit() + .respreadysignalintren() + .set_bit() + .cccupdatedsignalen() + .set_bit() + .dynaddrassgnsignalen() + .set_bit() + .ibiupdatedsignalen() + .set_bit() + .readreqrecvsignalen() + .set_bit() + }); + } else { + self.i3c().i3cd040().write(|w| { + w.transfererrstaten() + .set_bit() + .respreadystatintren() + .set_bit() + }); + + self.i3c().i3cd044().write(|w| { + w.transfererrsignalen() + .set_bit() + .respreadysignalintren() + .set_bit() + }); + } + + config.sir_allowed_by_sw = false; + + self.i3c() + .i3cd01c() + .write(|w| unsafe { w.ibidata_threshold_value().bits(31) }); + + self.i3c() + .i3cd020() + .modify(|_, w| unsafe { w.rx_buffer_threshold_value().bits(0) }); + + self.init_pid(config); + + config.maxdevs = self.i3c().i3cd05c().read().devaddrtabledepth().bits(); + config.free_pos = if config.maxdevs == 32 { + u32::MAX + } else { + (1u32 << config.maxdevs) - 1 + }; + config.need_da = 0; + + for i in 0..(config.maxdevs) { + i3c_dat_write!(self, i, |w| { + w.sirreject().set_bit().mrreject().set_bit() + }); + } + + self.i3c().i3cd02c().write(|w| unsafe { w.bits(0xffff_ffff) }); + self.i3c().i3cd030().write(|w| unsafe { w.bits(0xffff_ffff) }); + self.i3c() + .i3cd000() + .modify(|_, w| w.hot_join_ack_nack_ctrl().set_bit()); + + if config.is_secondary { + self.i3c() + .i3cd004() + .write(|w| unsafe { w.dev_static_addr().bits(9).static_addr_valid().set_bit() }); + } else { + self.i3c() + .i3cd004() + .write(|w| unsafe { w.dev_dynamic_addr().bits(8).dynamic_addr_valid().set_bit() }); + } + + self.i3c_enable(config); + + if !config.is_secondary { + self.i3c() + .i3cd040() + .modify(|_, w| w.ibithldstaten().set_bit()); + self.i3c() + .i3cd044() + .modify(|_, w| w.ibithldsignalen().set_bit()); + } + self.i3c() + .i3cd000() + .modify(|_, w| w.hot_join_ack_nack_ctrl().clear_bit()); + + // Safety: Ensure memory barrier and init completion before interrupts are enabled by the caller + core::sync::atomic::compiler_fence(Ordering::SeqCst); + } + + fn bus_num(&self) -> u8 { + self.bus_num + } + + fn enable_irq(&mut self) { + unsafe { + match self.bus_num { + 0 => NVIC::unmask(ast1060_pac::Interrupt::i3c), + 1 => NVIC::unmask(ast1060_pac::Interrupt::i3c1), + 2 => NVIC::unmask(ast1060_pac::Interrupt::i3c2), + 3 => NVIC::unmask(ast1060_pac::Interrupt::i3c3), + _ => {} + } + } + } + + fn disable_irq(&mut self) { + match self.bus_num { + 0 => NVIC::mask(ast1060_pac::Interrupt::i3c), + 1 => NVIC::mask(ast1060_pac::Interrupt::i3c1), + 2 => NVIC::mask(ast1060_pac::Interrupt::i3c2), + 3 => NVIC::mask(ast1060_pac::Interrupt::i3c3), + _ => {} + } + } + + fn i3c_disable(&mut self, is_secondary: bool) { + if self.i3c().i3cd000().read().enbl_i3cctrl().bit_is_clear() { + return; + } + + if is_secondary { + self.enter_sw_mode(); + } + self.i3c() + .i3cd000() + .modify(|_, w| w.enbl_i3cctrl().clear_bit()); + + if is_secondary { + self.toggle_scl_in(8); + self.gen_internal_stop(); + self.exit_sw_mode(); + } + } + + fn i3c_enable(&mut self, config: &I3cConfig) { + if config.is_secondary { + self.i3c().i3cd038().write(|w| unsafe { w.bits(0) }); + self.enter_sw_mode(); + self.i3c().i3cd000().modify(|_, w| { + w.enbl_adaption_of_i2ci3cmode() + .clear_bit() + .ibipayloaden() + .set_bit() + .enbl_i3cctrl() + .set_bit() + }); + let wait_cnt = &self.i3c().i3cd0d4().read().i3cibifree().bits(); + let wait_ns = u32::from(*wait_cnt) * config.core_period; + (self.yield_ns)(wait_ns * 100_u32); + self.toggle_scl_in(8); + if self.i3c().i3cd000().read().enbl_i3cctrl().bit_is_set() { + self.gen_internal_stop(); + } + self.exit_sw_mode(); + } else { + self.i3c().i3cd000().modify(|_, w| { + w.i3cbroadcast_addr_include() + .set_bit() + .enbl_i3cctrl() + .set_bit() + }); + } + } + + fn set_role(&mut self, is_secondary: bool) { + if is_secondary { + self.i3c() + .i3cd0b0() + .modify(|_, w| unsafe { w.dev_op_mode().bits(1) }); + } else { + self.i3c() + .i3cd0b0() + .modify(|_, w| unsafe { w.dev_op_mode().bits(0) }); + } + } + + fn i3c_aspeed_isr(&mut self, config: &mut I3cConfig) { + self.disable_irq(); + let status = self.i3c().i3cd03c().read().bits(); + if status == 0 { + self.enable_irq(); + return; + } + + if config.is_secondary { + if status & INTR_DYN_ADDR_ASSGN_STAT != 0 { + let da = self.i3c().i3cd004().read().dev_dynamic_addr().bits(); + if let Some(tc) = &mut config.target_config { + tc.addr = Some(da); + } + let _ = ibi_workq::i3c_ibi_work_enqueue_target_da_assignment(self.bus_num.into()); + } + + if (status & INTR_RESP_READY_STAT) != 0 { + self.target_handle_response_ready(config); + } + + if (status & INTR_CCC_UPDATED_STAT) != 0 { + self.target_handle_ccc_update(config); + } + } else { + if (status & (INTR_RESP_READY_STAT | INTR_TRANSFER_ERR_STAT | INTR_TRANSFER_ABORT_STAT)) + != 0 + { + self.end_xfer(config); + } + + if (status & INTR_IBI_THLD_STAT) != 0 { + self.handle_ibis(config); + } + } + + self.i3c().i3cd03c().write(|w| unsafe { w.bits(status) }); + self.enable_irq(); + } +} + +impl<'a, Y: FnMut(u32)> HardwareClock for Ast1060I3c<'a, Y> { + fn init_clock(&mut self, config: &mut I3cConfig) { + let clk_rate = config.core_clk_hz.expect("core_clk_hz must be configured"); + config.core_period = (NSEC_PER_SEC).div_ceil(clk_rate); + + let ns_to_cnt_u8 = + |ns: u32| -> u8 { u8::try_from(ns.div_ceil(config.core_period)).unwrap_or(u8::MAX) }; + let ns_to_cnt_u16 = + |ns: u32| -> u16 { u16::try_from(ns.div_ceil(config.core_period)).unwrap_or(u16::MAX) }; + + // I2C FM + let (fm_hi_ns, fm_lo_ns) = self.calc_i2c_clk(config.i2c_scl_hz); + self.i3c().i3cd0bc().write(|w| unsafe { + w.i2cfmhcnt() + .bits(ns_to_cnt_u16(fm_hi_ns)) + .i2cfmlcnt() + .bits(ns_to_cnt_u16(fm_lo_ns)) + }); + + // I2C FMP + let (i2c_fmp_hi_ns, i2c_fmp_lo_ns) = self.calc_i2c_clk(1_000_000); + self.i3c().i3cd0c0().write(|w| unsafe { + w.i2cfmphcnt() + .bits(ns_to_cnt_u8(i2c_fmp_hi_ns)) + .i2cfmplcnt() + .bits(ns_to_cnt_u16(i2c_fmp_lo_ns)) + }); + + // I3C OD + let (od_hi_ns, od_lo_ns) = + if config.i3c_od_scl_hi_period_ns != 0 && config.i3c_od_scl_lo_period_ns != 0 { + ( + config.i3c_od_scl_hi_period_ns, + config.i3c_od_scl_lo_period_ns, + ) + } else { + (i2c_fmp_hi_ns, i2c_fmp_lo_ns) + }; + self.i3c().i3cd0b4().write(|w| unsafe { + w.i3codhcnt() + .bits(ns_to_cnt_u8(od_hi_ns)) + .i3codlcnt() + .bits(ns_to_cnt_u8(od_lo_ns)) + }); + + // I3C PP + let (i3c_pp_hi_ns, i3c_pp_lo_ns) = + if config.i3c_pp_scl_hi_period_ns != 0 && config.i3c_pp_scl_lo_period_ns != 0 { + ( + config.i3c_pp_scl_hi_period_ns, + config.i3c_pp_scl_lo_period_ns, + ) + } else { + let total_ns = NSEC_PER_SEC.div_ceil(config.i3c_scl_hz.max(1)); + let hi_ns = core::cmp::min(I3C_BUS_THIGH_MAX_NS, total_ns.saturating_sub(1)); + let lo_ns = total_ns.saturating_sub(hi_ns).max(1); + (hi_ns, lo_ns) + }; + self.i3c().i3cd0b8().write(|w| unsafe { + w.i3cpphcnt() + .bits(ns_to_cnt_u8(i3c_pp_hi_ns)) + .i3cpplcnt() + .bits(ns_to_cnt_u8(i3c_pp_lo_ns)) + }); + + // SDA TX hold time + let hold_steps = (config.sda_tx_hold_ns) + .div_ceil(config.core_period) + .clamp(SDA_TX_HOLD_MIN, SDA_TX_HOLD_MAX); + let mut reg = self.i3c().i3cd0d0().read().bits(); + reg = (reg & !SDA_TX_HOLD_MASK) | ((hold_steps & 0x7) << 16); + self.i3c().i3cd0d0().write(|w| unsafe { w.bits(reg) }); + + // BUS_FREE_TIMING + self.i3c().i3cd0d4().write(|w| unsafe { w.bits(0xffff_007c) }); + } + + fn calc_i2c_clk(&mut self, fscl_hz: u32) -> (u32, u32) { + use core::cmp::max; + + debug_assert!(fscl_hz > 0); + let period_ns: u32 = (1_000_000_000u32).div_ceil(fscl_hz); + + let (lo_min, hi_min): (u32, u32) = if fscl_hz <= 100_000 { + ( + (I3C_BUS_I2C_STD_TLOW_MIN_NS + I3C_BUS_I2C_STD_TF_MAX_NS).div_ceil(period_ns), + (I3C_BUS_I2C_STD_THIGH_MIN_NS + I3C_BUS_I2C_STD_TR_MAX_NS).div_ceil(period_ns), + ) + } else if fscl_hz <= 400_000 { + ( + (I3C_BUS_I2C_FM_TLOW_MIN_NS + I3C_BUS_I2C_FM_TF_MAX_NS).div_ceil(period_ns), + (I3C_BUS_I2C_FM_THIGH_MIN_NS + I3C_BUS_I2C_FM_TR_MAX_NS).div_ceil(period_ns), + ) + } else { + ( + (I3C_BUS_I2C_FMP_TLOW_MIN_NS + I3C_BUS_I2C_FMP_TF_MAX_NS).div_ceil(period_ns), + (I3C_BUS_I2C_FMP_THIGH_MIN_NS + I3C_BUS_I2C_FMP_TR_MAX_NS).div_ceil(period_ns), + ) + }; + + let leftover = period_ns.saturating_sub(lo_min + hi_min); + let lo = lo_min + leftover / 2; + let hi = max(period_ns.saturating_sub(lo), hi_min); + + (hi as u32, lo) + } + + fn init_pid(&mut self, config: &mut I3cConfig) { + self.i3c() + .i3cd070() + .write(|w| unsafe { w.slvmipimfgid().bits(0x3f6).slvpiddcr().clear_bit() }); + + // NOTE: rev_id must be set by caller via SCU before calling this + // This method only handles the i3c register setup, not SCU reset/clock/etc + self.i3c().i3cd074().write(|w| unsafe { w.bits(0xa000_0000) }); + let mut reg: u32 = self.i3c().i3cd078().read().bits(); + reg &= !SLV_DCR_MASK; + reg |= (config.dcr << 8) | 0x66; + self.i3c().i3cd078().write(|w| unsafe { w.bits(reg) }); + } +} + +impl<'a, Y: FnMut(u32)> HardwareFifo for Ast1060I3c<'a, Y> { + fn wr_tx_fifo(&mut self, bytes: &[u8]) { + let mut chunks = bytes.chunks_exact(4); + for chunk in &mut chunks { + let word = u32::from_le_bytes([chunk[0], chunk[1], chunk[2], chunk[3]]); + self.i3c() + .i3cd014() + .write(|w| unsafe { w.tx_data_port().bits(word) }); + } + + let rem = chunks.remainder(); + if !rem.is_empty() { + let mut tmp = [0u8; 4]; + tmp[..rem.len()].copy_from_slice(rem); + let word = u32::from_le_bytes(tmp); + self.i3c() + .i3cd014() + .write(|w| unsafe { w.tx_data_port().bits(word) }); + } + } + + fn rd_fifo<F>(&mut self, mut read_word: F, out: &mut [u8]) + where + F: FnMut() -> u32, + { + let mut chunks = out.chunks_exact_mut(4); + for chunk in &mut chunks { + let val = read_word(); + chunk.copy_from_slice(&val.to_le_bytes()); + } + + let rem = chunks.into_remainder(); + if !rem.is_empty() { + let val = read_word(); + let bytes = val.to_le_bytes(); + rem.copy_from_slice(&bytes[..rem.len()]); + } + } + + fn drain_fifo<F>(&mut self, mut read_word: F, len: usize) + where + F: FnMut() -> u32, + { + let nwords = (len + 3) >> 2; + for _ in 0..nwords { + let _ = read_word(); + } + } + + fn rd_rx_fifo(&mut self, out: &mut [u8]) { + let ptr = self.i3c; + self.rd_fifo(move || unsafe { (*ptr).i3cd014().read().rx_data_port().bits() }, out); + } + + fn rd_ibi_fifo(&mut self, out: &mut [u8]) { + let ptr = self.i3c; + self.rd_fifo(move || unsafe { (*ptr).i3cd018().read().bits() }, out); + } +} + +impl<'a, Y: FnMut(u32)> HardwareRecovery for Ast1060I3c<'a, Y> { + fn enter_sw_mode(&mut self) { + self.enter_sw_mode(); + } + + fn exit_sw_mode(&mut self) { + self.exit_sw_mode(); + } + + fn i3c_toggle_scl_in(&mut self, count: u32) { + self.toggle_scl_in(count); + } + + fn gen_internal_stop(&mut self) { + self.gen_internal_stop(); + } + + fn even_parity(byte: u8) -> bool { + let mut parity = false; + let mut b = byte; + + while b != 0 { + parity = !parity; + b &= b - 1; + } + + !parity + } +} + +impl<'drv, Y: FnMut(u32)> HardwareTransfer for Ast1060I3c<'drv, Y> { + fn set_ibi_mdb(&mut self, mdb: u8) { + self.i3c() + .i3cd000() + .modify(|_, w| unsafe { w.mdb().bits(mdb) }); + } + + fn exit_halt(&mut self, config: &mut I3cConfig) { + let state = self.i3c().i3cd054().read().cmtfrstatus().bits(); + let expected = if config.is_secondary { + CM_TFR_STS_TARGET_HALT + } else { + CM_TFR_STS_MASTER_HALT + }; + + if state != expected { + return; + } + + self.i3c().i3cd000().modify(|_, w| w.i3cresume().set_bit()); + + let ptr = self.i3c; + let rc = poll_with_timeout( + move || u32::from(unsafe { (*ptr).i3cd054().read().cmtfrstatus().bits() }), + |val| val != u32::from(expected), + &mut self.yield_ns, + 10000, + 1_000_000, + ); + + if rc.is_err() { + } + } + + fn enter_halt(&mut self, by_sw: bool, config: &mut I3cConfig) { + let expected = if config.is_secondary { + CM_TFR_STS_TARGET_HALT + } else { + CM_TFR_STS_MASTER_HALT + }; + + if by_sw { + self.i3c().i3cd000().modify(|_, w| w.i3cabort().set_bit()); + } + + let ptr = self.i3c; + let rc = poll_with_timeout( + move || u32::from(unsafe { (*ptr).i3cd054().read().cmtfrstatus().bits() }), + |val| val == u32::from(expected), + &mut self.yield_ns, + 10000, + 1_000_000, + ); + + if rc.is_err() { + } + } + + fn reset_ctrl(&mut self, reset: u32) { + let reg = reset & RESET_CTRL_ALL; + + if reg == 0 { + return; + } + + self.i3c().i3cd034().write(|w| unsafe { w.bits(reg) }); + let ptr = self.i3c; + let rc = poll_with_timeout( + move || unsafe { (*ptr).i3cd034().read().bits() }, + |val| val == 0, + &mut self.yield_ns, + 10_000, + 1_000_000, + ); + + if rc.is_err() { + } + } + + fn ibi_enable(&mut self, config: &mut I3cConfig, addr: u8) -> Result<(), I3cDrvError> { + let dev_idx = config + .attached + .find_dev_idx_by_addr(addr) + .ok_or(I3cDrvError::NoSuchDev)?; + let pos_opt = config + .attached + .pos_of(dev_idx) + .or(config.attached.devices[dev_idx].pos); + + let pos: u8 = pos_opt.ok_or(I3cDrvError::NoDatPos)?; + let dev = &config.attached.devices[dev_idx]; + let tgt_bcr: u32 = u32::from(dev.bcr); + let mut reg = i3c_dat_read!(self, u32::from(pos)); + reg &= !DEV_ADDR_TABLE_SIR_REJECT; + if tgt_bcr & I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE != 0 { + reg |= DEV_ADDR_TABLE_IBI_MDB | DEV_ADDR_TABLE_IBI_PEC; + } + + i3c_dat_write!(self, pos, |w| unsafe { w.bits(reg) }); + + let mut sir_reject = self.i3c().i3cd030().read().bits(); + sir_reject &= !bit(pos.into()); + self.i3c().i3cd030().write(|w| unsafe { w.bits(sir_reject) }); + + self.i3c() + .i3cd040() + .modify(|_, w| w.ibithldstaten().set_bit()); + + self.i3c() + .i3cd044() + .modify(|_, w| w.ibithldsignalen().set_bit()); + + let events = I3C_CCC_EVT_INTR; + // ccc_events_set requires HardwareTransfer trait bound on Self. + // We are inside HardwareTransfer impl for Ast1060I3c. + // Rust might have trouble inferring if Self: HardwareTransfer is not fully established yet? + // But Ast1060I3c implements HardwareTransfer (this block). + // However, ccc_events_set takes `&mut impl HardwareInterface`. + // Ast1060I3c implements HardwareInterface (blanket impl over all sub-traits). + // So this call should be valid. + let _ = ccc_events_set(self, config, dev.dyn_addr, true, events); + + Ok(()) + } + + fn start_xfer(&mut self, config: &mut I3cConfig, xfer: &mut I3cXfer) { + let prev = config + .curr_xfer + .swap(core::ptr::from_mut(xfer).cast::<()>(), Ordering::AcqRel); + if !prev.is_null() { + } + + xfer.ret = -1; + xfer.done.reset(); + + for cmd in xfer.cmds.iter() { + if let Some(tx) = cmd.tx { + let take = tx.len().min(cmd.tx_len as usize); + if take > 0 { + self.wr_tx_fifo(&tx[..take]); + } + } + } + self.i3c().i3cd01c().modify(|_, w| unsafe { + w.response_buffer_threshold_value() + .bits(u8::try_from(xfer.cmds.len().saturating_sub(1)).unwrap_or(0)) + }); + + for cmd in xfer.cmds.iter() { + self.i3c().i3cd00c().write(|w| unsafe { w.bits(cmd.cmd_hi) }); + self.i3c().i3cd00c().write(|w| unsafe { w.bits(cmd.cmd_lo) }); + } + } + + fn end_xfer(&mut self, config: &mut I3cConfig) { + let p = config + .curr_xfer + .swap(core::ptr::null_mut(), Ordering::AcqRel); + + if p.is_null() { + // Drain the response queue to prevent interrupt loops if no xfer is active + let nresp = self.i3c().i3cd04c().read().respbufblr().bits() as usize; + for _ in 0..nresp { + let _ = self.i3c().i3cd010().read().bits(); + } + return; + } + + let xfer: &mut I3cXfer = unsafe { &mut *(p.cast::<I3cXfer>()) }; + + let nresp = self.i3c().i3cd04c().read().respbufblr().bits() as usize; + + for _ in 0..nresp { + let resp = self.i3c().i3cd010().read().bits(); + + let tid = field_get(resp, RESPONSE_PORT_TID_MASK, RESPONSE_PORT_TID_SHIFT) as usize; + let rx_len = field_get( + resp, + RESPONSE_PORT_DATA_LEN_MASK, + RESPONSE_PORT_DATA_LEN_SHIFT, + ) as usize; + let err = field_get( + resp, + RESPONSE_PORT_ERR_STATUS_MASK, + RESPONSE_PORT_ERR_STATUS_SHIFT, + ); + + if tid >= xfer.cmds.len() { + if rx_len > 0 { + { let ptr = self.i3c; self.drain_fifo(move || unsafe { (*ptr).i3cd014().read().rx_data_port().bits() }, rx_len); } + } + continue; + } + + let cmd = &mut xfer.cmds[tid]; + cmd.rx_len = u32::try_from(rx_len).unwrap_or(0); + cmd.ret = i32::try_from(err).unwrap_or(-1); + + if rx_len == 0 { + continue; + } + + if err == 0 { + if let Some(rx_buf) = cmd.rx.as_deref_mut() { + self.rd_rx_fifo(&mut rx_buf[..rx_len]); + } else { + // Drain if no buffer provided + { let ptr = self.i3c; self.drain_fifo(move || unsafe { (*ptr).i3cd014().read().rx_data_port().bits() }, rx_len); } + } + } else if rx_len > 0 { + { let ptr = self.i3c; self.drain_fifo(move || unsafe { (*ptr).i3cd014().read().rx_data_port().bits() }, rx_len); } + } + } + let mut ret = 0; + for i in 0..nresp { + let r = xfer.cmds[i].ret; + if r != 0 { + ret = r; + } + } + + if ret != 0 { + self.enter_halt(false, config); + self.reset_ctrl(RESET_CTRL_QUEUES); + self.exit_halt(config); + } + + xfer.ret = ret; + xfer.done.complete(); + } + + fn get_addr_pos(&mut self, config: &I3cConfig, addr: u8) -> Option<u8> { + config + .addrs + .iter() + .take(config.maxdevs as usize) + .position(|&a| a == addr) + .and_then(|i| u8::try_from(i).ok()) + } + + fn detach_i3c_dev(&mut self, pos: usize) { + i3c_dat_write!(self, pos, |w| { + w.sirreject().set_bit().mrreject().set_bit() + }); + } + + fn attach_i3c_dev(&mut self, pos: usize, addr: u8) -> Result<(), I3cDrvError> { + let mut da_with_parity = addr; + if Self::even_parity(addr) { + da_with_parity |= 1 << 7; + } + + i3c_dat_write!(self, pos, |w| unsafe { + w.sirreject() + .set_bit() + .mrreject() + .set_bit() + .devdynamicaddr() + .bits(da_with_parity) + }); + + Ok(()) + } + + #[allow(clippy::too_many_lines)] + fn do_ccc( + &mut self, + config: &mut I3cConfig, + payload: &mut CccPayload<'_, '_>, + ) -> Result<(), I3cDrvError> { + let mut cmds = [I3cCmd { + cmd_lo: 0, + cmd_hi: 0, + tx: None, + rx: None, + tx_len: 0, + rx_len: 0, + ret: 0, + }]; + + let mut pos = 0; + let mut rnw: bool = false; + let mut is_broadcast = false; + + let (id, data_len) = { + let Some(ccc) = payload.ccc.as_ref() else { + return Err(I3cDrvError::Invalid); + }; + (ccc.id, ccc.data.as_deref().map_or(0, <[u8]>::len)) + }; + + let dbp_is_direct = id > 0x7F; + let db: u8 = if dbp_is_direct && data_len > 0 { + payload + .ccc + .as_ref() + .and_then(|c| c.data.as_deref()) + .map_or(0, |d| d[0]) + } else { + 0 + }; + + { + let cmd = &mut cmds[0]; + + if id <= 0x7F { + is_broadcast = true; + + if data_len > 0 { + if let Some(d) = payload.ccc.as_ref().and_then(|c| c.data.as_deref()) { + cmd.tx = Some(d); + cmd.tx_len = u32::try_from(data_len).map_err(|_| I3cDrvError::Invalid)?; + } + } + } else { + let Some(tgt_addr) = payload + .targets + .as_ref() + .and_then(|ts| ts.first()) + .map(|t| t.addr) + else { + return Err(I3cDrvError::Invalid); + }; + let pos_ops = config.attached.pos_of_addr(tgt_addr); + pos = match pos_ops { + Some(p) => p, + None => return Err(I3cDrvError::Invalid), + }; + + let Some(tp) = payload.targets.as_deref_mut().and_then(|ts| ts.first_mut()) else { + return Err(I3cDrvError::Invalid); + }; + + rnw = tp.rnw; + + if rnw { + let len = tp.data.as_deref().map_or(0, <[u8]>::len); + if len == 0 { + return Err(I3cDrvError::Invalid); + } + cmd.rx_len = u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?; + cmd.rx = tp.data.as_deref_mut(); + } else { + let (d_opt, len) = match tp.data.as_deref() { + Some(d) => (Some(d), d.len()), + None => (None, 0), + }; + cmd.tx = d_opt; + cmd.tx_len = u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?; + tp.num_xfer = len; + } + } + } + + let cmd = &mut cmds[0]; + cmd.cmd_hi = field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_XFER_ARG); + + if dbp_is_direct && data_len > 0 { + cmd.cmd_lo |= COMMAND_PORT_DBP; + cmd.cmd_hi |= field_prep(COMMAND_PORT_ARG_DB, db.into()); + } + + if rnw { + cmd.cmd_hi |= field_prep(COMMAND_PORT_ARG_DATA_LEN, cmd.rx_len); + } else { + cmd.cmd_hi |= field_prep(COMMAND_PORT_ARG_DATA_LEN, cmd.tx_len); + } + + cmd.cmd_lo |= field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_XFER_CMD) + | field_prep(COMMAND_PORT_CMD, id.into()) + | field_prep(COMMAND_PORT_READ_TRANSFER, u32::from(rnw)) + | COMMAND_PORT_CP + | COMMAND_PORT_ROC + | COMMAND_PORT_TOC; + + if !is_broadcast { + cmd.cmd_lo |= field_prep(COMMAND_PORT_DEV_INDEX, u32::from(pos)); + } + + if id == I3C_CCC_SETHID || id == I3C_CCC_DEVCTRL { + cmd.cmd_lo |= field_prep(COMMAND_PORT_SPEED, SpeedI3c::I2cFmAsI3c as u32); + } + + let mut xfer = I3cXfer::new(&mut cmds[..]); + self.start_xfer(config, &mut xfer); + + if !xfer.done.wait_for_us(1_000_000_000, &mut self.yield_ns) { + self.enter_halt(true, config); + self.reset_ctrl(RESET_CTRL_XFER_QUEUES); + self.exit_halt(config); + let _ = config + .curr_xfer + .swap(core::ptr::null_mut(), Ordering::AcqRel); + } + + let ret = xfer.ret; + if ret == i32::try_from(RESPONSE_ERROR_IBA_NACK).map_err(|_| I3cDrvError::Invalid)? { + return Ok(()); + } + + if is_broadcast { + if let Some(ccc_rw) = payload.ccc.as_mut() { + if let Some(d) = ccc_rw.data.as_deref() { + ccc_rw.num_xfer = d.len(); + } + } + } + + match ret { + 0 => Ok(()), + _ => Err(I3cDrvError::Invalid), + } + } + + fn do_entdaa(&mut self, config: &mut I3cConfig, pos: u32) -> Result<(), I3cDrvError> { + let cmd = I3cCmd { + cmd_lo: field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_ADDR_ASSGN_CMD) + | field_prep(COMMAND_PORT_CMD, u32::from(I3C_CCC_ENTDAA)) + | field_prep(COMMAND_PORT_DEV_COUNT, 1) + | field_prep(COMMAND_PORT_DEV_INDEX, pos) + | COMMAND_PORT_ROC + | COMMAND_PORT_TOC, + cmd_hi: field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_XFER_ARG), + tx: None, + rx: None, + tx_len: 0, + rx_len: 0, + ret: 0, + }; + + let mut cmds = [cmd]; + let mut xfer = I3cXfer::new(&mut cmds[..]); + xfer.ret = -1; + + self.start_xfer(config, &mut xfer); + + if !xfer.done.wait_for_us(1_000_000_000, &mut self.yield_ns) { + self.enter_halt(true, config); + self.reset_ctrl(RESET_CTRL_XFER_QUEUES); + self.exit_halt(config); + let _ = config + .curr_xfer + .swap(core::ptr::null_mut(), Ordering::AcqRel); + return Err(I3cDrvError::Invalid); + } + + match xfer.ret { + 0 => Ok(()), + _ => Err(I3cDrvError::Invalid), + } + } + + fn priv_xfer_build_cmds<'a>( + &mut self, + cmds: &mut [I3cCmd<'a>], + msgs: &mut [I3cMsg<'a>], + pos: u8, + ) -> Result<(), I3cDrvError> { + let cmds_len = cmds.len(); + if cmds_len != msgs.len() { + return Err(I3cDrvError::Invalid); + } + + for i in 0..cmds_len { + let (is_read, ptr, len) = { + let m = &mut msgs[i]; + let is_read = (m.flags & I3C_MSG_READ) != 0; + + if is_read { + let buf = match m.buf.as_deref_mut() { + Some(b) if !b.is_empty() => b, + _ => return Err(I3cDrvError::Invalid), + }; + (true, buf.as_mut_ptr(), buf.len()) + } else { + let buf = match m.buf.as_deref() { + Some(b) if !b.is_empty() => b, + _ => return Err(I3cDrvError::Invalid), + }; + m.num_xfer = u32::try_from(buf.len()).map_err(|_| I3cDrvError::Invalid)?; + (false, buf.as_ptr().cast_mut(), buf.len()) + } + }; + + let cmd = &mut cmds[i]; + *cmd = I3cCmd { + cmd_hi: field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_XFER_ARG) + | field_prep( + COMMAND_PORT_ARG_DATA_LEN, + u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?, + ), + cmd_lo: field_prep( + COMMAND_PORT_TID, + u32::try_from(i).map_err(|_| I3cDrvError::Invalid)?, + ) | field_prep(COMMAND_PORT_DEV_INDEX, u32::from(pos)) + | COMMAND_PORT_ROC, + tx: None, + rx: None, + tx_len: 0, + rx_len: 0, + ret: 0, + }; + + if is_read { + let rx_slice: &'a mut [u8] = unsafe { core::slice::from_raw_parts_mut(ptr, len) }; + cmd.rx = Some(rx_slice); + cmd.rx_len = u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?; + cmd.cmd_lo |= COMMAND_PORT_READ_TRANSFER; + } else { + let tx_slice: &'a [u8] = + unsafe { core::slice::from_raw_parts(ptr.cast_const(), len) }; + cmd.tx = Some(tx_slice); + cmd.tx_len = u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?; + } + + let is_last = i + 1 == cmds_len; + if is_last { + cmd.cmd_lo |= COMMAND_PORT_TOC; + } + } + + Ok(()) + } + + fn priv_xfer( + &mut self, + config: &mut I3cConfig, + pid: u64, + msgs: &mut [I3cMsg], + ) -> Result<(), I3cDrvError> { + let pos_opt = config.attached.pos_of_pid(pid); + let pos: u8 = pos_opt.ok_or(I3cDrvError::NoDatPos)?; + + let mut cmds: heapless::Vec<I3cCmd, MAX_CMDS> = heapless::Vec::new(); + for _ in 0..msgs.len() { + cmds.push(I3cCmd { + cmd_lo: 0, + cmd_hi: 0, + tx: None, + rx: None, + tx_len: 0, + rx_len: 0, + ret: 0, + }) + .unwrap(); + } + + let ret = self.priv_xfer_build_cmds(cmds.as_mut_slice(), msgs, pos); + match ret { + Ok(()) => {} + Err(e) => return Err(e), + } + + let mut xfer = I3cXfer::new(cmds.as_mut_slice()); + self.start_xfer(config, &mut xfer); + + if !xfer.done.wait_for_us(1_000_000_000, &mut self.yield_ns) { + self.enter_halt(true, config); + self.reset_ctrl(RESET_CTRL_XFER_QUEUES); + self.exit_halt(config); + let _ = config + .curr_xfer + .swap(core::ptr::null_mut(), Ordering::AcqRel); + return Err(I3cDrvError::Timeout); + } + + for (i, m) in msgs.iter_mut().enumerate() { + if (m.flags & I3C_MSG_READ) != 0 { + m.actual_len = xfer.cmds[i].rx_len; + } + } + + match xfer.ret { + 0 => Ok(()), + _ => Err(I3cDrvError::Timeout), + } + } + + fn handle_ibi_sir(&mut self, config: &mut I3cConfig, addr: u8, len: usize) { + let pos = config.attached.pos_of_addr(addr); + if pos.is_none() { + { let ptr = self.i3c; self.drain_fifo(move || unsafe { (*ptr).i3cd018().read().bits() }, len); } + } + + let mut ibi_buf: [u8; 2] = [0u8; 2]; + let take = core::cmp::min(len, ibi_buf.len()); + self.rd_ibi_fifo(&mut ibi_buf[..take]); + let bus = self.bus_num as usize; + let _ = ibi_workq::i3c_ibi_work_enqueue_target_irq(bus, addr, &ibi_buf[..take]); + } + + fn handle_ibis(&mut self, config: &mut I3cConfig) { + let nibis = self.i3c().i3cd04c().read().ibistatuscnt().bits(); + + if nibis == 0 { + return; + } + + for _ in 0..nibis { + let reg = self.i3c().i3cd018().read().bits(); + + let ibi_id = field_get(reg, IBIQ_STATUS_IBI_ID, IBIQ_STATUS_IBI_ID_SHIFT); + let ibi_data_len = field_get( + reg, + IBIQ_STATUS_IBI_DATA_LEN, + IBIQ_STATUS_IBI_DATA_LEN_SHIFT, + ) as usize; + let ibi_addr = (ibi_id >> 1) & 0x7F; + let rnw = (ibi_id & 1) != 0; + if ibi_addr != 2 && rnw { + // sirq + self.handle_ibi_sir(config, ibi_addr as u8, ibi_data_len); + } else if ibi_addr == 2 && !rnw { + // hot-join + let bus = self.bus_num as usize; + let _ = ibi_workq::i3c_ibi_work_enqueue_hotjoin(bus); + } else { + // normal ibi + { let ptr = self.i3c; self.drain_fifo(move || unsafe { (*ptr).i3cd018().read().bits() }, ibi_data_len); } + } + } + } +} + +impl<'a, Y: FnMut(u32)> HardwareTarget for Ast1060I3c<'a, Y> { + fn target_tx_write(&mut self, buf: &[u8]) { + self.wr_tx_fifo(buf); + let cmd = field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_SLAVE_DATA_CMD) + | field_prep( + COMMAND_PORT_ARG_DATA_LEN, + u32::try_from(buf.len()).map_or(0, |v| v), + ) + | field_prep(COMMAND_PORT_TID, Tid::TargetRdData as u32); + + self.i3c().i3cd00c().write(|w| unsafe { w.bits(cmd) }); + } + + fn target_ibi_raise_hj(&self, config: &mut I3cConfig) -> Result<(), I3cDrvError> { + if !config.is_secondary { + return Err(I3cDrvError::Invalid); + } + let hj_support = self.i3c().i3cd008().read().slvhjcap().bit(); + if !hj_support { + return Err(I3cDrvError::Invalid); + } + + let addr_valid = self.i3c().i3cd004().read().dynamic_addr_valid().bit(); + if addr_valid { + return Err(I3cDrvError::Access); + } + + self.i3c().i3cd038().write(|w| unsafe { w.bits(8) }); // set HJ request + + Ok(()) + } + + fn target_handle_response_ready(&mut self, config: &mut I3cConfig) { + let nresp = self.i3c().i3cd04c().read().respbufblr().bits(); + + for _ in 0..nresp { + let resp = self.i3c().i3cd010().read().bits(); + + let tid = field_get(resp, RESPONSE_PORT_TID_MASK, RESPONSE_PORT_TID_SHIFT) as usize; + let rx_len = field_get( + resp, + RESPONSE_PORT_DATA_LEN_MASK, + RESPONSE_PORT_DATA_LEN_SHIFT, + ) as usize; + let err = field_get( + resp, + RESPONSE_PORT_ERR_STATUS_MASK, + RESPONSE_PORT_ERR_STATUS_SHIFT, + ); + + if err != 0 { + self.enter_halt(false, config); + self.reset_ctrl(RESET_CTRL_QUEUES); + self.exit_halt(config); + continue; + } + + if rx_len != 0 { + let mut buf: [u8; 256] = [0u8; 256]; + self.rd_rx_fifo(&mut buf[..rx_len]); + } + + if tid == Tid::TargetIbi as usize { + config.target_ibi_done.complete(); + } + + if tid == Tid::TargetRdData as usize { + config.target_data_done.complete(); + } + } + } + + fn target_pending_read_notify( + &mut self, + config: &mut I3cConfig, + buf: &[u8], + notifier: &mut I3cIbi, + ) -> Result<(), I3cDrvError> { + let reg = self.i3c().i3cd038().read().bits(); + if !(config.sir_allowed_by_sw && (reg & SLV_EVENT_CTRL_SIR_EN != 0)) { + return Err(I3cDrvError::Access); + } + + let Some(mdb) = notifier.first_byte() else { + return Err(I3cDrvError::Invalid); + }; + + self.set_ibi_mdb(mdb); + if let Some(p) = notifier.payload { + if !p.is_empty() { + self.wr_tx_fifo(p); + } + } + + let payload_len = u32::try_from(notifier.payload.map_or(0, <[u8]>::len)) + .map_err(|_| I3cDrvError::Invalid)?; + let cmd: u32 = field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_SLAVE_DATA_CMD) + | field_prep(COMMAND_PORT_ARG_DATA_LEN, payload_len) + | field_prep(COMMAND_PORT_TID, Tid::TargetIbi as u32); + self.i3c().i3cd00c().write(|w| unsafe { w.bits(cmd) }); + + config.target_ibi_done.reset(); + + self.i3c() + .i3cd01c() + .modify(|_, w| unsafe { w.response_buffer_threshold_value().bits(0) }); + + self.target_tx_write(buf); + config.target_data_done.reset(); + + self.i3c().i3cd08c().write(|w| w.sir().set_bit()); + + if !config + .target_ibi_done + .wait_for_us(1_000_000_000, &mut self.yield_ns) + { + self.enter_halt(false, config); + self.reset_ctrl(RESET_CTRL_QUEUES); + self.exit_halt(config); + return Err(I3cDrvError::IoError); + } + + if !config + .target_data_done + .wait_for_us(1_000_000_000, &mut self.yield_ns) + { + self.i3c_disable(config.is_secondary); + self.reset_ctrl(RESET_CTRL_QUEUES); + self.i3c_enable(config); + return Err(I3cDrvError::Timeout); + } + + Ok(()) + } + + fn target_handle_ccc_update(&mut self, config: &mut I3cConfig) { + let event = self.i3c().i3cd038().read().bits(); + self.i3c().i3cd038().write(|w| unsafe { w.bits(event) }); + let reg = self.i3c().i3cd054().read().cmtfrstatus().bits(); + if reg == CM_TFR_STS_TARGET_HALT { + self.enter_halt(true, config); + self.exit_halt(config); + } + } +}
diff --git a/target/ast10x0/peripherals/i3c/ibi.rs b/target/ast10x0/peripherals/i3c/ibi.rs new file mode 100644 index 0000000..e8f5a42 --- /dev/null +++ b/target/ast10x0/peripherals/i3c/ibi.rs
@@ -0,0 +1,176 @@ +// Licensed under the Apache-2.0 license + +//! I3C In-Band Interrupt (IBI) Work Queue +//! +//! Handles IBI events including Hot-Join, SIR (Slave Interrupt Request), +//! and target dynamic address assignment. + +use core::cell::RefCell; +use critical_section::Mutex; +use heapless::spsc::Queue; + +/// IBI queue depth +const IBIQ_DEPTH: usize = 16; +/// Maximum IBI payload data size +const IBI_DATA_MAX: u8 = 16; + +// ============================================================================= +// IBI Work Item +// ============================================================================= + +/// IBI work item representing an interrupt event +#[derive(Debug, Clone, Copy)] +pub enum IbiWork { + /// Hot-Join request from a device + HotJoin, + /// Slave Interrupt Request + Sirq { + /// Address of requesting device + addr: u8, + /// Length of payload data + len: u8, + /// Payload data + data: [u8; IBI_DATA_MAX as usize], + }, + /// Target dynamic address assignment notification + TargetDaAssignment, +} + +// ============================================================================= +// Static Queue Storage +// ============================================================================= + +static mut IBIQ_BUFS: [Queue<IbiWork, IBIQ_DEPTH>; 4] = + [Queue::new(), Queue::new(), Queue::new(), Queue::new()]; + +struct IbiBus { + prod: Option<heapless::spsc::Producer<'static, IbiWork>>, + cons: Option<heapless::spsc::Consumer<'static, IbiWork>>, +} + +static IBI_WORKQS: [Mutex<RefCell<IbiBus>>; 4] = [ + Mutex::new(RefCell::new(IbiBus { + prod: None, + cons: None, + })), + Mutex::new(RefCell::new(IbiBus { + prod: None, + cons: None, + })), + Mutex::new(RefCell::new(IbiBus { + prod: None, + cons: None, + })), + Mutex::new(RefCell::new(IbiBus { + prod: None, + cons: None, + })), +]; + +// ============================================================================= +// Queue Management +// ============================================================================= + +/// Ensure the IBI queue for a bus has been split into producer/consumer. +/// +/// Returns `false` if bus index is out of range. +fn ensure_ibiq_split(bus: usize) -> bool { + let Some(workq) = IBI_WORKQS.get(bus) else { + return false; + }; + + critical_section::with(|cs| { + let mut b = workq.borrow(cs).borrow_mut(); + if b.prod.is_none() || b.cons.is_none() { + // SAFETY: Each bus's queue is only split once and we're in a critical section. + // The static mut is only accessed here, protected by the Mutex + critical section. + let (p, c) = unsafe { IBIQ_BUFS[bus].split() }; + b.prod = Some(p); + b.cons = Some(c); + } + }); + true +} + +/// Get the IBI work queue consumer for a bus +/// +/// Returns `None` if bus index is out of range or consumer already taken. +#[must_use] +pub fn i3c_ibi_workq_consumer( + bus: usize, +) -> Option<heapless::spsc::Consumer<'static, IbiWork>> { + if !ensure_ibiq_split(bus) { + return None; + } + + let workq = IBI_WORKQS.get(bus)?; + + critical_section::with(|cs| { + let mut b = workq.borrow(cs).borrow_mut(); + b.cons.take() + }) +} + +// ============================================================================= +// Enqueue Functions +// ============================================================================= + +/// Enqueue a target dynamic address assignment notification +#[must_use] +pub fn i3c_ibi_work_enqueue_target_da_assignment(bus: usize) -> bool { + if !ensure_ibiq_split(bus) { + return false; + } + critical_section::with(|cs| { + if let Some(workq) = IBI_WORKQS.get(bus) { + let mut ibi_bus = workq.borrow(cs).borrow_mut(); + if let Some(prod) = ibi_bus.prod.as_mut() { + return prod.enqueue(IbiWork::TargetDaAssignment).is_ok(); + } + } + false + }) +} + +/// Enqueue a Hot-Join notification +#[must_use] +pub fn i3c_ibi_work_enqueue_hotjoin(bus: usize) -> bool { + if !ensure_ibiq_split(bus) { + return false; + } + critical_section::with(|cs| { + if let Some(workq) = IBI_WORKQS.get(bus) { + let mut ibi_bus = workq.borrow(cs).borrow_mut(); + if let Some(prod) = ibi_bus.prod.as_mut() { + return prod.enqueue(IbiWork::HotJoin).is_ok(); + } + } + false + }) +} + +/// Enqueue a target interrupt (SIR) notification +#[must_use] +pub fn i3c_ibi_work_enqueue_target_irq(bus: usize, addr: u8, data: &[u8]) -> bool { + if !ensure_ibiq_split(bus) { + return false; + } + let mut ibi_buf = [0u8; IBI_DATA_MAX as usize]; + let take = core::cmp::min(IBI_DATA_MAX as usize, data.len()); + ibi_buf[..take].copy_from_slice(&data[..take]); + critical_section::with(|cs| { + if let Some(workq) = IBI_WORKQS.get(bus) { + let mut i3c_bus = workq.borrow(cs).borrow_mut(); + if let Some(prod) = i3c_bus.prod.as_mut() { + return prod + .enqueue(IbiWork::Sirq { + addr, + len: u8::try_from(take).unwrap_or(IBI_DATA_MAX), + data: ibi_buf, + }) + .is_ok(); + } + } + false + }) +}
diff --git a/target/ast10x0/peripherals/i3c/mod.rs b/target/ast10x0/peripherals/i3c/mod.rs new file mode 100644 index 0000000..7703e8f --- /dev/null +++ b/target/ast10x0/peripherals/i3c/mod.rs
@@ -0,0 +1,97 @@ +// Licensed under the Apache-2.0 license + +//! AST1060 I3C bare-metal driver core +//! +//! # Overview +//! +//! This module provides a hardware abstraction layer for I3C controllers, +//! supporting both controller (master) and target (slave) modes. +//! +//! # Architecture +//! +//! - [`controller`]: Main I3C controller abstraction +//! - [`config`]: Configuration types and device management +//! - [`types`]: Core data types (commands, messages, transfers) +//! - [`error`]: Error types with trait implementations +//! - [`constants`]: Hardware register definitions +//! - [`hardware`]: Hardware interface +//! - [`ccc`]: Common Command Code operations +//! - [`ibi`]: In-Band Interrupt work queue +//! - [`hal_impl`]: External trait implementations (embedded-hal, proposed-traits) +//! +//! # Features +//! +//! - I3C SDR and HDR modes +//! - Dynamic address assignment (ENTDAA) +//! - In-Band Interrupts (IBI) +//! - Hot-Join support +//! - Target mode operation +//! - Legacy I2C device support +//! +//! # Usage Example +//! +//! ```rust,no_run +//! use aspeed_rust::i3c_refactored::*; +//! +//! // Create controller with hardware implementation +//! let mut ctrl = I3cController::new(hw, I3cConfig::new(), logger); +//! ctrl.init(); +//! +//! // Attach a device +//! ctrl.attach_i3c_dev(pid, dynamic_addr, slot)?; +//! ``` + +// Private module declarations +pub mod ccc; +pub mod config; +pub mod constants; +pub mod controller; +pub mod error; +pub mod hal_impl; +pub mod hardware; +pub mod ibi; +pub mod types; + +// ============================================================================= +// Public Re-exports +// ============================================================================= + +// Controller +pub use controller::I3cController; + +// Error types +pub use error::{CccErrorKind, I3cError, Result}; + +// Configuration +pub use config::{ + AddrBook, Attached, CommonCfg, CommonState, DeviceEntry, I3cConfig, I3cTargetConfig, ResetSpec, + I3C_MAX_CORE_CLK, I3C_MIN_CORE_CLK_HDR, I3C_MIN_CORE_CLK_SDR, +}; + +// Core types +pub use types::{ + Completion, DevKind, I3cCmd, I3cDeviceId, I3cIbi, I3cIbiType, I3cMsg, I3cPid, I3cStatus, + I3cXfer, SpeedI2c, SpeedI3c, Tid, +}; + +// Hardware interface +pub use hardware::{ + dispatch_i3c_irq, register_i3c_irq_handler, HardwareClock, HardwareCore, HardwareFifo, + HardwareInterface, HardwareRecovery, HardwareTarget, HardwareTransfer, +}; + +// CCC operations +pub use ccc::{ + ccc_events_all_set, ccc_events_set, ccc_getbcr, ccc_getpid, ccc_getstatus, ccc_getstatus_fmt1, + ccc_rstact_all, ccc_rstdaa_all, ccc_setnewda, Ccc, CccPayload, CccRstActDefByte, + CccTargetPayload, GetStatusDefByte, GetStatusFormat, GetStatusResp, +}; + +// IBI work queue +pub use ibi::{ + i3c_ibi_work_enqueue_hotjoin, i3c_ibi_work_enqueue_target_da_assignment, + i3c_ibi_work_enqueue_target_irq, i3c_ibi_workq_consumer, IbiWork, +}; + +// Constants (wildcard export for convenience) +pub use constants::*;
diff --git a/target/ast10x0/peripherals/i3c/types.rs b/target/ast10x0/peripherals/i3c/types.rs new file mode 100644 index 0000000..814174e --- /dev/null +++ b/target/ast10x0/peripherals/i3c/types.rs
@@ -0,0 +1,390 @@ +// Licensed under the Apache-2.0 license + +//! I3C core types +//! +//! This module contains the core data types used throughout the I3C subsystem. + +use core::sync::atomic::{AtomicBool, Ordering}; + +// ============================================================================= +// Speed Enumerations +// ============================================================================= + +/// I3C transfer speed modes +#[repr(u32)] +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum SpeedI3c { + /// SDR0 - Standard Data Rate 0 (12.5 `MHz` max) + Sdr0 = 0x0, + /// SDR1 - Standard Data Rate 1 (8 `MHz` max) + Sdr1 = 0x1, + /// SDR2 - Standard Data Rate 2 (6 `MHz` max) + Sdr2 = 0x2, + /// SDR3 - Standard Data Rate 3 (4 `MHz` max) + Sdr3 = 0x3, + /// SDR4 - Standard Data Rate 4 (2 `MHz` max) + Sdr4 = 0x4, + /// HDR-TS - High Data Rate Ternary Symbol + HdrTs = 0x5, + /// HDR-DDR - High Data Rate Double Data Rate + HdrDdr = 0x6, + /// I2C FM as I3C fallback + I2cFmAsI3c = 0x7, +} + +/// I2C transfer speed modes +#[repr(u32)] +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum SpeedI2c { + /// Fast Mode (400 kHz) + Fm = 0x0, + /// Fast Mode Plus (1 `MHz`) + Fmp = 0x1, +} + +// ============================================================================= +// Transaction ID +// ============================================================================= + +/// Transaction ID for tracking transfers +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum Tid { + /// Target IBI transaction + TargetIbi = 0x1, + /// Target read data transaction + TargetRdData = 0x2, + /// Target master write transaction + TargetMasterWr = 0x8, + /// Target master default transaction + TargetMasterDef = 0xF, +} + +// ============================================================================= +// Transfer Status +// ============================================================================= + +/// I3C operation status +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum I3cStatus { + /// Operation completed successfully + Ok, + /// Operation timed out + Timeout, + /// Bus is busy + Busy, + /// Operation is pending + /// Invalid operation or parameter + Invalid, + /// Pending status + Pending, +} + +// ============================================================================= +// Transfer Structures +// ============================================================================= + +/// I3C command descriptor +#[derive(Debug)] +pub struct I3cCmd<'a> { + /// Lower 32 bits of command + pub cmd_lo: u32, + /// Upper 32 bits of command + pub cmd_hi: u32, + /// Transmit data buffer (optional) + pub tx: Option<&'a [u8]>, + /// Receive data buffer (optional) + pub rx: Option<&'a mut [u8]>, + /// Transmit length in bytes + pub tx_len: u32, + /// Receive length in bytes + pub rx_len: u32, + /// Return code from hardware + pub ret: i32, +} + +impl I3cCmd<'_> { + /// Create a new command with default values + #[must_use] + pub const fn new() -> Self { + Self { + cmd_lo: 0, + cmd_hi: 0, + tx: None, + rx: None, + tx_len: 0, + rx_len: 0, + ret: 0, + } + } +} + +impl Default for I3cCmd<'_> { + fn default() -> Self { + Self::new() + } +} + +/// I3C message descriptor +pub struct I3cMsg<'a> { + /// Data buffer + pub buf: Option<&'a mut [u8]>, + /// Actual bytes transferred + pub actual_len: u32, + /// Number of transfers completed + pub num_xfer: u32, + /// Message flags (read/write/stop) + pub flags: u8, + /// HDR mode + pub hdr_mode: u8, + /// HDR command mode + pub hdr_cmd_mode: u8, +} + +impl I3cMsg<'_> { + /// Create a new message with default values + #[must_use] + pub const fn new() -> Self { + Self { + buf: None, + actual_len: 0, + num_xfer: 0, + flags: 0, + hdr_mode: 0, + hdr_cmd_mode: 0, + } + } + + /// Check if this is a read message + #[inline] + #[must_use] + pub const fn is_read(&self) -> bool { + (self.flags & super::constants::I3C_MSG_READ) != 0 + } + + /// Check if this message should terminate with STOP + #[inline] + #[must_use] + pub const fn has_stop(&self) -> bool { + (self.flags & super::constants::I3C_MSG_STOP) != 0 + } +} + +impl Default for I3cMsg<'_> { + fn default() -> Self { + Self::new() + } +} + +/// I3C transfer descriptor with multiple commands +pub struct I3cXfer<'cmds, 'buf> { + /// Array of commands for this transfer + pub cmds: &'cmds mut [I3cCmd<'buf>], + /// Return code from transfer + pub ret: i32, + /// Completion signaling primitive + pub done: Completion, +} + +impl<'cmds, 'buf> I3cXfer<'cmds, 'buf> { + /// Create a new transfer with the given commands + #[must_use] + pub fn new(cmds: &'cmds mut [I3cCmd<'buf>]) -> Self { + Self { + cmds, + ret: 0, + done: Completion::new(), + } + } + + /// Get the number of commands in this transfer + #[inline] + #[must_use] + pub fn ncmds(&self) -> usize { + self.cmds.len() + } +} + +// ============================================================================= +// Device Identification +// ============================================================================= + +/// I3C Provisional ID (48-bit) +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct I3cPid(pub u64); + +impl I3cPid { + /// Create a new PID from raw value + #[must_use] + pub const fn new(pid: u64) -> Self { + Self(pid) + } + + /// Get the manufacturer ID (bits 47:33) + #[must_use] + pub const fn manuf_id(self) -> u16 { + ((self.0 >> 33) & 0x1FFF) as u16 + } + + /// Check if lower 32 bits are random (bit 32) + #[must_use] + pub const fn has_random_lower32(self) -> bool { + (self.0 & (1u64 << 32)) != 0 + } + + /// Get raw PID value + #[inline] + #[must_use] + pub const fn raw(self) -> u64 { + self.0 + } +} + +/// I3C device identifier +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct I3cDeviceId { + /// Provisional ID + pub pid: I3cPid, +} + +impl I3cDeviceId { + /// Create a new device ID from raw PID + #[must_use] + pub const fn new(pid: u64) -> Self { + Self { pid: I3cPid(pid) } + } +} + +// ============================================================================= +// IBI (In-Band Interrupt) Types +// ============================================================================= + +/// Type of In-Band Interrupt +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum I3cIbiType { + /// Target-initiated interrupt + TargetIntr, + /// Controller role request + ControllerRoleRequest, + /// Hot-join request + HotJoin, + /// Workqueue callback + WorkqueueCb, +} + +/// In-Band Interrupt descriptor +#[derive(Clone, Copy, Debug)] +pub struct I3cIbi<'a> { + /// Type of IBI + pub ibi_type: I3cIbiType, + /// Optional payload data + pub payload: Option<&'a [u8]>, +} + +impl<'a> I3cIbi<'a> { + /// Create a new IBI descriptor + #[must_use] + pub const fn new(ibi_type: I3cIbiType) -> Self { + Self { + ibi_type, + payload: None, + } + } + + /// Create an IBI with payload + #[must_use] + pub const fn with_payload(ibi_type: I3cIbiType, payload: &'a [u8]) -> Self { + Self { + ibi_type, + payload: Some(payload), + } + } + + /// Get payload length + #[inline] + #[must_use] + pub fn payload_len(&self) -> u8 { + self.payload.map_or(0, |p| { + u8::try_from(p.len().min(u8::MAX as usize)).unwrap_or(u8::MAX) + }) + } + + /// Get first byte of payload + #[must_use] + pub fn first_byte(&self) -> Option<u8> { + self.payload.and_then(|p| p.first().copied()) + } +} + +// ============================================================================= +// Completion Primitive +// ============================================================================= + +/// Synchronization primitive for signaling completion +pub struct Completion { + done: AtomicBool, +} + +impl Default for Completion { + fn default() -> Self { + Self::new() + } +} + +impl Completion { + /// Create a new completion in non-signaled state + #[must_use] + pub const fn new() -> Self { + Self { + done: AtomicBool::new(false), + } + } + + /// Reset to non-signaled state + #[inline] + pub fn reset(&self) { + self.done.store(false, Ordering::Release); + } + + /// Signal completion + #[inline] + pub fn complete(&self) { + self.done.store(true, Ordering::Release); + // Wake any waiting cores + cortex_m::asm::sev(); + } + + /// Check if completed + #[inline] + #[must_use] + pub fn is_completed(&self) -> bool { + self.done.load(Ordering::Acquire) + } + + /// Wait for completion with timeout + /// + /// Returns `true` if completed, `false` if timed out. + pub fn wait_for_us<Y: FnMut(u32)>(&self, timeout_us: u32, yield_ns: &mut Y) -> bool { + let mut left = timeout_us; + while !self.is_completed() { + if left == 0 { + return false; + } + yield_ns(1000); + left -= 1; + } + true + } +} + +// ============================================================================= +// Device Kind +// ============================================================================= + +/// Device type on the I3C bus +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DevKind { + /// Native I3C device + I3c, + /// Legacy I2C device + I2c, +}
diff --git a/target/ast10x0/peripherals/lib.rs b/target/ast10x0/peripherals/lib.rs index 4ae0fac..5cb465d 100644 --- a/target/ast10x0/peripherals/lib.rs +++ b/target/ast10x0/peripherals/lib.rs
@@ -3,7 +3,9 @@ #![no_std] +pub mod common; pub mod i2c; +pub mod i3c; pub mod scu; pub mod smc; pub mod uart;
diff --git a/third_party/crates_io/Cargo.toml b/third_party/crates_io/Cargo.toml index c878162..10f0137 100644 --- a/third_party/crates_io/Cargo.toml +++ b/third_party/crates_io/Cargo.toml
@@ -42,6 +42,7 @@ cortex-m = "0.7.7" cortex-m-rt = "0.7.5" cortex-m-semihosting = "0.5.0" +critical-section = "1.2" embedded-hal = "1.0" embedded-hal-async = "1.0" embedded-hal-nb = "1.0" @@ -51,6 +52,7 @@ fugit = "0.3.7" openprot-hal-blocking = { git = "https://github.com/rusty1968/openprot.git", rev = "c6cd23a" } heapless = { version = "0.9", default-features = false } +proposed-traits = { git = "https://github.com/rusty1968/proposed_traits.git", rev = "85641310df5a5276c67f81621b104322cff0286c" } mctp = { git = "https://github.com/CodeConstruct/mctp-rs.git" } mctp-lib = { git = "https://github.com/OpenPRoT/mctp-lib.git", branch = "9e-buildup" } # Pin to match Hubris ecosystem