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| <div id="projectname">CMSIS-Core (Cortex-A) |
|  <span id="projectnumber">Version 1.1.4</span> |
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| <div class="title">Device Header File <device.h> </div> </div> |
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| <div class="contents"> |
| <div class="textblock"><p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the following sections that are device specific:</p> |
| <ul> |
| <li><a class="el" href="device_h_pg.html#irqn_defs">Interrupt Number Definition</a> provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.</li> |
| <li><a class="el" href="device_h_pg.html#config_perifs">Configuration of the Processor and Core Peripherals</a> reflect the features of the device.</li> |
| <li><a class="el" href="device_h_pg.html#access_perifs">Device Peripheral Access Layer</a> definitions for the <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.</li> |
| <li><b>Access Functions for Peripherals (optioal)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.</li> |
| </ul> |
| <h1><a class="anchor" id="irqn_defs"></a> |
| Interrupt Number Definition</h1> |
| <h1><a class="anchor" id="config_perifs"></a> |
| Configuration of the Processor and Core Peripherals</h1> |
| <h1><a class="anchor" id="access_perifs"></a> |
| Device Peripheral Access Layer</h1> |
| <p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the following sections that are device specific:</p> |
| <ul> |
| <li><a class="el" href="device_h_pg.html#irqn_defs">Interrupt Number Definition</a> provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.</li> |
| <li><a class="el" href="device_h_pg.html#config_perifs">Configuration of the Processor and Core Peripherals</a> reflect the features of the device.</li> |
| <li><a class="el" href="device_h_pg.html#access_perifs">Device Peripheral Access Layer</a> definitions for the <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.</li> |
| <li><b>Access Functions for Peripherals (optional)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.</li> |
| </ul> |
| <p><a href="Modules.html"><b>Reference</b> </a> describes the standard features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</p> |
| <h1><a class="anchor" id="interrupt_number_sec"></a> |
| Interrupt Number Definition</h1> |
| <p><a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the enumeration <a class="el" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all exceptions and interrupts of the device. For devices implementing an Arm GIC these are defined as:</p> |
| <ul> |
| <li>IRQn 0-15 represents software generated interrupts (SGI), local to each processor core.</li> |
| <li>IRQn 16-31 represents private peripheral interrupts (PPI), local to each processor core.</li> |
| <li>IRQn 32-1019 represents shared peripheral interrupts (SPI), routable to all processor cores.</li> |
| <li>IRQn 1020-1023 represents special interrupts, refer to the GIC Architecture Specification.</li> |
| </ul> |
| <p><b>Example:</b> </p> |
| <p>The following example shows the extension of the interrupt vector table for Cortex-A9 class device.</p> |
| <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">enum</span> IRQn</div> |
| <div class="line">{</div> |
| <div class="line"><span class="comment">/****** SGI Interrupts Numbers ****************************************/</span></div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a056f32088a9c8bdb9309b005dfeb648e">SGI0_IRQn</a> = 0, </div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ab335b8b84021cd5714807d6cd2404c3b">SGI1_IRQn</a> = 1,</div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a2a1cc64c0a2dc0e7f339fbf21c9a2b07">SGI2_IRQn</a> = 2,</div> |
| <div class="line"> : :</div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ac6958eebc9d41a42c739de555cad2321">SGI15_IRQn</a> = 15,</div> |
| <div class="line"></div> |
| <div class="line"><span class="comment">/****** Cortex-A9 Processor Exceptions Numbers ****************************************/</span></div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a69c74fffb53f9a8739613443943a94c3">GlobalTimer_IRQn</a> = 27, </div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a116d3d8a9fcc5fef99becc9d25a56249">PrivTimer_IRQn</a> = 29, </div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8aeb45b2fc32150bf94ecf305ee223f28f">PrivWatchdog_IRQn</a> = 30, </div> |
| <div class="line"><span class="comment">/****** Platform Exceptions Numbers ***************************************************/</span></div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8a3f04766f3177f0152623a86e39ccef06">Watchdog_IRQn</a> = 32, </div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8adffcd012ea2c7bf76124965d8506df72">Timer0_IRQn</a> = 34, </div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ad0611a4c93162877ed3eb622f49e14a3">Timer1_IRQn</a> = 35, </div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8abdd513b1533957e93fe0d7f26024d28e">RTClock_IRQn</a> = 36, </div> |
| <div class="line"> <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8ae9122b85b58f7c24033a8515615a7b74">UART0_IRQn</a> = 37, </div> |
| <div class="line"> : :</div> |
| <div class="line"> : :</div> |
| <div class="line">} <a class="code" href="ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>;</div> |
| </div><!-- fragment --><h1><a class="anchor" id="core_config_sect"></a> |
| Configuration of the Processor and Core Peripherals</h1> |
| <p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> configures the Cortex-A processor and the core peripherals with <em>#defines</em> that are set prior to including the file <b>core_<cpu>.h</b>.</p> |
| <p>The following tables list the <em>#defines</em> along with the possible values for each processor core. If these <em>#defines</em> are missing default values are used.</p> |
| <table class="cmtable"> |
| <tr> |
| <th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> |
| <tr> |
| <td>__CM0_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> |
| <tr> |
| <td>__CORTEX_A </td><td>5, 7, 9 </td><td>(n/a) </td><td>Core type number </td></tr> |
| <tr> |
| <td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if an FPU is present or not </td></tr> |
| <tr> |
| <td>__GIC_PRESENT </td><td>0 ..1 </td><td>Defines if an GIC is present or not </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> |
| <tr> |
| <td>__TIM_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a private timer is present or not </td></tr> |
| <tr> |
| <td>__L2C_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a level 2 cache controller is present or not </td></tr> |
| </table> |
| <p><b>Example</b> </p> |
| <p>The following code exemplifies the configuration of the Cortex-A9 Processor and Core Peripherals.</p> |
| <div class="fragment"><div class="line"><span class="preprocessor">#define __CA_REV 0x0000U </span></div> |
| <div class="line"><span class="preprocessor">#define __CORTEX_A 9U </span></div> |
| <div class="line"><span class="preprocessor">#define __FPU_PRESENT 1U </span></div> |
| <div class="line"><span class="preprocessor">#define __GIC_PRESENT 1U </span></div> |
| <div class="line"><span class="preprocessor">#define __TIM_PRESENT 0U </span></div> |
| <div class="line"><span class="preprocessor">#define __L2C_PRESENT 0U </span></div> |
| <div class="line"><span class="preprocessor">:</span></div> |
| <div class="line"><span class="preprocessor"></span>:</div> |
| <div class="line"><span class="preprocessor">#include "<a class="code" href="core__ca_8h.html">core_ca.h</a>"</span> <span class="comment">/* Cortex-A processor and core peripherals */</span></div> |
| </div><!-- fragment --><h1><a class="anchor" id="core_version_sect"></a> |
| CMSIS Version and Processor Information</h1> |
| <p>Defines in the core_<em>cpu</em>.h file identify the version of the CMSIS-Core-A and the processor used. The following shows the defines in the various core_<em>cpu</em>.h files that may be used in the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> to verify a minimum version or ensure that the right processor core is used.</p> |
| <div class="fragment"><div class="line"><span class="preprocessor">#define __CA_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS Core main version */</span><span class="preprocessor"></span></div> |
| <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CA_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS Core sub version */</span><span class="preprocessor"></span></div> |
| <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \</span></div> |
| <div class="line"><span class="preprocessor"> __CA_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS Core version number */</span><span class="preprocessor"></span></div> |
| </div><!-- fragment --><h1><a class="anchor" id="device_access"></a> |
| Device Peripheral Access Layer</h1> |
| <p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains for each peripheral:</p> |
| <ul> |
| <li>Register Layout Typedef</li> |
| <li>Base Address</li> |
| <li>Access Definitions</li> |
| </ul> |
| <p>The section <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> shows examples for peripheral definitions.</p> |
| <h1><a class="anchor" id="device_h_sec"></a> |
| Device.h Template File</h1> |
| <p>The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> may contain functions to access device-specific peripherals. The <a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> which is provided as part of the CMSIS specification is shown below.</p> |
| <pre class="fragment">/**************************************************************************//** |
| * @file <Device>.h |
| * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File |
| * @version V1.00 |
| * @date 10. January 2018 |
| ******************************************************************************/ |
| /* |
| * Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| * |
| * Licensed under the Apache License, Version 2.0 (the License); you may |
| * not use this file except in compliance with the License. |
| * You may obtain a copy of the License at |
| * |
| * www.apache.org/licenses/LICENSE-2.0 |
| * |
| * Unless required by applicable law or agreed to in writing, software |
| * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| * See the License for the specific language governing permissions and |
| * limitations under the License. |
| */ |
| |
| #ifndef <Device>_H /* ToDo: replace '<Device>' with your device name */ |
| #define <Device>_H |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| /* ToDo: replace '<Vendor>' with vendor name; add your doxyGen comment */ |
| /** @addtogroup <Vendor> |
| * @{ |
| */ |
| |
| |
| /* ToDo: replace '<Device>' with device name; add your doxyGen comment */ |
| /** @addtogroup <Device> |
| * @{ |
| */ |
| |
| |
| /** @addtogroup Configuration_of_CMSIS |
| * @{ |
| */ |
| |
| |
| /* =========================================================================================================================== */ |
| /* ================ Interrupt Number Definition ================ */ |
| /* =========================================================================================================================== */ |
| |
| typedef enum IRQn |
| { |
| /* ======================================= ARM Cortex-A Specific Interrupt Numbers ========================================= */ |
| |
| /* Software Generated Interrupts */ |
| SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ |
| SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ |
| SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ |
| SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ |
| SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ |
| SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ |
| SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ |
| SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ |
| SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ |
| SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ |
| SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ |
| SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ |
| SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ |
| SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ |
| SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ |
| SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ |
| |
| /* Private Peripheral Interrupts */ |
| VirtualMaintenanceInterrupt_IRQn = 25, /*!< Virtual Maintenance Interrupt */ |
| HypervisorTimer_IRQn = 26, /*!< Hypervisor Timer Interrupt */ |
| VirtualTimer_IRQn = 27, /*!< Virtual Timer Interrupt */ |
| Legacy_nFIQ_IRQn = 28, /*!< Legacy nFIQ Interrupt */ |
| SecurePhysicalTimer_IRQn = 29, /*!< Secure Physical Timer Interrupt */ |
| NonSecurePhysicalTimer_IRQn = 30, /*!< Non-Secure Physical Timer Interrupt */ |
| Legacy_nIRQ_IRQn = 31, /*!< Legacy nIRQ Interrupt */ |
| |
| /* Shared Peripheral Interrupts */ |
| /* ToDo: add here your device specific external interrupt numbers */ |
| <DeviceInterrupt>_IRQn = 0, /*!< Device Interrupt */ |
| |
| } IRQn_Type; |
| |
| |
| /* =========================================================================================================================== */ |
| /* ================ Processor and Core Peripheral Section ================ */ |
| /* =========================================================================================================================== */ |
| |
| /* =========================== Configuration of the Arm Cortex-A Processor and Core Peripherals ============================ */ |
| /* ToDo: set the defines according your Device */ |
| /* ToDo: define the correct core revision |
| 5U if your device is a CORTEX-A5 device |
| 7U if your device is a CORTEX-A7 device |
| 9U if your device is a CORTEX-A9 device */ |
| #define __CORTEX_A #U /*!< Cortex-A# Core */ |
| #define __CA_REV 0x0000U /*!< Core revision r0p0 */ |
| /* ToDo: define the correct core features for the <Device> */ |
| #define __FPU_PRESENT 1U /*!< Set to 1 if FPU is present */ |
| #define __GIC_PRESENT 1U /*!< Set to 1 if GIC is present */ |
| #define __TIM_PRESENT 1U /*!< Set to 1 if TIM is present */ |
| #define __L2C_PRESENT 1U /*!< Set to 1 if L2C is present */ |
| |
| /** @} */ /* End of group Configuration_of_CMSIS */ |
| |
| /* ToDo: include the correct core_ca#.h file |
| core_ca5.h if your device is a CORTEX-A5 device |
| core_ca7.h if your device is a CORTEX-A7 device |
| core_ca9.h if your device is a CORTEX-A9 device */ |
| #include <core_ca#.h> /*!< Arm Cortex-A# processor and core peripherals */ |
| /* ToDo: include your system_<Device>.h file |
| replace '<Device>' with your device name */ |
| #include "system_<Device>.h" /*!< <Device> System */ |
| |
| |
| /* ======================================== Start of section using anonymous unions ======================================== */ |
| #if defined (__CC_ARM) |
| #pragma push |
| #pragma anon_unions |
| #elif defined (__ICCARM__) |
| #pragma language=extended |
| #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| #pragma clang diagnostic push |
| #pragma clang diagnostic ignored "-Wc11-extensions" |
| #pragma clang diagnostic ignored "-Wreserved-id-macro" |
| #elif defined (__GNUC__) |
| /* anonymous unions are enabled by default */ |
| #elif defined (__TMS470__) |
| /* anonymous unions are enabled by default */ |
| #elif defined (__TASKING__) |
| #pragma warning 586 |
| #elif defined (__CSMC__) |
| /* anonymous unions are enabled by default */ |
| #else |
| #warning Not supported compiler type |
| #endif |
| |
| |
| /* =========================================================================================================================== */ |
| /* ================ Device Specific Peripheral Section ================ */ |
| /* =========================================================================================================================== */ |
| |
| |
| /** @addtogroup Device_Peripheral_peripherals |
| * @{ |
| */ |
| |
| /* ToDo: add here your device specific peripheral access structure typedefs |
| following is an example for a timer */ |
| |
| /* =========================================================================================================================== */ |
| /* ================ TMR ================ */ |
| /* =========================================================================================================================== */ |
| |
| |
| /** |
| * @brief Timer (TMR) |
| */ |
| |
| typedef struct |
| { /*!< (@ 0x40000000) TIM Structure */ |
| __IOM uint32_t TimerLoad; /*!< (@ 0x00000004) Timer Load */ |
| __IM uint32_t TimerValue; /*!< (@ 0x00000008) Timer Counter Current Value */ |
| __IOM uint32_t TimerControl; /*!< (@ 0x0000000C) Timer Control */ |
| __OM uint32_t TimerIntClr; /*!< (@ 0x00000010) Timer Interrupt Clear */ |
| __IM uint32_t TimerRIS; /*!< (@ 0x00000014) Timer Raw Interrupt Status */ |
| __IM uint32_t TimerMIS; /*!< (@ 0x00000018) Timer Masked Interrupt Status */ |
| __IM uint32_t RESERVED[1]; |
| __IOM uint32_t TimerBGLoad; /*!< (@ 0x00000020) Background Load Register */ |
| } <DeviceAbbreviation>_TMR_TypeDef; |
| |
| /*@}*/ /* end of group <Device>_Peripherals */ |
| |
| |
| /* ========================================= End of section using anonymous unions ========================================= */ |
| #if defined (__CC_ARM) |
| #pragma pop |
| #elif defined (__ICCARM__) |
| /* leave anonymous unions enabled */ |
| #elif (__ARMCC_VERSION >= 6010050) |
| #pragma clang diagnostic pop |
| #elif defined (__GNUC__) |
| /* anonymous unions are enabled by default */ |
| #elif defined (__TMS470__) |
| /* anonymous unions are enabled by default */ |
| #elif defined (__TASKING__) |
| #pragma warning restore |
| #elif defined (__CSMC__) |
| /* anonymous unions are enabled by default */ |
| #else |
| #warning Not supported compiler type |
| #endif |
| |
| |
| /* =========================================================================================================================== */ |
| /* ================ Device Specific Peripheral Address Map ================ */ |
| /* =========================================================================================================================== */ |
| |
| |
| /* ToDo: add here your device peripherals base addresses |
| following is an example for timer */ |
| /** @addtogroup Device_Peripheral_peripheralAddr |
| * @{ |
| */ |
| |
| /* Peripheral and SRAM base address */ |
| #define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */ |
| #define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ |
| #define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ |
| |
| /* Peripheral memory map */ |
| #define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /*!< (Timer0 ) Base Address */ |
| #define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1 ) Base Address */ |
| #define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2 ) Base Address */ |
| |
| /** @} */ /* End of group Device_Peripheral_peripheralAddr */ |
| |
| |
| /* =========================================================================================================================== */ |
| /* ================ Peripheral declaration ================ */ |
| /* =========================================================================================================================== */ |
| |
| |
| /* ToDo: add here your device peripherals pointer definitions |
| following is an example for timer */ |
| /** @addtogroup Device_Peripheral_declaration |
| * @{ |
| */ |
| |
| #define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) |
| #define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) |
| #define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) |
| |
| |
| /** @} */ /* End of group <Device> */ |
| |
| /** @} */ /* End of group <Vendor> */ |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| |
| #endif /* <Device>_H */ |
| </pre> </div></div><!-- contents --> |
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