| ;/* File: startup_armv6-m.s |
| ; * Purpose: startup file for armv7-m architecture devices. |
| ; * Should be used with ARMCC |
| ; * Version: V2.00 |
| ; * Date: 16 November 2015 |
| ; * |
| ; */ |
| ;/* Copyright (c) 2011 - 2014 ARM LIMITED |
| ; |
| ; All rights reserved. |
| ; Redistribution and use in source and binary forms, with or without |
| ; modification, are permitted provided that the following conditions are met: |
| ; - Redistributions of source code must retain the above copyright |
| ; notice, this list of conditions and the following disclaimer. |
| ; - Redistributions in binary form must reproduce the above copyright |
| ; notice, this list of conditions and the following disclaimer in the |
| ; documentation and/or other materials provided with the distribution. |
| ; - Neither the name of ARM nor the names of its contributors may be used |
| ; to endorse or promote products derived from this software without |
| ; specific prior written permission. |
| ; * |
| ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
| ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| ; POSSIBILITY OF SUCH DAMAGE. |
| ; ---------------------------------------------------------------------------*/ |
| |
| PRESERVE8 |
| THUMB |
| |
| |
| ; Vector Table Mapped to Address 0 at Reset |
| |
| AREA RESET, DATA, READONLY |
| IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| |
| EXPORT __Vectors |
| EXPORT __Vectors_End |
| EXPORT __Vectors_Size |
| |
| __Vectors DCD ||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; Top of Stack |
| DCD Reset_Handler ; Reset Handler |
| DCD NMI_Handler ; NMI Handler |
| DCD HardFault_Handler ; Hard Fault Handler |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD SVC_Handler ; SVCall Handler |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD PendSV_Handler ; PendSV Handler |
| DCD SysTick_Handler ; SysTick Handler |
| __Vectors_End |
| |
| __Vectors_Size EQU __Vectors_End - __Vectors |
| |
| AREA |.text|, CODE, READONLY |
| |
| |
| ; Reset Handler |
| |
| Reset_Handler PROC |
| EXPORT Reset_Handler [WEAK] |
| IMPORT SystemInit |
| IMPORT __main |
| LDR R0, =SystemInit |
| BLX R0 |
| LDR R0, =__main |
| BX R0 |
| ENDP |
| |
| |
| ; Dummy Exception Handlers (infinite loops which can be modified) |
| |
| NMI_Handler PROC |
| EXPORT NMI_Handler [WEAK] |
| BKPT #0 |
| B . |
| ENDP |
| HardFault_Handler\ |
| PROC |
| EXPORT HardFault_Handler [WEAK] |
| BKPT #0 |
| B . |
| ENDP |
| SVC_Handler PROC |
| EXPORT SVC_Handler [WEAK] |
| B . |
| ENDP |
| PendSV_Handler PROC |
| EXPORT PendSV_Handler [WEAK] |
| B . |
| ENDP |
| SysTick_Handler PROC |
| EXPORT SysTick_Handler [WEAK] |
| B . |
| ENDP |
| |
| ALIGN |
| |
| END |