| ;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** |
| ;* File Name : startup_stm32f098xx.s |
| ;* Author : MCD Application Team |
| ;* Description : STM32F098xx devices vector table for EWARM toolchain. |
| ;* This module performs: |
| ;* - Set the initial SP |
| ;* - Set the initial PC == __iar_program_start, |
| ;* - Set the vector table entries with the exceptions ISR |
| ;* address, |
| ;* - Branches to main in the C library (which eventually |
| ;* calls main()). |
| ;* After Reset the Cortex-M0 processor is in Thread mode, |
| ;* priority is Privileged, and the Stack is set to Main. |
| ;******************************************************************************* |
| ;* |
| ;* Redistribution and use in source and binary forms, with or without modification, |
| ;* are permitted provided that the following conditions are met: |
| ;* 1. Redistributions of source code must retain the above copyright notice, |
| ;* this list of conditions and the following disclaimer. |
| ;* 2. Redistributions in binary form must reproduce the above copyright notice, |
| ;* this list of conditions and the following disclaimer in the documentation |
| ;* and/or other materials provided with the distribution. |
| ;* 3. Neither the name of STMicroelectronics nor the names of its contributors |
| ;* may be used to endorse or promote products derived from this software |
| ;* without specific prior written permission. |
| ;* |
| ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| ;* |
| ;******************************************************************************* |
| ; |
| ; |
| ; The modules in this file are included in the libraries, and may be replaced |
| ; by any user-defined modules that define the PUBLIC symbol _program_start or |
| ; a user defined start symbol. |
| ; To override the cstartup defined in the library, simply add your modified |
| ; version to the workbench project. |
| ; |
| ; The vector table is normally located at address 0. |
| ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. |
| ; The name "__vector_table" has special meaning for C-SPY: |
| ; it is where the SP start value is found, and the NVIC vector |
| ; table register (VTOR) is initialized to this address if != 0. |
| ; |
| ; Cortex-M version |
| ; |
| |
| MODULE ?cstartup |
| |
| ;; Forward declaration of sections. |
| SECTION CSTACK:DATA:NOROOT(3) |
| |
| SECTION .intvec:CODE:NOROOT(2) |
| |
| EXTERN __iar_program_start |
| EXTERN SystemInit |
| PUBLIC __vector_table |
| |
| DATA |
| __vector_table |
| DCD sfe(CSTACK) |
| DCD Reset_Handler ; Reset Handler |
| |
| DCD NMI_Handler ; NMI Handler |
| DCD HardFault_Handler ; Hard Fault Handler |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD SVC_Handler ; SVCall Handler |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD PendSV_Handler ; PendSV Handler |
| DCD SysTick_Handler ; SysTick Handler |
| |
| ; External Interrupts |
| DCD WWDG_IRQHandler ; Window Watchdog |
| DCD VDDIO2_IRQHandler ; VDDIO2 Monitor through EXTI Line 31 |
| DCD RTC_IRQHandler ; RTC through EXTI Line |
| DCD FLASH_IRQHandler ; FLASH |
| DCD RCC_CRS_IRQHandler ; RCC and CRS |
| DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 |
| DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 |
| DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 |
| DCD TSC_IRQHandler ; TS |
| DCD DMA1_Ch1_IRQHandler ; DMA1 Channel 1 |
| DCD DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 |
| DCD DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 |
| DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 |
| DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation |
| DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare |
| DCD TIM2_IRQHandler ; TIM2 |
| DCD TIM3_IRQHandler ; TIM3 |
| DCD TIM6_DAC_IRQHandler ; TIM6 and DAC |
| DCD TIM7_IRQHandler ; TIM7 |
| DCD TIM14_IRQHandler ; TIM14 |
| DCD TIM15_IRQHandler ; TIM15 |
| DCD TIM16_IRQHandler ; TIM16 |
| DCD TIM17_IRQHandler ; TIM17 |
| DCD I2C1_IRQHandler ; I2C1 |
| DCD I2C2_IRQHandler ; I2C2 |
| DCD SPI1_IRQHandler ; SPI1 |
| DCD SPI2_IRQHandler ; SPI2 |
| DCD USART1_IRQHandler ; USART1 |
| DCD USART2_IRQHandler ; USART2 |
| DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8 |
| DCD CEC_CAN_IRQHandler ; CEC and CAN |
| |
| ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
| ;; |
| ;; Default interrupt handlers. |
| ;; |
| THUMB |
| |
| PUBWEAK Reset_Handler |
| SECTION .text:CODE:NOROOT:REORDER(2) |
| Reset_Handler |
| LDR R0, =SystemInit |
| BLX R0 |
| LDR R0, =__iar_program_start |
| BX R0 |
| |
| PUBWEAK NMI_Handler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| NMI_Handler |
| B NMI_Handler |
| |
| PUBWEAK HardFault_Handler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| HardFault_Handler |
| B HardFault_Handler |
| |
| PUBWEAK SVC_Handler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| SVC_Handler |
| B SVC_Handler |
| |
| PUBWEAK PendSV_Handler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| PendSV_Handler |
| B PendSV_Handler |
| |
| PUBWEAK SysTick_Handler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| SysTick_Handler |
| B SysTick_Handler |
| |
| PUBWEAK WWDG_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| WWDG_IRQHandler |
| B WWDG_IRQHandler |
| |
| PUBWEAK VDDIO2_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| VDDIO2_IRQHandler |
| B VDDIO2_IRQHandler |
| |
| PUBWEAK RTC_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| RTC_IRQHandler |
| B RTC_IRQHandler |
| |
| PUBWEAK FLASH_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| FLASH_IRQHandler |
| B FLASH_IRQHandler |
| |
| PUBWEAK RCC_CRS_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| RCC_CRS_IRQHandler |
| B RCC_CRS_IRQHandler |
| |
| PUBWEAK EXTI0_1_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| EXTI0_1_IRQHandler |
| B EXTI0_1_IRQHandler |
| |
| PUBWEAK EXTI2_3_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| EXTI2_3_IRQHandler |
| B EXTI2_3_IRQHandler |
| |
| PUBWEAK EXTI4_15_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| EXTI4_15_IRQHandler |
| B EXTI4_15_IRQHandler |
| |
| PUBWEAK TSC_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| TSC_IRQHandler |
| B TSC_IRQHandler |
| |
| PUBWEAK DMA1_Ch1_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| DMA1_Ch1_IRQHandler |
| B DMA1_Ch1_IRQHandler |
| |
| PUBWEAK DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler |
| B DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler |
| |
| PUBWEAK DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler |
| B DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler |
| |
| PUBWEAK ADC1_COMP_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| ADC1_COMP_IRQHandler |
| B ADC1_COMP_IRQHandler |
| |
| PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| TIM1_BRK_UP_TRG_COM_IRQHandler |
| B TIM1_BRK_UP_TRG_COM_IRQHandler |
| |
| PUBWEAK TIM1_CC_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| TIM1_CC_IRQHandler |
| B TIM1_CC_IRQHandler |
| |
| PUBWEAK TIM2_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| TIM2_IRQHandler |
| B TIM2_IRQHandler |
| |
| PUBWEAK TIM3_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| TIM3_IRQHandler |
| B TIM3_IRQHandler |
| |
| PUBWEAK TIM6_DAC_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| TIM6_DAC_IRQHandler |
| B TIM6_DAC_IRQHandler |
| |
| PUBWEAK TIM7_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| TIM7_IRQHandler |
| B TIM7_IRQHandler |
| |
| PUBWEAK TIM14_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| TIM14_IRQHandler |
| B TIM14_IRQHandler |
| |
| PUBWEAK TIM15_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| TIM15_IRQHandler |
| B TIM15_IRQHandler |
| |
| PUBWEAK TIM16_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| TIM16_IRQHandler |
| B TIM16_IRQHandler |
| |
| PUBWEAK TIM17_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| TIM17_IRQHandler |
| B TIM17_IRQHandler |
| |
| PUBWEAK I2C1_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| I2C1_IRQHandler |
| B I2C1_IRQHandler |
| |
| PUBWEAK I2C2_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| I2C2_IRQHandler |
| B I2C2_IRQHandler |
| |
| PUBWEAK SPI1_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| SPI1_IRQHandler |
| B SPI1_IRQHandler |
| |
| PUBWEAK SPI2_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| SPI2_IRQHandler |
| B SPI2_IRQHandler |
| |
| PUBWEAK USART1_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| USART1_IRQHandler |
| B USART1_IRQHandler |
| |
| PUBWEAK USART2_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| USART2_IRQHandler |
| B USART2_IRQHandler |
| |
| PUBWEAK USART3_8_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| USART3_8_IRQHandler |
| B USART3_8_IRQHandler |
| |
| PUBWEAK CEC_CAN_IRQHandler |
| SECTION .text:CODE:NOROOT:REORDER(1) |
| CEC_CAN_IRQHandler |
| B CEC_CAN_IRQHandler |
| |
| END |
| ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** |