| /** |
| ****************************************************************************** |
| * @file stm32f038xx.h |
| * @author MCD Application Team |
| * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. |
| * This file contains all the peripheral register's definitions, bits |
| * definitions and memory mapping for STM32F0xx devices. |
| * |
| * This file contains: |
| * - Data structures and the address mapping for all peripherals |
| * - Peripheral's registers declarations and bits definition |
| * - Macros to access peripheralÂ’s registers hardware |
| * |
| ****************************************************************************** |
| * @attention |
| * |
| * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
| * All rights reserved.</center></h2> |
| * |
| * This software component is licensed by ST under BSD 3-Clause license, |
| * the "License"; You may not use this file except in compliance with the |
| * License. You may obtain a copy of the License at: |
| * opensource.org/licenses/BSD-3-Clause |
| * |
| ****************************************************************************** |
| */ |
| |
| /** @addtogroup CMSIS |
| * @{ |
| */ |
| |
| /** @addtogroup stm32f038xx |
| * @{ |
| */ |
| |
| #ifndef __STM32F038xx_H |
| #define __STM32F038xx_H |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif /* __cplusplus */ |
| |
| /** @addtogroup Configuration_section_for_CMSIS |
| * @{ |
| */ |
| /** |
| * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
| */ |
| #define __CM0_REV 0 /*!< Core Revision r0p0 */ |
| #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ |
| #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ |
| #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_interrupt_number_definition |
| * @{ |
| */ |
| |
| /** |
| * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
| * in @ref Library_configuration_section |
| */ |
| |
| /*!< Interrupt Number Definition */ |
| typedef enum |
| { |
| /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
| NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
| SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ |
| PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ |
| SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ |
| |
| /****** STM32F0 specific Interrupt Numbers ******************************************************************/ |
| WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ |
| FLASH_IRQn = 3, /*!< FLASH global Interrupt */ |
| RCC_IRQn = 4, /*!< RCC global Interrupt */ |
| EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ |
| EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ |
| EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ |
| DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ |
| DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ |
| DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ |
| ADC1_IRQn = 12, /*!< ADC1 Interrupt */ |
| TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ |
| TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ |
| TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ |
| TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ |
| TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ |
| TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ |
| TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ |
| I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ |
| SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ |
| USART1_IRQn = 27 /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ |
| } IRQn_Type; |
| |
| /** |
| * @} |
| */ |
| |
| #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ |
| #include "system_stm32f0xx.h" /* STM32F0xx System Header */ |
| #include <stdint.h> |
| |
| /** @addtogroup Peripheral_registers_structures |
| * @{ |
| */ |
| |
| /** |
| * @brief Analog to Digital Converter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ |
| __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ |
| __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ |
| __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ |
| __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ |
| __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ |
| uint32_t RESERVED1; /*!< Reserved, 0x18 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x1C */ |
| __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ |
| uint32_t RESERVED3; /*!< Reserved, 0x24 */ |
| __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ |
| uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ |
| __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ |
| } ADC_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ |
| } ADC_Common_TypeDef; |
| |
| /** |
| * @brief CRC calculation unit |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| uint8_t RESERVED0; /*!< Reserved, 0x05 */ |
| uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x0C */ |
| __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ |
| __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ |
| } CRC_TypeDef; |
| |
| /** |
| * @brief Debug MCU |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ |
| __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ |
| }DBGMCU_TypeDef; |
| |
| /** |
| * @brief DMA Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CCR; /*!< DMA channel x configuration register */ |
| __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ |
| __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ |
| __IO uint32_t CMAR; /*!< DMA channel x memory address register */ |
| } DMA_Channel_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ |
| __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ |
| } DMA_TypeDef; |
| |
| /** |
| * @brief External Interrupt/Event Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ |
| __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ |
| __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ |
| __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ |
| __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ |
| __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ |
| } EXTI_TypeDef; |
| |
| /** |
| * @brief FLASH Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */ |
| __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */ |
| __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */ |
| __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */ |
| __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */ |
| __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */ |
| __IO uint32_t RESERVED; /*!< Reserved, 0x18 */ |
| __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */ |
| __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */ |
| } FLASH_TypeDef; |
| |
| /** |
| * @brief Option Bytes Registers |
| */ |
| typedef struct |
| { |
| __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ |
| __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ |
| __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ |
| __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ |
| __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ |
| } OB_TypeDef; |
| |
| /** |
| * @brief General Purpose I/O |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ |
| __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ |
| __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ |
| } GPIO_TypeDef; |
| |
| /** |
| * @brief SysTem Configuration |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ |
| uint32_t RESERVED; /*!< Reserved, 0x04 */ |
| __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ |
| __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ |
| } SYSCFG_TypeDef; |
| |
| /** |
| * @brief Inter-integrated Circuit Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ |
| __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ |
| __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ |
| __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ |
| __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ |
| __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ |
| __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ |
| __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ |
| __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ |
| } I2C_TypeDef; |
| |
| /** |
| * @brief Independent WATCHDOG |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
| __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
| __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
| __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
| __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ |
| } IWDG_TypeDef; |
| |
| /** |
| * @brief Power Control |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ |
| __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ |
| } PWR_TypeDef; |
| |
| /** |
| * @brief Reset and Clock Control |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
| __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ |
| __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ |
| __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ |
| __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ |
| __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ |
| __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ |
| __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ |
| __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ |
| __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ |
| __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ |
| __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ |
| __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ |
| __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */ |
| } RCC_TypeDef; |
| |
| /** |
| * @brief Real-Time Clock |
| */ |
| typedef struct |
| { |
| __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
| __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
| __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
| __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
| __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
| uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ |
| uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ |
| __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
| uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */ |
| __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
| __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
| __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
| __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
| __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
| __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
| __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
| __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ |
| __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ |
| uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */ |
| uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */ |
| __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ |
| __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
| __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
| __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
| __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
| } RTC_TypeDef; |
| |
| /** |
| * @brief Serial Peripheral Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ |
| __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ |
| __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ |
| __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ |
| __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ |
| __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ |
| } SPI_TypeDef; |
| |
| /** |
| * @brief TIM |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ |
| __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ |
| __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ |
| __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
| } TIM_TypeDef; |
| |
| /** |
| * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ |
| __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ |
| __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ |
| __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ |
| __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ |
| __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ |
| __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ |
| __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ |
| __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ |
| uint16_t RESERVED1; /*!< Reserved, 0x26 */ |
| __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ |
| uint16_t RESERVED2; /*!< Reserved, 0x2A */ |
| } USART_TypeDef; |
| |
| /** |
| * @brief Window WATCHDOG |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| } WWDG_TypeDef; |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_memory_map |
| * @{ |
| */ |
| |
| #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ |
| #define FLASH_BANK1_END 0x08007FFFUL /*!< FLASH END address of bank1 */ |
| #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ |
| #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ |
| |
| /*!< Peripheral memory map */ |
| #define APBPERIPH_BASE PERIPH_BASE |
| #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
| #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) |
| |
| /*!< APB peripherals */ |
| #define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL) |
| #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) |
| #define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) |
| #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) |
| #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) |
| #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) |
| #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) |
| #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) |
| #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) |
| #define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL) |
| #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) |
| #define ADC_BASE (APBPERIPH_BASE + 0x00012708UL) |
| #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) |
| #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) |
| #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) |
| #define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) |
| #define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) |
| #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) |
| |
| /*!< AHB peripherals */ |
| #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) |
| #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) |
| #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) |
| #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) |
| #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) |
| #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) |
| |
| #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) |
| #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ |
| #define OB_BASE 0x1FFFF800UL /*!< FLASH Option Bytes base address */ |
| #define FLASHSIZE_BASE 0x1FFFF7CCUL /*!< FLASH Size register base address */ |
| #define UID_BASE 0x1FFFF7ACUL /*!< Unique device ID register base address */ |
| #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) |
| |
| /*!< AHB2 peripherals */ |
| #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL) |
| #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL) |
| #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL) |
| #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL) |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_declaration |
| * @{ |
| */ |
| |
| #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
| #define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
| #define RTC ((RTC_TypeDef *) RTC_BASE) |
| #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| #define PWR ((PWR_TypeDef *) PWR_BASE) |
| #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
| #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) |
| #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */ |
| #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
| #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| #define USART1 ((USART_TypeDef *) USART1_BASE) |
| #define TIM16 ((TIM_TypeDef *) TIM16_BASE) |
| #define TIM17 ((TIM_TypeDef *) TIM17_BASE) |
| #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
| #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
| #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
| #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
| #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
| #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| #define OB ((OB_TypeDef *) OB_BASE) |
| #define RCC ((RCC_TypeDef *) RCC_BASE) |
| #define CRC ((CRC_TypeDef *) CRC_BASE) |
| #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Exported_constants |
| * @{ |
| */ |
| |
| /** @addtogroup Hardware_Constant_Definition |
| * @{ |
| */ |
| #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_Registers_Bits_Definition |
| * @{ |
| */ |
| |
| /******************************************************************************/ |
| /* Peripheral Registers Bits Definition */ |
| /******************************************************************************/ |
| |
| /******************************************************************************/ |
| /* */ |
| /* Analog to Digital Converter (ADC) */ |
| /* */ |
| /******************************************************************************/ |
| |
| /* |
| * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) |
| */ |
| #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ |
| |
| /******************** Bits definition for ADC_ISR register ******************/ |
| #define ADC_ISR_ADRDY_Pos (0U) |
| #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ |
| #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ |
| #define ADC_ISR_EOSMP_Pos (1U) |
| #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ |
| #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ |
| #define ADC_ISR_EOC_Pos (2U) |
| #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ |
| #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ |
| #define ADC_ISR_EOS_Pos (3U) |
| #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ |
| #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ |
| #define ADC_ISR_OVR_Pos (4U) |
| #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ |
| #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ |
| #define ADC_ISR_AWD1_Pos (7U) |
| #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ |
| #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ |
| |
| /* Legacy defines */ |
| #define ADC_ISR_AWD (ADC_ISR_AWD1) |
| #define ADC_ISR_EOSEQ (ADC_ISR_EOS) |
| |
| /******************** Bits definition for ADC_IER register ******************/ |
| #define ADC_IER_ADRDYIE_Pos (0U) |
| #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ |
| #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ |
| #define ADC_IER_EOSMPIE_Pos (1U) |
| #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ |
| #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ |
| #define ADC_IER_EOCIE_Pos (2U) |
| #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ |
| #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ |
| #define ADC_IER_EOSIE_Pos (3U) |
| #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ |
| #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ |
| #define ADC_IER_OVRIE_Pos (4U) |
| #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ |
| #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ |
| #define ADC_IER_AWD1IE_Pos (7U) |
| #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ |
| #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ |
| |
| /* Legacy defines */ |
| #define ADC_IER_AWDIE (ADC_IER_AWD1IE) |
| #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) |
| |
| /******************** Bits definition for ADC_CR register *******************/ |
| #define ADC_CR_ADEN_Pos (0U) |
| #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ |
| #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ |
| #define ADC_CR_ADDIS_Pos (1U) |
| #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ |
| #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ |
| #define ADC_CR_ADSTART_Pos (2U) |
| #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ |
| #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ |
| #define ADC_CR_ADSTP_Pos (4U) |
| #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ |
| #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ |
| #define ADC_CR_ADCAL_Pos (31U) |
| #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ |
| #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ |
| |
| /******************* Bits definition for ADC_CFGR1 register *****************/ |
| #define ADC_CFGR1_DMAEN_Pos (0U) |
| #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ |
| #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ |
| #define ADC_CFGR1_DMACFG_Pos (1U) |
| #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ |
| #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ |
| #define ADC_CFGR1_SCANDIR_Pos (2U) |
| #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ |
| #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ |
| |
| #define ADC_CFGR1_RES_Pos (3U) |
| #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ |
| #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ |
| #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ |
| #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ |
| |
| #define ADC_CFGR1_ALIGN_Pos (5U) |
| #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ |
| #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ |
| |
| #define ADC_CFGR1_EXTSEL_Pos (6U) |
| #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ |
| #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ |
| #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ |
| #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ |
| #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ |
| |
| #define ADC_CFGR1_EXTEN_Pos (10U) |
| #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ |
| #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ |
| #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ |
| #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_CFGR1_OVRMOD_Pos (12U) |
| #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ |
| #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ |
| #define ADC_CFGR1_CONT_Pos (13U) |
| #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ |
| #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ |
| #define ADC_CFGR1_WAIT_Pos (14U) |
| #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ |
| #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ |
| #define ADC_CFGR1_AUTOFF_Pos (15U) |
| #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ |
| #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ |
| #define ADC_CFGR1_DISCEN_Pos (16U) |
| #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ |
| #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ |
| |
| #define ADC_CFGR1_AWD1SGL_Pos (22U) |
| #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ |
| #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ |
| #define ADC_CFGR1_AWD1EN_Pos (23U) |
| #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ |
| #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ |
| |
| #define ADC_CFGR1_AWD1CH_Pos (26U) |
| #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ |
| #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ |
| #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ |
| #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ |
| #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ |
| #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ |
| #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ |
| |
| /* Legacy defines */ |
| #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) |
| #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL) |
| #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN) |
| #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH) |
| #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0) |
| #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1) |
| #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2) |
| #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) |
| #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) |
| |
| /******************* Bits definition for ADC_CFGR2 register *****************/ |
| #define ADC_CFGR2_CKMODE_Pos (30U) |
| #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ |
| #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ |
| #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ |
| #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ |
| |
| /* Legacy defines */ |
| #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */ |
| #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */ |
| |
| /****************** Bit definition for ADC_SMPR register ********************/ |
| #define ADC_SMPR_SMP_Pos (0U) |
| #define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ |
| #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */ |
| #define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ |
| #define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ |
| #define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ |
| |
| /* Legacy defines */ |
| #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */ |
| #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */ |
| #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */ |
| #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */ |
| |
| /******************* Bit definition for ADC_TR register ********************/ |
| #define ADC_TR1_LT1_Pos (0U) |
| #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ |
| #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ |
| #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ |
| #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ |
| #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ |
| #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ |
| #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ |
| #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ |
| #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ |
| #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ |
| #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ |
| #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ |
| #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ |
| #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_TR1_HT1_Pos (16U) |
| #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ |
| #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ |
| #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ |
| #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ |
| #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ |
| #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ |
| #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ |
| #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ |
| #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ |
| #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ |
| #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ |
| #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ |
| #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ |
| #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ |
| |
| /* Legacy defines */ |
| #define ADC_TR_HT (ADC_TR1_HT1) |
| #define ADC_TR_LT (ADC_TR1_LT1) |
| #define ADC_HTR_HT (ADC_TR1_HT1) |
| #define ADC_LTR_LT (ADC_TR1_LT1) |
| |
| /****************** Bit definition for ADC_CHSELR register ******************/ |
| #define ADC_CHSELR_CHSEL_Pos (0U) |
| #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ |
| #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL18_Pos (18U) |
| #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ |
| #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL17_Pos (17U) |
| #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ |
| #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL16_Pos (16U) |
| #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ |
| #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL15_Pos (15U) |
| #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ |
| #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL14_Pos (14U) |
| #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ |
| #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL13_Pos (13U) |
| #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ |
| #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL12_Pos (12U) |
| #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ |
| #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL11_Pos (11U) |
| #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ |
| #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL10_Pos (10U) |
| #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ |
| #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL9_Pos (9U) |
| #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ |
| #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL8_Pos (8U) |
| #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ |
| #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL7_Pos (7U) |
| #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ |
| #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL6_Pos (6U) |
| #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ |
| #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL5_Pos (5U) |
| #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ |
| #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL4_Pos (4U) |
| #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ |
| #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL3_Pos (3U) |
| #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ |
| #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL2_Pos (2U) |
| #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ |
| #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL1_Pos (1U) |
| #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ |
| #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL0_Pos (0U) |
| #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ |
| #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ |
| |
| /******************** Bit definition for ADC_DR register ********************/ |
| #define ADC_DR_DATA_Pos (0U) |
| #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ |
| #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ |
| #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ |
| #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ |
| #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ |
| #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ |
| #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ |
| #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ |
| #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ |
| #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ |
| #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ |
| #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ |
| #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ |
| #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ |
| #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ |
| #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ |
| #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ |
| |
| /************************* ADC Common registers *****************************/ |
| /******************* Bit definition for ADC_CCR register ********************/ |
| #define ADC_CCR_VREFEN_Pos (22U) |
| #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ |
| #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ |
| #define ADC_CCR_TSEN_Pos (23U) |
| #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ |
| #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ |
| |
| #define ADC_CCR_VBATEN_Pos (24U) |
| #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ |
| #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* CRC calculation unit (CRC) */ |
| /* */ |
| /******************************************************************************/ |
| /******************* Bit definition for CRC_DR register *********************/ |
| #define CRC_DR_DR_Pos (0U) |
| #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ |
| #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ |
| |
| /******************* Bit definition for CRC_IDR register ********************/ |
| #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ |
| |
| /******************** Bit definition for CRC_CR register ********************/ |
| #define CRC_CR_RESET_Pos (0U) |
| #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ |
| #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ |
| #define CRC_CR_REV_IN_Pos (5U) |
| #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ |
| #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ |
| #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ |
| #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ |
| #define CRC_CR_REV_OUT_Pos (7U) |
| #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ |
| #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ |
| |
| /******************* Bit definition for CRC_INIT register *******************/ |
| #define CRC_INIT_INIT_Pos (0U) |
| #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ |
| #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* Debug MCU (DBGMCU) */ |
| /* */ |
| /******************************************************************************/ |
| |
| /**************** Bit definition for DBGMCU_IDCODE register *****************/ |
| #define DBGMCU_IDCODE_DEV_ID_Pos (0U) |
| #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ |
| #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ |
| |
| #define DBGMCU_IDCODE_REV_ID_Pos (16U) |
| #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ |
| #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ |
| #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ |
| #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ |
| #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ |
| #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ |
| #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ |
| #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ |
| #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ |
| #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ |
| #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ |
| #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ |
| #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ |
| #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ |
| #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ |
| #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ |
| #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ |
| #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ |
| |
| /****************** Bit definition for DBGMCU_CR register *******************/ |
| #define DBGMCU_CR_DBG_STOP_Pos (1U) |
| #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ |
| #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ |
| #define DBGMCU_CR_DBG_STANDBY_Pos (2U) |
| #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ |
| #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ |
| |
| /****************** Bit definition for DBGMCU_APB1_FZ register **************/ |
| #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) |
| #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ |
| #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ |
| #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) |
| #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ |
| #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ |
| #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) |
| #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ |
| #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */ |
| #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) |
| #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ |
| #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ |
| #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) |
| #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ |
| #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ |
| #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) |
| #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ |
| #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ |
| #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) |
| #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ |
| #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ |
| |
| /****************** Bit definition for DBGMCU_APB2_FZ register **************/ |
| #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U) |
| #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ |
| #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ |
| #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U) |
| #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ |
| #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */ |
| #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U) |
| #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ |
| #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* DMA Controller (DMA) */ |
| /* */ |
| /******************************************************************************/ |
| /******************* Bit definition for DMA_ISR register ********************/ |
| #define DMA_ISR_GIF1_Pos (0U) |
| #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ |
| #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ |
| #define DMA_ISR_TCIF1_Pos (1U) |
| #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ |
| #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ |
| #define DMA_ISR_HTIF1_Pos (2U) |
| #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ |
| #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ |
| #define DMA_ISR_TEIF1_Pos (3U) |
| #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ |
| #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ |
| #define DMA_ISR_GIF2_Pos (4U) |
| #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ |
| #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ |
| #define DMA_ISR_TCIF2_Pos (5U) |
| #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ |
| #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ |
| #define DMA_ISR_HTIF2_Pos (6U) |
| #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ |
| #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ |
| #define DMA_ISR_TEIF2_Pos (7U) |
| #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ |
| #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ |
| #define DMA_ISR_GIF3_Pos (8U) |
| #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ |
| #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ |
| #define DMA_ISR_TCIF3_Pos (9U) |
| #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ |
| #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ |
| #define DMA_ISR_HTIF3_Pos (10U) |
| #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ |
| #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ |
| #define DMA_ISR_TEIF3_Pos (11U) |
| #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ |
| #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ |
| #define DMA_ISR_GIF4_Pos (12U) |
| #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ |
| #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ |
| #define DMA_ISR_TCIF4_Pos (13U) |
| #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ |
| #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ |
| #define DMA_ISR_HTIF4_Pos (14U) |
| #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ |
| #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ |
| #define DMA_ISR_TEIF4_Pos (15U) |
| #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ |
| #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ |
| #define DMA_ISR_GIF5_Pos (16U) |
| #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ |
| #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ |
| #define DMA_ISR_TCIF5_Pos (17U) |
| #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ |
| #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ |
| #define DMA_ISR_HTIF5_Pos (18U) |
| #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ |
| #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ |
| #define DMA_ISR_TEIF5_Pos (19U) |
| #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ |
| #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ |
| |
| /******************* Bit definition for DMA_IFCR register *******************/ |
| #define DMA_IFCR_CGIF1_Pos (0U) |
| #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ |
| #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF1_Pos (1U) |
| #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ |
| #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF1_Pos (2U) |
| #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ |
| #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF1_Pos (3U) |
| #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ |
| #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ |
| #define DMA_IFCR_CGIF2_Pos (4U) |
| #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ |
| #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF2_Pos (5U) |
| #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ |
| #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF2_Pos (6U) |
| #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ |
| #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF2_Pos (7U) |
| #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ |
| #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ |
| #define DMA_IFCR_CGIF3_Pos (8U) |
| #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ |
| #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF3_Pos (9U) |
| #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ |
| #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF3_Pos (10U) |
| #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ |
| #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF3_Pos (11U) |
| #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ |
| #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ |
| #define DMA_IFCR_CGIF4_Pos (12U) |
| #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ |
| #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF4_Pos (13U) |
| #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ |
| #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF4_Pos (14U) |
| #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ |
| #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF4_Pos (15U) |
| #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ |
| #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ |
| #define DMA_IFCR_CGIF5_Pos (16U) |
| #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ |
| #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF5_Pos (17U) |
| #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ |
| #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF5_Pos (18U) |
| #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ |
| #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF5_Pos (19U) |
| #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ |
| #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ |
| |
| /******************* Bit definition for DMA_CCR register ********************/ |
| #define DMA_CCR_EN_Pos (0U) |
| #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ |
| #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ |
| #define DMA_CCR_TCIE_Pos (1U) |
| #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ |
| #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ |
| #define DMA_CCR_HTIE_Pos (2U) |
| #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ |
| #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ |
| #define DMA_CCR_TEIE_Pos (3U) |
| #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ |
| #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ |
| #define DMA_CCR_DIR_Pos (4U) |
| #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ |
| #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ |
| #define DMA_CCR_CIRC_Pos (5U) |
| #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ |
| #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ |
| #define DMA_CCR_PINC_Pos (6U) |
| #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ |
| #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ |
| #define DMA_CCR_MINC_Pos (7U) |
| #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ |
| #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ |
| |
| #define DMA_CCR_PSIZE_Pos (8U) |
| #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ |
| #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ |
| #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ |
| #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ |
| |
| #define DMA_CCR_MSIZE_Pos (10U) |
| #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ |
| #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ |
| #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ |
| #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ |
| |
| #define DMA_CCR_PL_Pos (12U) |
| #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ |
| #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ |
| #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ |
| #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ |
| |
| #define DMA_CCR_MEM2MEM_Pos (14U) |
| #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ |
| #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ |
| |
| /****************** Bit definition for DMA_CNDTR register *******************/ |
| #define DMA_CNDTR_NDT_Pos (0U) |
| #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ |
| #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ |
| |
| /****************** Bit definition for DMA_CPAR register ********************/ |
| #define DMA_CPAR_PA_Pos (0U) |
| #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ |
| #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ |
| |
| /****************** Bit definition for DMA_CMAR register ********************/ |
| #define DMA_CMAR_MA_Pos (0U) |
| #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* External Interrupt/Event Controller (EXTI) */ |
| /* */ |
| /******************************************************************************/ |
| /******************* Bit definition for EXTI_IMR register *******************/ |
| #define EXTI_IMR_MR0_Pos (0U) |
| #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ |
| #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ |
| #define EXTI_IMR_MR1_Pos (1U) |
| #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ |
| #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ |
| #define EXTI_IMR_MR2_Pos (2U) |
| #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ |
| #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ |
| #define EXTI_IMR_MR3_Pos (3U) |
| #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ |
| #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ |
| #define EXTI_IMR_MR4_Pos (4U) |
| #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ |
| #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ |
| #define EXTI_IMR_MR5_Pos (5U) |
| #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ |
| #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ |
| #define EXTI_IMR_MR6_Pos (6U) |
| #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ |
| #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ |
| #define EXTI_IMR_MR7_Pos (7U) |
| #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ |
| #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ |
| #define EXTI_IMR_MR8_Pos (8U) |
| #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ |
| #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ |
| #define EXTI_IMR_MR9_Pos (9U) |
| #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ |
| #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ |
| #define EXTI_IMR_MR10_Pos (10U) |
| #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ |
| #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ |
| #define EXTI_IMR_MR11_Pos (11U) |
| #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ |
| #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ |
| #define EXTI_IMR_MR12_Pos (12U) |
| #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ |
| #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ |
| #define EXTI_IMR_MR13_Pos (13U) |
| #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ |
| #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ |
| #define EXTI_IMR_MR14_Pos (14U) |
| #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ |
| #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ |
| #define EXTI_IMR_MR15_Pos (15U) |
| #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ |
| #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ |
| #define EXTI_IMR_MR16_Pos (16U) |
| #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ |
| #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ |
| #define EXTI_IMR_MR17_Pos (17U) |
| #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ |
| #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ |
| #define EXTI_IMR_MR19_Pos (19U) |
| #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ |
| #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ |
| #define EXTI_IMR_MR21_Pos (21U) |
| #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ |
| #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ |
| #define EXTI_IMR_MR22_Pos (22U) |
| #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ |
| #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ |
| #define EXTI_IMR_MR23_Pos (23U) |
| #define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ |
| #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ |
| #define EXTI_IMR_MR25_Pos (25U) |
| #define EXTI_IMR_MR25_Msk (0x1UL << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */ |
| #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */ |
| #define EXTI_IMR_MR27_Pos (27U) |
| #define EXTI_IMR_MR27_Msk (0x1UL << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */ |
| #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */ |
| |
| /* References Defines */ |
| #define EXTI_IMR_IM0 EXTI_IMR_MR0 |
| #define EXTI_IMR_IM1 EXTI_IMR_MR1 |
| #define EXTI_IMR_IM2 EXTI_IMR_MR2 |
| #define EXTI_IMR_IM3 EXTI_IMR_MR3 |
| #define EXTI_IMR_IM4 EXTI_IMR_MR4 |
| #define EXTI_IMR_IM5 EXTI_IMR_MR5 |
| #define EXTI_IMR_IM6 EXTI_IMR_MR6 |
| #define EXTI_IMR_IM7 EXTI_IMR_MR7 |
| #define EXTI_IMR_IM8 EXTI_IMR_MR8 |
| #define EXTI_IMR_IM9 EXTI_IMR_MR9 |
| #define EXTI_IMR_IM10 EXTI_IMR_MR10 |
| #define EXTI_IMR_IM11 EXTI_IMR_MR11 |
| #define EXTI_IMR_IM12 EXTI_IMR_MR12 |
| #define EXTI_IMR_IM13 EXTI_IMR_MR13 |
| #define EXTI_IMR_IM14 EXTI_IMR_MR14 |
| #define EXTI_IMR_IM15 EXTI_IMR_MR15 |
| #define EXTI_IMR_IM16 EXTI_IMR_MR16 |
| #define EXTI_IMR_IM17 EXTI_IMR_MR17 |
| #define EXTI_IMR_IM19 EXTI_IMR_MR19 |
| #define EXTI_IMR_IM21 EXTI_IMR_MR21 |
| #define EXTI_IMR_IM22 EXTI_IMR_MR22 |
| #define EXTI_IMR_IM23 EXTI_IMR_MR23 |
| #define EXTI_IMR_IM25 EXTI_IMR_MR25 |
| #define EXTI_IMR_IM27 EXTI_IMR_MR27 |
| |
| #define EXTI_IMR_IM_Pos (0U) |
| #define EXTI_IMR_IM_Msk (0xAEFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x0AEFFFFF */ |
| #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ |
| |
| |
| /****************** Bit definition for EXTI_EMR register ********************/ |
| #define EXTI_EMR_MR0_Pos (0U) |
| #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ |
| #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ |
| #define EXTI_EMR_MR1_Pos (1U) |
| #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ |
| #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ |
| #define EXTI_EMR_MR2_Pos (2U) |
| #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ |
| #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ |
| #define EXTI_EMR_MR3_Pos (3U) |
| #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ |
| #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ |
| #define EXTI_EMR_MR4_Pos (4U) |
| #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ |
| #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ |
| #define EXTI_EMR_MR5_Pos (5U) |
| #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ |
| #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ |
| #define EXTI_EMR_MR6_Pos (6U) |
| #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ |
| #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ |
| #define EXTI_EMR_MR7_Pos (7U) |
| #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ |
| #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ |
| #define EXTI_EMR_MR8_Pos (8U) |
| #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ |
| #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ |
| #define EXTI_EMR_MR9_Pos (9U) |
| #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ |
| #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ |
| #define EXTI_EMR_MR10_Pos (10U) |
| #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ |
| #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ |
| #define EXTI_EMR_MR11_Pos (11U) |
| #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ |
| #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ |
| #define EXTI_EMR_MR12_Pos (12U) |
| #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ |
| #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ |
| #define EXTI_EMR_MR13_Pos (13U) |
| #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ |
| #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ |
| #define EXTI_EMR_MR14_Pos (14U) |
| #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ |
| #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ |
| #define EXTI_EMR_MR15_Pos (15U) |
| #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ |
| #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ |
| #define EXTI_EMR_MR16_Pos (16U) |
| #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ |
| #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ |
| #define EXTI_EMR_MR17_Pos (17U) |
| #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ |
| #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ |
| #define EXTI_EMR_MR19_Pos (19U) |
| #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ |
| #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ |
| #define EXTI_EMR_MR21_Pos (21U) |
| #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ |
| #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ |
| #define EXTI_EMR_MR22_Pos (22U) |
| #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ |
| #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ |
| #define EXTI_EMR_MR23_Pos (23U) |
| #define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ |
| #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ |
| #define EXTI_EMR_MR25_Pos (25U) |
| #define EXTI_EMR_MR25_Msk (0x1UL << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */ |
| #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */ |
| #define EXTI_EMR_MR27_Pos (27U) |
| #define EXTI_EMR_MR27_Msk (0x1UL << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */ |
| #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */ |
| |
| /* References Defines */ |
| #define EXTI_EMR_EM0 EXTI_EMR_MR0 |
| #define EXTI_EMR_EM1 EXTI_EMR_MR1 |
| #define EXTI_EMR_EM2 EXTI_EMR_MR2 |
| #define EXTI_EMR_EM3 EXTI_EMR_MR3 |
| #define EXTI_EMR_EM4 EXTI_EMR_MR4 |
| #define EXTI_EMR_EM5 EXTI_EMR_MR5 |
| #define EXTI_EMR_EM6 EXTI_EMR_MR6 |
| #define EXTI_EMR_EM7 EXTI_EMR_MR7 |
| #define EXTI_EMR_EM8 EXTI_EMR_MR8 |
| #define EXTI_EMR_EM9 EXTI_EMR_MR9 |
| #define EXTI_EMR_EM10 EXTI_EMR_MR10 |
| #define EXTI_EMR_EM11 EXTI_EMR_MR11 |
| #define EXTI_EMR_EM12 EXTI_EMR_MR12 |
| #define EXTI_EMR_EM13 EXTI_EMR_MR13 |
| #define EXTI_EMR_EM14 EXTI_EMR_MR14 |
| #define EXTI_EMR_EM15 EXTI_EMR_MR15 |
| #define EXTI_EMR_EM16 EXTI_EMR_MR16 |
| #define EXTI_EMR_EM17 EXTI_EMR_MR17 |
| #define EXTI_EMR_EM19 EXTI_EMR_MR19 |
| #define EXTI_EMR_EM21 EXTI_EMR_MR21 |
| #define EXTI_EMR_EM22 EXTI_EMR_MR22 |
| #define EXTI_EMR_EM23 EXTI_EMR_MR23 |
| #define EXTI_EMR_EM25 EXTI_EMR_MR25 |
| #define EXTI_EMR_EM27 EXTI_EMR_MR27 |
| |
| /******************* Bit definition for EXTI_RTSR register ******************/ |
| #define EXTI_RTSR_TR0_Pos (0U) |
| #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ |
| #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ |
| #define EXTI_RTSR_TR1_Pos (1U) |
| #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ |
| #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ |
| #define EXTI_RTSR_TR2_Pos (2U) |
| #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ |
| #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ |
| #define EXTI_RTSR_TR3_Pos (3U) |
| #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ |
| #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ |
| #define EXTI_RTSR_TR4_Pos (4U) |
| #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ |
| #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ |
| #define EXTI_RTSR_TR5_Pos (5U) |
| #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ |
| #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ |
| #define EXTI_RTSR_TR6_Pos (6U) |
| #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ |
| #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ |
| #define EXTI_RTSR_TR7_Pos (7U) |
| #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ |
| #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ |
| #define EXTI_RTSR_TR8_Pos (8U) |
| #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ |
| #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ |
| #define EXTI_RTSR_TR9_Pos (9U) |
| #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ |
| #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ |
| #define EXTI_RTSR_TR10_Pos (10U) |
| #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ |
| #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ |
| #define EXTI_RTSR_TR11_Pos (11U) |
| #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ |
| #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ |
| #define EXTI_RTSR_TR12_Pos (12U) |
| #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ |
| #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ |
| #define EXTI_RTSR_TR13_Pos (13U) |
| #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ |
| #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ |
| #define EXTI_RTSR_TR14_Pos (14U) |
| #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ |
| #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ |
| #define EXTI_RTSR_TR15_Pos (15U) |
| #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ |
| #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ |
| #define EXTI_RTSR_TR16_Pos (16U) |
| #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ |
| #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ |
| #define EXTI_RTSR_TR17_Pos (17U) |
| #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ |
| #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ |
| #define EXTI_RTSR_TR19_Pos (19U) |
| #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ |
| #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ |
| #define EXTI_RTSR_TR21_Pos (21U) |
| #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ |
| #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ |
| #define EXTI_RTSR_TR22_Pos (22U) |
| #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ |
| #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ |
| |
| /* References Defines */ |
| #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 |
| #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 |
| #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 |
| #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 |
| #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 |
| #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 |
| #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 |
| #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 |
| #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 |
| #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 |
| #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 |
| #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 |
| #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 |
| #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 |
| #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 |
| #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 |
| #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 |
| #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 |
| #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 |
| #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 |
| #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 |
| |
| /******************* Bit definition for EXTI_FTSR register *******************/ |
| #define EXTI_FTSR_TR0_Pos (0U) |
| #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ |
| #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ |
| #define EXTI_FTSR_TR1_Pos (1U) |
| #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ |
| #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ |
| #define EXTI_FTSR_TR2_Pos (2U) |
| #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ |
| #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ |
| #define EXTI_FTSR_TR3_Pos (3U) |
| #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ |
| #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ |
| #define EXTI_FTSR_TR4_Pos (4U) |
| #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ |
| #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ |
| #define EXTI_FTSR_TR5_Pos (5U) |
| #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ |
| #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ |
| #define EXTI_FTSR_TR6_Pos (6U) |
| #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ |
| #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ |
| #define EXTI_FTSR_TR7_Pos (7U) |
| #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ |
| #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ |
| #define EXTI_FTSR_TR8_Pos (8U) |
| #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ |
| #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ |
| #define EXTI_FTSR_TR9_Pos (9U) |
| #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ |
| #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ |
| #define EXTI_FTSR_TR10_Pos (10U) |
| #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ |
| #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ |
| #define EXTI_FTSR_TR11_Pos (11U) |
| #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ |
| #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ |
| #define EXTI_FTSR_TR12_Pos (12U) |
| #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ |
| #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ |
| #define EXTI_FTSR_TR13_Pos (13U) |
| #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ |
| #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ |
| #define EXTI_FTSR_TR14_Pos (14U) |
| #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ |
| #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ |
| #define EXTI_FTSR_TR15_Pos (15U) |
| #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ |
| #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ |
| #define EXTI_FTSR_TR16_Pos (16U) |
| #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ |
| #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ |
| #define EXTI_FTSR_TR17_Pos (17U) |
| #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ |
| #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ |
| #define EXTI_FTSR_TR19_Pos (19U) |
| #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ |
| #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ |
| #define EXTI_FTSR_TR21_Pos (21U) |
| #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ |
| #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ |
| #define EXTI_FTSR_TR22_Pos (22U) |
| #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ |
| #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ |
| |
| /* References Defines */ |
| #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 |
| #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 |
| #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 |
| #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 |
| #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 |
| #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 |
| #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 |
| #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 |
| #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 |
| #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 |
| #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 |
| #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 |
| #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 |
| #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 |
| #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 |
| #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 |
| #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 |
| #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 |
| #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 |
| #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 |
| #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 |
| |
| /******************* Bit definition for EXTI_SWIER register *******************/ |
| #define EXTI_SWIER_SWIER0_Pos (0U) |
| #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ |
| #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ |
| #define EXTI_SWIER_SWIER1_Pos (1U) |
| #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ |
| #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ |
| #define EXTI_SWIER_SWIER2_Pos (2U) |
| #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ |
| #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ |
| #define EXTI_SWIER_SWIER3_Pos (3U) |
| #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ |
| #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ |
| #define EXTI_SWIER_SWIER4_Pos (4U) |
| #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ |
| #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ |
| #define EXTI_SWIER_SWIER5_Pos (5U) |
| #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ |
| #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ |
| #define EXTI_SWIER_SWIER6_Pos (6U) |
| #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ |
| #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ |
| #define EXTI_SWIER_SWIER7_Pos (7U) |
| #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ |
| #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ |
| #define EXTI_SWIER_SWIER8_Pos (8U) |
| #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ |
| #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ |
| #define EXTI_SWIER_SWIER9_Pos (9U) |
| #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ |
| #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ |
| #define EXTI_SWIER_SWIER10_Pos (10U) |
| #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ |
| #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ |
| #define EXTI_SWIER_SWIER11_Pos (11U) |
| #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ |
| #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ |
| #define EXTI_SWIER_SWIER12_Pos (12U) |
| #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ |
| #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ |
| #define EXTI_SWIER_SWIER13_Pos (13U) |
| #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ |
| #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ |
| #define EXTI_SWIER_SWIER14_Pos (14U) |
| #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ |
| #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ |
| #define EXTI_SWIER_SWIER15_Pos (15U) |
| #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ |
| #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ |
| #define EXTI_SWIER_SWIER16_Pos (16U) |
| #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ |
| #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ |
| #define EXTI_SWIER_SWIER17_Pos (17U) |
| #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ |
| #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ |
| #define EXTI_SWIER_SWIER19_Pos (19U) |
| #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ |
| #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ |
| #define EXTI_SWIER_SWIER21_Pos (21U) |
| #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ |
| #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ |
| #define EXTI_SWIER_SWIER22_Pos (22U) |
| #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ |
| #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ |
| |
| /* References Defines */ |
| #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 |
| #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 |
| #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 |
| #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 |
| #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 |
| #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 |
| #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 |
| #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 |
| #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 |
| #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 |
| #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 |
| #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 |
| #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 |
| #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 |
| #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 |
| #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 |
| #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 |
| #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 |
| #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 |
| #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 |
| #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 |
| |
| /****************** Bit definition for EXTI_PR register *********************/ |
| #define EXTI_PR_PR0_Pos (0U) |
| #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ |
| #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */ |
| #define EXTI_PR_PR1_Pos (1U) |
| #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ |
| #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */ |
| #define EXTI_PR_PR2_Pos (2U) |
| #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ |
| #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */ |
| #define EXTI_PR_PR3_Pos (3U) |
| #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ |
| #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */ |
| #define EXTI_PR_PR4_Pos (4U) |
| #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ |
| #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */ |
| #define EXTI_PR_PR5_Pos (5U) |
| #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ |
| #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */ |
| #define EXTI_PR_PR6_Pos (6U) |
| #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ |
| #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */ |
| #define EXTI_PR_PR7_Pos (7U) |
| #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ |
| #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */ |
| #define EXTI_PR_PR8_Pos (8U) |
| #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ |
| #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */ |
| #define EXTI_PR_PR9_Pos (9U) |
| #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ |
| #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */ |
| #define EXTI_PR_PR10_Pos (10U) |
| #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ |
| #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */ |
| #define EXTI_PR_PR11_Pos (11U) |
| #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ |
| #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */ |
| #define EXTI_PR_PR12_Pos (12U) |
| #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ |
| #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */ |
| #define EXTI_PR_PR13_Pos (13U) |
| #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ |
| #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */ |
| #define EXTI_PR_PR14_Pos (14U) |
| #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ |
| #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */ |
| #define EXTI_PR_PR15_Pos (15U) |
| #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ |
| #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */ |
| #define EXTI_PR_PR16_Pos (16U) |
| #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ |
| #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */ |
| #define EXTI_PR_PR17_Pos (17U) |
| #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ |
| #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */ |
| #define EXTI_PR_PR19_Pos (19U) |
| #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ |
| #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */ |
| #define EXTI_PR_PR21_Pos (21U) |
| #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ |
| #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit 21 */ |
| #define EXTI_PR_PR22_Pos (22U) |
| #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ |
| #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit 22 */ |
| |
| /* References Defines */ |
| #define EXTI_PR_PIF0 EXTI_PR_PR0 |
| #define EXTI_PR_PIF1 EXTI_PR_PR1 |
| #define EXTI_PR_PIF2 EXTI_PR_PR2 |
| #define EXTI_PR_PIF3 EXTI_PR_PR3 |
| #define EXTI_PR_PIF4 EXTI_PR_PR4 |
| #define EXTI_PR_PIF5 EXTI_PR_PR5 |
| #define EXTI_PR_PIF6 EXTI_PR_PR6 |
| #define EXTI_PR_PIF7 EXTI_PR_PR7 |
| #define EXTI_PR_PIF8 EXTI_PR_PR8 |
| #define EXTI_PR_PIF9 EXTI_PR_PR9 |
| #define EXTI_PR_PIF10 EXTI_PR_PR10 |
| #define EXTI_PR_PIF11 EXTI_PR_PR11 |
| #define EXTI_PR_PIF12 EXTI_PR_PR12 |
| #define EXTI_PR_PIF13 EXTI_PR_PR13 |
| #define EXTI_PR_PIF14 EXTI_PR_PR14 |
| #define EXTI_PR_PIF15 EXTI_PR_PR15 |
| #define EXTI_PR_PIF16 EXTI_PR_PR16 |
| #define EXTI_PR_PIF17 EXTI_PR_PR17 |
| #define EXTI_PR_PIF19 EXTI_PR_PR19 |
| #define EXTI_PR_PIF21 EXTI_PR_PR21 |
| #define EXTI_PR_PIF22 EXTI_PR_PR22 |
| |
| /******************************************************************************/ |
| /* */ |
| /* FLASH and Option Bytes Registers */ |
| /* */ |
| /******************************************************************************/ |
| |
| /******************* Bit definition for FLASH_ACR register ******************/ |
| #define FLASH_ACR_LATENCY_Pos (0U) |
| #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
| #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ |
| |
| #define FLASH_ACR_PRFTBE_Pos (4U) |
| #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ |
| #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ |
| #define FLASH_ACR_PRFTBS_Pos (5U) |
| #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ |
| #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ |
| |
| /****************** Bit definition for FLASH_KEYR register ******************/ |
| #define FLASH_KEYR_FKEYR_Pos (0U) |
| #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ |
| #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ |
| |
| /***************** Bit definition for FLASH_OPTKEYR register ****************/ |
| #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) |
| #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ |
| #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ |
| |
| /****************** FLASH Keys **********************************************/ |
| #define FLASH_KEY1_Pos (0U) |
| #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ |
| #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */ |
| #define FLASH_KEY2_Pos (0U) |
| #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ |
| #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1 |
| to unlock the write access to the FPEC. */ |
| |
| #define FLASH_OPTKEY1_Pos (0U) |
| #define FLASH_OPTKEY1_Msk (0x45670123UL << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */ |
| #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */ |
| #define FLASH_OPTKEY2_Pos (0U) |
| #define FLASH_OPTKEY2_Msk (0xCDEF89ABUL << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */ |
| #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to |
| unlock the write access to the option byte block */ |
| |
| /****************** Bit definition for FLASH_SR register *******************/ |
| #define FLASH_SR_BSY_Pos (0U) |
| #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ |
| #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ |
| #define FLASH_SR_PGERR_Pos (2U) |
| #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ |
| #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ |
| #define FLASH_SR_WRPRTERR_Pos (4U) |
| #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ |
| #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ |
| #define FLASH_SR_EOP_Pos (5U) |
| #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ |
| #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ |
| #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */ |
| |
| /******************* Bit definition for FLASH_CR register *******************/ |
| #define FLASH_CR_PG_Pos (0U) |
| #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ |
| #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ |
| #define FLASH_CR_PER_Pos (1U) |
| #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ |
| #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ |
| #define FLASH_CR_MER_Pos (2U) |
| #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ |
| #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ |
| #define FLASH_CR_OPTPG_Pos (4U) |
| #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ |
| #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ |
| #define FLASH_CR_OPTER_Pos (5U) |
| #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ |
| #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ |
| #define FLASH_CR_STRT_Pos (6U) |
| #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ |
| #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ |
| #define FLASH_CR_LOCK_Pos (7U) |
| #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ |
| #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ |
| #define FLASH_CR_OPTWRE_Pos (9U) |
| #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ |
| #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ |
| #define FLASH_CR_ERRIE_Pos (10U) |
| #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ |
| #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ |
| #define FLASH_CR_EOPIE_Pos (12U) |
| #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ |
| #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ |
| #define FLASH_CR_OBL_LAUNCH_Pos (13U) |
| #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */ |
| #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */ |
| |
| /******************* Bit definition for FLASH_AR register *******************/ |
| #define FLASH_AR_FAR_Pos (0U) |
| #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ |
| #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ |
| |
| /****************** Bit definition for FLASH_OBR register *******************/ |
| #define FLASH_OBR_OPTERR_Pos (0U) |
| #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ |
| #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ |
| #define FLASH_OBR_RDPRT1_Pos (1U) |
| #define FLASH_OBR_RDPRT1_Msk (0x1UL << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */ |
| #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */ |
| #define FLASH_OBR_RDPRT2_Pos (2U) |
| #define FLASH_OBR_RDPRT2_Msk (0x1UL << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */ |
| #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */ |
| |
| #define FLASH_OBR_USER_Pos (8U) |
| #define FLASH_OBR_USER_Msk (0x77UL << FLASH_OBR_USER_Pos) /*!< 0x00007700 */ |
| #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ |
| #define FLASH_OBR_IWDG_SW_Pos (8U) |
| #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */ |
| #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ |
| #define FLASH_OBR_nRST_STOP_Pos (9U) |
| #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */ |
| #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ |
| #define FLASH_OBR_nRST_STDBY_Pos (10U) |
| #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */ |
| #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ |
| #define FLASH_OBR_nBOOT1_Pos (12U) |
| #define FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */ |
| #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */ |
| #define FLASH_OBR_VDDA_MONITOR_Pos (13U) |
| #define FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */ |
| #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */ |
| #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U) |
| #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */ |
| #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */ |
| #define FLASH_OBR_DATA0_Pos (16U) |
| #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */ |
| #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ |
| #define FLASH_OBR_DATA1_Pos (24U) |
| #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */ |
| #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ |
| |
| /* Old BOOT1 bit definition, maintained for legacy purpose */ |
| #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 |
| |
| /* Old OBR_VDDA bit definition, maintained for legacy purpose */ |
| #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR |
| |
| /****************** Bit definition for FLASH_WRPR register ******************/ |
| #define FLASH_WRPR_WRP_Pos (0U) |
| #define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ |
| #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ |
| |
| /*----------------------------------------------------------------------------*/ |
| |
| /****************** Bit definition for OB_RDP register **********************/ |
| #define OB_RDP_RDP_Pos (0U) |
| #define OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos) /*!< 0x000000FF */ |
| #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */ |
| #define OB_RDP_nRDP_Pos (8U) |
| #define OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */ |
| #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */ |
| |
| /****************** Bit definition for OB_USER register *********************/ |
| #define OB_USER_USER_Pos (16U) |
| #define OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos) /*!< 0x00FF0000 */ |
| #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */ |
| #define OB_USER_nUSER_Pos (24U) |
| #define OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos) /*!< 0xFF000000 */ |
| #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */ |
| |
| /****************** Bit definition for OB_WRP0 register *********************/ |
| #define OB_WRP0_WRP0_Pos (0U) |
| #define OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */ |
| #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ |
| #define OB_WRP0_nWRP0_Pos (8U) |
| #define OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ |
| #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* General Purpose IOs (GPIO) */ |
| /* */ |
| /******************************************************************************/ |
| /******************* Bit definition for GPIO_MODER register *****************/ |
| #define GPIO_MODER_MODER0_Pos (0U) |
| #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ |
| #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk |
| #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ |
| #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ |
| #define GPIO_MODER_MODER1_Pos (2U) |
| #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ |
| #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk |
| #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ |
| #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ |
| #define GPIO_MODER_MODER2_Pos (4U) |
| #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ |
| #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk |
| #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ |
| #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ |
| #define GPIO_MODER_MODER3_Pos (6U) |
| #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ |
| #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk |
| #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ |
| #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ |
| #define GPIO_MODER_MODER4_Pos (8U) |
| #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ |
| #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk |
| #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ |
| #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ |
| #define GPIO_MODER_MODER5_Pos (10U) |
| #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ |
| #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk |
| #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ |
| #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ |
| #define GPIO_MODER_MODER6_Pos (12U) |
| #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ |
| #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk |
| #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ |
| #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ |
| #define GPIO_MODER_MODER7_Pos (14U) |
| #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ |
| #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk |
| #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ |
| #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ |
| #define GPIO_MODER_MODER8_Pos (16U) |
| #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ |
| #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk |
| #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ |
| #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ |
| #define GPIO_MODER_MODER9_Pos (18U) |
| #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ |
| #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk |
| #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ |
| #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ |
| #define GPIO_MODER_MODER10_Pos (20U) |
| #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ |
| #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk |
| #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ |
| #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ |
| #define GPIO_MODER_MODER11_Pos (22U) |
| #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ |
| #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk |
| #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ |
| #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ |
| #define GPIO_MODER_MODER12_Pos (24U) |
| #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ |
| #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk |
| #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ |
| #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ |
| #define GPIO_MODER_MODER13_Pos (26U) |
| #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ |
| #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk |
| #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ |
| #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ |
| #define GPIO_MODER_MODER14_Pos (28U) |
| #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ |
| #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk |
| #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ |
| #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ |
| #define GPIO_MODER_MODER15_Pos (30U) |
| #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ |
| #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk |
| #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ |
| #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ |
| |
| /****************** Bit definition for GPIO_OTYPER register *****************/ |
| #define GPIO_OTYPER_OT_0 (0x00000001U) |
| #define GPIO_OTYPER_OT_1 (0x00000002U) |
| #define GPIO_OTYPER_OT_2 (0x00000004U) |
| #define GPIO_OTYPER_OT_3 (0x00000008U) |
| #define GPIO_OTYPER_OT_4 (0x00000010U) |
| #define GPIO_OTYPER_OT_5 (0x00000020U) |
| #define GPIO_OTYPER_OT_6 (0x00000040U) |
| #define GPIO_OTYPER_OT_7 (0x00000080U) |
| #define GPIO_OTYPER_OT_8 (0x00000100U) |
| #define GPIO_OTYPER_OT_9 (0x00000200U) |
| #define GPIO_OTYPER_OT_10 (0x00000400U) |
| #define GPIO_OTYPER_OT_11 (0x00000800U) |
| #define GPIO_OTYPER_OT_12 (0x00001000U) |
| #define GPIO_OTYPER_OT_13 (0x00002000U) |
| #define GPIO_OTYPER_OT_14 (0x00004000U) |
| #define GPIO_OTYPER_OT_15 (0x00008000U) |
| |
| /**************** Bit definition for GPIO_OSPEEDR register ******************/ |
| #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U) |
| #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */ |
| #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk |
| #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */ |
| #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */ |
| #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U) |
| #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */ |
| #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk |
| #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */ |
| #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */ |
| #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U) |
| #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */ |
| #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk |
| #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */ |
| #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */ |
| #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U) |
| #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */ |
| #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk |
| #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */ |
| #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */ |
| #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U) |
| #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */ |
| #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk |
| #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */ |
| #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */ |
| #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U) |
| #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */ |
| #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk |
| #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */ |
| #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */ |
| #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U) |
| #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */ |
| #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk |
| #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */ |
| #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */ |
| #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U) |
| #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */ |
| #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk |
| #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */ |
| #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */ |
| #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U) |
| #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */ |
| #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk |
| #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */ |
| #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */ |
| #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U) |
| #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */ |
| #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk |
| #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */ |
| #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */ |
| #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U) |
| #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */ |
| #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk |
| #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */ |
| #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */ |
| #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U) |
| #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */ |
| #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk |
| #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */ |
| #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */ |
| #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U) |
| #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */ |
| #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk |
| #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */ |
| #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */ |
| #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U) |
| #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */ |
| #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk |
| #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */ |
| #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */ |
| #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U) |
| #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */ |
| #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk |
| #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */ |
| #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */ |
| #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U) |
| #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */ |
| #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk |
| #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */ |
| #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */ |
| |
| /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */ |
| #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 |
| #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0 |
| #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1 |
| #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1 |
| #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0 |
| #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1 |
| #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2 |
| #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0 |
| #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1 |
| #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3 |
| #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0 |
| #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1 |
| #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4 |
| #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0 |
| #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1 |
| #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5 |
| #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0 |
| #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1 |
| #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6 |
| #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0 |
| #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1 |
| #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7 |
| #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0 |
| #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1 |
| #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8 |
| #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0 |
| #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1 |
| #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9 |
| #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0 |
| #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1 |
| #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10 |
| #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0 |
| #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1 |
| #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11 |
| #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0 |
| #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1 |
| #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12 |
| #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0 |
| #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1 |
| #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13 |
| #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0 |
| #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1 |
| #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14 |
| #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0 |
| #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1 |
| #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15 |
| #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0 |
| #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 |
| |
| /******************* Bit definition for GPIO_PUPDR register ******************/ |
| #define GPIO_PUPDR_PUPDR0_Pos (0U) |
| #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ |
| #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk |
| #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ |
| #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ |
| #define GPIO_PUPDR_PUPDR1_Pos (2U) |
| #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ |
| #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk |
| #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ |
| #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ |
| #define GPIO_PUPDR_PUPDR2_Pos (4U) |
| #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ |
| #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk |
| #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ |
| #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ |
| #define GPIO_PUPDR_PUPDR3_Pos (6U) |
| #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ |
| #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk |
| #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ |
| #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ |
| #define GPIO_PUPDR_PUPDR4_Pos (8U) |
| #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ |
| #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk |
| #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ |
| #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ |
| #define GPIO_PUPDR_PUPDR5_Pos (10U) |
| #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ |
| #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk |
| #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ |
| #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ |
| #define GPIO_PUPDR_PUPDR6_Pos (12U) |
| #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ |
| #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk |
| #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ |
| #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ |
| #define GPIO_PUPDR_PUPDR7_Pos (14U) |
| #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ |
| #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk |
| #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ |
| #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ |
| #define GPIO_PUPDR_PUPDR8_Pos (16U) |
| #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ |
| #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk |
| #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ |
| #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ |
| #define GPIO_PUPDR_PUPDR9_Pos (18U) |
| #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ |
| #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk |
| #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ |
| #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ |
| #define GPIO_PUPDR_PUPDR10_Pos (20U) |
| #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ |
| #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk |
| #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ |
| #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ |
| #define GPIO_PUPDR_PUPDR11_Pos (22U) |
| #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ |
| #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk |
| #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ |
| #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ |
| #define GPIO_PUPDR_PUPDR12_Pos (24U) |
| #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ |
| #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk |
| #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ |
| #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ |
| #define GPIO_PUPDR_PUPDR13_Pos (26U) |
| #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ |
| #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk |
| #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ |
| #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ |
| #define GPIO_PUPDR_PUPDR14_Pos (28U) |
| #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ |
| #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk |
| #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ |
| #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ |
| #define GPIO_PUPDR_PUPDR15_Pos (30U) |
| #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ |
| #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk |
| #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ |
| #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ |
| |
| /******************* Bit definition for GPIO_IDR register *******************/ |
| #define GPIO_IDR_0 (0x00000001U) |
| #define GPIO_IDR_1 (0x00000002U) |
| #define GPIO_IDR_2 (0x00000004U) |
| #define GPIO_IDR_3 (0x00000008U) |
| #define GPIO_IDR_4 (0x00000010U) |
| #define GPIO_IDR_5 (0x00000020U) |
| #define GPIO_IDR_6 (0x00000040U) |
| #define GPIO_IDR_7 (0x00000080U) |
| #define GPIO_IDR_8 (0x00000100U) |
| #define GPIO_IDR_9 (0x00000200U) |
| #define GPIO_IDR_10 (0x00000400U) |
| #define GPIO_IDR_11 (0x00000800U) |
| #define GPIO_IDR_12 (0x00001000U) |
| #define GPIO_IDR_13 (0x00002000U) |
| #define GPIO_IDR_14 (0x00004000U) |
| #define GPIO_IDR_15 (0x00008000U) |
| |
| /****************** Bit definition for GPIO_ODR register ********************/ |
| #define GPIO_ODR_0 (0x00000001U) |
| #define GPIO_ODR_1 (0x00000002U) |
| #define GPIO_ODR_2 (0x00000004U) |
| #define GPIO_ODR_3 (0x00000008U) |
| #define GPIO_ODR_4 (0x00000010U) |
| #define GPIO_ODR_5 (0x00000020U) |
| #define GPIO_ODR_6 (0x00000040U) |
| #define GPIO_ODR_7 (0x00000080U) |
| #define GPIO_ODR_8 (0x00000100U) |
| #define GPIO_ODR_9 (0x00000200U) |
| #define GPIO_ODR_10 (0x00000400U) |
| #define GPIO_ODR_11 (0x00000800U) |
| #define GPIO_ODR_12 (0x00001000U) |
| #define GPIO_ODR_13 (0x00002000U) |
| #define GPIO_ODR_14 (0x00004000U) |
| #define GPIO_ODR_15 (0x00008000U) |
| |
| /****************** Bit definition for GPIO_BSRR register ********************/ |
| #define GPIO_BSRR_BS_0 (0x00000001U) |
| #define GPIO_BSRR_BS_1 (0x00000002U) |
| #define GPIO_BSRR_BS_2 (0x00000004U) |
| #define GPIO_BSRR_BS_3 (0x00000008U) |
| #define GPIO_BSRR_BS_4 (0x00000010U) |
| #define GPIO_BSRR_BS_5 (0x00000020U) |
| #define GPIO_BSRR_BS_6 (0x00000040U) |
| #define GPIO_BSRR_BS_7 (0x00000080U) |
| #define GPIO_BSRR_BS_8 (0x00000100U) |
| #define GPIO_BSRR_BS_9 (0x00000200U) |
| #define GPIO_BSRR_BS_10 (0x00000400U) |
| #define GPIO_BSRR_BS_11 (0x00000800U) |
| #define GPIO_BSRR_BS_12 (0x00001000U) |
| #define GPIO_BSRR_BS_13 (0x00002000U) |
| #define GPIO_BSRR_BS_14 (0x00004000U) |
| #define GPIO_BSRR_BS_15 (0x00008000U) |
| #define GPIO_BSRR_BR_0 (0x00010000U) |
| #define GPIO_BSRR_BR_1 (0x00020000U) |
| #define GPIO_BSRR_BR_2 (0x00040000U) |
| #define GPIO_BSRR_BR_3 (0x00080000U) |
| #define GPIO_BSRR_BR_4 (0x00100000U) |
| #define GPIO_BSRR_BR_5 (0x00200000U) |
| #define GPIO_BSRR_BR_6 (0x00400000U) |
| #define GPIO_BSRR_BR_7 (0x00800000U) |
| #define GPIO_BSRR_BR_8 (0x01000000U) |
| #define GPIO_BSRR_BR_9 (0x02000000U) |
| #define GPIO_BSRR_BR_10 (0x04000000U) |
| #define GPIO_BSRR_BR_11 (0x08000000U) |
| #define GPIO_BSRR_BR_12 (0x10000000U) |
| #define GPIO_BSRR_BR_13 (0x20000000U) |
| #define GPIO_BSRR_BR_14 (0x40000000U) |
| #define GPIO_BSRR_BR_15 (0x80000000U) |
| |
| /****************** Bit definition for GPIO_LCKR register ********************/ |
| #define GPIO_LCKR_LCK0_Pos (0U) |
| #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ |
| #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk |
| #define GPIO_LCKR_LCK1_Pos (1U) |
| #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ |
| #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk |
| #define GPIO_LCKR_LCK2_Pos (2U) |
| #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ |
| #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk |
| #define GPIO_LCKR_LCK3_Pos (3U) |
| #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ |
| #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk |
| #define GPIO_LCKR_LCK4_Pos (4U) |
| #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ |
| #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk |
| #define GPIO_LCKR_LCK5_Pos (5U) |
| #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ |
| #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk |
| #define GPIO_LCKR_LCK6_Pos (6U) |
| #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ |
| #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk |
| #define GPIO_LCKR_LCK7_Pos (7U) |
| #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ |
| #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk |
| #define GPIO_LCKR_LCK8_Pos (8U) |
| #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ |
| #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk |
| #define GPIO_LCKR_LCK9_Pos (9U) |
| #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ |
| #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk |
| #define GPIO_LCKR_LCK10_Pos (10U) |
| #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ |
| #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk |
| #define GPIO_LCKR_LCK11_Pos (11U) |
| #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ |
| #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk |
| #define GPIO_LCKR_LCK12_Pos (12U) |
| #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ |
| #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk |
| #define GPIO_LCKR_LCK13_Pos (13U) |
| #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ |
| #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk |
| #define GPIO_LCKR_LCK14_Pos (14U) |
| #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ |
| #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk |
| #define GPIO_LCKR_LCK15_Pos (15U) |
| #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ |
| #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk |
| #define GPIO_LCKR_LCKK_Pos (16U) |
| #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ |
| #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk |
| |
| /****************** Bit definition for GPIO_AFRL register ********************/ |
| #define GPIO_AFRL_AFSEL0_Pos (0U) |
| #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ |
| #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk |
| #define GPIO_AFRL_AFSEL1_Pos (4U) |
| #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ |
| #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk |
| #define GPIO_AFRL_AFSEL2_Pos (8U) |
| #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ |
| #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk |
| #define GPIO_AFRL_AFSEL3_Pos (12U) |
| #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ |
| #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk |
| #define GPIO_AFRL_AFSEL4_Pos (16U) |
| #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ |
| #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk |
| #define GPIO_AFRL_AFSEL5_Pos (20U) |
| #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ |
| #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk |
| #define GPIO_AFRL_AFSEL6_Pos (24U) |
| #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ |
| #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
| #define GPIO_AFRL_AFSEL7_Pos (28U) |
| #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
| #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
| |
| /* Legacy aliases */ |
| #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
| #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
| #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
| #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
| #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
| #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 |
| #define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos |
| #define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk |
| #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 |
| #define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos |
| #define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk |
| #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 |
| #define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos |
| #define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk |
| #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 |
| #define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos |
| #define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk |
| #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 |
| #define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos |
| #define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk |
| #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 |
| #define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos |
| #define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk |
| #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 |
| |
| /****************** Bit definition for GPIO_AFRH register ********************/ |
| #define GPIO_AFRH_AFSEL8_Pos (0U) |
| #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ |
| #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk |
| #define GPIO_AFRH_AFSEL9_Pos (4U) |
| #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ |
| #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk |
| #define GPIO_AFRH_AFSEL10_Pos (8U) |
| #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ |
| #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk |
| #define GPIO_AFRH_AFSEL11_Pos (12U) |
| #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ |
| #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk |
| #define GPIO_AFRH_AFSEL12_Pos (16U) |
| #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ |
| #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk |
| #define GPIO_AFRH_AFSEL13_Pos (20U) |
| #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ |
| #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk |
| #define GPIO_AFRH_AFSEL14_Pos (24U) |
| #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ |
| #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk |
| #define GPIO_AFRH_AFSEL15_Pos (28U) |
| #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ |
| #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk |
| |
| /* Legacy aliases */ |
| #define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos |
| #define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk |
| #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 |
| #define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos |
| #define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk |
| #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 |
| #define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos |
| #define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk |
| #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 |
| #define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos |
| #define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk |
| #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 |
| #define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos |
| #define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk |
| #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 |
| #define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos |
| #define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk |
| #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 |
| #define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos |
| #define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk |
| #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 |
| #define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos |
| #define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk |
| #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 |
| |
| /****************** Bit definition for GPIO_BRR register *********************/ |
| #define GPIO_BRR_BR_0 (0x00000001U) |
| #define GPIO_BRR_BR_1 (0x00000002U) |
| #define GPIO_BRR_BR_2 (0x00000004U) |
| #define GPIO_BRR_BR_3 (0x00000008U) |
| #define GPIO_BRR_BR_4 (0x00000010U) |
| #define GPIO_BRR_BR_5 (0x00000020U) |
| #define GPIO_BRR_BR_6 (0x00000040U) |
| #define GPIO_BRR_BR_7 (0x00000080U) |
| #define GPIO_BRR_BR_8 (0x00000100U) |
| #define GPIO_BRR_BR_9 (0x00000200U) |
| #define GPIO_BRR_BR_10 (0x00000400U) |
| #define GPIO_BRR_BR_11 (0x00000800U) |
| #define GPIO_BRR_BR_12 (0x00001000U) |
| #define GPIO_BRR_BR_13 (0x00002000U) |
| #define GPIO_BRR_BR_14 (0x00004000U) |
| #define GPIO_BRR_BR_15 (0x00008000U) |
| |
| /******************************************************************************/ |
| /* */ |
| /* Inter-integrated Circuit Interface (I2C) */ |
| /* */ |
| /******************************************************************************/ |
| |
| /******************* Bit definition for I2C_CR1 register *******************/ |
| #define I2C_CR1_PE_Pos (0U) |
| #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ |
| #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ |
| #define I2C_CR1_TXIE_Pos (1U) |
| #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ |
| #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ |
| #define I2C_CR1_RXIE_Pos (2U) |
| #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ |
| #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ |
| #define I2C_CR1_ADDRIE_Pos (3U) |
| #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ |
| #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ |
| #define I2C_CR1_NACKIE_Pos (4U) |
| #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ |
| #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ |
| #define I2C_CR1_STOPIE_Pos (5U) |
| #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ |
| #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ |
| #define I2C_CR1_TCIE_Pos (6U) |
| #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ |
| #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ |
| #define I2C_CR1_ERRIE_Pos (7U) |
| #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ |
| #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ |
| #define I2C_CR1_DNF_Pos (8U) |
| #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ |
| #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ |
| #define I2C_CR1_ANFOFF_Pos (12U) |
| #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ |
| #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ |
| #define I2C_CR1_SWRST_Pos (13U) |
| #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ |
| #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ |
| #define I2C_CR1_TXDMAEN_Pos (14U) |
| #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ |
| #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ |
| #define I2C_CR1_RXDMAEN_Pos (15U) |
| #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ |
| #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ |
| #define I2C_CR1_SBC_Pos (16U) |
| #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ |
| #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ |
| #define I2C_CR1_NOSTRETCH_Pos (17U) |
| #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ |
| #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ |
| #define I2C_CR1_WUPEN_Pos (18U) |
| #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ |
| #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ |
| #define I2C_CR1_GCEN_Pos (19U) |
| #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ |
| #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ |
| #define I2C_CR1_SMBHEN_Pos (20U) |
| #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ |
| #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ |
| #define I2C_CR1_SMBDEN_Pos (21U) |
| #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ |
| #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ |
| #define I2C_CR1_ALERTEN_Pos (22U) |
| #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ |
| #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ |
| #define I2C_CR1_PECEN_Pos (23U) |
| #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ |
| #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ |
| |
| /****************** Bit definition for I2C_CR2 register ********************/ |
| #define I2C_CR2_SADD_Pos (0U) |
| #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ |
| #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ |
| #define I2C_CR2_RD_WRN_Pos (10U) |
| #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ |
| #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ |
| #define I2C_CR2_ADD10_Pos (11U) |
| #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ |
| #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ |
| #define I2C_CR2_HEAD10R_Pos (12U) |
| #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ |
| #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ |
| #define I2C_CR2_START_Pos (13U) |
| #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ |
| #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ |
| #define I2C_CR2_STOP_Pos (14U) |
| #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ |
| #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ |
| #define I2C_CR2_NACK_Pos (15U) |
| #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ |
| #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ |
| #define I2C_CR2_NBYTES_Pos (16U) |
| #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ |
| #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ |
| #define I2C_CR2_RELOAD_Pos (24U) |
| #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ |
| #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ |
| #define I2C_CR2_AUTOEND_Pos (25U) |
| #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ |
| #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ |
| #define I2C_CR2_PECBYTE_Pos (26U) |
| #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ |
| #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ |
| |
| /******************* Bit definition for I2C_OAR1 register ******************/ |
| #define I2C_OAR1_OA1_Pos (0U) |
| #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ |
| #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ |
| #define I2C_OAR1_OA1MODE_Pos (10U) |
| #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ |
| #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ |
| #define I2C_OAR1_OA1EN_Pos (15U) |
| #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ |
| #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ |
| |
| /******************* Bit definition for I2C_OAR2 register ******************/ |
| #define I2C_OAR2_OA2_Pos (1U) |
| #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ |
| #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ |
| #define I2C_OAR2_OA2MSK_Pos (8U) |
| #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ |
| #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ |
| #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ |
| #define I2C_OAR2_OA2MASK01_Pos (8U) |
| #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ |
| #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ |
| #define I2C_OAR2_OA2MASK02_Pos (9U) |
| #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ |
| #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ |
| #define I2C_OAR2_OA2MASK03_Pos (8U) |
| #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ |
| #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ |
| #define I2C_OAR2_OA2MASK04_Pos (10U) |
| #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ |
| #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ |
| #define I2C_OAR2_OA2MASK05_Pos (8U) |
| #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ |
| #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ |
| #define I2C_OAR2_OA2MASK06_Pos (9U) |
| #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ |
| #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ |
| #define I2C_OAR2_OA2MASK07_Pos (8U) |
| #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ |
| #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ |
| #define I2C_OAR2_OA2EN_Pos (15U) |
| #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ |
| #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ |
| |
| /******************* Bit definition for I2C_TIMINGR register ****************/ |
| #define I2C_TIMINGR_SCLL_Pos (0U) |
| #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ |
| #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ |
| #define I2C_TIMINGR_SCLH_Pos (8U) |
| #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ |
| #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ |
| #define I2C_TIMINGR_SDADEL_Pos (16U) |
| #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ |
| #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ |
| #define I2C_TIMINGR_SCLDEL_Pos (20U) |
| #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ |
| #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ |
| #define I2C_TIMINGR_PRESC_Pos (28U) |
| #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ |
| #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ |
| |
| /******************* Bit definition for I2C_TIMEOUTR register ****************/ |
| #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) |
| #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ |
|
