| /** |
| ****************************************************************************** |
| * @file stm32f078xx.h |
| * @author MCD Application Team |
| * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. |
| * This file contains all the peripheral register's definitions, bits |
| * definitions and memory mapping for STM32F0xx devices. |
| * |
| * This file contains: |
| * - Data structures and the address mapping for all peripherals |
| * - Peripheral's registers declarations and bits definition |
| * - Macros to access peripheralÂ’s registers hardware |
| * |
| ****************************************************************************** |
| * @attention |
| * |
| * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
| * All rights reserved.</center></h2> |
| * |
| * This software component is licensed by ST under BSD 3-Clause license, |
| * the "License"; You may not use this file except in compliance with the |
| * License. You may obtain a copy of the License at: |
| * opensource.org/licenses/BSD-3-Clause |
| * |
| ****************************************************************************** |
| */ |
| |
| /** @addtogroup CMSIS |
| * @{ |
| */ |
| |
| /** @addtogroup stm32f078xx |
| * @{ |
| */ |
| |
| #ifndef __STM32F078xx_H |
| #define __STM32F078xx_H |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif /* __cplusplus */ |
| |
| /** @addtogroup Configuration_section_for_CMSIS |
| * @{ |
| */ |
| /** |
| * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
| */ |
| #define __CM0_REV 0 /*!< Core Revision r0p0 */ |
| #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ |
| #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ |
| #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_interrupt_number_definition |
| * @{ |
| */ |
| |
| /** |
| * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
| * in @ref Library_configuration_section |
| */ |
| |
| /*!< Interrupt Number Definition */ |
| typedef enum |
| { |
| /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
| NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
| SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ |
| PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ |
| SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ |
| |
| /****** STM32F0 specific Interrupt Numbers ******************************************************************/ |
| WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| VDDIO2_IRQn = 1, /*!< VDDIO2 Interrupt through EXTI Line 31 */ |
| RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ |
| FLASH_IRQn = 3, /*!< FLASH global Interrupt */ |
| RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupt */ |
| EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ |
| EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ |
| EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ |
| TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ |
| DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ |
| DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ |
| DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 Interrupt */ |
| ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */ |
| TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ |
| TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ |
| TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ |
| TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ |
| TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupt */ |
| TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ |
| TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ |
| TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ |
| TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ |
| TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ |
| I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ |
| I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ |
| SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ |
| SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ |
| USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ |
| USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ |
| USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupt */ |
| CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ |
| USB_IRQn = 31 /*!< USB global Interrupt & EXTI Line18 Interrupt */ |
| } IRQn_Type; |
| |
| /** |
| * @} |
| */ |
| |
| #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ |
| #include "system_stm32f0xx.h" /* STM32F0xx System Header */ |
| #include <stdint.h> |
| |
| /** @addtogroup Peripheral_registers_structures |
| * @{ |
| */ |
| |
| /** |
| * @brief Analog to Digital Converter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ |
| __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ |
| __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ |
| __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ |
| __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ |
| __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ |
| uint32_t RESERVED1; /*!< Reserved, 0x18 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x1C */ |
| __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ |
| uint32_t RESERVED3; /*!< Reserved, 0x24 */ |
| __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ |
| uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ |
| __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ |
| } ADC_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ |
| } ADC_Common_TypeDef; |
| |
| /** |
| * @brief Controller Area Network TxMailBox |
| */ |
| typedef struct |
| { |
| __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ |
| __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ |
| __IO uint32_t TDLR; /*!< CAN mailbox data low register */ |
| __IO uint32_t TDHR; /*!< CAN mailbox data high register */ |
| }CAN_TxMailBox_TypeDef; |
| |
| /** |
| * @brief Controller Area Network FIFOMailBox |
| */ |
| typedef struct |
| { |
| __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ |
| __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ |
| __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ |
| __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ |
| }CAN_FIFOMailBox_TypeDef; |
| |
| /** |
| * @brief Controller Area Network FilterRegister |
| */ |
| typedef struct |
| { |
| __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ |
| __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ |
| }CAN_FilterRegister_TypeDef; |
| |
| /** |
| * @brief Controller Area Network |
| */ |
| typedef struct |
| { |
| __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ |
| __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ |
| __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ |
| __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ |
| __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ |
| __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ |
| __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ |
| __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ |
| uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ |
| CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ |
| CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ |
| uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ |
| __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ |
| __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x208 */ |
| __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ |
| uint32_t RESERVED3; /*!< Reserved, 0x210 */ |
| __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ |
| uint32_t RESERVED4; /*!< Reserved, 0x218 */ |
| __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ |
| uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ |
| CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN Filter Register, Address offset: 0x240-0x2AC */ |
| }CAN_TypeDef; |
| |
| /** |
| * @brief HDMI-CEC |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ |
| __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ |
| __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ |
| __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ |
| __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ |
| __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ |
| }CEC_TypeDef; |
| |
| /** |
| * @brief Comparator |
| */ |
| |
| typedef struct |
| { |
| __IO uint16_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ |
| } COMP_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ |
| } COMP_Common_TypeDef; |
| |
| /* Legacy defines */ |
| typedef struct |
| { |
| __IO uint32_t CSR; /*!< Kept for legacy purpose. Use structure 'COMP_Common_TypeDef'. */ |
| }COMP1_2_TypeDef; |
| |
| /** |
| * @brief CRC calculation unit |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| uint8_t RESERVED0; /*!< Reserved, 0x05 */ |
| uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x0C */ |
| __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ |
| __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ |
| } CRC_TypeDef; |
| |
| /** |
| * @brief Clock Recovery System |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ |
| __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ |
| __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ |
| __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ |
| }CRS_TypeDef; |
| |
| /** |
| * @brief Digital to Analog Converter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ |
| __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ |
| __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ |
| __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ |
| __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ |
| __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ |
| __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ |
| __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ |
| __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ |
| __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ |
| __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ |
| __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ |
| __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ |
| __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ |
| } DAC_TypeDef; |
| |
| /** |
| * @brief Debug MCU |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ |
| __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ |
| }DBGMCU_TypeDef; |
| |
| /** |
| * @brief DMA Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CCR; /*!< DMA channel x configuration register */ |
| __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ |
| __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ |
| __IO uint32_t CMAR; /*!< DMA channel x memory address register */ |
| } DMA_Channel_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ |
| __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ |
| } DMA_TypeDef; |
| |
| /** |
| * @brief External Interrupt/Event Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ |
| __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ |
| __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ |
| __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ |
| __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ |
| __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ |
| } EXTI_TypeDef; |
| |
| /** |
| * @brief FLASH Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */ |
| __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */ |
| __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */ |
| __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */ |
| __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */ |
| __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */ |
| __IO uint32_t RESERVED; /*!< Reserved, 0x18 */ |
| __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */ |
| __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */ |
| } FLASH_TypeDef; |
| |
| /** |
| * @brief Option Bytes Registers |
| */ |
| typedef struct |
| { |
| __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ |
| __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ |
| __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ |
| __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ |
| __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ |
| __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ |
| __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */ |
| __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */ |
| } OB_TypeDef; |
| |
| /** |
| * @brief General Purpose I/O |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ |
| __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ |
| __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ |
| } GPIO_TypeDef; |
| |
| /** |
| * @brief SysTem Configuration |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ |
| uint32_t RESERVED; /*!< Reserved, 0x04 */ |
| __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ |
| __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ |
| } SYSCFG_TypeDef; |
| |
| /** |
| * @brief Inter-integrated Circuit Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ |
| __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ |
| __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ |
| __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ |
| __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ |
| __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ |
| __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ |
| __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ |
| __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ |
| } I2C_TypeDef; |
| |
| /** |
| * @brief Independent WATCHDOG |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
| __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
| __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
| __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
| __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ |
| } IWDG_TypeDef; |
| |
| /** |
| * @brief Power Control |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ |
| __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ |
| } PWR_TypeDef; |
| |
| /** |
| * @brief Reset and Clock Control |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
| __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ |
| __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ |
| __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ |
| __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ |
| __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ |
| __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ |
| __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ |
| __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ |
| __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ |
| __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ |
| __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ |
| __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ |
| __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */ |
| } RCC_TypeDef; |
| |
| /** |
| * @brief Real-Time Clock |
| */ |
| typedef struct |
| { |
| __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
| __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
| __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
| __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
| __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
| __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
| uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ |
| __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
| uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ |
| __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
| __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
| __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
| __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
| __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
| __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
| __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
| __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ |
| __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ |
| uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ |
| uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */ |
| __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ |
| __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
| __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
| __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
| __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
| } RTC_TypeDef; |
| |
| /** |
| * @brief Serial Peripheral Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ |
| __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ |
| __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ |
| __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ |
| __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ |
| __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ |
| } SPI_TypeDef; |
| |
| /** |
| * @brief TIM |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ |
| __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ |
| __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ |
| __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
| } TIM_TypeDef; |
| |
| /** |
| * @brief Touch Sensing Controller (TSC) |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ |
| __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ |
| __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ |
| __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ |
| __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ |
| uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ |
| __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ |
| uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ |
| __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ |
| uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ |
| __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ |
| uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ |
| __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ |
| __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ |
| }TSC_TypeDef; |
| |
| /** |
| * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ |
| __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ |
| __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ |
| __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ |
| __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ |
| __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ |
| __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ |
| __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ |
| __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ |
| uint16_t RESERVED1; /*!< Reserved, 0x26 */ |
| __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ |
| uint16_t RESERVED2; /*!< Reserved, 0x2A */ |
| } USART_TypeDef; |
| |
| /** |
| * @brief Universal Serial Bus Full Speed Device |
| */ |
| |
| typedef struct |
| { |
| __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ |
| __IO uint16_t RESERVED0; /*!< Reserved */ |
| __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ |
| __IO uint16_t RESERVED1; /*!< Reserved */ |
| __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ |
| __IO uint16_t RESERVED2; /*!< Reserved */ |
| __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ |
| __IO uint16_t RESERVED3; /*!< Reserved */ |
| __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ |
| __IO uint16_t RESERVED4; /*!< Reserved */ |
| __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ |
| __IO uint16_t RESERVED5; /*!< Reserved */ |
| __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ |
| __IO uint16_t RESERVED6; /*!< Reserved */ |
| __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ |
| __IO uint16_t RESERVED7[17]; /*!< Reserved */ |
| __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ |
| __IO uint16_t RESERVED8; /*!< Reserved */ |
| __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ |
| __IO uint16_t RESERVED9; /*!< Reserved */ |
| __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ |
| __IO uint16_t RESERVEDA; /*!< Reserved */ |
| __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ |
| __IO uint16_t RESERVEDB; /*!< Reserved */ |
| __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ |
| __IO uint16_t RESERVEDC; /*!< Reserved */ |
| __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ |
| __IO uint16_t RESERVEDD; /*!< Reserved */ |
| __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ |
| __IO uint16_t RESERVEDE; /*!< Reserved */ |
| } USB_TypeDef; |
| |
| /** |
| * @brief Window WATCHDOG |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| } WWDG_TypeDef; |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_memory_map |
| * @{ |
| */ |
| |
| #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ |
| #define FLASH_BANK1_END 0x0801FFFFUL /*!< FLASH END address of bank1 */ |
| #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ |
| #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ |
| |
| /*!< Peripheral memory map */ |
| #define APBPERIPH_BASE PERIPH_BASE |
| #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
| #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) |
| |
| /*!< APB peripherals */ |
| #define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL) |
| #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) |
| #define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) |
| #define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) |
| #define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) |
| #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) |
| #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) |
| #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) |
| #define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) |
| #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) |
| #define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) |
| #define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) |
| #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) |
| #define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) |
| #define USB_BASE (APBPERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ |
| #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ |
| #define CAN_BASE (APBPERIPH_BASE + 0x00006400UL) |
| #define CRS_BASE (APBPERIPH_BASE + 0x00006C00UL) |
| #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) |
| #define DAC_BASE (APBPERIPH_BASE + 0x00007400UL) |
| |
| #define CEC_BASE (APBPERIPH_BASE + 0x00007800UL) |
| |
| #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) |
| #define COMP_BASE (APBPERIPH_BASE + 0x0001001CUL) |
| #define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL) |
| #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) |
| #define ADC_BASE (APBPERIPH_BASE + 0x00012708UL) |
| #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) |
| #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) |
| #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) |
| #define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) |
| #define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) |
| #define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) |
| #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) |
| |
| /*!< AHB peripherals */ |
| #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) |
| #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) |
| #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) |
| #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) |
| #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) |
| #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) |
| #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) |
| #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) |
| |
| #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) |
| #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ |
| #define OB_BASE 0x1FFFF800UL /*!< FLASH Option Bytes base address */ |
| #define FLASHSIZE_BASE 0x1FFFF7CCUL /*!< FLASH Size register base address */ |
| #define UID_BASE 0x1FFFF7ACUL /*!< Unique device ID register base address */ |
| #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) |
| #define TSC_BASE (AHBPERIPH_BASE + 0x00004000UL) |
| |
| /*!< AHB2 peripherals */ |
| #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL) |
| #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL) |
| #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL) |
| #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL) |
| #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000UL) |
| #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL) |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_declaration |
| * @{ |
| */ |
| |
| #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
| #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
| #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
| #define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
| #define RTC ((RTC_TypeDef *) RTC_BASE) |
| #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| #define USART2 ((USART_TypeDef *) USART2_BASE) |
| #define USART3 ((USART_TypeDef *) USART3_BASE) |
| #define USART4 ((USART_TypeDef *) USART4_BASE) |
| #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
| #define CAN ((CAN_TypeDef *) CAN_BASE) |
| #define CRS ((CRS_TypeDef *) CRS_BASE) |
| #define PWR ((PWR_TypeDef *) PWR_BASE) |
| #define DAC1 ((DAC_TypeDef *) DAC_BASE) |
| #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ |
| #define CEC ((CEC_TypeDef *) CEC_BASE) |
| #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
| #define COMP1 ((COMP_TypeDef *) COMP_BASE) |
| #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002)) |
| #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) |
| #define COMP ((COMP1_2_TypeDef *) COMP_BASE) /* Kept for legacy purpose */ |
| #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) |
| #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */ |
| #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
| #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
| #define USART1 ((USART_TypeDef *) USART1_BASE) |
| #define TIM15 ((TIM_TypeDef *) TIM15_BASE) |
| #define TIM16 ((TIM_TypeDef *) TIM16_BASE) |
| #define TIM17 ((TIM_TypeDef *) TIM17_BASE) |
| #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
| #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
| #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
| #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
| #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
| #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
| #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
| #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| #define OB ((OB_TypeDef *) OB_BASE) |
| #define RCC ((RCC_TypeDef *) RCC_BASE) |
| #define CRC ((CRC_TypeDef *) CRC_BASE) |
| #define TSC ((TSC_TypeDef *) TSC_BASE) |
| #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
| #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
| #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
| #define USB ((USB_TypeDef *) USB_BASE) |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Exported_constants |
| * @{ |
| */ |
| |
| /** @addtogroup Hardware_Constant_Definition |
| * @{ |
| */ |
| #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_Registers_Bits_Definition |
| * @{ |
| */ |
| |
| /******************************************************************************/ |
| /* Peripheral Registers Bits Definition */ |
| /******************************************************************************/ |
| |
| /******************************************************************************/ |
| /* */ |
| /* Analog to Digital Converter (ADC) */ |
| /* */ |
| /******************************************************************************/ |
| |
| /* |
| * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) |
| */ |
| #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */ |
| |
| /******************** Bits definition for ADC_ISR register ******************/ |
| #define ADC_ISR_ADRDY_Pos (0U) |
| #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ |
| #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ |
| #define ADC_ISR_EOSMP_Pos (1U) |
| #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ |
| #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ |
| #define ADC_ISR_EOC_Pos (2U) |
| #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ |
| #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ |
| #define ADC_ISR_EOS_Pos (3U) |
| #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ |
| #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ |
| #define ADC_ISR_OVR_Pos (4U) |
| #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ |
| #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ |
| #define ADC_ISR_AWD1_Pos (7U) |
| #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ |
| #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ |
| |
| /* Legacy defines */ |
| #define ADC_ISR_AWD (ADC_ISR_AWD1) |
| #define ADC_ISR_EOSEQ (ADC_ISR_EOS) |
| |
| /******************** Bits definition for ADC_IER register ******************/ |
| #define ADC_IER_ADRDYIE_Pos (0U) |
| #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ |
| #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ |
| #define ADC_IER_EOSMPIE_Pos (1U) |
| #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ |
| #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ |
| #define ADC_IER_EOCIE_Pos (2U) |
| #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ |
| #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ |
| #define ADC_IER_EOSIE_Pos (3U) |
| #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ |
| #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ |
| #define ADC_IER_OVRIE_Pos (4U) |
| #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ |
| #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ |
| #define ADC_IER_AWD1IE_Pos (7U) |
| #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ |
| #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ |
| |
| /* Legacy defines */ |
| #define ADC_IER_AWDIE (ADC_IER_AWD1IE) |
| #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) |
| |
| /******************** Bits definition for ADC_CR register *******************/ |
| #define ADC_CR_ADEN_Pos (0U) |
| #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ |
| #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ |
| #define ADC_CR_ADDIS_Pos (1U) |
| #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ |
| #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ |
| #define ADC_CR_ADSTART_Pos (2U) |
| #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ |
| #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ |
| #define ADC_CR_ADSTP_Pos (4U) |
| #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ |
| #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ |
| #define ADC_CR_ADCAL_Pos (31U) |
| #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ |
| #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ |
| |
| /******************* Bits definition for ADC_CFGR1 register *****************/ |
| #define ADC_CFGR1_DMAEN_Pos (0U) |
| #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ |
| #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ |
| #define ADC_CFGR1_DMACFG_Pos (1U) |
| #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ |
| #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ |
| #define ADC_CFGR1_SCANDIR_Pos (2U) |
| #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ |
| #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ |
| |
| #define ADC_CFGR1_RES_Pos (3U) |
| #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ |
| #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ |
| #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ |
| #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ |
| |
| #define ADC_CFGR1_ALIGN_Pos (5U) |
| #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ |
| #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ |
| |
| #define ADC_CFGR1_EXTSEL_Pos (6U) |
| #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ |
| #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ |
| #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ |
| #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ |
| #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ |
| |
| #define ADC_CFGR1_EXTEN_Pos (10U) |
| #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ |
| #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ |
| #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ |
| #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_CFGR1_OVRMOD_Pos (12U) |
| #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ |
| #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ |
| #define ADC_CFGR1_CONT_Pos (13U) |
| #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ |
| #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ |
| #define ADC_CFGR1_WAIT_Pos (14U) |
| #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ |
| #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ |
| #define ADC_CFGR1_AUTOFF_Pos (15U) |
| #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ |
| #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ |
| #define ADC_CFGR1_DISCEN_Pos (16U) |
| #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ |
| #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ |
| |
| #define ADC_CFGR1_AWD1SGL_Pos (22U) |
| #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ |
| #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ |
| #define ADC_CFGR1_AWD1EN_Pos (23U) |
| #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ |
| #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ |
| |
| #define ADC_CFGR1_AWD1CH_Pos (26U) |
| #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ |
| #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ |
| #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ |
| #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ |
| #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ |
| #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ |
| #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ |
| |
| /* Legacy defines */ |
| #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) |
| #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL) |
| #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN) |
| #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH) |
| #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0) |
| #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1) |
| #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2) |
| #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) |
| #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) |
| |
| /******************* Bits definition for ADC_CFGR2 register *****************/ |
| #define ADC_CFGR2_CKMODE_Pos (30U) |
| #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ |
| #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ |
| #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ |
| #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ |
| |
| /* Legacy defines */ |
| #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */ |
| #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */ |
| |
| /****************** Bit definition for ADC_SMPR register ********************/ |
| #define ADC_SMPR_SMP_Pos (0U) |
| #define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ |
| #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */ |
| #define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ |
| #define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ |
| #define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ |
| |
| /* Legacy defines */ |
| #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */ |
| #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */ |
| #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */ |
| #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */ |
| |
| /******************* Bit definition for ADC_TR register ********************/ |
| #define ADC_TR1_LT1_Pos (0U) |
| #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ |
| #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ |
| #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ |
| #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ |
| #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ |
| #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ |
| #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ |
| #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ |
| #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ |
| #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ |
| #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ |
| #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ |
| #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ |
| #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_TR1_HT1_Pos (16U) |
| #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ |
| #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ |
| #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ |
| #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ |
| #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ |
| #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ |
| #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ |
| #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ |
| #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ |
| #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ |
| #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ |
| #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ |
| #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ |
| #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ |
| |
| /* Legacy defines */ |
| #define ADC_TR_HT (ADC_TR1_HT1) |
| #define ADC_TR_LT (ADC_TR1_LT1) |
| #define ADC_HTR_HT (ADC_TR1_HT1) |
| #define ADC_LTR_LT (ADC_TR1_LT1) |
| |
| /****************** Bit definition for ADC_CHSELR register ******************/ |
| #define ADC_CHSELR_CHSEL_Pos (0U) |
| #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ |
| #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL18_Pos (18U) |
| #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ |
| #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL17_Pos (17U) |
| #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ |
| #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL16_Pos (16U) |
| #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ |
| #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL15_Pos (15U) |
| #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ |
| #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL14_Pos (14U) |
| #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ |
| #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL13_Pos (13U) |
| #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ |
| #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL12_Pos (12U) |
| #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ |
| #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL11_Pos (11U) |
| #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ |
| #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL10_Pos (10U) |
| #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ |
| #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL9_Pos (9U) |
| #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ |
| #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL8_Pos (8U) |
| #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ |
| #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL7_Pos (7U) |
| #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ |
| #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL6_Pos (6U) |
| #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ |
| #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL5_Pos (5U) |
| #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ |
| #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL4_Pos (4U) |
| #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ |
| #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL3_Pos (3U) |
| #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ |
| #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL2_Pos (2U) |
| #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ |
| #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL1_Pos (1U) |
| #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ |
| #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ |
| #define ADC_CHSELR_CHSEL0_Pos (0U) |
| #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ |
| #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ |
| |
| /******************** Bit definition for ADC_DR register ********************/ |
| #define ADC_DR_DATA_Pos (0U) |
| #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ |
| #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ |
| #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ |
| #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ |
| #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ |
| #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ |
| #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ |
| #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ |
| #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ |
| #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ |
| #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ |
| #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ |
| #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ |
| #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ |
| #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ |
| #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ |
| #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ |
| |
| /************************* ADC Common registers *****************************/ |
| /******************* Bit definition for ADC_CCR register ********************/ |
| #define ADC_CCR_VREFEN_Pos (22U) |
| #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ |
| #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ |
| #define ADC_CCR_TSEN_Pos (23U) |
| #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ |
| #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ |
| |
| #define ADC_CCR_VBATEN_Pos (24U) |
| #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ |
| #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* Controller Area Network (CAN ) */ |
| /* */ |
| /******************************************************************************/ |
| /*!<CAN control and status registers */ |
| /******************* Bit definition for CAN_MCR register ********************/ |
| #define CAN_MCR_INRQ_Pos (0U) |
| #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ |
| #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */ |
| #define CAN_MCR_SLEEP_Pos (1U) |
| #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ |
| #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */ |
| #define CAN_MCR_TXFP_Pos (2U) |
| #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ |
| #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */ |
| #define CAN_MCR_RFLM_Pos (3U) |
| #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ |
| #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */ |
| #define CAN_MCR_NART_Pos (4U) |
| #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */ |
| #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */ |
| #define CAN_MCR_AWUM_Pos (5U) |
| #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ |
| #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */ |
| #define CAN_MCR_ABOM_Pos (6U) |
| #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ |
| #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */ |
| #define CAN_MCR_TTCM_Pos (7U) |
| #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ |
| #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */ |
| #define CAN_MCR_RESET_Pos (15U) |
| #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ |
| #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */ |
| |
| /******************* Bit definition for CAN_MSR register ********************/ |
| #define CAN_MSR_INAK_Pos (0U) |
| #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ |
| #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */ |
| #define CAN_MSR_SLAK_Pos (1U) |
| #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ |
| #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */ |
| #define CAN_MSR_ERRI_Pos (2U) |
| #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ |
| #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */ |
| #define CAN_MSR_WKUI_Pos (3U) |
| #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ |
| #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */ |
| #define CAN_MSR_SLAKI_Pos (4U) |
| #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ |
| #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */ |
| #define CAN_MSR_TXM_Pos (8U) |
| #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ |
| #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */ |
| #define CAN_MSR_RXM_Pos (9U) |
| #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ |
| #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */ |
| #define CAN_MSR_SAMP_Pos (10U) |
| #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ |
| #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */ |
| #define CAN_MSR_RX_Pos (11U) |
| #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */ |
| #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */ |
| |
| /******************* Bit definition for CAN_TSR register ********************/ |
| #define CAN_TSR_RQCP0_Pos (0U) |
| #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ |
| #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */ |
| #define CAN_TSR_TXOK0_Pos (1U) |
| #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ |
| #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */ |
| #define CAN_TSR_ALST0_Pos (2U) |
| #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ |
| #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */ |
| #define CAN_TSR_TERR0_Pos (3U) |
| #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ |
| #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */ |
| #define CAN_TSR_ABRQ0_Pos (7U) |
| #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ |
| #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */ |
| #define CAN_TSR_RQCP1_Pos (8U) |
| #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ |
| #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */ |
| #define CAN_TSR_TXOK1_Pos (9U) |
| #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ |
| #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */ |
| #define CAN_TSR_ALST1_Pos (10U) |
| #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ |
| #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */ |
| #define CAN_TSR_TERR1_Pos (11U) |
| #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ |
| #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */ |
| #define CAN_TSR_ABRQ1_Pos (15U) |
| #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ |
| #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */ |
| #define CAN_TSR_RQCP2_Pos (16U) |
| #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ |
| #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */ |
| #define CAN_TSR_TXOK2_Pos (17U) |
| #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ |
| #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */ |
| #define CAN_TSR_ALST2_Pos (18U) |
| #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ |
| #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */ |
| #define CAN_TSR_TERR2_Pos (19U) |
| #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ |
| #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */ |
| #define CAN_TSR_ABRQ2_Pos (23U) |
| #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ |
| #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */ |
| #define CAN_TSR_CODE_Pos (24U) |
| #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ |
| #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */ |
| |
| #define CAN_TSR_TME_Pos (26U) |
| #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ |
| #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */ |
| #define CAN_TSR_TME0_Pos (26U) |
| #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ |
| #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */ |
| #define CAN_TSR_TME1_Pos (27U) |
| #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ |
| #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */ |
| #define CAN_TSR_TME2_Pos (28U) |
| #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ |
| #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */ |
| |
| #define CAN_TSR_LOW_Pos (29U) |
| #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ |
| #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */ |
| #define CAN_TSR_LOW0_Pos (29U) |
| #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ |
| #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */ |
| #define CAN_TSR_LOW1_Pos (30U) |
| #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ |
| #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */ |
| #define CAN_TSR_LOW2_Pos (31U) |
| #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ |
| #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */ |
| |
| /******************* Bit definition for CAN_RF0R register *******************/ |
| #define CAN_RF0R_FMP0_Pos (0U) |
| #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ |
| #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */ |
| #define CAN_RF0R_FULL0_Pos (3U) |
| #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ |
| #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */ |
| #define CAN_RF0R_FOVR0_Pos (4U) |
| #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ |
| #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */ |
| #define CAN_RF0R_RFOM0_Pos (5U) |
| #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ |
| #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */ |
| |
| /******************* Bit definition for CAN_RF1R register *******************/ |
| #define CAN_RF1R_FMP1_Pos (0U) |
| #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ |
| #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */ |
| #define CAN_RF1R_FULL1_Pos (3U) |
| #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ |
| #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */ |
| #define CAN_RF1R_FOVR1_Pos (4U) |
| #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ |
| #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */ |
| #define CAN_RF1R_RFOM1_Pos (5U) |
| #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ |
| #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */ |
| |
| /******************** Bit definition for CAN_IER register *******************/ |
| #define CAN_IER_TMEIE_Pos (0U) |
| #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ |
| #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */ |
| #define CAN_IER_FMPIE0_Pos (1U) |
| #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ |
| #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */ |
| #define CAN_IER_FFIE0_Pos (2U) |
| #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ |
| #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */ |
| #define CAN_IER_FOVIE0_Pos (3U) |
| #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ |
| #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */ |
| #define CAN_IER_FMPIE1_Pos (4U) |
| #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ |
| #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */ |
| #define CAN_IER_FFIE1_Pos (5U) |
| #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ |
| #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */ |
| #define CAN_IER_FOVIE1_Pos (6U) |
| #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ |
| #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */ |
| #define CAN_IER_EWGIE_Pos (8U) |
| #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ |
| #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */ |
| #define CAN_IER_EPVIE_Pos (9U) |
| #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ |
| #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */ |
| #define CAN_IER_BOFIE_Pos (10U) |
| #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ |
| #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */ |
| #define CAN_IER_LECIE_Pos (11U) |
| #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ |
| #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */ |
| #define CAN_IER_ERRIE_Pos (15U) |
| #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ |
| #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */ |
| #define CAN_IER_WKUIE_Pos (16U) |
| #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ |
| #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */ |
| #define CAN_IER_SLKIE_Pos (17U) |
| #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ |
| #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */ |
| |
| /******************** Bit definition for CAN_ESR register *******************/ |
| #define CAN_ESR_EWGF_Pos (0U) |
| #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ |
| #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */ |
| #define CAN_ESR_EPVF_Pos (1U) |
| #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ |
| #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */ |
| #define CAN_ESR_BOFF_Pos (2U) |
| #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ |
| #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */ |
| |
| #define CAN_ESR_LEC_Pos (4U) |
| #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ |
| #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */ |
| #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ |
| #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ |
| #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ |
| |
| #define CAN_ESR_TEC_Pos (16U) |
| #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ |
| #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */ |
| #define CAN_ESR_REC_Pos (24U) |
| #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ |
| #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */ |
| |
| /******************* Bit definition for CAN_BTR register ********************/ |
| #define CAN_BTR_BRP_Pos (0U) |
| #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ |
| #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ |
| #define CAN_BTR_TS1_Pos (16U) |
| #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ |
| #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ |
| #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ |
| #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ |
| #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ |
| #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ |
| #define CAN_BTR_TS2_Pos (20U) |
| #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ |
| #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ |
| #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ |
| #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ |
| #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ |
| #define CAN_BTR_SJW_Pos (24U) |
| #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ |
| #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ |
| #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ |
| #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ |
| #define CAN_BTR_LBKM_Pos (30U) |
| #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ |
| #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ |
| #define CAN_BTR_SILM_Pos (31U) |
| #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ |
| #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ |
| |
| /*!<Mailbox registers */ |
| /****************** Bit definition for CAN_TI0R register ********************/ |
| #define CAN_TI0R_TXRQ_Pos (0U) |
| #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ |
| #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| #define CAN_TI0R_RTR_Pos (1U) |
| #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ |
| #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */ |
| #define CAN_TI0R_IDE_Pos (2U) |
| #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ |
| #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */ |
| #define CAN_TI0R_EXID_Pos (3U) |
| #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */ |
| #define CAN_TI0R_STID_Pos (21U) |
| #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ |
| #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| |
| /****************** Bit definition for CAN_TDT0R register *******************/ |
| #define CAN_TDT0R_DLC_Pos (0U) |
| #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ |
| #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */ |
| #define CAN_TDT0R_TGT_Pos (8U) |
| #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ |
| #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */ |
| #define CAN_TDT0R_TIME_Pos (16U) |
| #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */ |
| |
| /****************** Bit definition for CAN_TDL0R register *******************/ |
| #define CAN_TDL0R_DATA0_Pos (0U) |
| #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */ |
| #define CAN_TDL0R_DATA1_Pos (8U) |
| #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */ |
| #define CAN_TDL0R_DATA2_Pos (16U) |
| #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */ |
| #define CAN_TDL0R_DATA3_Pos (24U) |
| #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */ |
| |
| /****************** Bit definition for CAN_TDH0R register *******************/ |
| #define CAN_TDH0R_DATA4_Pos (0U) |
| #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */ |
| #define CAN_TDH0R_DATA5_Pos (8U) |
| #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */ |
| #define CAN_TDH0R_DATA6_Pos (16U) |
| #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */ |
| #define CAN_TDH0R_DATA7_Pos (24U) |
| #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */ |
| |
| /******************* Bit definition for CAN_TI1R register *******************/ |
| #define CAN_TI1R_TXRQ_Pos (0U) |
| #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ |
| #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| #define CAN_TI1R_RTR_Pos (1U) |
| #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ |
| #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */ |
| #define CAN_TI1R_IDE_Pos (2U) |
| #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ |
| #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */ |
| #define CAN_TI1R_EXID_Pos (3U) |
| #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */ |
| #define CAN_TI1R_STID_Pos (21U) |
| #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ |
| #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| |
| /******************* Bit definition for CAN_TDT1R register ******************/ |
| #define CAN_TDT1R_DLC_Pos (0U) |
| #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ |
| #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */ |
| #define CAN_TDT1R_TGT_Pos (8U) |
| #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ |
| #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */ |
| #define CAN_TDT1R_TIME_Pos (16U) |
| #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */ |
| |
| /******************* Bit definition for CAN_TDL1R register ******************/ |
| #define CAN_TDL1R_DATA0_Pos (0U) |
| #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */ |
| #define CAN_TDL1R_DATA1_Pos (8U) |
| #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */ |
| #define CAN_TDL1R_DATA2_Pos (16U) |
| #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */ |
| #define CAN_TDL1R_DATA3_Pos (24U) |
| #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */ |
| |
| /******************* Bit definition for CAN_TDH1R register ******************/ |
| #define CAN_TDH1R_DATA4_Pos (0U) |
| #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */ |
| #define CAN_TDH1R_DATA5_Pos (8U) |
| #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */ |
| #define CAN_TDH1R_DATA6_Pos (16U) |
| #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */ |
| #define CAN_TDH1R_DATA7_Pos (24U) |
| #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */ |
| |
| /******************* Bit definition for CAN_TI2R register *******************/ |
| #define CAN_TI2R_TXRQ_Pos (0U) |
| #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ |
| #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| #define CAN_TI2R_RTR_Pos (1U) |
| #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ |
| #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */ |
| #define CAN_TI2R_IDE_Pos (2U) |
| #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ |
| #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */ |
| #define CAN_TI2R_EXID_Pos (3U) |
| #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ |
| #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */ |
| #define CAN_TI2R_STID_Pos (21U) |
| #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ |
| #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| |
| /******************* Bit definition for CAN_TDT2R register ******************/ |
| #define CAN_TDT2R_DLC_Pos (0U) |
| #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ |
| #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */ |
| #define CAN_TDT2R_TGT_Pos (8U) |
| #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ |
| #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */ |
| #define CAN_TDT2R_TIME_Pos (16U) |
| #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ |
| #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */ |
| |
| /******************* Bit definition for CAN_TDL2R register ******************/ |
| #define CAN_TDL2R_DATA0_Pos (0U) |
| #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ |
| #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */ |
| #define CAN_TDL2R_DATA1_Pos (8U) |
| #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ |
| #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */ |
| #define CAN_TDL2R_DATA2_Pos (16U) |
| #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ |
| #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */ |
| #define CAN_TDL2R_DATA3_Pos (24U) |
| #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ |
| #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */ |
| |
| /******************* Bit definition for CAN_TDH2R register ******************/ |
| #define CAN_TDH2R_DATA4_Pos (0U) |
| #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ |
| #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */ |
| #define CAN_TDH2R_DATA5_Pos (8U) |
| #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ |
| #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */ |
| #define CAN_TDH2R_DATA6_Pos (16U) |
| #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ |
| #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */ |
| #define CAN_TDH2R_DATA7_Pos (24U) |
| #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ |
| #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */ |
| |
| /******************* Bit definition for CAN_RI0R register *******************/ |
| #define CAN_RI0R_RTR_Pos (1U) |
| #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ |
| #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */ |
| #define CAN_RI0R_IDE_Pos (2U) |
| #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ |
| #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */ |
| #define CAN_RI0R_EXID_Pos (3U) |
| #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */ |
| #define CAN_RI0R_STID_Pos (21U) |
| #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ |
| #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| |
| /******************* Bit definition for CAN_RDT0R register ******************/ |
| #define CAN_RDT0R_DLC_Pos (0U) |
| #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ |
| #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */ |
| #define CAN_RDT0R_FMI_Pos (8U) |
| #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ |
| #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */ |
| #define CAN_RDT0R_TIME_Pos (16U) |
| #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */ |
| |
| /******************* Bit definition for CAN_RDL0R register ******************/ |
| #define CAN_RDL0R_DATA0_Pos (0U) |
| #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */ |
| #define CAN_RDL0R_DATA1_Pos (8U) |
| #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */ |
| #define CAN_RDL0R_DATA2_Pos (16U) |
| #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */ |
| #define CAN_RDL0R_DATA3_Pos (24U) |
| #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */ |
| |
| /******************* Bit definition for CAN_RDH0R register ******************/ |
| #define CAN_RDH0R_DATA4_Pos (0U) |
| #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */ |
| #define CAN_RDH0R_DATA5_Pos (8U) |
| #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */ |
| #define CAN_RDH0R_DATA6_Pos (16U) |
| #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */ |
| #define CAN_RDH0R_DATA7_Pos (24U) |
| #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */ |
| |
| /******************* Bit definition for CAN_RI1R register *******************/ |
| #define CAN_RI1R_RTR_Pos (1U) |
| #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ |
| #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */ |
| #define CAN_RI1R_IDE_Pos (2U) |
| #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ |
| #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */ |
| #define CAN_RI1R_EXID_Pos (3U) |
| #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */ |
| #define CAN_RI1R_STID_Pos (21U) |
| #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ |
| #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| |
| /******************* Bit definition for CAN_RDT1R register ******************/ |
| #define CAN_RDT1R_DLC_Pos (0U) |
| #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ |
| #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */ |
| #define CAN_RDT1R_FMI_Pos (8U) |
| #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ |
| #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */ |
| #define CAN_RDT1R_TIME_Pos (16U) |
| #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */ |
| |
| /******************* Bit definition for CAN_RDL1R register ******************/ |
| #define CAN_RDL1R_DATA0_Pos (0U) |
| #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */ |
| #define CAN_RDL1R_DATA1_Pos (8U) |
| #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */ |
| #define CAN_RDL1R_DATA2_Pos (16U) |
| #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */ |
| #define CAN_RDL1R_DATA3_Pos (24U) |
| #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */ |
| |
| /******************* Bit definition for CAN_RDH1R register ******************/ |
| #define CAN_RDH1R_DATA4_Pos (0U) |
| #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */ |
| #define CAN_RDH1R_DATA5_Pos (8U) |
| #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */ |
| #define CAN_RDH1R_DATA6_Pos (16U) |
| #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */ |
| #define CAN_RDH1R_DATA7_Pos (24U) |
| #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */ |
| |
| /*!<CAN filter registers */ |
| /******************* Bit definition for CAN_FMR register ********************/ |
| #define CAN_FMR_FINIT_Pos (0U) |
| #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ |
| #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */ |
| #define CAN_FMR_CAN2SB_Pos (8U) |
| #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */ |
| #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */ |
| |
| /******************* Bit definition for CAN_FM1R register *******************/ |
| #define CAN_FM1R_FBM_Pos (0U) |
| #define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */ |
| #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */ |
| #define CAN_FM1R_FBM0_Pos (0U) |
| #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ |
| #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */ |
| #define CAN_FM1R_FBM1_Pos (1U) |
| #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ |
| #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */ |
| #define CAN_FM1R_FBM2_Pos (2U) |
| #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ |
| #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */ |
| #define CAN_FM1R_FBM3_Pos (3U) |
| #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ |
| #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */ |
| #define CAN_FM1R_FBM4_Pos (4U) |
| #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ |
| #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */ |
| #define CAN_FM1R_FBM5_Pos (5U) |
| #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ |
| #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */ |
| #define CAN_FM1R_FBM6_Pos (6U) |
| #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ |
| #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */ |
| #define CAN_FM1R_FBM7_Pos (7U) |
| #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ |
| #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */ |
| #define CAN_FM1R_FBM8_Pos (8U) |
| #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ |
| #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */ |
| #define CAN_FM1R_FBM9_Pos (9U) |
| #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ |
| #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */ |
| #define CAN_FM1R_FBM10_Pos (10U) |
| #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ |
| #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */ |
| #define CAN_FM1R_FBM11_Pos (11U) |
| #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ |
| #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */ |
| #define CAN_FM1R_FBM12_Pos (12U) |
| #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ |
| #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */ |
| #define CAN_FM1R_FBM13_Pos (13U) |
| #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ |
| #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */ |
| |
| /******************* Bit definition for CAN_FS1R register *******************/ |
| #define CAN_FS1R_FSC_Pos (0U) |
| #define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */ |
| #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */ |
| #define CAN_FS1R_FSC0_Pos (0U) |
| #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ |
| #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */ |
| #define CAN_FS1R_FSC1_Pos (1U) |
| #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ |
| #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */ |
| #define CAN_FS1R_FSC2_Pos (2U) |
| #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ |
| #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */ |
| #define CAN_FS1R_FSC3_Pos (3U) |
| #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ |
| #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */ |
| #define CAN_FS1R_FSC4_Pos (4U) |
| #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ |
| #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */ |
| #define CAN_FS1R_FSC5_Pos (5U) |
| #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ |
| #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */ |
| #define CAN_FS1R_FSC6_Pos (6U) |
| #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ |
| #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */ |
| #define CAN_FS1R_FSC7_Pos (7U) |
| #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ |
| #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */ |
| #define CAN_FS1R_FSC8_Pos (8U) |
| #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ |
| #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */ |
| #define CAN_FS1R_FSC9_Pos (9U) |
| #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ |
| #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */ |
| #define CAN_FS1R_FSC10_Pos (10U) |
| #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ |
| #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */ |
| #define CAN_FS1R_FSC11_Pos (11U) |
| #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ |
| #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */ |
| #define CAN_FS1R_FSC12_Pos (12U) |
| #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ |
| #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */ |
| #define CAN_FS1R_FSC13_Pos (13U) |
| #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ |
| #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */ |
| |
| /****************** Bit definition for CAN_FFA1R register *******************/ |
| #define CAN_FFA1R_FFA_Pos (0U) |
| #define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */ |
| #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */ |
| #define CAN_FFA1R_FFA0_Pos (0U) |
| #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ |
| #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */ |
| #define CAN_FFA1R_FFA1_Pos (1U) |
| #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ |
| #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */ |
| #define CAN_FFA1R_FFA2_Pos (2U) |
| #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ |
| #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */ |
| #define CAN_FFA1R_FFA3_Pos (3U) |
| #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ |
| #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */ |
| #define CAN_FFA1R_FFA4_Pos (4U) |
| #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ |
| #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */ |
| #define CAN_FFA1R_FFA5_Pos (5U) |
| #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ |
| #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */ |
| #define CAN_FFA1R_FFA6_Pos (6U) |
| #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ |
| #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */ |
| #define CAN_FFA1R_FFA7_Pos (7U) |
| #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ |
| #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */ |
| #define CAN_FFA1R_FFA8_Pos (8U) |
| #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ |
| #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */ |
| #define CAN_FFA1R_FFA9_Pos (9U) |
| #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ |
| #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */ |
| #define CAN_FFA1R_FFA10_Pos (10U) |
| #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ |
| #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */ |
| #define CAN_FFA1R_FFA11_Pos (11U) |
| #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ |
| #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */ |
| #define CAN_FFA1R_FFA12_Pos (12U) |
| #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ |
| #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */ |
| #define CAN_FFA1R_FFA13_Pos (13U) |
| #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ |
| #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */ |
| |
| /******************* Bit definition for CAN_FA1R register *******************/ |
| #define CAN_FA1R_FACT_Pos (0U) |
| #define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */ |
| #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */ |
| #define CAN_FA1R_FACT0_Pos (0U) |
| #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ |
| #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */ |
| #define CAN_FA1R_FACT1_Pos (1U) |
| #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ |
| #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */ |
| #define CAN_FA1R_FACT2_Pos (2U) |
| #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ |
| #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */ |
| #define CAN_FA1R_FACT3_Pos (3U) |
| #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ |
| #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */ |
| #define CAN_FA1R_FACT4_Pos (4U) |
| #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ |
| #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */ |
| #define CAN_FA1R_FACT5_Pos (5U) |
| #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ |
| #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */ |
| #define CAN_FA1R_FACT6_Pos (6U) |
| #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ |
| #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */ |
| #define CAN_FA1R_FACT7_Pos (7U) |
| #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ |
| #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */ |
| #define CAN_FA1R_FACT8_Pos (8U) |
| #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ |
| #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */ |
| #define CAN_FA1R_FACT9_Pos (9U) |
| #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ |
| #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */ |
| #define CAN_FA1R_FACT10_Pos (10U) |
| #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ |
| #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */ |
| #define CAN_FA1R_FACT11_Pos (11U) |
| #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ |
| #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */ |
| #define CAN_FA1R_FACT12_Pos (12U) |
| #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ |
| #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */ |
| #define CAN_FA1R_FACT13_Pos (13U) |
| #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ |
| #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */ |
| |
| /******************* Bit definition for CAN_F0R1 register *******************/ |
| #define CAN_F0R1_FB0_Pos (0U) |
| #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ |
| #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */ |
| #define CAN_F0R1_FB1_Pos (1U) |
| #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ |
| #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */ |
| #define CAN_F0R1_FB2_Pos (2U) |
| #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ |
| #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */ |
| #define CAN_F0R1_FB3_Pos (3U) |
| #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ |
| #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */ |
| #define CAN_F0R1_FB4_Pos (4U) |
| #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ |
| #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */ |
| #define CAN_F0R1_FB5_Pos (5U) |
| #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ |
| #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */ |
| #define CAN_F0R1_FB6_Pos (6U) |
| #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ |
| #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */ |
| #define CAN_F0R1_FB7_Pos (7U) |
| #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ |
| #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */ |
| #define CAN_F0R1_FB8_Pos (8U) |
| #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ |
| #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */ |
| #define CAN_F0R1_FB9_Pos (9U) |
| #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ |
| #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */ |
| #define CAN_F0R1_FB10_Pos (10U) |
| #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ |
| #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */ |
| #define CAN_F0R1_FB11_Pos (11U) |
| #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ |
| #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */ |
| #define CAN_F0R1_FB12_Pos (12U) |
| #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ |
| #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */ |
| #define CAN_F0R1_FB13_Pos (13U) |
| #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ |
| #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */ |
| #define CAN_F0R1_FB14_Pos (14U) |
| #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ |
| #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */ |
| #define CAN_F0R1_FB15_Pos (15U) |
| #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ |
| #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */ |
| #define CAN_F0R1_FB16_Pos (16U) |
| #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ |
| #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */ |
| #define CAN_F0R1_FB17_Pos (17U) |
| #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ |
| #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */ |
| #define CAN_F0R1_FB18_Pos (18U) |
| #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ |
| #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */ |
| #define CAN_F0R1_FB19_Pos (19U) |
| #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ |
| #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */ |
| #define CAN_F0R1_FB20_Pos (20U) |
| #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ |
| #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */ |
| #define CAN_F0R1_FB21_Pos (21U) |
| #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ |
| #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */ |
| #define CAN_F0R1_FB22_Pos (22U) |
| #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ |
| #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */ |
| #define CAN_F0R1_FB23_Pos (23U) |
| #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ |
| #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */ |
| #define CAN_F0R1_FB24_Pos (24U) |
| #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ |
| #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */ |
| #define CAN_F0R1_FB25_Pos (25U) |
| #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ |
| #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */ |
| #define CAN_F0R1_FB26_Pos (26U) |
| #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ |
| #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */ |
| #define CAN_F0R1_FB27_Pos (27U) |
| #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ |
| #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */ |
| #define CAN_F0R1_FB28_Pos (28U) |
| #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ |
| #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */ |
| #define CAN_F0R1_FB29_Pos (29U) |
| #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ |
| #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */ |
| #define CAN_F0R1_FB30_Pos (30U) |
| #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ |
| #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */ |
| #define CAN_F0R1_FB31_Pos (31U) |
| #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ |
| #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */ |
| |
| /******************* Bit definition for CAN_F1R1 register *******************/ |
| #define CAN_F1R1_FB0_Pos (0U) |
| #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ |
| #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */ |
| #define CAN_F1R1_FB1_Pos (1U) |
| #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ |
| #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */ |
| #define CAN_F1R1_FB2_Pos (2U) |
| #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ |
| #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */ |
| #define CAN_F1R1_FB3_Pos (3U) |
| #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ |
| #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */ |
| #define CAN_F1R1_FB4_Pos (4U) |
| #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ |
| #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */ |
| #define CAN_F1R1_FB5_Pos (5U) |
| #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ |
| #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */ |
| #define CAN_F1R1_FB6_Pos (6U) |
| #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ |
| #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */ |
| #define CAN_F1R1_FB7_Pos (7U) |
| #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ |
| #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */ |
| #define CAN_F1R1_FB8_Pos (8U) |
| #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ |
| #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */ |
| #define CAN_F1R1_FB9_Pos (9U) |
| #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ |
| #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */ |
| #define CAN_F1R1_FB10_Pos (10U) |
| #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ |
| #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */ |
| #define CAN_F1R1_FB11_Pos (11U) |
| #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ |
| #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */ |
| #define CAN_F1R1_FB12_Pos (12U) |
| #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ |
| #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */ |
| #define CAN_F1R1_FB13_Pos (13U) |
| #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ |
| #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */ |
| #define CAN_F1R1_FB14_Pos (14U) |
| #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ |
| #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */ |
| #define CAN_F1R1_FB15_Pos (15U) |
| #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ |
| #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */ |
| #define CAN_F1R1_FB16_Pos (16U) |
| #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ |
| #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */ |
| #define CAN_F1R1_FB17_Pos (17U) |
| #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ |
| #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */ |
| #define CAN_F1R1_FB18_Pos (18U) |
| #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ |
| #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */ |
| #define CAN_F1R1_FB19_Pos (19U) |
| #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ |
| #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */ |
| #define CAN_F1R1_FB20_Pos (20U) |
| #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ |
| #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */ |
| #define CAN_F1R1_FB21_Pos (21U) |
| #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ |
| #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */ |
| #define CAN_F1R1_FB22_Pos (22U) |
| #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ |
| #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */ |
| #define CAN_F1R1_FB23_Pos (23U) |
| #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ |
| #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */ |
| #define CAN_F1R1_FB24_Pos (24U) |
| #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ |
| #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */ |
| #define CAN_F1R1_FB25_Pos (25U) |
| #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ |
| #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */ |
| #define CAN_F1R1_FB26_Pos (26U) |
| #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ |
| #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */ |
| #define CAN_F1R1_FB27_Pos (27U) |
| #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ |
| #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */ |
| #define CAN_F1R1_FB28_Pos (28U) |
| #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ |
| #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */ |
| #define CAN_F1R1_FB29_Pos (29U) |
| #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ |
| #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */ |
| #define CAN_F1R1_FB30_Pos (30U) |
| #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ |
| #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */ |
| #define CAN_F1R1_FB31_Pos (31U) |
| #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ |
| #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */ |
| |
| /******************* Bit definition for CAN_F2R1 register *******************/ |
| #define CAN_F2R1_FB0_Pos (0U) |
| #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ |
| #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */ |
| #define CAN_F2R1_FB1_Pos (1U) |
| #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ |
| #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */ |
| #define CAN_F2R1_FB2_Pos (2U) |
| #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ |
| #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */ |
| #define CAN_F2R1_FB3_Pos (3U) |
| #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ |
| #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */ |
| #define CAN_F2R1_FB4_Pos (4U) |
| #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ |
| #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */ |
| #define CAN_F2R1_FB5_Pos (5U) |
| #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ |
| #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */ |
| #define CAN_F2R1_FB6_Pos (6U) |
| #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ |
| #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */ |
| #define CAN_F2R1_FB7_Pos (7U) |
| #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ |
| #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */ |
| #define CAN_F2R1_FB8_Pos (8U) |
| #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ |
| #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */ |
| #define CAN_F2R1_FB9_Pos (9U) |
| #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ |
| #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */ |
| #define CAN_F2R1_FB10_Pos (10U) |
| #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ |
| #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */ |
| #define CAN_F2R1_FB11_Pos (11U) |
| #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ |
| #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */ |
| #define CAN_F2R1_FB12_Pos (12U) |
| #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ |
| #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */ |
| #define CAN_F2R1_FB13_Pos (13U) |
| #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ |
| #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */ |
| #define CAN_F2R1_FB14_Pos (14U) |
| #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ |
| #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */ |
| #define CAN_F2R1_FB15_Pos (15U) |
| #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ |
| #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */ |
| #define CAN_F2R1_FB16_Pos (16U) |
| #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ |
| #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */ |
| #define CAN_F2R1_FB17_Pos (17U) |
| #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ |
| #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */ |
| #define CAN_F2R1_FB18_Pos (18U) |
| #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ |
| #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */ |
| #define CAN_F2R1_FB19_Pos (19U) |
| #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ |
| #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */ |
| #define CAN_F2R1_FB20_Pos (20U) |
| #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ |
| #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */ |
| #define CAN_F2R1_FB21_Pos (21U) |
| #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ |
| #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */ |
| #define CAN_F2R1_FB22_Pos (22U) |
| #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ |
| #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */ |
| #define CAN_F2R1_FB23_Pos (23U) |
| #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ |
| #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */ |
| #define CAN_F2R1_FB24_Pos (24U) |
| #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ |
| #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */ |
| #define CAN_F2R1_FB25_Pos (25U) |
| #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ |
| #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */ |
| #define CAN_F2R1_FB26_Pos (26U) |
| #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ |
| #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */ |
| #define CAN_F2R1_FB27_Pos (27U) |
| #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ |
| #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */ |
| #define CAN_F2R1_FB28_Pos (28U) |
| #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ |
| #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */ |
| #define CAN_F2R1_FB29_Pos (29U) |
| #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ |
| #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */ |
| #define CAN_F2R1_FB30_Pos (30U) |
| #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ |
| #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */ |
| #define CAN_F2R1_FB31_Pos (31U) |
| #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ |
| #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */ |
| |
| /******************* Bit definition for CAN_F3R1 register *******************/ |
| #define CAN_F3R1_FB0_Pos (0U) |
| #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ |
| #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */ |
| #define CAN_F3R1_FB1_Pos (1U) |
| #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ |
| #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */ |
| #define CAN_F3R1_FB2_Pos (2U) |
| #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ |
| #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */ |
| #define CAN_F3R1_FB3_Pos (3U) |
| #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ |
| #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */ |
| #define CAN_F3R1_FB4_Pos (4U) |
| #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ |
| #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */ |
| #define CAN_F3R1_FB5_Pos (5U) |
| #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ |
| #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */ |
| #define CAN_F3R1_FB6_Pos (6U) |
| #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ |
| #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */ |
| #define CAN_F3R1_FB7_Pos (7U) |
| #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ |
| #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */ |
| #define CAN_F3R1_FB8_Pos (8U) |
| #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ |
| #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */ |
| #define CAN_F3R1_FB9_Pos (9U) |
| #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ |
| #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */ |
| #define CAN_F3R1_FB10_Pos (10U) |
| #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ |
| #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */ |
| #define CAN_F3R1_FB11_Pos (11U) |
| #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ |
| #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */ |
| #define CAN_F3R1_FB12_Pos (12U) |
| #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ |
| #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */ |
| #define CAN_F3R1_FB13_Pos (13U) |
| #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ |
| #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */ |
| #define CAN_F3R1_FB14_Pos (14U) |
| #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ |
| #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */ |
| #define CAN_F3R1_FB15_Pos (15U) |
| #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ |
| #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */ |
| #define CAN_F3R1_FB16_Pos (16U) |
| #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ |
| #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */ |
| #define CAN_F3R1_FB17_Pos (17U) |
| #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ |
| #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */ |
| #define CAN_F3R1_FB18_Pos (18U) |
| #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ |
| #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */ |
| #define CAN_F3R1_FB19_Pos (19U) |
| #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ |
| #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */ |
| #define CAN_F3R1_FB20_Pos (20U) |
| #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ |
| #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */ |
| #define CAN_F3R1_FB21_Pos (21U) |
| #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ |
| #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */ |
| #define CAN_F3R1_FB22_Pos (22U) |
| #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ |
| #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */ |
| #define CAN_F3R1_FB23_Pos (23U) |
| #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ |
| #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */ |
| #define CAN_F3R1_FB24_Pos (24U) |
| #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ |
| #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */ |
| #define CAN_F3R1_FB25_Pos (25U) |
| #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ |
| #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */ |
| #define CAN_F3R1_FB26_Pos (26U) |
| #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ |
| #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */ |
| #define CAN_F3R1_FB27_Pos (27U) |
| #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ |
| #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */ |
| #define CAN_F3R1_FB28_Pos (28U) |
| #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ |
| #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */ |
| #define CAN_F3R1_FB29_Pos (29U) |
| #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ |
| #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */ |
| #define CAN_F3R1_FB30_Pos (30U) |
| #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ |
| #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */ |
| #define CAN_F3R1_FB31_Pos (31U) |
| #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ |
| #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */ |
| |
| /******************* Bit definition for CAN_F4R1 register *******************/ |
| #define CAN_F4R1_FB0_Pos (0U) |
| #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ |
| #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */ |
| #define CAN_F4R1_FB1_Pos (1U) |
| #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ |
| #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */ |
| #define CAN_F4R1_FB2_Pos (2U) |
| #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ |
| #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */ |
| #define CAN_F4R1_FB3_Pos (3U) |
| #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ |
| #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */ |
| #define CAN_F4R1_FB4_Pos (4U) |
| #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ |
| #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */ |
| #define CAN_F4R1_FB5_Pos (5U) |
| #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ |
| #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */ |
| #define CAN_F4R1_FB6_Pos (6U) |
| #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ |
| #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */ |
| #define CAN_F4R1_FB7_Pos (7U) |
| #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ |
| #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */ |
| #define CAN_F4R1_FB8_Pos (8U) |
| #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ |
| #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */ |
| #define CAN_F4R1_FB9_Pos (9U) |
| #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ |
| #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */ |
| #define CAN_F4R1_FB10_Pos (10U) |
| #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ |
| #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */ |
| #define CAN_F4R1_FB11_Pos (11U) |
| #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ |
| #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */ |
| #define CAN_F4R1_FB12_Pos (12U) |
| #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ |
| #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */ |
| #define CAN_F4R1_FB13_Pos (13U) |
| #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ |
| #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */ |
| #define CAN_F4R1_FB14_Pos (14U) |
| #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ |
| #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */ |
| #define CAN_F4R1_FB15_Pos (15U) |
| #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ |
| #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */ |
| #define CAN_F4R1_FB16_Pos (16U) |
| #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ |
| #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */ |
| #define CAN_F4R1_FB17_Pos (17U) |
| #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ |
| #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */ |
| #define CAN_F4R1_FB18_Pos (18U) |
| #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ |
| #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */ |
| #define CAN_F4R1_FB19_Pos (19U) |
| #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ |
| #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */ |
| #define CAN_F4R1_FB20_Pos (20U) |
| #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ |
| #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */ |
| #define CAN_F4R1_FB21_Pos (21U) |
| #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ |
| #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */ |
| #define CAN_F4R1_FB22_Pos (22U) |
| #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ |
| #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */ |
| #define CAN_F4R1_FB23_Pos (23U) |
| #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ |
| #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */ |
| #define CAN_F4R1_FB24_Pos (24U) |
| #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ |
| #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */ |
| #define CAN_F4R1_FB25_Pos (25U) |
| #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ |
| #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */ |
| #define CAN_F4R1_FB26_Pos (26U) |
| #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ |
| #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */ |
| #define CAN_F4R1_FB27_Pos (27U) |
| #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ |
| #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */ |
| #define CAN_F4R1_FB28_Pos (28U) |
| #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ |
| #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */ |
| #define CAN_F4R1_FB29_Pos (29U) |
| #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ |
| #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */ |
| #define CAN_F4R1_FB30_Pos (30U) |
| #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ |
| #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */ |
| #define CAN_F4R1_FB31_Pos (31U) |
| #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ |
| #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */ |
| |
| /******************* Bit definition for CAN_F5R1 register *******************/ |
| #define CAN_F5R1_FB0_Pos (0U) |
| #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ |
| #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */ |
| #define CAN_F5R1_FB1_Pos (1U) |
| #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ |
| #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */ |
| #define CAN_F5R1_FB2_Pos (2U) |
| #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ |
| #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */ |
| #define CAN_F5R1_FB3_Pos (3U) |
| #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ |
| #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */ |
| #define CAN_F5R1_FB4_Pos (4U) |
| #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ |
| #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */ |
| #define CAN_F5R1_FB5_Pos (5U) |
| #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ |
| #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */ |
| #define CAN_F5R1_FB6_Pos (6U) |
| #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ |
| #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */ |
| #define CAN_F5R1_FB7_Pos (7U) |
| #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ |
| #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */ |
| #define CAN_F5R1_FB8_Pos (8U) |
| #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ |
| #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */ |
| #define CAN_F5R1_FB9_Pos (9U) |
| #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ |
| #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */ |
| #define CAN_F5R1_FB10_Pos (10U) |
| #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ |
| #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */ |
| #define CAN_F5R1_FB11_Pos (11U) |
| #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ |
| #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */ |
| #define CAN_F5R1_FB12_Pos (12U) |
| #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ |
| #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */ |
| #define CAN_F5R1_FB13_Pos (13U) |
| #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ |
| #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */ |
| #define CAN_F5R1_FB14_Pos (14U) |
| #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ |
| #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */ |
| #define CAN_F5R1_FB15_Pos (15U) |
| #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ |
| #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */ |
| #define CAN_F5R1_FB16_Pos (16U) |
| #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ |
| #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */ |
| #define CAN_F5R1_FB17_Pos (17U) |
| #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ |
| #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */ |
| #define CAN_F5R1_FB18_Pos (18U) |
| #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ |
| #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */ |
| #define CAN_F5R1_FB19_Pos (19U) |
| #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ |
| #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */ |
| #define CAN_F5R1_FB20_Pos (20U) |
| #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ |
| #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */ |
| #define CAN_F5R1_FB21_Pos (21U) |
| #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ |
| #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */ |
| #define CAN_F5R1_FB22_Pos (22U) |
| #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ |
| #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */ |
| #define CAN_F5R1_FB23_Pos (23U) |
| #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ |
| #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */ |
| #define CAN_F5R1_FB24_Pos (24U) |
| #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ |
| #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */ |
| #define CAN_F5R1_FB25_Pos (25U) |
| #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ |
| #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */ |
| #define CAN_F5R1_FB26_Pos (26U) |
| #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ |
| #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */ |
| #define CAN_F5R1_FB27_Pos (27U) |
| #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ |
| #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */ |
| #define CAN_F5R1_FB28_Pos (28U) |
| #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ |
| #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */ |
| #define CAN_F5R1_FB29_Pos (29U) |
| #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ |
| #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */ |
| #define CAN_F5R1_FB30_Pos (30U) |
| #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ |
| #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */ |
| #define CAN_F5R1_FB31_Pos (31U) |
| #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ |
| #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */ |
| |
| /******************* Bit definition for CAN_F6R1 register *******************/ |
| #define CAN_F6R1_FB0_Pos (0U) |
| #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ |
| #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */ |
| #define CAN_F6R1_FB1_Pos (1U) |
| #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ |
| #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */ |
| #define CAN_F6R1_FB2_Pos (2U) |
| #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ |
| #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */ |
| #define CAN_F6R1_FB3_Pos (3U) |
| #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ |
| #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */ |
| #define CAN_F6R1_FB4_Pos (4U) |
| #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ |
| #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */ |
| #define CAN_F6R1_FB5_Pos (5U) |
| #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ |
| #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */ |
| #define CAN_F6R1_FB6_Pos (6U) |
| #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ |
| #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */ |
| #define CAN_F6R1_FB7_Pos (7U) |
| #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ |
| #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */ |
| #define CAN_F6R1_FB8_Pos (8U) |
| #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ |
| #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */ |
| #define CAN_F6R1_FB9_Pos (9U) |
| #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ |
| #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */ |
| #define CAN_F6R1_FB10_Pos (10U) |
| #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ |
| #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */ |
| #define CAN_F6R1_FB11_Pos (11U) |
| #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ |
| #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */ |
| #define CAN_F6R1_FB12_Pos (12U) |
| #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ |
| #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */ |
| #define CAN_F6R1_FB13_Pos (13U) |
| #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ |
| #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */ |
| #define CAN_F6R1_FB14_Pos (14U) |
| #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ |
| #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */ |
| #define CAN_F6R1_FB15_Pos (15U) |
| #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ |
| #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */ |
| #define CAN_F6R1_FB16_Pos (16U) |
| #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ |
| #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */ |
| #define CAN_F6R1_FB17_Pos (17U) |
| #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ |
| #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */ |
| #define CAN_F6R1_FB18_Pos (18U) |
| #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ |
| #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */ |
| #define CAN_F6R1_FB19_Pos (19U) |
| #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ |
| #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */ |
| #define CAN_F6R1_FB20_Pos (20U) |
| #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ |
| #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */ |
| #define CAN_F6R1_FB21_Pos (21U) |
| #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ |
| #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */ |
| #define CAN_F6R1_FB22_Pos (22U) |
| #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ |
| #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */ |
| #define CAN_F6R1_FB23_Pos (23U) |
| #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ |
| #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */ |
| #define CAN_F6R1_FB24_Pos (24U) |
| #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ |
| #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */ |
| #define CAN_F6R1_FB25_Pos (25U) |
| #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ |
| #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */ |
| #define CAN_F6R1_FB26_Pos (26U) |
| #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ |
| #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */ |
| #define CAN_F6R1_FB27_Pos (27U) |
| #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ |
| #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */ |
| #define CAN_F6R1_FB28_Pos (28U) |
| #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ |
| #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */ |
| #define CAN_F6R1_FB29_Pos (29U) |
| #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ |
| #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */ |
| #define CAN_F6R1_FB30_Pos (30U) |
| #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ |
| #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */ |
| #define CAN_F6R1_FB31_Pos (31U) |
| #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ |
| #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */ |
| |
| /******************* Bit definition for CAN_F7R1 register *******************/ |
| #define CAN_F7R1_FB0_Pos (0U) |
| #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ |
| #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */ |
| #define CAN_F7R1_FB1_Pos (1U) |
| #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ |
| #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */ |
| #define CAN_F7R1_FB2_Pos (2U) |
| #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ |
| #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */ |
| #define CAN_F7R1_FB3_Pos (3U) |
| #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ |
| #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */ |
| #define CAN_F7R1_FB4_Pos (4U) |
| #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ |
| #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */ |
| #define CAN_F7R1_FB5_Pos (5U) |
| #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ |
| #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */ |
| #define CAN_F7R1_FB6_Pos (6U) |
| #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ |
| #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */ |
| #define CAN_F7R1_FB7_Pos (7U) |
| #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ |
| #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */ |
| #define CAN_F7R1_FB8_Pos (8U) |
| #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ |
| #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */ |
| #define CAN_F7R1_FB9_Pos (9U) |
| #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ |
| #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */ |
| #define CAN_F7R1_FB10_Pos (10U) |
| #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ |
| #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */ |
| #define CAN_F7R1_FB11_Pos (11U) |
| #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ |
| #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */ |
| #define CAN_F7R1_FB12_Pos (12U) |
| #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ |
| #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */ |
| #define CAN_F7R1_FB13_Pos (13U) |
|
