Release v4.3.2
diff --git a/Include/stm32f100xb.h b/Include/stm32f100xb.h
index 1b0177d..ab78980 100644
--- a/Include/stm32f100xb.h
+++ b/Include/stm32f100xb.h
@@ -4880,7 +4880,6 @@
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
-
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
@@ -5718,8 +5717,6 @@
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM15))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -5921,15 +5918,15 @@
#define ADC1_2_IRQn ADC1_IRQn
#define USBWakeUp_IRQn CEC_IRQn
#define OTG_FS_WKUP_IRQn CEC_IRQn
-#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
#define TIM10_IRQn TIM1_UP_TIM16_IRQn
-#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
#define TIM6_IRQn TIM6_DAC_IRQn
@@ -5937,15 +5934,15 @@
#define ADC1_2_IRQHandler ADC1_IRQHandler
#define USBWakeUp_IRQHandler CEC_IRQHandler
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
-#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
diff --git a/Include/stm32f100xe.h b/Include/stm32f100xe.h
index 0895dba..334c4dc 100644
--- a/Include/stm32f100xe.h
+++ b/Include/stm32f100xe.h
@@ -5394,7 +5394,6 @@
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
-
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
@@ -6283,8 +6282,6 @@
((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -6522,17 +6519,17 @@
/* Aliases for __IRQn */
#define ADC1_2_IRQn ADC1_IRQn
-#define USBWakeUp_IRQn CEC_IRQn
#define OTG_FS_WKUP_IRQn CEC_IRQn
+#define USBWakeUp_IRQn CEC_IRQn
#define TIM8_BRK_IRQn TIM12_IRQn
#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
-#define TIM8_UP_TIM13_IRQn TIM13_IRQn
#define TIM8_UP_IRQn TIM13_IRQn
-#define TIM8_TRG_COM_IRQn TIM14_IRQn
+#define TIM8_UP_TIM13_IRQn TIM13_IRQn
#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
+#define TIM8_TRG_COM_IRQn TIM14_IRQn
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
@@ -6544,17 +6541,17 @@
/* Aliases for __IRQHandler */
#define ADC1_2_IRQHandler ADC1_IRQHandler
-#define USBWakeUp_IRQHandler CEC_IRQHandler
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
+#define USBWakeUp_IRQHandler CEC_IRQHandler
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
-#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
#define TIM8_UP_IRQHandler TIM13_IRQHandler
-#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
+#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
+#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
diff --git a/Include/stm32f101x6.h b/Include/stm32f101x6.h
index dd3f3d4..250962d 100644
--- a/Include/stm32f101x6.h
+++ b/Include/stm32f101x6.h
@@ -4412,12 +4412,10 @@
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
-/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
@@ -5170,8 +5168,6 @@
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
diff --git a/Include/stm32f101xb.h b/Include/stm32f101xb.h
index 4fbf3f3..aa524a9 100644
--- a/Include/stm32f101xb.h
+++ b/Include/stm32f101xb.h
@@ -4474,12 +4474,10 @@
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
-/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
@@ -5279,8 +5277,6 @@
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
diff --git a/Include/stm32f101xe.h b/Include/stm32f101xe.h
index e6fb3ba..bde6d7a 100644
--- a/Include/stm32f101xe.h
+++ b/Include/stm32f101xe.h
@@ -514,6 +514,7 @@
__IO uint32_t RXCRCR;
__IO uint32_t TXCRCR;
__IO uint32_t I2SCFGR;
+ __IO uint32_t I2SPR;
} SPI_TypeDef;
/**
@@ -5283,6 +5284,10 @@
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
#define SPI_CRC_ERROR_WORKAROUND_FEATURE
/******************* Bit definition for SPI_CR1 register ********************/
@@ -5401,10 +5406,52 @@
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */
/******************************************************************************/
/* */
@@ -6153,6 +6200,10 @@
/******************************* SMBUS Instances ******************************/
#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -6253,8 +6304,6 @@
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
diff --git a/Include/stm32f101xg.h b/Include/stm32f101xg.h
index 84edbda..35a142d 100644
--- a/Include/stm32f101xg.h
+++ b/Include/stm32f101xg.h
@@ -526,6 +526,7 @@
__IO uint32_t RXCRCR;
__IO uint32_t TXCRCR;
__IO uint32_t I2SCFGR;
+ __IO uint32_t I2SPR;
} SPI_TypeDef;
/**
@@ -5358,6 +5359,10 @@
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
@@ -5475,10 +5480,52 @@
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */
/******************************************************************************/
/* */
@@ -6286,6 +6333,10 @@
/******************************* SMBUS Instances ******************************/
#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -6407,8 +6458,6 @@
((INSTANCE) == TIM9) || \
((INSTANCE) == TIM12))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -6602,18 +6651,18 @@
#define TIM1_UP_TIM16_IRQn TIM10_IRQn
#define TIM1_UP_IRQn TIM10_IRQn
#define TIM1_UP_TIM10_IRQn TIM10_IRQn
+#define TIM1_TRG_COM_IRQn TIM11_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM11_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM11_IRQn
-#define TIM1_TRG_COM_IRQn TIM11_IRQn
-#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
#define TIM8_BRK_IRQn TIM12_IRQn
+#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
#define TIM8_UP_TIM13_IRQn TIM13_IRQn
#define TIM8_UP_IRQn TIM13_IRQn
#define TIM8_TRG_COM_IRQn TIM14_IRQn
#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
#define TIM6_DAC_IRQn TIM6_IRQn
-#define TIM1_BRK_IRQn TIM9_IRQn
#define TIM1_BRK_TIM15_IRQn TIM9_IRQn
+#define TIM1_BRK_IRQn TIM9_IRQn
#define TIM1_BRK_TIM9_IRQn TIM9_IRQn
@@ -6623,18 +6672,18 @@
#define TIM1_UP_TIM16_IRQHandler TIM10_IRQHandler
#define TIM1_UP_IRQHandler TIM10_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM10_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM11_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM11_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM11_IRQHandler
-#define TIM1_TRG_COM_IRQHandler TIM11_IRQHandler
-#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
+#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
#define TIM8_UP_IRQHandler TIM13_IRQHandler
#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
-#define TIM1_BRK_IRQHandler TIM9_IRQHandler
#define TIM1_BRK_TIM15_IRQHandler TIM9_IRQHandler
+#define TIM1_BRK_IRQHandler TIM9_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM9_IRQHandler
diff --git a/Include/stm32f102x6.h b/Include/stm32f102x6.h
index a822a31..9917ec3 100644
--- a/Include/stm32f102x6.h
+++ b/Include/stm32f102x6.h
@@ -5531,12 +5531,10 @@
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
-/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
@@ -6289,8 +6287,6 @@
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
diff --git a/Include/stm32f102xb.h b/Include/stm32f102xb.h
index 468e63a..f5d0042 100644
--- a/Include/stm32f102xb.h
+++ b/Include/stm32f102xb.h
@@ -5585,12 +5585,10 @@
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
-/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
@@ -6389,8 +6387,6 @@
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -6532,20 +6528,20 @@
#define ADC1_2_IRQn ADC1_IRQn
#define CEC_IRQn USBWakeUp_IRQn
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
-#define CAN1_TX_IRQn USB_HP_IRQn
#define USB_HP_CAN1_TX_IRQn USB_HP_IRQn
-#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn
+#define CAN1_TX_IRQn USB_HP_IRQn
#define CAN1_RX0_IRQn USB_LP_IRQn
+#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn
/* Aliases for __IRQHandler */
#define ADC1_2_IRQHandler ADC1_IRQHandler
#define CEC_IRQHandler USBWakeUp_IRQHandler
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
-#define CAN1_TX_IRQHandler USB_HP_IRQHandler
#define USB_HP_CAN1_TX_IRQHandler USB_HP_IRQHandler
-#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_IRQHandler
#define CAN1_RX0_IRQHandler USB_LP_IRQHandler
+#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler
/**
diff --git a/Include/stm32f103x6.h b/Include/stm32f103x6.h
index f8f6448..a484645 100644
--- a/Include/stm32f103x6.h
+++ b/Include/stm32f103x6.h
@@ -9128,12 +9128,10 @@
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
-/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
@@ -9912,8 +9910,6 @@
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -10051,40 +10047,40 @@
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
-#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM9_IRQn TIM1_BRK_IRQn
-#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
#define TIM10_IRQn TIM1_UP_IRQn
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
#define CEC_IRQn USBWakeUp_IRQn
-#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
-#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
+#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
+#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM10_IRQHandler TIM1_UP_IRQHandler
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
#define CEC_IRQHandler USBWakeUp_IRQHandler
-#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
-#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
/**
diff --git a/Include/stm32f103xb.h b/Include/stm32f103xb.h
index cf34a2f..4bd7e5d 100644
--- a/Include/stm32f103xb.h
+++ b/Include/stm32f103xb.h
@@ -9190,12 +9190,10 @@
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
-/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
@@ -10021,8 +10019,6 @@
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -10182,40 +10178,40 @@
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
-#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
-#define TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
-#define TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM10_IRQn TIM1_UP_IRQn
-#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
#define CEC_IRQn USBWakeUp_IRQn
#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
-#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
+#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
-#define TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
-#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM10_IRQHandler TIM1_UP_IRQHandler
-#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
#define CEC_IRQHandler USBWakeUp_IRQHandler
#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
-#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
/**
diff --git a/Include/stm32f103xe.h b/Include/stm32f103xe.h
index 299c0fb..1001fd8 100644
--- a/Include/stm32f103xe.h
+++ b/Include/stm32f103xe.h
@@ -10583,7 +10583,6 @@
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
@@ -11484,8 +11483,6 @@
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
@@ -11693,20 +11690,20 @@
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
-#define TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
-#define TIM10_IRQn TIM1_UP_IRQn
-#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
#define TIM6_DAC_IRQn TIM6_IRQn
-#define TIM12_IRQn TIM8_BRK_IRQn
#define TIM8_BRK_TIM12_IRQn TIM8_BRK_IRQn
-#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM12_IRQn TIM8_BRK_IRQn
#define TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn
#define TIM8_UP_TIM13_IRQn TIM8_UP_IRQn
#define TIM13_IRQn TIM8_UP_IRQn
#define CEC_IRQn USBWakeUp_IRQn
@@ -11720,20 +11717,20 @@
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
-#define TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM10_IRQHandler TIM1_UP_IRQHandler
-#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
-#define TIM12_IRQHandler TIM8_BRK_IRQHandler
#define TIM8_BRK_TIM12_IRQHandler TIM8_BRK_IRQHandler
-#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM12_IRQHandler TIM8_BRK_IRQHandler
#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
#define TIM8_UP_TIM13_IRQHandler TIM8_UP_IRQHandler
#define TIM13_IRQHandler TIM8_UP_IRQHandler
#define CEC_IRQHandler USBWakeUp_IRQHandler
diff --git a/Include/stm32f103xg.h b/Include/stm32f103xg.h
index 90d9292..f74beff 100644
--- a/Include/stm32f103xg.h
+++ b/Include/stm32f103xg.h
@@ -10652,7 +10652,6 @@
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
@@ -11642,8 +11641,6 @@
((INSTANCE) == TIM9) || \
((INSTANCE) == TIM12))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
@@ -11878,11 +11875,11 @@
#define ADC1_IRQn ADC1_2_IRQn
#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
#define TIM9_IRQn TIM1_BRK_TIM9_IRQn
-#define TIM1_BRK_TIM15_IRQn TIM1_BRK_TIM9_IRQn
#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_TIM9_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
#define TIM11_IRQn TIM1_TRG_COM_TIM11_IRQn
-#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn
#define TIM10_IRQn TIM1_UP_TIM10_IRQn
#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
#define TIM1_UP_TIM16_IRQn TIM1_UP_TIM10_IRQn
@@ -11891,25 +11888,25 @@
#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
#define TIM14_IRQn TIM8_TRG_COM_TIM14_IRQn
#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
-#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
#define TIM13_IRQn TIM8_UP_TIM13_IRQn
+#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
#define CEC_IRQn USBWakeUp_IRQn
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
-#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
+#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_TIM9_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_TIM9_IRQHandler
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM9_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_TIM9_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
-#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
#define TIM10_IRQHandler TIM1_UP_TIM10_IRQHandler
#define TIM1_UP_IRQHandler TIM1_UP_TIM10_IRQHandler
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_TIM10_IRQHandler
@@ -11918,14 +11915,14 @@
#define TIM8_BRK_IRQHandler TIM8_BRK_TIM12_IRQHandler
#define TIM14_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
#define TIM8_TRG_COM_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
-#define TIM8_UP_IRQHandler TIM8_UP_TIM13_IRQHandler
#define TIM13_IRQHandler TIM8_UP_TIM13_IRQHandler
+#define TIM8_UP_IRQHandler TIM8_UP_TIM13_IRQHandler
#define CEC_IRQHandler USBWakeUp_IRQHandler
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
-#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
/**
diff --git a/Include/stm32f105xc.h b/Include/stm32f105xc.h
index dcedb68..7421593 100644
--- a/Include/stm32f105xc.h
+++ b/Include/stm32f105xc.h
@@ -1250,6 +1250,11 @@
/* Reset and Clock Control */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
+#define RCC_PLLI2S_SUPPORT
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (0U)
@@ -1283,11 +1288,6 @@
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
- */
-#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
-
#define RCC_CR_PLL2ON_Pos (26U)
#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */
@@ -1295,11 +1295,6 @@
#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
- */
-#define RCC_PLLI2S_SUPPORT /*!< Support PLL3 (PLLI2S)*/
-
#define RCC_CR_PLL3ON_Pos (28U)
#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */
@@ -11914,7 +11909,6 @@
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
@@ -14092,8 +14086,6 @@
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -14289,15 +14281,15 @@
#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn
#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
#define CEC_IRQn OTG_FS_WKUP_IRQn
-#define TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM9_IRQn TIM1_BRK_IRQn
#define TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
-#define TIM10_IRQn TIM1_UP_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
#define TIM6_DAC_IRQn TIM6_IRQn
@@ -14310,15 +14302,15 @@
#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler
#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
-#define TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
diff --git a/Include/stm32f107xc.h b/Include/stm32f107xc.h
index d38b003..5c40b46 100644
--- a/Include/stm32f107xc.h
+++ b/Include/stm32f107xc.h
@@ -1330,6 +1330,11 @@
/* Reset and Clock Control */
/* */
/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
+#define RCC_PLLI2S_SUPPORT
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (0U)
@@ -1363,11 +1368,6 @@
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
- */
-#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
-
#define RCC_CR_PLL2ON_Pos (26U)
#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */
@@ -1375,11 +1375,6 @@
#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
- */
-#define RCC_PLLI2S_SUPPORT /*!< Support PLL3 (PLLI2S)*/
-
#define RCC_CR_PLL3ON_Pos (28U)
#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */
@@ -12006,7 +12001,6 @@
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
@@ -15003,8 +14997,6 @@
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -15195,42 +15187,42 @@
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
-#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
#define USB_LP_IRQn CAN1_RX0_IRQn
-#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
+#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
#define USB_HP_IRQn CAN1_TX_IRQn
+#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn
#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
#define CEC_IRQn OTG_FS_WKUP_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM9_IRQn TIM1_BRK_IRQn
-#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
#define TIM10_IRQn TIM1_UP_IRQn
#define TIM6_DAC_IRQn TIM6_IRQn
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
-#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
+#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
#define USB_HP_IRQHandler CAN1_TX_IRQHandler
+#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler
#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
diff --git a/Include/stm32f1xx.h b/Include/stm32f1xx.h
index 2f47c00..e34cc48 100644
--- a/Include/stm32f1xx.h
+++ b/Include/stm32f1xx.h
@@ -90,11 +90,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V4.3.1
+ * @brief CMSIS Device version number V4.3.2
*/
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F1_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
diff --git a/License.md b/License.md
index 64783f9..72fbf79 100644
--- a/License.md
+++ b/License.md
@@ -80,5 +80,4 @@
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
- limitations under the License.
-
+ limitations under the License.
\ No newline at end of file
diff --git a/README.md b/README.md
index 8deee66..294bcb8 100644
--- a/README.md
+++ b/README.md
@@ -19,6 +19,10 @@
This **cmsis_device_f1** MCU component repo is one element of the STM32CubeF1 MCU embedded software package, providing the **cmsis device** part.
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_f1/blob/master/Release_Notes.html).
+
## Compatibility information
In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package:
@@ -26,10 +30,12 @@
CMSIS Device F1 | CMSIS Core | Was delivered in the full MCU package
--------------- | ---------- | -------------------------------------
Tag v4.3.1 | Tag v5.4.0_cm3 | Tag v1.8.0
+Tag v4.3.1 | Tag v5.4.0_cm3 | Tag v1.8.1
+Tag v4.3.2 | Tag v5.4.0_cm3 | Tag v1.8.2
The full **STM32CubeF1** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF1).
## Troubleshooting
If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_f1/issues/new).
-For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
\ No newline at end of file
diff --git a/Release_Notes.html b/Release_Notes.html
index 1dd0004..38ec2ab 100644
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-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.3.1 / 26-June-2019 <o:p></o:p></span></h3>
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-Changes</span></u></b></p>
- <ul>
- <li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman"; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix </span><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2012 Compilation errors: update to use </span><span style="font-size: 10pt; font-family: Verdana;">"UL" postfix for bits mask definitions(_Msk) and memory/peripheral base addresses</span></li>
- <li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman"; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix wrong initialization value for "SystemCoreClock" in System_stm32f1xx.c file<br>
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- <li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman"; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Update gcc linker file template to be aligned with AC6 linker file template</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman"; color: black;"><span style="font-size: 10pt; font-family: Verdana;">stm32f1xx.h</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman"; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Align ErrorStatus typedef to common error handling<br></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman"; color: black;"><span style="font-size: 10pt; font-family: Verdana;">TIM:</span></li>
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-<li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman"; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update IS_TIM_SLAVE_INSTANCE() macro to add reference to TIM9 instance</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><br>
-</li>
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- <li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman"; color: black;"><span style="font-size: 10pt; font-family: Verdana;">SDMMC:</span></li>
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- <li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman"; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Re</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">move SDIO_TypeDef() structure, SDIO_BASE define and SDIO Bits definitions : feature not available on all devices <br>
-except <span style="font-weight: bold;">STM32F103xE</span> and </span><span style="font-family: Verdana,sans-serif; font-size: 10pt; font-weight: bold;">STM32F103xG</span></li>
- </ul>
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- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new PCD/HCD macros:</span></li>
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- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new SPI_CRC_ERROR_WORKAROUND_FEATURE define to enable SPI CRC workaround feature for <span style="font-weight: bold;">STM32F101xE/STM32F103xE</span> devices <br>
- </span></li>
- </ul>
- </ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.3.0 / 09-October-2018 <o:p></o:p></span></h3>
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- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add missing IS_TIM_SYNCHRO_INSTANCE macro definition </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">to check TIM SYNCHRO feature instance support.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.2.0 / 31-March-2017 <o:p></o:p></span></h3>
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- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Use _Pos and _Mask macros for all Bit Definitions</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove Core-CM3 bit definitions from CMSIS devices drivers: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">duplicated</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> with bit definitions in core_cm3.h.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates in header files to support LL drivers</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove TIM </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SMCR OCCS and TIM CCER CC4NP</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> bit definitions<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new USART defines: USART_CR1_OVER8 and USART_CR3_ONEBIT<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add I2C_DR_DR bit definition</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new I2C macros: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IS_SMBUS_ALL_INSTANCE</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new LL I2S defines: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SPI_I2S_SUPPORT and I2S2_I2S3_CLOCK_FEATURE</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename DAC instance to DAC1<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename PWR_CR_PLS_<span style="font-weight: bold;">XXX</span> to PWR_CR_PLS_LEV<span style="font-weight: bold;">X</span></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add RCC LL defines</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">RCC_HSE_MIN</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">RCC_HSE_MAX</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">RCC_MAX_FREQUENCY</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">RCC_PLL_SUPPORT</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">RCC_PLLI2S_SUPPORT<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new TIM macros to check TIM feature instance support:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IS_TIM_COUNTER_MODE_SELECT_INSTANCE()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IS_TIM_ADVANCED_INSTANCE</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IS_TIM_ETR_INSTANCE</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IS_TIM_32B_COUNTER_INSTANCE</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IS_TIM_BREAK_INSTANCE()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IS_TIM_CCXN_INSTANCE()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IS_TIM_REPETITION_COUNTER_INSTANCE()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IS_TIM_COMMUTATION_EVENT_INSTANCE()</span></li></ul></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.1.0 / 29-April-2016 <o:p></o:p></span></h3>
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-Changes</span></u></b></p><ul style="list-style-type: square;"><li>Add _Pos and _Msk defines to be used with _VAL2FLD(field, value) and _FLD2VAL(field, value). </li><ul><li>The previous naming are kept for backward compatibility.<span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;">RCC: Add define RCC_CFGR_MCOSEL for compatibility across all STM32 series.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">ADC: Add define ADC_MULTIMODE_SUPPORT for devices supporting the ADC multimode feature.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">ADC: Add define ADC_SR_EOS and ADC_SR_JEOS for compatibility accross all STM32 series.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">stm32f1xx.h:
-Replace __STM32F1xx_CMSIS_DEVICE_VERSION_MAIN by
-__STM32F1_CMSIS_VERSION_MAIN for MISRA compliancy on define length name.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add APBPrescTable constant to list APB prescalers values.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add FLASHSIZE_BASE for the FLASH Size register base address.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add UID_BASE for the unique device ID register base address.<br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.0.2 / 18-December-2015 <o:p></o:p></span></h3>
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- <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">Remove __IO or __I on constant table declaration (AHBPrescTable in system_stm32f1xx.c) due to issue with </span>mbed C++ code. The table content was filled with random value at initialization phase.</li><li>uint8_t alignment done on CMSIS CRC registers structure.</li><li>Removing
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-applicable to those products.</li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.0.0 / 16-December-2014 <o:p></o:p></span></h3>
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-
-
-
- <ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">Update
-based on STM32Cube specification<br>
-</span></li><li style="font-weight: bold;"><span style="font-size: 10pt; font-family: Verdana;">This version has to be used only with </span><span style="font-size: 10pt; font-family: Verdana;">STM32CubeF1</span><span style="font-size: 10pt; font-family: Verdana;"> based development</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.3 / 10-April-2014<o:p></o:p></span></h3>
-
-
-
-
-
-
-
-
-
-
-
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-
-
-
-
-
-
-
-
-
-
-
- <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version.</span></li></ul>
-
-
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.2 / 28-February-2013<o:p></o:p></span></h3>
-
-
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-
-
- <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change <span style="font-style: italic;">#define FLASH_ACR_LATENCY ((uint8_t)<span style="font-weight: bold;">0x03</span>)</span> by <span style="font-style: italic;">#define FLASH_ACR_LATENCY ((uint8_t)<span style="font-weight: bold;">0x07</span>)</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove '<span style="font-weight: bold;">,</span>' from <span style="font-style: italic;">#define DMA_CCR7_PSIZE <span style="font-weight: bold;">,</span> ((uint16_t)0x0300)</span></span></li></ul></ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.1 / 09-March-2012<o:p></o:p></span></h3>
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
- <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: license disclaimer text update and add link to the License file on ST Internet.</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.6.0 / 27-January-2012<o:p></o:p></span></h3>
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
- <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update directory structure to be compliant with CMSIS V2.1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: update disclaimer to add reference to the new license agreement</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add define for Cortex-M3 revision <span style="font-style: italic;">__CM3_REV</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Allow
-modification of some constants by the application code, definition of
-these constants is now bracketed by <span style="font-style: italic;">#if !defined</span><span style="font-style: italic;"></span>. The concerned constant are <span style="font-style: italic;">HSE_VALUE</span>, <span style="font-style: italic;">HSI_VALUE</span> and <span style="font-style: italic;">HSE_STARTUP_TIMEOUT</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add missing bits definition for <span style="font-style: italic;">DAC CR</span> register</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add missing bits definition for <span style="font-style: italic;">FSMC BTR1, BTR2, BTR3, BWTR1, BWTR2, BWTR3 and BWTR4</span> registers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Definition for </span><span style="font-size: 10pt; font-family: Verdana;">Flash keys moved from stm32f10x_flash.c to stm32f10x.h<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add startup file for <span style="font-style: italic;">TASKING</span> toolchain</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana; text-decoration: underline; font-style: italic;">V3.5.0 (based CMSIS V1.3) vs. V3.6.0 (based on CMSIS V2.1)</span><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline; font-style: italic;"> compatibility update</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Due to the </span><span style="font-size: 10pt; font-family: Verdana;"> directory structure </span><span style="font-size: 10pt; font-family: Verdana;">difference between CMSIS V1.3 and V2.1, when migrating a project based on STM32F10x drivers V3.5.0 to </span><span style="font-size: 10pt; font-family: Verdana;">V3.6.0 </span><span style="font-size: 10pt; font-family: Verdana;">you need to perform the following update:</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">In
-the compiler preprocessor, remove CortexM3 CMSIS include path. CortexM3
-CMSIS files are included by default in your development toolchain</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove core_cm3.c file (if it is used). Almost of CortexM3 CMSIS function are provided as intrinsic by the compiler</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">In the compiler preprocessor, update path of </span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STM32F10x</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> CMSIS</span> <span style="font-style: italic;">include</span> files from </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Libraries\CMSIS\CM3\DeviceSupport\ST\</span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STM32F10x </span><span style="font-size: 10pt; font-family: Verdana;">to</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;"> </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Libraries\CMSIS\Device\ST\STM32F10x\Include</span><span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">In the project settings, update path of <span style="font-style: italic;">startup_stm32f10x_xx.s</span> file from</span><span style="font-size: 10pt; font-family: Verdana;"> Libraries\CMSIS\CM3\DeviceSupport\ST\</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">STM32F10x</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">\startup\”Compiler”</span> to </span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">Libraries\CMSIS\Device\ST\STM32F10x\Source\Templates\”Compiler”</span></li></ul></ul></ul><div style="margin-left: 40px;"><div style="margin-left: 80px;"><span style="font-size: 10pt; font-family: Verdana;">where, "Compiler" refer to arm, gcc_ride7, iar, TASKING or TrueSTUDIO</span><br></div><span style="font-size: 10pt; font-family: Verdana;"></span></div>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
- <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32f10x.h
-</span>and <span style="font-style: italic;">startup_stm32f10x_hd_vl.s</span> files: remove the FSMC interrupt
-definition for STM32F10x High-density Value line devices.<br>
-</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">system_stm32f10x.c</span> file provided within the CMSIS folder. <br>
-</span></li></ul>
-
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
-- 10/15/2010</span></h3>
-
- <ol><li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li></ol>
-
- <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for <b>STM32F10x High-density Value line devices</b>.</span></li></ul>
- <ol start="2"><li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li></ol>
-
-
-
- <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
- </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support High-density Value line devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_HD_VL</span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, FSMC bits definition updated</span></li></ul><li class="MsoNormal" style="">
-
- <span style="font-size: 10pt; font-family: "Verdana","sans-serif";">All
-STM32 devices definitions are commented by default. User has to select the
-appropriate device before starting else an error will be signaled on compile
-time.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new IRQs definitions inside the IRQn_Type enumeration for STM23 High-density Value line devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">"<span style="font-weight: bold;">bool</span>" type removed.</span><br>
- <span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
- <span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">"system_stm32f10x.c" </span><span style="font-weight: bold;"></span>moved to to "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Template</span>" directory. This file is also moved to each example directory under "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Examples</span>".</span><br>
-<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support High-density Value line devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add "<span style="font-style: italic;">VECT_TAB_SRAM</span>" inside "</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">system_stm32f10x.c</span></span><span style="font-size: 10pt; font-family: Verdana;">"
-to select if the user want to place the Vector Table in internal SRAM.
-An additional define is also to specify the Vector Table offset "<span style="font-style: italic;">VECT_TAB_OFFSET</span>".<br>
- </span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add three
-startup files for STM32 High-density Value line devices:
- <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_hd_vl.s</span></span></li></ul></ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0
-- 04/16/2010</span></h3>
-
-<ol><li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li></ol>
-<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for <b>STM32F10x XL-density devices</b>.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain<br></span></li></ul><ol start="2"><li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li></ol>
-
- <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
- </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support XL-density devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_XL</span></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IRQs for </span><span style="font-size: 10pt; font-family: Verdana;">TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update FLASH_TypeDef structure</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IP instances TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, DBGMCU bits definition updated</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma "," at the end of enum list)<br></span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
- <span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support XL-density devices</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span> function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions. </span><span style="font-size: 10pt; font-family: Verdana;"><br>
- </span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span><span style="font-weight: bold; font-style: italic;"></span><span style="font-style: italic;"><span style="font-weight: bold;"></span></span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">add three
-startup files for STM32 XL-density devices:
- <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xl.s</span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">startup_stm32f10x_md_vl.s</span> for RIDE7: add USART3 IRQ Handler (was missing in previous version)</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
-- 03/01/2010</span></h3>
-<ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>
-<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS files updated to <span style="font-weight: bold;">CMSIS V1.30</span> release</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Directory structure updated to be aligned with CMSIS V1.30<br>
- </span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for <b>STM32 Low-density Value line (STM32F100x4/6) and
-Medium-density Value line (STM32F100x8/B) devices</b>. </span><span style="font-size: 10pt;"><o:p></o:p></span></li></ul>
-<ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">CMSIS Core Peripheral Access Layer</span></i></b></li></ol>
- <ul><li><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b><span style="font-size: 10pt; font-family: Verdana;"> Refer to <a href="../../../../../../../../CMSIS_changes.htm" target="_blank">CMSIS changes</a></span></li></ul>
- <ol style="margin-top: 0in; list-style-type: decimal;" start="3"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>
-
- <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
- </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update
-the stm32f10x.h file to support new Value line devices features: CEC
-peripheral, new General purpose timers TIM15, TIM16 and TIM17.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Peripherals Bits definitions updated to be in line with Value line devices available features.<br>
- </span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">HSE_Value,
-HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE,
-HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy
-purposes.<br>
- </span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
- <span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemFrequency variable name changed to SystemCoreClock</span><br>
- <span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Default
- </span></span><span style="font-size: 10pt; font-family: Verdana;">SystemCoreClock</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.</span></span><span style="font-size: 10pt;"><o:p></o:p></span><span style="font-size: 10pt; font-family: Verdana;"> <br>
- </span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.<br>
- </span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Additional function <span style="font-weight: bold; font-style: italic;">void SystemCoreClockUpdate (void)</span> is provided.<br>
- </span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Startup files:</span> <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new
-startup files for STM32 Low-density Value line devices:
- <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_ld_vl.s</span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new startup
-files for STM32 Medium-density Value line devices:
- <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_md_vl.s</span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.<br>
-To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file <br>
-</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.<br>
-</span></li></ul></ul>
-
-
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">package</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></div><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"><br>Unless
-required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
-the License for the specific language governing permissions and
-limitations under the License.</span>
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%"></span></div>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers
-visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
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+<h1 id="release-notes-for-stm32f1xx-cmsis"><strong>Release Notes for STM32F1xx CMSIS</strong></h1>
+<p>Copyright © 2016 STMicroelectronics<br />
+</p>
+<a href="https://www.st.com" class="logo"><img src="./_htmresc/st_logo.png" alt="ST logo" /></a>
+</center>
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+</div>
+<h1 id="license"><strong>License</strong></h1>
+This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
+<center>
+<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
+</center>
+</div>
+<div class="col-sm-12 col-lg-8">
+<h1 id="update-history"><strong>Update History</strong></h1>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4_3_2" checked aria-hidden="true"> <label for="collapse-section4_3_2" aria-hidden="true"><strong>V4.3.2 / 07-September-2020</strong></label>
+<div>
+<h2 id="main-changes">Main Changes</h2>
+<ul>
+<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS</li>
+<li>SystemInit(): update to don’t reset RCC registers to its reset values.</li>
+<li>TIM:
+<ul>
+<li>Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro</li>
+</ul></li>
+<li>I2S:
+<ul>
+<li>Add missing I2SCFG and I2SPR bits difinitions for STM32F101xE and STM32F101xG</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4_3_1" aria-hidden="true"> <label for="collapse-section4_3_1" aria-hidden="true"><strong>V4.3.1 / 26-June-2019</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>Fix MISRA C 2012 Compilation errors: update to use “UL” postfix for bits mask definitions(_Msk) and memory/peripheral base addresses</li>
+<li>Fix wrong initialization value for “SystemCoreClock” in System_stm32f1xx.c file</li>
+<li>Update gcc linker file template to be aligned with AC6 linker file template</li>
+<li>stm32f1xx.h
+<ul>
+<li>Align ErrorStatus typedef to common error handling</li>
+</ul></li>
+<li>TIM:
+<ul>
+<li>Update IS_TIM_SLAVE_INSTANCE() macro to add reference to TIM9 instance</li>
+</ul></li>
+<li>SDMMC:
+<ul>
+<li>Remove SDIO_TypeDef() structure, SDIO_BASE define and SDIO Bits definitions : feature not available on all devices except <strong>STM32F103xE</strong> and <strong>STM32F103xG</strong></li>
+</ul></li>
+<li>USB:
+<ul>
+<li>Add new PCD/HCD macros:
+<ul>
+<li>IS_PCD_ALL_INSTANCE()</li>
+<li>IS_HCD_ALL_INSTANCE()</li>
+</ul></li>
+</ul></li>
+<li>SPI:
+<ul>
+<li>Add new SPI_CRC_ERROR_WORKAROUND_FEATURE define to enable SPI CRC workaround feature for <strong>STM32F101xE/STM32F103xE</strong> devices</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4_3_0" aria-hidden="true"> <label for="collapse-section4_3_0" aria-hidden="true"><strong>V4.3.0 / 09-October-2018</strong></label>
+<div>
+<h2 id="main-changes-2">Main Changes</h2>
+<ul>
+<li>Add missing IS_TIM_SYNCHRO_INSTANCE macro definition to check TIM SYNCHRO feature instance support.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4_2_0" aria-hidden="true"> <label for="collapse-section4_2_0" aria-hidden="true"><strong>V4.2.0 / 31-March-2017</strong></label>
+<div>
+<h2 id="main-changes-3">Main Changes</h2>
+<ul>
+<li>Use _Pos and _Mask macros for all Bit Definitions</li>
+<li>Remove Core-CM3 bit definitions from CMSIS devices drivers: duplicated with bit definitions in core_cm3.h.</li>
+<li>General updates in header files to support LL drivers
+<ul>
+<li>Remove TIM SMCR OCCS and TIM CCER CC4NP bit definitions</li>
+<li>Add new USART defines: USART_CR1_OVER8 and USART_CR3_ONEBIT</li>
+<li>Add I2C_DR_DR bit definition</li>
+<li>Add new I2C macros: IS_SMBUS_ALL_INSTANCE</li>
+<li>Add new LL I2S defines: SPI_I2S_SUPPORT and I2S2_I2S3_CLOCK_FEATURE</li>
+<li>Rename DAC instance to DAC1</li>
+<li>Rename PWR_CR_PLS_<strong>XXX</strong> to PWR_CR_PLS_LEV<strong>X</strong></li>
+<li>Add RCC LL defines
+<ul>
+<li>RCC_HSE_MIN</li>
+<li>RCC_HSE_MAX</li>
+<li>RCC_MAX_FREQUENCY</li>
+<li>RCC_PLL_SUPPORT</li>
+<li>RCC_PLLI2S_SUPPORT</li>
+</ul></li>
+<li>Add new TIM macros to check TIM feature instance support:
+<ul>
+<li>IS_TIM_COUNTER_MODE_SELECT_INSTANCE()</li>
+<li>IS_TIM_ADVANCED_INSTANCE</li>
+<li>IS_TIM_ETR_INSTANCE</li>
+<li>IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE</li>
+<li>IS_TIM_32B_COUNTER_INSTANCE</li>
+<li>IS_TIM_BREAK_INSTANCE()</li>
+<li>IS_TIM_CCXN_INSTANCE()</li>
+<li>IS_TIM_REPETITION_COUNTER_INSTANCE()</li>
+<li>IS_TIM_COMMUTATION_EVENT_INSTANCE()</li>
+</ul></li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4_1_0" aria-hidden="true"> <label for="collapse-section4_1_0" aria-hidden="true"><strong>V4.1.0 / 29-April-2016</strong></label>
+<div>
+<h2 id="main-changes-4">Main Changes</h2>
+<ul>
+<li>Add _Pos and _Msk defines to be used with _VAL2FLD(field, value) and _FLD2VAL(field, value).
+<ul>
+<li>The previous naming are kept for backward compatibility.</li>
+</ul></li>
+<li>RCC: Add define RCC_CFGR_MCOSEL for compatibility across all STM32 series.</li>
+<li>ADC: Add define ADC_MULTIMODE_SUPPORT for devices supporting the ADC multimode feature.</li>
+<li>ADC: Add define ADC_SR_EOS and ADC_SR_JEOS for compatibility accross all STM32 series.</li>
+<li>stm32f1xx.h: Replace __STM32F1xx_CMSIS_DEVICE_VERSION_MAIN by __STM32F1_CMSIS_VERSION_MAIN for MISRA compliancy on define length name.</li>
+<li>Add APBPrescTable constant to list APB prescalers values.</li>
+<li>Add FLASHSIZE_BASE for the FLASH Size register base address.</li>
+<li>Add UID_BASE for the unique device ID register base address.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4_0_2" aria-hidden="true"> <label for="collapse-section4_0_2" aria-hidden="true"><strong>V4.0.2 / 18-December-2016</strong></label>
+<div>
+<h2 id="main-changes-5">Main Changes</h2>
+<ul>
+<li>FLASH: Add FLASH_OBR_DATA0 and FLASH_OBR_DATA1 for FLASH_OBR register.</li>
+<li>WWDG: Align bit name across all STM32 families.
+<ul>
+<li>WWDG_CR_T0 renmaed to WWDG_CR_T_0.</li>
+<li>WWDG_CFR_W0 renamed to WWDG_CFR_W_0.</li>
+<li>WWDG_CFR_WDGTB0 renamed to WWDG_CFR_WDGTB_0.</li>
+<li>WWDG_CFR_WDGTB1 renamed to WWDG_CFR_WDGTB_1.</li>
+</ul></li>
+<li>Interrupt: Add HardFault_IRQn with value -13.</li>
+<li>EXTI:: Align bit name across all STM32 families.
+<ul>
+<li>EXTI_IMR_MR0 renamed to EXTI_IMR_IM0.</li>
+<li>EXTI_EMR_MR0 renamed to EXTI_EMR_EM0.</li>
+<li>EXTI_RTSR_TR0 renamed to EXTI_RTSR_RT0.</li>
+<li>EXTI_FTSR_TR0 renamed to EXTI_FTSR_FT0.</li>
+<li>EXTI_SWIER_SWIER0 renamed to EXTI_SWIER_SWI0.</li>
+<li>EXTI_PR_PR0 renamed to EXTI_PR_PIF0.</li>
+<li>Aliases are created for backward compatibilities.</li>
+</ul></li>
+<li>USB OTG: Remove USB_OTG_GCCFG_NOVBUSSENS from USB_OTG_GCCFG as this feature is not present in F1 devices.</li>
+<li>USB_OTG: Remove USB_OTG_GCCFG_I2CPADEN from USB_OTG_GCCFG as this feature is not present in F1 devices.</li>
+<li>ADC: Add the notion of common instance for compatibility with other STM32 families.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4_0_1" aria-hidden="true"> <label for="collapse-section4_0_1" aria-hidden="true"><strong>V4.0.1 / 31-July-2015</strong></label>
+<div>
+<h2 id="main-changes-6">Main Changes</h2>
+<ul>
+<li>Remove __IO or __I on constant table declaration (AHBPrescTable in system_stm32f1xx.c) due to issue with mbed C++ code. The table content was filled with random value at initialization phase.</li>
+<li>uint8_t alignment done on CMSIS CRC registers structure.</li>
+<li>Removing definition of FLASH_WRP1_WRP1, FLASH_WRP1_nWRP1, FLASH_WRP2_WRP2, FLASH_WRP2_nWRP2, FLASH_WRP3_WRP3 and FLASH_WRP3_nWRP3 for product STM32F101x6, STM32F102x6 and STM32F103x6. Those defines are not applicable to those products.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section4_0_0" aria-hidden="true"> <label for="collapse-section4_0_0" aria-hidden="true"><strong>V4.0.0 / 16-December-2014</strong></label>
+<div>
+<h2 id="main-changes-7">Main Changes</h2>
+<ul>
+<li>Update based on STM32Cube specification</li>
+<li><strong>This version has to be used only with STM32CubeF1 based development</strong></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3_6_3" aria-hidden="true"> <label for="collapse-section3_6_3" aria-hidden="true"><strong>V3.6.3 / 10-April-2014</strong></label>
+<div>
+<h2 id="main-changes-8">Main Changes</h2>
+<ul>
+<li>Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3_6_2" aria-hidden="true"> <label for="collapse-section3_6_2" aria-hidden="true"><strong>V3.6.2 / 28-February-2013</strong></label>
+<div>
+<h2 id="main-changes-9">Main Changes</h2>
+<ul>
+<li>stm32f10x.h
+<ul>
+<li>Change <em>#define FLASH_ACR_LATENCY ((uint8_t)<strong>0x03</strong>)</em> by #define <em>FLASH_ACR_LATENCY ((uint8_t)<strong>0x07</strong>)</em></li>
+<li>Remove ‘<strong>,</strong>’ from #define <em>DMA_CCR7_PSIZE , ((uint16_t)0x0300)</em></li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3_6_1" aria-hidden="true"> <label for="collapse-section3_6_1" aria-hidden="true"><strong>V3.6.1 / 09-March-2012</strong></label>
+<div>
+<h2 id="main-changes-10">Main Changes</h2>
+<ul>
+<li>All source files: license disclaimer text update and add link to the License file on ST Internet.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3_6_0" aria-hidden="true"> <label for="collapse-section3_6_0" aria-hidden="true"><strong>V3.6.0 / 27-January-2012</strong></label>
+<div>
+<h2 id="main-changes-11">Main Changes</h2>
+<ul>
+<li>Update directory structure to be compliant with CMSIS V2.1</li>
+<li>All source files: update disclaimer to add reference to the new license agreement</li>
+<li>stm32f10x.h
+<ul>
+<li>Add define for Cortex-M3 revision __<em>CM3_REV</em></li>
+<li>Allow modification of some constants by the application code, definition of these constants is now bracketed by <em>#if !defined</em>. The concerned constant are <em>HSE_VALUE</em>, <em>HSI_VALUE</em> and <em>HSE_STARTUP_TIMEOUT</em></li>
+<li>Add missing bits definition for <em>DAC CR</em> register</li>
+<li>Add missing bits definition for <em>FSMC BTR1</em>, _BTR2__, <em>BTR3</em>, <em>BWTR1</em>, <em>BWTR2</em>, <em>BWTR3</em> and <em>BWTR4</em> registers</li>
+<li>Definition for Flash keys moved from stm32f10x_flash.c to stm32f10x.h</li>
+</ul></li>
+<li>V3.5.0 (based CMSIS V1.3) vs. V3.6.0 (based on CMSIS V2.1) compatibility update
+<ul>
+<li>Due to the directory structure difference between CMSIS V1.3 and V2.1, when migrating a project based on STM32F10x drivers V3.5.0 to V3.6.0 you need to perform the following update:
+<ul>
+<li>Rename ADC1_COMP_IRQn to ADC1_IRQn</li>
+<li>In the compiler preprocessor, remove CortexM3 CMSIS include path. CortexM3 CMSIS files are included by default in your development toolchain</li>
+<li>Remove core_cm3.c file (if it is used). Almost of CortexM3 CMSIS_ function are provided as intrinsic by the compiler</li>
+<li>In the compiler preprocessor, update path of _STM32F10x CMSIS include files from <em>Libraries332F10x to Libraries32F10x</em></li>
+<li>In the project settings, update path of <em>startup_stm32f10x_xx.s</em> file from <em>Libraries332F10x”Compiler”</em> to <em>Libraries32F10x”Compiler”</em> where, “Compiler” refer to arm, gcc_ride7, iar, TASKING or TrueSTUDIO</li>
+</ul></li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3_5_0" aria-hidden="true"> <label for="collapse-section3_5_0" aria-hidden="true"><strong>V3.5.0 / 11-March-2011</strong></label>
+<div>
+<h2 id="main-changes-12">Main Changes</h2>
+<ul>
+<li><em>stm32f10x.h</em> and <em>startup_stm32f10x_hd_vl.s</em> files: remove the FSMC interrupt definition for STM32F10x High-density Value line devices.</li>
+<li>system_stm32f10x.c file provided within the CMSIS folder.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3_4_0" aria-hidden="true"> <label for="collapse-section3_4_0" aria-hidden="true"><strong>V3.4.0 / 15-October-2010</strong></label>
+<div>
+<h2 id="main-changes-13">Main Changes</h2>
+<ul>
+<li>General
+<ul>
+<li>Add support for <strong>STM32F10x High-density Value line devices</strong>.</li>
+</ul></li>
+<li>STM32F10x CMSIS Device Peripheral Access Layer
+<ul>
+<li>STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: <em><strong>stm32f10x.h</strong></em>
+<ul>
+<li>Update to support High-density Value line devices
+<ul>
+<li>Add new define <em>STM32F10X_HD_VL</em></li>
+<li>RCC, AFIO, FSMC bits definition updated</li>
+</ul></li>
+<li>All STM32 devices definitions are commented by default. User has to select the appropriate device before starting else an error will be signaled on compile time.</li>
+<li>Add new IRQs definitions inside the IRQn_Type enumeration for STM23 High-density Value line devices.</li>
+<li>“<strong>bool</strong>” type removed.</li>
+</ul></li>
+</ul></li>
+<li>STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: <em><strong>system_stm32f10x.h</strong></em> and <em><strong>system_stm32f10x.c</strong></em>
+<ul>
+<li>“<em><strong>system_stm32f10x.c</strong></em>” moved to to “<em><strong>STM32F10x_StdPeriph_Template</strong></em>” directory. This file is also moved to each example directory under “<strong>STM32F10x_StdPeriph_Examples</strong>”.</li>
+<li>SystemInit_ExtMemCtl() function: update to support High-density Value line devices.</li>
+<li>Add “VECT_TAB_SRAM” inside “<em><strong>system_stm32f10x.c</strong></em>” to select if the user want to place the Vector Table in internal SRAM. An additional define is also to specify the Vector Table offset “VECT_TAB_OFFSET”.</li>
+</ul></li>
+<li>STM32F10x CMSIS startup files:<em><strong>startup_stm32f10x_xx.s</strong></em>
+<ul>
+<li>Add three startup files for STM32 High-density Value line devices: <em><strong>startup_stm32f10x_hd_vl.s</strong></em></li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3_3_0" aria-hidden="true"> <label for="collapse-section3_3_0" aria-hidden="true"><strong>V3.3.0 / 16-April-2010</strong></label>
+<div>
+<h2 id="main-changes-14">Main Changes</h2>
+<ul>
+<li>General
+<ul>
+<li>Add support for <strong>STM32F10x XL-density devices</strong>.</li>
+<li>Add startup files for TrueSTUDIO toolchain</li>
+</ul></li>
+<li><strong>STM32F10x CMSIS Device Peripheral Access Layer</strong>
+<ul>
+<li>STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: <em><strong>stm32f10x.h</strong></em>
+<ul>
+<li>Update to support XL-density devices
+<ul>
+<li>Add new define STM32F10X_XL</li>
+<li>Add new IRQs for TIM9..14</li>
+<li>Update FLASH_TypeDef structure</li>
+<li>Add new IP instances TIM9..14</li>
+<li>RCC, AFIO, DBGMCU bits definition updated</li>
+</ul></li>
+<li>Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices (remove comma “,” at the end of enum list)</li>
+</ul></li>
+<li>STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: <em><strong>system_stm32f10x.h</strong></em> and <em><strong>system_stm32f0xx.c</strong></em>
+<ul>
+<li>SystemInit_ExtMemCtl() function: update to support XL-density devices</li>
+<li>SystemInit() function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions.</li>
+</ul></li>
+<li>STM32F10x CMSIS startup files:
+<ul>
+<li>add three startup files for STM32 XL-density devices: <em><strong>startup_stm32f10x_xl.s</strong></em></li>
+<li><em><strong>startup_stm32f10x_md_vl.s</strong></em> for RIDE7: add USART3 IRQ Handler (was missing in previous version)</li>
+<li>Add startup files for TrueSTUDIO toolchain</li>
+</ul></li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3_2_0" aria-hidden="true"> <label for="collapse-section3_2_0" aria-hidden="true"><strong>V3.2.0 / 01-March-2010</strong></label>
+<div>
+<h2 id="main-changes-15">Main Changes</h2>
+<ul>
+<li>General
+<ul>
+<li>STM32F10x CMSIS files updated to <strong>CMSIS V1.30</strong> release</li>
+<li>Directory structure updated to be aligned with CMSIS V1.30</li>
+<li>Add support for <strong>STM32 Low-density Value line (STM32F100x4/6)</strong> and <strong>Medium-density Value line (STM32F100x8/B) devices</strong>.</li>
+</ul></li>
+<li>CMSIS Core Peripheral Access Layer</li>
+<li><strong>STM32F10x CMSIS Device Peripheral Access Layer</strong>
+<ul>
+<li>STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File: <em><strong>stm32f10x.h</strong></em>
+<ul>
+<li>Update the stm32f10x.h file to support new Value line devices features: CEC peripheral, new General purpose timers TIM15, TIM16 and TIM17.</li>
+<li>Peripherals Bits definitions updated to be in line with Value line devices available features.</li>
+<li>HSE_Value, HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE, HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy purposes.</li>
+</ul></li>
+<li>STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files: <em><strong>system_stm32f10x.h</strong></em> and <em><strong>system_stm32f10x.c</strong></em>
+<ul>
+<li>SystemFrequency variable name changed to SystemCoreClock</li>
+<li>Default SystemCoreClock is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.</li>
+<li>All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.</li>
+<li>Additional function <em><strong>void SystemCoreClockUpdate (void)</strong></em> is provided.</li>
+</ul></li>
+<li>STM32F10x CMSIS Startup files: <em><strong>startup_stm32f10x_xx.s</strong></em>
+<ul>
+<li>Add new startup files for STM32 Low-density Value line devices: <em><strong>startup_stm32f10x_ld_vl.s</strong></em></li>
+<li>Add new startup files for STM32 Medium-density Value line devices: <em><strong>startup_stm32f10x_md_vl.s</strong></em></li>
+<li>SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main. To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file</li>
+</ul></li>
+</ul></li>
+<li>GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.</li>
+</ul>
+</div>
+</div>
+</div>
+</div>
+<footer class="sticky">
+For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span> <em>This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.</em>
+</footer>
+</body>
+</html>
diff --git a/Source/Templates/system_stm32f1xx.c b/Source/Templates/system_stm32f1xx.c
index 7cacb32..bc96aae 100644
--- a/Source/Templates/system_stm32f1xx.c
+++ b/Source/Templates/system_stm32f1xx.c
@@ -89,12 +89,31 @@
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in Flash or Sram, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in Sram else user remap will be done in Flash. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x200. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+/******************************************************************************/
/**
* @}
@@ -156,57 +175,16 @@
*/
void SystemInit (void)
{
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
- /* Set HSION bit */
- RCC->CR |= 0x00000001U;
-
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#if !defined(STM32F105xC) && !defined(STM32F107xC)
- RCC->CFGR &= 0xF8FF0000U;
-#else
- RCC->CFGR &= 0xF0FF0000U;
-#endif /* STM32F105xC */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= 0xFEF6FFFFU;
-
- /* Reset HSEBYP bit */
- RCC->CR &= 0xFFFBFFFFU;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
- RCC->CFGR &= 0xFF80FFFFU;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- /* Reset PLL2ON and PLL3ON bits */
- RCC->CR &= 0xEBFFFFFFU;
-
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x00FF0000U;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000U;
-#elif defined(STM32F100xB) || defined(STM32F100xE)
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000U;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000U;
-#else
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000U;
-#endif /* STM32F105xC */
-
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#endif /* USER_VECT_TAB_ADDRESS */
}
/**
