| /** |
| ****************************************************************************** |
| * @file stm32f411xe.h |
| * @author MCD Application Team |
| * @brief CMSIS STM32F411xE Device Peripheral Access Layer Header File. |
| * |
| * This file contains: |
| * - Data structures and the address mapping for all peripherals |
| * - peripherals registers declarations and bits definition |
| * - Macros to access peripheral’s registers hardware |
| * |
| ****************************************************************************** |
| * @attention |
| * |
| * Copyright (c) 2017 STMicroelectronics. |
| * All rights reserved. |
| * |
| * This software is licensed under terms that can be found in the LICENSE file |
| * in the root directory of this software component. |
| * If no LICENSE file comes with this software, it is provided AS-IS. |
| * |
| ****************************************************************************** |
| */ |
| |
| /** @addtogroup CMSIS_Device |
| * @{ |
| */ |
| |
| /** @addtogroup stm32f411xe |
| * @{ |
| */ |
| |
| #ifndef __STM32F411xE_H |
| #define __STM32F411xE_H |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif /* __cplusplus */ |
| |
| /** @addtogroup Configuration_section_for_CMSIS |
| * @{ |
| */ |
| |
| /** |
| * @brief Configuration of the Cortex-M4 Processor and Core Peripherals |
| */ |
| #define __CM4_REV 0x0001U /*!< Core revision r0p1 */ |
| #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ |
| #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ |
| #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ |
| #define __FPU_PRESENT 1U /*!< FPU present */ |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_interrupt_number_definition |
| * @{ |
| */ |
| |
| /** |
| * @brief STM32F4XX Interrupt Number Definition, according to the selected device |
| * in @ref Library_configuration_section |
| */ |
| typedef enum |
| { |
| /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ |
| NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
| BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ |
| UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ |
| SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ |
| DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ |
| PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ |
| SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ |
| /****** STM32 specific Interrupt Numbers **********************************************************************/ |
| WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
| TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ |
| RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ |
| FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
| RCC_IRQn = 5, /*!< RCC global Interrupt */ |
| EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
| EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
| EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
| EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
| EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
| DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ |
| DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ |
| DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ |
| DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ |
| DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ |
| DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ |
| DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ |
| ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ |
| EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ |
| TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ |
| TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ |
| TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ |
| OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ |
| DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ |
| SDIO_IRQn = 49, /*!< SDIO global Interrupt */ |
| TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ |
| DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ |
| DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ |
| DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ |
| DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ |
| OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ |
| DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ |
| DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ |
| DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ |
| USART6_IRQn = 71, /*!< USART6 global interrupt */ |
| I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ |
| I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ |
| FPU_IRQn = 81, /*!< FPU global interrupt */ |
| SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ |
| SPI5_IRQn = 85 /*!< SPI5 global Interrupt */ |
| } IRQn_Type; |
| |
| /** |
| * @} |
| */ |
| |
| #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
| #include "system_stm32f4xx.h" |
| #include <stdint.h> |
| |
| /** @addtogroup Peripheral_registers_structures |
| * @{ |
| */ |
| |
| /** |
| * @brief Analog to Digital Converter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ |
| __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ |
| __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ |
| __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ |
| __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ |
| __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ |
| __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ |
| __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ |
| __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ |
| __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ |
| __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ |
| __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ |
| __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ |
| __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ |
| __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ |
| __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ |
| __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ |
| __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ |
| __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ |
| __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ |
| } ADC_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ |
| __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ |
| __IO uint32_t CDR; /*!< ADC common regular data register for dual |
| AND triple modes, Address offset: ADC1 base address + 0x308 */ |
| } ADC_Common_TypeDef; |
| |
| /** |
| * @brief CRC calculation unit |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| uint8_t RESERVED0; /*!< Reserved, 0x05 */ |
| uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| } CRC_TypeDef; |
| |
| /** |
| * @brief Debug MCU |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ |
| __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ |
| }DBGMCU_TypeDef; |
| |
| |
| /** |
| * @brief DMA Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< DMA stream x configuration register */ |
| __IO uint32_t NDTR; /*!< DMA stream x number of data register */ |
| __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ |
| __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ |
| __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ |
| __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ |
| } DMA_Stream_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ |
| __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ |
| __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ |
| __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ |
| } DMA_TypeDef; |
| |
| /** |
| * @brief External Interrupt/Event Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ |
| __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ |
| __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ |
| __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ |
| __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ |
| __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ |
| } EXTI_TypeDef; |
| |
| /** |
| * @brief FLASH Registers |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ |
| __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ |
| __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ |
| __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ |
| __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ |
| __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ |
| __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ |
| } FLASH_TypeDef; |
| |
| /** |
| * @brief General Purpose I/O |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ |
| __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ |
| } GPIO_TypeDef; |
| |
| /** |
| * @brief System configuration controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ |
| __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ |
| __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ |
| uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ |
| __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ |
| } SYSCFG_TypeDef; |
| |
| /** |
| * @brief Inter-integrated Circuit Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ |
| __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ |
| __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ |
| __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ |
| __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ |
| __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ |
| __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ |
| __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ |
| } I2C_TypeDef; |
| |
| /** |
| * @brief Independent WATCHDOG |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
| __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
| __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
| __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
| } IWDG_TypeDef; |
| |
| |
| /** |
| * @brief Power Control |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ |
| __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ |
| } PWR_TypeDef; |
| |
| /** |
| * @brief Reset and Clock Control |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
| __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ |
| __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ |
| __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ |
| __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ |
| __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ |
| __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ |
| uint32_t RESERVED0; /*!< Reserved, 0x1C */ |
| __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ |
| __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ |
| uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ |
| __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ |
| __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ |
| __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x3C */ |
| __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ |
| __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ |
| uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ |
| __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ |
| __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ |
| __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ |
| uint32_t RESERVED4; /*!< Reserved, 0x5C */ |
| __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ |
| __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ |
| uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ |
| __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ |
| __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ |
| uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ |
| __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ |
| __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ |
| uint32_t RESERVED7[1]; /*!< Reserved, 0x88 */ |
| __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ |
| } RCC_TypeDef; |
| |
| /** |
| * @brief Real-Time Clock |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
| __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
| __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
| __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
| __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
| __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
| __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ |
| __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
| __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ |
| __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
| __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
| __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
| __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
| __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
| __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
| __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
| __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ |
| __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ |
| __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ |
| uint32_t RESERVED7; /*!< Reserved, 0x4C */ |
| __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ |
| __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
| __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
| __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
| __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
| __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ |
| __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ |
| __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ |
| __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ |
| __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ |
| __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ |
| __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ |
| __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ |
| __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ |
| __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ |
| __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ |
| __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ |
| __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ |
| __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ |
| __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ |
| } RTC_TypeDef; |
| |
| /** |
| * @brief SD host Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ |
| __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ |
| __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ |
| __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ |
| __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ |
| __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ |
| __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ |
| __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ |
| __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ |
| __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ |
| __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ |
| __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ |
| __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ |
| __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ |
| __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ |
| __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ |
| uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ |
| __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ |
| uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ |
| __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ |
| } SDIO_TypeDef; |
| |
| /** |
| * @brief Serial Peripheral Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ |
| __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ |
| __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ |
| __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ |
| __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ |
| __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ |
| } SPI_TypeDef; |
| |
| |
| /** |
| * @brief TIM |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ |
| __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ |
| __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ |
| __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
| } TIM_TypeDef; |
| |
| /** |
| * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ |
| __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ |
| __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ |
| __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ |
| __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ |
| __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ |
| __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ |
| } USART_TypeDef; |
| |
| /** |
| * @brief Window WATCHDOG |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| } WWDG_TypeDef; |
| /** |
| * @brief USB_OTG_Core_Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ |
| __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ |
| __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ |
| __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ |
| __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ |
| __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ |
| __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ |
| __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ |
| __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ |
| __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ |
| __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ |
| __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ |
| uint32_t Reserved30[2]; /*!< Reserved 030h */ |
| __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ |
| __IO uint32_t CID; /*!< User ID Register 03Ch */ |
| uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */ |
| __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ |
| __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ |
| } USB_OTG_GlobalTypeDef; |
| |
| /** |
| * @brief USB_OTG_device_Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ |
| __IO uint32_t DCTL; /*!< dev Control Register 804h */ |
| __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ |
| uint32_t Reserved0C; /*!< Reserved 80Ch */ |
| __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ |
| __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ |
| __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ |
| __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ |
| uint32_t Reserved20; /*!< Reserved 820h */ |
| uint32_t Reserved9; /*!< Reserved 824h */ |
| __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ |
| __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ |
| __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ |
| __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ |
| __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ |
| __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ |
| uint32_t Reserved40; /*!< dedicated EP mask 840h */ |
| __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ |
| uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ |
| __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ |
| } USB_OTG_DeviceTypeDef; |
| |
| /** |
| * @brief USB_OTG_IN_Endpoint-Specific_Register |
| */ |
| typedef struct |
| { |
| __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ |
| uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ |
| __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ |
| uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ |
| __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ |
| __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ |
| __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ |
| uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ |
| } USB_OTG_INEndpointTypeDef; |
| |
| /** |
| * @brief USB_OTG_OUT_Endpoint-Specific_Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ |
| uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ |
| __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ |
| uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ |
| __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ |
| __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ |
| uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ |
| } USB_OTG_OUTEndpointTypeDef; |
| |
| /** |
| * @brief USB_OTG_Host_Mode_Register_Structures |
| */ |
| typedef struct |
| { |
| __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ |
| __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ |
| __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ |
| uint32_t Reserved40C; /*!< Reserved 40Ch */ |
| __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ |
| __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ |
| __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ |
| } USB_OTG_HostTypeDef; |
| |
| /** |
| * @brief USB_OTG_Host_Channel_Specific_Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ |
| __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ |
| __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ |
| __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ |
| __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ |
| __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ |
| uint32_t Reserved[2]; /*!< Reserved */ |
| } USB_OTG_HostChannelTypeDef; |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_memory_map |
| * @{ |
| */ |
| #define FLASH_BASE 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */ |
| #define SRAM1_BASE 0x20000000UL /*!< SRAM1(128 KB) base address in the alias region */ |
| #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ |
| #define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(128 KB) base address in the bit-band region */ |
| #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ |
| #define BKPSRAM_BB_BASE 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */ |
| #define FLASH_END 0x0807FFFFUL /*!< FLASH end address */ |
| #define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ |
| #define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ |
| |
| /* Legacy defines */ |
| #define SRAM_BASE SRAM1_BASE |
| #define SRAM_BB_BASE SRAM1_BB_BASE |
| |
| /*!< Peripheral memory map */ |
| #define APB1PERIPH_BASE PERIPH_BASE |
| #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
| #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
| #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) |
| |
| /*!< APB1 peripherals */ |
| #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) |
| #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) |
| #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) |
| #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) |
| #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) |
| #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) |
| #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) |
| #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL) |
| #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) |
| #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) |
| #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL) |
| #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) |
| #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) |
| #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) |
| #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) |
| #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) |
| |
| /*!< APB2 peripherals */ |
| #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) |
| #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) |
| #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL) |
| #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) |
| #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL) |
| /* Legacy define */ |
| #define ADC_BASE ADC1_COMMON_BASE |
| #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL) |
| #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) |
| #define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) |
| #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) |
| #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) |
| #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) |
| #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) |
| #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) |
| #define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) |
| |
| /*!< AHB1 peripherals */ |
| #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) |
| #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) |
| #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) |
| #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) |
| #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) |
| #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) |
| #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) |
| #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) |
| #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) |
| #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) |
| #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) |
| #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) |
| #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) |
| #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) |
| #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) |
| #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) |
| #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) |
| #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) |
| #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) |
| #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) |
| #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) |
| #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) |
| #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) |
| #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) |
| #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) |
| #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) |
| #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) |
| |
| |
| /*!< Debug MCU registers base address */ |
| #define DBGMCU_BASE 0xE0042000UL |
| /*!< USB registers base address */ |
| #define USB_OTG_FS_PERIPH_BASE 0x50000000UL |
| |
| #define USB_OTG_GLOBAL_BASE 0x000UL |
| #define USB_OTG_DEVICE_BASE 0x800UL |
| #define USB_OTG_IN_ENDPOINT_BASE 0x900UL |
| #define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL |
| #define USB_OTG_EP_REG_SIZE 0x20UL |
| #define USB_OTG_HOST_BASE 0x400UL |
| #define USB_OTG_HOST_PORT_BASE 0x440UL |
| #define USB_OTG_HOST_CHANNEL_BASE 0x500UL |
| #define USB_OTG_HOST_CHANNEL_SIZE 0x20UL |
| #define USB_OTG_PCGCCTL_BASE 0xE00UL |
| #define USB_OTG_FIFO_BASE 0x1000UL |
| #define USB_OTG_FIFO_SIZE 0x1000UL |
| |
| #define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */ |
| #define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */ |
| #define PACKAGE_BASE 0x1FFF7BF0UL /*!< Package size register base address */ |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_declaration |
| * @{ |
| */ |
| #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
| #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
| #define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
| #define RTC ((RTC_TypeDef *) RTC_BASE) |
| #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) |
| #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
| #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
| #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) |
| #define USART2 ((USART_TypeDef *) USART2_BASE) |
| #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
| #define I2C3 ((I2C_TypeDef *) I2C3_BASE) |
| #define PWR ((PWR_TypeDef *) PWR_BASE) |
| #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
| #define USART1 ((USART_TypeDef *) USART1_BASE) |
| #define USART6 ((USART_TypeDef *) USART6_BASE) |
| #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) |
| /* Legacy define */ |
| #define ADC ADC1_COMMON |
| #define SDIO ((SDIO_TypeDef *) SDIO_BASE) |
| #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| #define SPI4 ((SPI_TypeDef *) SPI4_BASE) |
| #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
| #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| #define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
| #define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
| #define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
| #define SPI5 ((SPI_TypeDef *) SPI5_BASE) |
| #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
| #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
| #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
| #define CRC ((CRC_TypeDef *) CRC_BASE) |
| #define RCC ((RCC_TypeDef *) RCC_BASE) |
| #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) |
| #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) |
| #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) |
| #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) |
| #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) |
| #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) |
| #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) |
| #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) |
| #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
| #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) |
| #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) |
| #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) |
| #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) |
| #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) |
| #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) |
| #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) |
| #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) |
| #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Exported_constants |
| * @{ |
| */ |
| |
| /** @addtogroup Hardware_Constant_Definition |
| * @{ |
| */ |
| #define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_Registers_Bits_Definition |
| * @{ |
| */ |
| |
| /******************************************************************************/ |
| /* Peripheral Registers_Bits_Definition */ |
| /******************************************************************************/ |
| |
| /******************************************************************************/ |
| /* */ |
| /* Analog to Digital Converter */ |
| /* */ |
| /******************************************************************************/ |
| |
| /******************** Bit definition for ADC_SR register ********************/ |
| #define ADC_SR_AWD_Pos (0U) |
| #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ |
| #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */ |
| #define ADC_SR_EOC_Pos (1U) |
| #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */ |
| #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */ |
| #define ADC_SR_JEOC_Pos (2U) |
| #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */ |
| #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */ |
| #define ADC_SR_JSTRT_Pos (3U) |
| #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ |
| #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */ |
| #define ADC_SR_STRT_Pos (4U) |
| #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ |
| #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */ |
| #define ADC_SR_OVR_Pos (5U) |
| #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */ |
| #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */ |
| |
| /******************* Bit definition for ADC_CR1 register ********************/ |
| #define ADC_CR1_AWDCH_Pos (0U) |
| #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ |
| #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
| #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ |
| #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ |
| #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ |
| #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ |
| #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ |
| #define ADC_CR1_EOCIE_Pos (5U) |
| #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */ |
| #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */ |
| #define ADC_CR1_AWDIE_Pos (6U) |
| #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ |
| #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */ |
| #define ADC_CR1_JEOCIE_Pos (7U) |
| #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */ |
| #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */ |
| #define ADC_CR1_SCAN_Pos (8U) |
| #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ |
| #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */ |
| #define ADC_CR1_AWDSGL_Pos (9U) |
| #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ |
| #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */ |
| #define ADC_CR1_JAUTO_Pos (10U) |
| #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ |
| #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */ |
| #define ADC_CR1_DISCEN_Pos (11U) |
| #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ |
| #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */ |
| #define ADC_CR1_JDISCEN_Pos (12U) |
| #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ |
| #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */ |
| #define ADC_CR1_DISCNUM_Pos (13U) |
| #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ |
| #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ |
| #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ |
| #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ |
| #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ |
| #define ADC_CR1_JAWDEN_Pos (22U) |
| #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ |
| #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */ |
| #define ADC_CR1_AWDEN_Pos (23U) |
| #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ |
| #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */ |
| #define ADC_CR1_RES_Pos (24U) |
| #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */ |
| #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */ |
| #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */ |
| #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */ |
| #define ADC_CR1_OVRIE_Pos (26U) |
| #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ |
| #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */ |
| |
| /******************* Bit definition for ADC_CR2 register ********************/ |
| #define ADC_CR2_ADON_Pos (0U) |
| #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ |
| #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */ |
| #define ADC_CR2_CONT_Pos (1U) |
| #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ |
| #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */ |
| #define ADC_CR2_DMA_Pos (8U) |
| #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ |
| #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */ |
| #define ADC_CR2_DDS_Pos (9U) |
| #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ |
| #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */ |
| #define ADC_CR2_EOCS_Pos (10U) |
| #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ |
| #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */ |
| #define ADC_CR2_ALIGN_Pos (11U) |
| #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ |
| #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */ |
| #define ADC_CR2_JEXTSEL_Pos (16U) |
| #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ |
| #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */ |
| #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ |
| #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ |
| #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ |
| #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ |
| #define ADC_CR2_JEXTEN_Pos (20U) |
| #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ |
| #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ |
| #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ |
| #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ |
| #define ADC_CR2_JSWSTART_Pos (22U) |
| #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ |
| #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */ |
| #define ADC_CR2_EXTSEL_Pos (24U) |
| #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ |
| #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ |
| #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ |
| #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ |
| #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ |
| #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ |
| #define ADC_CR2_EXTEN_Pos (28U) |
| #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ |
| #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ |
| #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ |
| #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ |
| #define ADC_CR2_SWSTART_Pos (30U) |
| #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ |
| #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */ |
| |
| /****************** Bit definition for ADC_SMPR1 register *******************/ |
| #define ADC_SMPR1_SMP10_Pos (0U) |
| #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ |
| #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ |
| #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ |
| #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ |
| #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ |
| #define ADC_SMPR1_SMP11_Pos (3U) |
| #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ |
| #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ |
| #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ |
| #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ |
| #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ |
| #define ADC_SMPR1_SMP12_Pos (6U) |
| #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ |
| #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ |
| #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ |
| #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ |
| #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ |
| #define ADC_SMPR1_SMP13_Pos (9U) |
| #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ |
| #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ |
| #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ |
| #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ |
| #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ |
| #define ADC_SMPR1_SMP14_Pos (12U) |
| #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ |
| #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ |
| #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ |
| #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ |
| #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ |
| #define ADC_SMPR1_SMP15_Pos (15U) |
| #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ |
| #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ |
| #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ |
| #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ |
| #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ |
| #define ADC_SMPR1_SMP16_Pos (18U) |
| #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ |
| #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ |
| #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ |
| #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ |
| #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ |
| #define ADC_SMPR1_SMP17_Pos (21U) |
| #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ |
| #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ |
| #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ |
| #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ |
| #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ |
| #define ADC_SMPR1_SMP18_Pos (24U) |
| #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */ |
| #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ |
| #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */ |
| #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */ |
| #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */ |
| |
| /****************** Bit definition for ADC_SMPR2 register *******************/ |
| #define ADC_SMPR2_SMP0_Pos (0U) |
| #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ |
| #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ |
| #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ |
| #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ |
| #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ |
| #define ADC_SMPR2_SMP1_Pos (3U) |
| #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ |
| #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ |
| #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ |
| #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ |
| #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ |
| #define ADC_SMPR2_SMP2_Pos (6U) |
| #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ |
| #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ |
| #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ |
| #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ |
| #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ |
| #define ADC_SMPR2_SMP3_Pos (9U) |
| #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ |
| #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ |
| #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ |
| #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ |
| #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ |
| #define ADC_SMPR2_SMP4_Pos (12U) |
| #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ |
| #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ |
| #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ |
| #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ |
| #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ |
| #define ADC_SMPR2_SMP5_Pos (15U) |
| #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ |
| #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ |
| #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ |
| #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ |
| #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ |
| #define ADC_SMPR2_SMP6_Pos (18U) |
| #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ |
| #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ |
| #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ |
| #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ |
| #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ |
| #define ADC_SMPR2_SMP7_Pos (21U) |
| #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ |
| #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ |
| #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ |
| #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ |
| #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ |
| #define ADC_SMPR2_SMP8_Pos (24U) |
| #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ |
| #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ |
| #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ |
| #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ |
| #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ |
| #define ADC_SMPR2_SMP9_Pos (27U) |
| #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ |
| #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ |
| #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ |
| #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ |
| #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ |
| |
| /****************** Bit definition for ADC_JOFR1 register *******************/ |
| #define ADC_JOFR1_JOFFSET1_Pos (0U) |
| #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ |
| #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */ |
| |
| /****************** Bit definition for ADC_JOFR2 register *******************/ |
| #define ADC_JOFR2_JOFFSET2_Pos (0U) |
| #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ |
| #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */ |
| |
| /****************** Bit definition for ADC_JOFR3 register *******************/ |
| #define ADC_JOFR3_JOFFSET3_Pos (0U) |
| #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ |
| #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */ |
| |
| /****************** Bit definition for ADC_JOFR4 register *******************/ |
| #define ADC_JOFR4_JOFFSET4_Pos (0U) |
| #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ |
| #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */ |
| |
| /******************* Bit definition for ADC_HTR register ********************/ |
| #define ADC_HTR_HT_Pos (0U) |
| #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ |
| #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */ |
| |
| /******************* Bit definition for ADC_LTR register ********************/ |
| #define ADC_LTR_LT_Pos (0U) |
| #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ |
| #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */ |
| |
| /******************* Bit definition for ADC_SQR1 register *******************/ |
| #define ADC_SQR1_SQ13_Pos (0U) |
| #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ |
| #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ |
| #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ |
| #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ |
| #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ |
| #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ |
| #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ |
| #define ADC_SQR1_SQ14_Pos (5U) |
| #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ |
| #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ |
| #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ |
| #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ |
| #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ |
| #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ |
| #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ |
| #define ADC_SQR1_SQ15_Pos (10U) |
| #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ |
| #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ |
| #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ |
| #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ |
| #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ |
| #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ |
| #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ |
| #define ADC_SQR1_SQ16_Pos (15U) |
| #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ |
| #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ |
| #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ |
| #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ |
| #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ |
| #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ |
| #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ |
| #define ADC_SQR1_L_Pos (20U) |
| #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ |
| #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */ |
| #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ |
| #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ |
| #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ |
| #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ |
| |
| /******************* Bit definition for ADC_SQR2 register *******************/ |
| #define ADC_SQR2_SQ7_Pos (0U) |
| #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ |
| #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ |
| #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ |
| #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ |
| #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ |
| #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ |
| #define ADC_SQR2_SQ8_Pos (5U) |
| #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ |
| #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ |
| #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ |
| #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ |
| #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ |
| #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ |
| #define ADC_SQR2_SQ9_Pos (10U) |
| #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ |
| #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ |
| #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ |
| #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ |
| #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ |
| #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ |
| #define ADC_SQR2_SQ10_Pos (15U) |
| #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ |
| #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ |
| #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ |
| #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ |
| #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ |
| #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ |
| #define ADC_SQR2_SQ11_Pos (20U) |
| #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ |
| #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ |
| #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ |
| #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ |
| #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ |
| #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ |
| #define ADC_SQR2_SQ12_Pos (25U) |
| #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ |
| #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ |
| #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ |
| #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ |
| #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ |
| #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ |
| #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ |
| |
| /******************* Bit definition for ADC_SQR3 register *******************/ |
| #define ADC_SQR3_SQ1_Pos (0U) |
| #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ |
| #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ |
| #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ |
| #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ |
| #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ |
| #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ |
| #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ |
| #define ADC_SQR3_SQ2_Pos (5U) |
| #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ |
| #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ |
| #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ |
| #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ |
| #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ |
| #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ |
| #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ |
| #define ADC_SQR3_SQ3_Pos (10U) |
| #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ |
| #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ |
| #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ |
| #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ |
| #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ |
| #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ |
| #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ |
| #define ADC_SQR3_SQ4_Pos (15U) |
| #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ |
| #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ |
| #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ |
| #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ |
| #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ |
| #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ |
| #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ |
| #define ADC_SQR3_SQ5_Pos (20U) |
| #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ |
| #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ |
| #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ |
| #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ |
| #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ |
| #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ |
| #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ |
| #define ADC_SQR3_SQ6_Pos (25U) |
| #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ |
| #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ |
| #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ |
| #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ |
| #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ |
| #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ |
| #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ |
| |
| /******************* Bit definition for ADC_JSQR register *******************/ |
| #define ADC_JSQR_JSQ1_Pos (0U) |
| #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ |
| #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ |
| #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ |
| #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ |
| #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ |
| #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ |
| #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ |
| #define ADC_JSQR_JSQ2_Pos (5U) |
| #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ |
| #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ |
| #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ |
| #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ |
| #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ |
| #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ |
| #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ |
| #define ADC_JSQR_JSQ3_Pos (10U) |
| #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ |
| #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ |
| #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ |
| #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ |
| #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ |
| #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ |
| #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ |
| #define ADC_JSQR_JSQ4_Pos (15U) |
| #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ |
| #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ |
| #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ |
| #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ |
| #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ |
| #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ |
| #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ |
| #define ADC_JSQR_JL_Pos (20U) |
| #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ |
| #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */ |
| #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ |
| #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ |
| |
| /******************* Bit definition for ADC_JDR1 register *******************/ |
| #define ADC_JDR1_JDATA_Pos (0U) |
| #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */ |
| |
| /******************* Bit definition for ADC_JDR2 register *******************/ |
| #define ADC_JDR2_JDATA_Pos (0U) |
| #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */ |
| |
| /******************* Bit definition for ADC_JDR3 register *******************/ |
| #define ADC_JDR3_JDATA_Pos (0U) |
| #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */ |
| |
| /******************* Bit definition for ADC_JDR4 register *******************/ |
| #define ADC_JDR4_JDATA_Pos (0U) |
| #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */ |
| |
| /******************** Bit definition for ADC_DR register ********************/ |
| #define ADC_DR_DATA_Pos (0U) |
| #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */ |
| #define ADC_DR_ADC2DATA_Pos (16U) |
| #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ |
| #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */ |
| |
| /******************* Bit definition for ADC_CSR register ********************/ |
| #define ADC_CSR_AWD1_Pos (0U) |
| #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ |
| #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */ |
| #define ADC_CSR_EOC1_Pos (1U) |
| #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */ |
| #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */ |
| #define ADC_CSR_JEOC1_Pos (2U) |
| #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */ |
| #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */ |
| #define ADC_CSR_JSTRT1_Pos (3U) |
| #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ |
| #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */ |
| #define ADC_CSR_STRT1_Pos (4U) |
| #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ |
| #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */ |
| #define ADC_CSR_OVR1_Pos (5U) |
| #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ |
| #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */ |
| |
| /* Legacy defines */ |
| #define ADC_CSR_DOVR1 ADC_CSR_OVR1 |
| |
| /******************* Bit definition for ADC_CCR register ********************/ |
| #define ADC_CCR_MULTI_Pos (0U) |
| #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */ |
| #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ |
| #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */ |
| #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */ |
| #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */ |
| #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */ |
| #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */ |
| #define ADC_CCR_DELAY_Pos (8U) |
| #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ |
| #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ |
| #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ |
| #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ |
| #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ |
| #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ |
| #define ADC_CCR_DDS_Pos (13U) |
| #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */ |
| #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */ |
| #define ADC_CCR_DMA_Pos (14U) |
| #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */ |
| #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ |
| #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */ |
| #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */ |
| #define ADC_CCR_ADCPRE_Pos (16U) |
| #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ |
| #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */ |
| #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ |
| #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ |
| #define ADC_CCR_VBATE_Pos (22U) |
| #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */ |
| #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */ |
| #define ADC_CCR_TSVREFE_Pos (23U) |
| #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ |
| #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */ |
| |
| /******************* Bit definition for ADC_CDR register ********************/ |
| #define ADC_CDR_DATA1_Pos (0U) |
| #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */ |
| #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */ |
| #define ADC_CDR_DATA2_Pos (16U) |
| #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */ |
| #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */ |
| |
| /* Legacy defines */ |
| #define ADC_CDR_RDATA_MST ADC_CDR_DATA1 |
| #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2 |
| |
| /******************************************************************************/ |
| /* */ |
| /* CRC calculation unit */ |
| /* */ |
| /******************************************************************************/ |
| /******************* Bit definition for CRC_DR register *********************/ |
| #define CRC_DR_DR_Pos (0U) |
| #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ |
| #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ |
| |
| |
| /******************* Bit definition for CRC_IDR register ********************/ |
| #define CRC_IDR_IDR_Pos (0U) |
| #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ |
| #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ |
| |
| |
| /******************** Bit definition for CRC_CR register ********************/ |
| #define CRC_CR_RESET_Pos (0U) |
| #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ |
| #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ |
| |
| |
| /******************************************************************************/ |
| /* */ |
| /* DMA Controller */ |
| /* */ |
| /******************************************************************************/ |
| /******************** Bits definition for DMA_SxCR register *****************/ |
| #define DMA_SxCR_CHSEL_Pos (25U) |
| #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */ |
| #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk |
| #define DMA_SxCR_CHSEL_0 0x02000000U |
| #define DMA_SxCR_CHSEL_1 0x04000000U |
| #define DMA_SxCR_CHSEL_2 0x08000000U |
| #define DMA_SxCR_MBURST_Pos (23U) |
| #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */ |
| #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk |
| #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */ |
| #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */ |
| #define DMA_SxCR_PBURST_Pos (21U) |
| #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */ |
| #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk |
| #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ |
| #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ |
| #define DMA_SxCR_CT_Pos (19U) |
| #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ |
| #define DMA_SxCR_CT DMA_SxCR_CT_Msk |
| #define DMA_SxCR_DBM_Pos (18U) |
| #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */ |
| #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk |
| #define DMA_SxCR_PL_Pos (16U) |
| #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */ |
| #define DMA_SxCR_PL DMA_SxCR_PL_Msk |
| #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */ |
| #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */ |
| #define DMA_SxCR_PINCOS_Pos (15U) |
| #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */ |
| #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk |
| #define DMA_SxCR_MSIZE_Pos (13U) |
| #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */ |
| #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk |
| #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */ |
| #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */ |
| #define DMA_SxCR_PSIZE_Pos (11U) |
| #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */ |
| #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk |
| #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */ |
| #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */ |
| #define DMA_SxCR_MINC_Pos (10U) |
| #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */ |
| #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk |
| #define DMA_SxCR_PINC_Pos (9U) |
| #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */ |
| #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk |
| #define DMA_SxCR_CIRC_Pos (8U) |
| #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */ |
| #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk |
| #define DMA_SxCR_DIR_Pos (6U) |
| #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */ |
| #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk |
| #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */ |
| #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */ |
| #define DMA_SxCR_PFCTRL_Pos (5U) |
| #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */ |
| #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk |
| #define DMA_SxCR_TCIE_Pos (4U) |
| #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */ |
| #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk |
| #define DMA_SxCR_HTIE_Pos (3U) |
| #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */ |
| #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk |
| #define DMA_SxCR_TEIE_Pos (2U) |
| #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */ |
| #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk |
| #define DMA_SxCR_DMEIE_Pos (1U) |
| #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */ |
| #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk |
| #define DMA_SxCR_EN_Pos (0U) |
| #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */ |
| #define DMA_SxCR_EN DMA_SxCR_EN_Msk |
| |
| /* Legacy defines */ |
| #define DMA_SxCR_ACK_Pos (20U) |
| #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ |
| #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk |
| |
| /******************** Bits definition for DMA_SxCNDTR register **************/ |
| #define DMA_SxNDT_Pos (0U) |
| #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */ |
| #define DMA_SxNDT DMA_SxNDT_Msk |
| #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */ |
| #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */ |
| #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */ |
| #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */ |
| #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */ |
| #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */ |
| #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */ |
| #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */ |
| #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */ |
| #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */ |
| #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */ |
| #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */ |
| #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */ |
| #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */ |
| #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */ |
| #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */ |
| |
| /******************** Bits definition for DMA_SxFCR register ****************/ |
| #define DMA_SxFCR_FEIE_Pos (7U) |
| #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */ |
| #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk |
| #define DMA_SxFCR_FS_Pos (3U) |
| #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */ |
| #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk |
| #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */ |
| #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */ |
| #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */ |
| #define DMA_SxFCR_DMDIS_Pos (2U) |
| #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */ |
| #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk |
| #define DMA_SxFCR_FTH_Pos (0U) |
| #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */ |
| #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk |
| #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */ |
| #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */ |
| |
| /******************** Bits definition for DMA_LISR register *****************/ |
| #define DMA_LISR_TCIF3_Pos (27U) |
| #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */ |
| #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk |
| #define DMA_LISR_HTIF3_Pos (26U) |
| #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */ |
| #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk |
| #define DMA_LISR_TEIF3_Pos (25U) |
| #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */ |
| #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk |
| #define DMA_LISR_DMEIF3_Pos (24U) |
| #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */ |
| #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk |
| #define DMA_LISR_FEIF3_Pos (22U) |
| #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */ |
| #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk |
| #define DMA_LISR_TCIF2_Pos (21U) |
| #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */ |
| #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk |
| #define DMA_LISR_HTIF2_Pos (20U) |
| #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */ |
| #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk |
| #define DMA_LISR_TEIF2_Pos (19U) |
| #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */ |
| #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk |
| #define DMA_LISR_DMEIF2_Pos (18U) |
| #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */ |
| #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk |
| #define DMA_LISR_FEIF2_Pos (16U) |
| #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */ |
| #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk |
| #define DMA_LISR_TCIF1_Pos (11U) |
| #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */ |
| #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk |
| #define DMA_LISR_HTIF1_Pos (10U) |
| #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */ |
| #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk |
| #define DMA_LISR_TEIF1_Pos (9U) |
| #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */ |
| #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk |
| #define DMA_LISR_DMEIF1_Pos (8U) |
| #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */ |
| #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk |
| #define DMA_LISR_FEIF1_Pos (6U) |
| #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */ |
| #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk |
| #define DMA_LISR_TCIF0_Pos (5U) |
| #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */ |
| #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk |
| #define DMA_LISR_HTIF0_Pos (4U) |
| #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */ |
| #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk |
| #define DMA_LISR_TEIF0_Pos (3U) |
| #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */ |
| #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk |
| #define DMA_LISR_DMEIF0_Pos (2U) |
| #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */ |
| #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk |
| #define DMA_LISR_FEIF0_Pos (0U) |
| #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */ |
| #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk |
| |
| /******************** Bits definition for DMA_HISR register *****************/ |
| #define DMA_HISR_TCIF7_Pos (27U) |
| #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */ |
| #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk |
| #define DMA_HISR_HTIF7_Pos (26U) |
| #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */ |
| #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk |
| #define DMA_HISR_TEIF7_Pos (25U) |
| #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */ |
| #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk |
| #define DMA_HISR_DMEIF7_Pos (24U) |
| #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */ |
| #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk |
| #define DMA_HISR_FEIF7_Pos (22U) |
| #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */ |
| #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk |
| #define DMA_HISR_TCIF6_Pos (21U) |
| #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */ |
| #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk |
| #define DMA_HISR_HTIF6_Pos (20U) |
| #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */ |
| #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk |
| #define DMA_HISR_TEIF6_Pos (19U) |
| #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */ |
| #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk |
| #define DMA_HISR_DMEIF6_Pos (18U) |
| #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */ |
| #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk |
| #define DMA_HISR_FEIF6_Pos (16U) |
| #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */ |
| #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk |
| #define DMA_HISR_TCIF5_Pos (11U) |
| #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ |
| #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk |
| #define DMA_HISR_HTIF5_Pos (10U) |
| #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */ |
| #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk |
| #define DMA_HISR_TEIF5_Pos (9U) |
| #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */ |
| #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk |
| #define DMA_HISR_DMEIF5_Pos (8U) |
| #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */ |
| #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk |
| #define DMA_HISR_FEIF5_Pos (6U) |
| #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */ |
| #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk |
| #define DMA_HISR_TCIF4_Pos (5U) |
| #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */ |
| #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk |
| #define DMA_HISR_HTIF4_Pos (4U) |
| #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */ |
| #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk |
| #define DMA_HISR_TEIF4_Pos (3U) |
| #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */ |
| #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk |
| #define DMA_HISR_DMEIF4_Pos (2U) |
| #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */ |
| #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk |
| #define DMA_HISR_FEIF4_Pos (0U) |
| #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */ |
| #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk |
| |
| /******************** Bits definition for DMA_LIFCR register ****************/ |
| #define DMA_LIFCR_CTCIF3_Pos (27U) |
| #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */ |
| #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk |
| #define DMA_LIFCR_CHTIF3_Pos (26U) |
| #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */ |
| #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk |
| #define DMA_LIFCR_CTEIF3_Pos (25U) |
| #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */ |
| #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk |
| #define DMA_LIFCR_CDMEIF3_Pos (24U) |
| #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */ |
| #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk |
| #define DMA_LIFCR_CFEIF3_Pos (22U) |
| #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */ |
| #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk |
| #define DMA_LIFCR_CTCIF2_Pos (21U) |
| #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */ |
| #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk |
| #define DMA_LIFCR_CHTIF2_Pos (20U) |
| #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */ |
| #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk |
| #define DMA_LIFCR_CTEIF2_Pos (19U) |
| #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */ |
| #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk |
| #define DMA_LIFCR_CDMEIF2_Pos (18U) |
| #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */ |
| #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk |
| #define DMA_LIFCR_CFEIF2_Pos (16U) |
| #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */ |
| #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk |
| #define DMA_LIFCR_CTCIF1_Pos (11U) |
| #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */ |
| #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk |
| #define DMA_LIFCR_CHTIF1_Pos (10U) |
| #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */ |
| #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk |
| #define DMA_LIFCR_CTEIF1_Pos (9U) |
| #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */ |
| #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk |
| #define DMA_LIFCR_CDMEIF1_Pos (8U) |
| #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */ |
| #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk |
| #define DMA_LIFCR_CFEIF1_Pos (6U) |
| #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */ |
| #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk |
| #define DMA_LIFCR_CTCIF0_Pos (5U) |
| #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */ |
| #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk |
| #define DMA_LIFCR_CHTIF0_Pos (4U) |
| #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */ |
| #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk |
| #define DMA_LIFCR_CTEIF0_Pos (3U) |
| #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */ |
| #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk |
| #define DMA_LIFCR_CDMEIF0_Pos (2U) |
| #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */ |
| #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk |
| #define DMA_LIFCR_CFEIF0_Pos (0U) |
| #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */ |
| #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk |
| |
| /******************** Bits definition for DMA_HIFCR register ****************/ |
| #define DMA_HIFCR_CTCIF7_Pos (27U) |
| #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */ |
| #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk |
| #define DMA_HIFCR_CHTIF7_Pos (26U) |
| #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */ |
| #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk |
| #define DMA_HIFCR_CTEIF7_Pos (25U) |
| #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */ |
| #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk |
| #define DMA_HIFCR_CDMEIF7_Pos (24U) |
| #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */ |
| #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk |
| #define DMA_HIFCR_CFEIF7_Pos (22U) |
| #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */ |
| #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk |
| #define DMA_HIFCR_CTCIF6_Pos (21U) |
| #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */ |
| #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk |
| #define DMA_HIFCR_CHTIF6_Pos (20U) |
| #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */ |
| #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk |
| #define DMA_HIFCR_CTEIF6_Pos (19U) |
| #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */ |
| #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk |
| #define DMA_HIFCR_CDMEIF6_Pos (18U) |
| #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */ |
| #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk |
| #define DMA_HIFCR_CFEIF6_Pos (16U) |
| #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */ |
| #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk |
| #define DMA_HIFCR_CTCIF5_Pos (11U) |
| #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */ |
| #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk |
| #define DMA_HIFCR_CHTIF5_Pos (10U) |
| #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */ |
| #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk |
| #define DMA_HIFCR_CTEIF5_Pos (9U) |
| #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */ |
| #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk |
| #define DMA_HIFCR_CDMEIF5_Pos (8U) |
| #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */ |
| #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk |
| #define DMA_HIFCR_CFEIF5_Pos (6U) |
| #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */ |
| #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk |
| #define DMA_HIFCR_CTCIF4_Pos (5U) |
| #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */ |
| #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk |
| #define DMA_HIFCR_CHTIF4_Pos (4U) |
| #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */ |
| #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk |
| #define DMA_HIFCR_CTEIF4_Pos (3U) |
| #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */ |
| #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk |
| #define DMA_HIFCR_CDMEIF4_Pos (2U) |
| #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */ |
| #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk |
| #define DMA_HIFCR_CFEIF4_Pos (0U) |
| #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */ |
| #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk |
| |
| /****************** Bit definition for DMA_SxPAR register ********************/ |
| #define DMA_SxPAR_PA_Pos (0U) |
| #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */ |
| #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */ |
| |
| /****************** Bit definition for DMA_SxM0AR register ********************/ |
| #define DMA_SxM0AR_M0A_Pos (0U) |
| #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */ |
| #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */ |
| |
| /****************** Bit definition for DMA_SxM1AR register ********************/ |
| #define DMA_SxM1AR_M1A_Pos (0U) |
| #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */ |
| #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */ |
| |
| |
| /******************************************************************************/ |
| /* */ |
| /* External Interrupt/Event Controller */ |
| /* */ |
| /******************************************************************************/ |
| /******************* Bit definition for EXTI_IMR register *******************/ |
| #define EXTI_IMR_MR0_Pos (0U) |
| #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ |
| #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ |
| #define EXTI_IMR_MR1_Pos (1U) |
| #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ |
| #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ |
| #define EXTI_IMR_MR2_Pos (2U) |
| #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ |
| #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ |
| #define EXTI_IMR_MR3_Pos (3U) |
| #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ |
| #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ |
| #define EXTI_IMR_MR4_Pos (4U) |
| #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ |
| #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ |
| #define EXTI_IMR_MR5_Pos (5U) |
| #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ |
| #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ |
| #define EXTI_IMR_MR6_Pos (6U) |
| #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ |
| #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ |
| #define EXTI_IMR_MR7_Pos (7U) |
| #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ |
| #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ |
| #define EXTI_IMR_MR8_Pos (8U) |
| #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ |
| #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ |
| #define EXTI_IMR_MR9_Pos (9U) |
| #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ |
| #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ |
| #define EXTI_IMR_MR10_Pos (10U) |
| #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ |
| #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ |
| #define EXTI_IMR_MR11_Pos (11U) |
| #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ |
| #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ |
| #define EXTI_IMR_MR12_Pos (12U) |
| #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ |
| #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ |
| #define EXTI_IMR_MR13_Pos (13U) |
| #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ |
| #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ |
| #define EXTI_IMR_MR14_Pos (14U) |
| #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ |
| #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ |
| #define EXTI_IMR_MR15_Pos (15U) |
| #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ |
| #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ |
| #define EXTI_IMR_MR16_Pos (16U) |
| #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ |
| #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ |
| #define EXTI_IMR_MR17_Pos (17U) |
| #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ |
| #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ |
| #define EXTI_IMR_MR18_Pos (18U) |
| #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ |
| #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ |
| #define EXTI_IMR_MR19_Pos (19U) |
| #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ |
| #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ |
| #define EXTI_IMR_MR20_Pos (20U) |
| #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ |
| #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ |
| #define EXTI_IMR_MR21_Pos (21U) |
| #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ |
| #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ |
| #define EXTI_IMR_MR22_Pos (22U) |
| #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ |
| #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ |
| |
| /* Reference Defines */ |
| #define EXTI_IMR_IM0 EXTI_IMR_MR0 |
| #define EXTI_IMR_IM1 EXTI_IMR_MR1 |
| #define EXTI_IMR_IM2 EXTI_IMR_MR2 |
| #define EXTI_IMR_IM3 EXTI_IMR_MR3 |
| #define EXTI_IMR_IM4 EXTI_IMR_MR4 |
| #define EXTI_IMR_IM5 EXTI_IMR_MR5 |
| #define EXTI_IMR_IM6 EXTI_IMR_MR6 |
| #define EXTI_IMR_IM7 EXTI_IMR_MR7 |
| #define EXTI_IMR_IM8 EXTI_IMR_MR8 |
| #define EXTI_IMR_IM9 EXTI_IMR_MR9 |
| #define EXTI_IMR_IM10 EXTI_IMR_MR10 |
| #define EXTI_IMR_IM11 EXTI_IMR_MR11 |
| #define EXTI_IMR_IM12 EXTI_IMR_MR12 |
| #define EXTI_IMR_IM13 EXTI_IMR_MR13 |
| #define EXTI_IMR_IM14 EXTI_IMR_MR14 |
| #define EXTI_IMR_IM15 EXTI_IMR_MR15 |
| #define EXTI_IMR_IM16 EXTI_IMR_MR16 |
| #define EXTI_IMR_IM17 EXTI_IMR_MR17 |
| #define EXTI_IMR_IM18 EXTI_IMR_MR18 |
| #define EXTI_IMR_IM19 EXTI_IMR_MR19 |
| #define EXTI_IMR_IM20 EXTI_IMR_MR20 |
| #define EXTI_IMR_IM21 EXTI_IMR_MR21 |
| #define EXTI_IMR_IM22 EXTI_IMR_MR22 |
| #define EXTI_IMR_IM_Pos (0U) |
| #define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */ |
| #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ |
| |
| /******************* Bit definition for EXTI_EMR register *******************/ |
| #define EXTI_EMR_MR0_Pos (0U) |
| #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ |
| #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ |
| #define EXTI_EMR_MR1_Pos (1U) |
| #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ |
| #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ |
| #define EXTI_EMR_MR2_Pos (2U) |
| #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ |
| #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ |
| #define EXTI_EMR_MR3_Pos (3U) |
| #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ |
| #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ |
| #define EXTI_EMR_MR4_Pos (4U) |
| #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ |
| #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ |
| #define EXTI_EMR_MR5_Pos (5U) |
| #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ |
| #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ |
| #define EXTI_EMR_MR6_Pos (6U) |
| #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ |
| #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ |
| #define EXTI_EMR_MR7_Pos (7U) |
| #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ |
| #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ |
| #define EXTI_EMR_MR8_Pos (8U) |
| #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ |
| #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ |
| #define EXTI_EMR_MR9_Pos (9U) |
| #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ |
| #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ |
| #define EXTI_EMR_MR10_Pos (10U) |
| #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ |
| #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ |
| #define EXTI_EMR_MR11_Pos (11U) |
| #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ |
| #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ |
| #define EXTI_EMR_MR12_Pos (12U) |
| #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ |
| #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ |
| #define EXTI_EMR_MR13_Pos (13U) |
| #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ |
| #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ |
| #define EXTI_EMR_MR14_Pos (14U) |
| #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ |
| #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ |
| #define EXTI_EMR_MR15_Pos (15U) |
| #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ |
| #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ |
| #define EXTI_EMR_MR16_Pos (16U) |
| #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ |
| #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ |
| #define EXTI_EMR_MR17_Pos (17U) |
| #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ |
| #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ |
| #define EXTI_EMR_MR18_Pos (18U) |
| #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ |
| #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ |
| #define EXTI_EMR_MR19_Pos (19U) |
| #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ |
| #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ |
| #define EXTI_EMR_MR20_Pos (20U) |
| #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ |
| #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ |
| #define EXTI_EMR_MR21_Pos (21U) |
| #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ |
| #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ |
| #define EXTI_EMR_MR22_Pos (22U) |
| #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ |
| #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ |
| |
| /* Reference Defines */ |
| #define EXTI_EMR_EM0 EXTI_EMR_MR0 |
| #define EXTI_EMR_EM1 EXTI_EMR_MR1 |
| #define EXTI_EMR_EM2 EXTI_EMR_MR2 |
| #define EXTI_EMR_EM3 EXTI_EMR_MR3 |
| #define EXTI_EMR_EM4 EXTI_EMR_MR4 |
| #define EXTI_EMR_EM5 EXTI_EMR_MR5 |
| #define EXTI_EMR_EM6 EXTI_EMR_MR6 |
| #define EXTI_EMR_EM7 EXTI_EMR_MR7 |
| #define EXTI_EMR_EM8 EXTI_EMR_MR8 |
| #define EXTI_EMR_EM9 EXTI_EMR_MR9 |
| #define EXTI_EMR_EM10 EXTI_EMR_MR10 |
| #define EXTI_EMR_EM11 EXTI_EMR_MR11 |
| #define EXTI_EMR_EM12 EXTI_EMR_MR12 |
| #define EXTI_EMR_EM13 EXTI_EMR_MR13 |
| #define EXTI_EMR_EM14 EXTI_EMR_MR14 |
| #define EXTI_EMR_EM15 EXTI_EMR_MR15 |
| #define EXTI_EMR_EM16 EXTI_EMR_MR16 |
| #define EXTI_EMR_EM17 EXTI_EMR_MR17 |
| #define EXTI_EMR_EM18 EXTI_EMR_MR18 |
| #define EXTI_EMR_EM19 EXTI_EMR_MR19 |
| #define EXTI_EMR_EM20 EXTI_EMR_MR20 |
| #define EXTI_EMR_EM21 EXTI_EMR_MR21 |
| #define EXTI_EMR_EM22 EXTI_EMR_MR22 |
| |
| /****************** Bit definition for EXTI_RTSR register *******************/ |
| #define EXTI_RTSR_TR0_Pos (0U) |
| #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ |
| #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ |
| #define EXTI_RTSR_TR1_Pos (1U) |
| #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ |
| #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ |
| #define EXTI_RTSR_TR2_Pos (2U) |
| #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ |
| #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ |
| #define EXTI_RTSR_TR3_Pos (3U) |
| #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ |
| #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ |
| #define EXTI_RTSR_TR4_Pos (4U) |
| #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ |
| #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ |
| #define EXTI_RTSR_TR5_Pos (5U) |
| #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ |
| #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ |
| #define EXTI_RTSR_TR6_Pos (6U) |
| #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ |
| #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ |
| #define EXTI_RTSR_TR7_Pos (7U) |
| #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ |
| #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ |
| #define EXTI_RTSR_TR8_Pos (8U) |
| #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ |
| #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ |
| #define EXTI_RTSR_TR9_Pos (9U) |
| #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ |
| #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ |
| #define EXTI_RTSR_TR10_Pos (10U) |
| #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ |
| #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ |
| #define EXTI_RTSR_TR11_Pos (11U) |
| #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ |
| #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ |
| #define EXTI_RTSR_TR12_Pos (12U) |
| #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ |
| #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ |
| #define EXTI_RTSR_TR13_Pos (13U) |
| #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ |
| #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ |
| #define EXTI_RTSR_TR14_Pos (14U) |
| #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ |
| #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ |
| #define EXTI_RTSR_TR15_Pos (15U) |
| #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ |
| #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ |
| #define EXTI_RTSR_TR16_Pos (16U) |
| #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ |
| #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ |
| #define EXTI_RTSR_TR17_Pos (17U) |
| #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ |
| #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ |
| #define EXTI_RTSR_TR18_Pos (18U) |
| #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ |
| #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ |
| #define EXTI_RTSR_TR19_Pos (19U) |
| #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ |
| #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ |
| #define EXTI_RTSR_TR20_Pos (20U) |
| #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ |
| #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ |
| #define EXTI_RTSR_TR21_Pos (21U) |
| #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ |
| #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ |
| #define EXTI_RTSR_TR22_Pos (22U) |
| #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ |
| #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ |
| |
| /****************** Bit definition for EXTI_FTSR register *******************/ |
| #define EXTI_FTSR_TR0_Pos (0U) |
| #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ |
| #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ |
| #define EXTI_FTSR_TR1_Pos (1U) |
| #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ |
| #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ |
| #define EXTI_FTSR_TR2_Pos (2U) |
| #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ |
| #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ |
| #define EXTI_FTSR_TR3_Pos (3U) |
| #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ |
| #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ |
| #define EXTI_FTSR_TR4_Pos (4U) |
| #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ |
| #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ |
| #define EXTI_FTSR_TR5_Pos (5U) |
| #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ |
| #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ |
| #define EXTI_FTSR_TR6_Pos (6U) |
| #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ |
| #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ |
| #define EXTI_FTSR_TR7_Pos (7U) |
| #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ |
| #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ |
| #define EXTI_FTSR_TR8_Pos (8U) |
| #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ |
| #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ |
| #define EXTI_FTSR_TR9_Pos (9U) |
| #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ |
| #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ |
| #define EXTI_FTSR_TR10_Pos (10U) |
| #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ |
| #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ |
| #define EXTI_FTSR_TR11_Pos (11U) |
| #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ |
| #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ |
| #define EXTI_FTSR_TR12_Pos (12U) |
| #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ |
| #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ |
| #define EXTI_FTSR_TR13_Pos (13U) |
| #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ |
| #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ |
| #define EXTI_FTSR_TR14_Pos (14U) |
| #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ |
| #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ |
| #define EXTI_FTSR_TR15_Pos (15U) |
| #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ |
| #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ |
| #define EXTI_FTSR_TR16_Pos (16U) |
| #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ |
| #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ |
| #define EXTI_FTSR_TR17_Pos (17U) |
| #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ |
| #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ |
| #define EXTI_FTSR_TR18_Pos (18U) |
| #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ |
| #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ |
| #define EXTI_FTSR_TR19_Pos (19U) |
| #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ |
| #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ |
| #define EXTI_FTSR_TR20_Pos (20U) |
| #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ |
| #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ |
| #define EXTI_FTSR_TR21_Pos (21U) |
| #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ |
| #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ |
| #define EXTI_FTSR_TR22_Pos (22U) |
| #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ |
| #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ |
| |
| /****************** Bit definition for EXTI_SWIER register ******************/ |
| #define EXTI_SWIER_SWIER0_Pos (0U) |
| #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ |
| #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ |
| #define EXTI_SWIER_SWIER1_Pos (1U) |
| #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ |
| #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ |
| #define EXTI_SWIER_SWIER2_Pos (2U) |
| #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ |
| #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ |
| #define EXTI_SWIER_SWIER3_Pos (3U) |
| #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ |
| #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ |
| #define EXTI_SWIER_SWIER4_Pos (4U) |
| #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ |
| #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ |
| #define EXTI_SWIER_SWIER5_Pos (5U) |
| #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ |
| #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ |
| #define EXTI_SWIER_SWIER6_Pos (6U) |
| #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ |
| #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ |
| #define EXTI_SWIER_SWIER7_Pos (7U) |
| #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ |
| #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ |
| #define EXTI_SWIER_SWIER8_Pos (8U) |
| #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ |
| #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ |
| #define EXTI_SWIER_SWIER9_Pos (9U) |
| #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ |
| #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ |
| #define EXTI_SWIER_SWIER10_Pos (10U) |
| #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ |
| #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ |
| #define EXTI_SWIER_SWIER11_Pos (11U) |
| #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ |
| #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ |
| #define EXTI_SWIER_SWIER12_Pos (12U) |
| #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ |
| #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ |
| #define EXTI_SWIER_SWIER13_Pos (13U) |
| #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ |
| #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ |
| #define EXTI_SWIER_SWIER14_Pos (14U) |
| #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ |
| #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ |
| #define EXTI_SWIER_SWIER15_Pos (15U) |
| #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ |
| #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ |
| #define EXTI_SWIER_SWIER16_Pos (16U) |
| #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ |
| #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ |
| #define EXTI_SWIER_SWIER17_Pos (17U) |
| #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ |
| #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ |
| #define EXTI_SWIER_SWIER18_Pos (18U) |
| #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ |
| #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ |
| #define EXTI_SWIER_SWIER19_Pos (19U) |
| #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ |
| #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ |
| #define EXTI_SWIER_SWIER20_Pos (20U) |
| #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ |
| #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ |
| #define EXTI_SWIER_SWIER21_Pos (21U) |
| #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ |
| #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ |
| #define EXTI_SWIER_SWIER22_Pos (22U) |
| #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ |
| #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ |
| |
| /******************* Bit definition for EXTI_PR register ********************/ |
| #define EXTI_PR_PR0_Pos (0U) |
| #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ |
| #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ |
| #define EXTI_PR_PR1_Pos (1U) |
| #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ |
| #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ |
| #define EXTI_PR_PR2_Pos (2U) |
| #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ |
| #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ |
| #define EXTI_PR_PR3_Pos (3U) |
| #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ |
| #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ |
| #define EXTI_PR_PR4_Pos (4U) |
| #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ |
| #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ |
| #define EXTI_PR_PR5_Pos (5U) |
| #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ |
| #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ |
| #define EXTI_PR_PR6_Pos (6U) |
| #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ |
| #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ |
| #define EXTI_PR_PR7_Pos (7U) |
| #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ |
| #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ |
| #define EXTI_PR_PR8_Pos (8U) |
| #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ |
| #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ |
| #define EXTI_PR_PR9_Pos (9U) |
| #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ |
| #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ |
| #define EXTI_PR_PR10_Pos (10U) |
| #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ |
| #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ |
| #define EXTI_PR_PR11_Pos (11U) |
| #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ |
| #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ |
| #define EXTI_PR_PR12_Pos (12U) |
| #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ |
| #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ |
| #define EXTI_PR_PR13_Pos (13U) |
| #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ |
| #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ |
| #define EXTI_PR_PR14_Pos (14U) |
| #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ |
| #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ |
| #define EXTI_PR_PR15_Pos (15U) |
| #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ |
| #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ |
| #define EXTI_PR_PR16_Pos (16U) |
| #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ |
| #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ |
| #define EXTI_PR_PR17_Pos (17U) |
| #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ |
| #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ |
| #define EXTI_PR_PR18_Pos (18U) |
| #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ |
| #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ |
| #define EXTI_PR_PR19_Pos (19U) |
| #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ |
| #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ |
| #define EXTI_PR_PR20_Pos (20U) |
| #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ |
| #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ |
| #define EXTI_PR_PR21_Pos (21U) |
| #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ |
| #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ |
| #define EXTI_PR_PR22_Pos (22U) |
| #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ |
| #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* FLASH */ |
| /* */ |
| /******************************************************************************/ |
| /******************* Bits definition for FLASH_ACR register *****************/ |
| #define FLASH_ACR_LATENCY_Pos (0U) |
| #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ |
| #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk |
| #define FLASH_ACR_LATENCY_0WS 0x00000000U |
| #define FLASH_ACR_LATENCY_1WS 0x00000001U |
| #define FLASH_ACR_LATENCY_2WS 0x00000002U |
| #define FLASH_ACR_LATENCY_3WS 0x00000003U |
| #define FLASH_ACR_LATENCY_4WS 0x00000004U |
| #define FLASH_ACR_LATENCY_5WS 0x00000005U |
| #define FLASH_ACR_LATENCY_6WS 0x00000006U |
| #define FLASH_ACR_LATENCY_7WS 0x00000007U |
| |
| |
| #define FLASH_ACR_PRFTEN_Pos (8U) |
| #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ |
| #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk |
| #define FLASH_ACR_ICEN_Pos (9U) |
| #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ |
| #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk |
| #define FLASH_ACR_DCEN_Pos (10U) |
| #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ |
| #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk |
| #define FLASH_ACR_ICRST_Pos (11U) |
| #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ |
| #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk |
| #define FLASH_ACR_DCRST_Pos (12U) |
| #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ |
| #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk |
| #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U) |
| #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */ |
| #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk |
| #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U) |
| #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */ |
| #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk |
| |
| /******************* Bits definition for FLASH_SR register ******************/ |
| #define FLASH_SR_EOP_Pos (0U) |
| #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ |
| #define FLASH_SR_EOP FLASH_SR_EOP_Msk |
| #define FLASH_SR_SOP_Pos (1U) |
| #define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos) /*!< 0x00000002 */ |
| #define FLASH_SR_SOP FLASH_SR_SOP_Msk |
| #define FLASH_SR_WRPERR_Pos (4U) |
| #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ |
| #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk |
| #define FLASH_SR_PGAERR_Pos (5U) |
| #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ |
| #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk |
| #define FLASH_SR_PGPERR_Pos (6U) |
| #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */ |
| #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk |
| #define FLASH_SR_PGSERR_Pos (7U) |
| #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ |
| #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk |
| #define FLASH_SR_RDERR_Pos (8U) |
| #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */ |
| #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk |
| #define FLASH_SR_BSY_Pos (16U) |
| #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ |
| #define FLASH_SR_BSY FLASH_SR_BSY_Msk |
| |
| /******************* Bits definition for FLASH_CR register ******************/ |
| #define FLASH_CR_PG_Pos (0U) |
| #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ |
| #define FLASH_CR_PG FLASH_CR_PG_Msk |
| #define FLASH_CR_SER_Pos (1U) |
| #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000002 */ |
| #define FLASH_CR_SER FLASH_CR_SER_Msk |
| #define FLASH_CR_MER_Pos (2U) |
| #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ |
| #define FLASH_CR_MER FLASH_CR_MER_Msk |
| #define FLASH_CR_SNB_Pos (3U) |
| #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */ |
| #define FLASH_CR_SNB FLASH_CR_SNB_Msk |
| #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000008 */ |
| #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000010 */ |
| #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000020 */ |
| #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ |
| #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ |
| #define FLASH_CR_PSIZE_Pos (8U) |
| #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */ |
| #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk |
| #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */ |
| #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */ |
| #define FLASH_CR_STRT_Pos (16U) |
| #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ |
| #define FLASH_CR_STRT FLASH_CR_STRT_Msk |
| #define FLASH_CR_EOPIE_Pos (24U) |
| #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ |
| #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk |
| #define FLASH_CR_ERRIE_Pos (25U) |
| #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) |
| #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk |
| #define FLASH_CR_LOCK_Pos (31U) |
| #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ |
| #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk |
| |
| /******************* Bits definition for FLASH_OPTCR register ***************/ |
| #define FLASH_OPTCR_OPTLOCK_Pos (0U) |
| #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ |
| #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk |
| #define FLASH_OPTCR_OPTSTRT_Pos (1U) |
| #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ |
| #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk |
| |
| #define FLASH_OPTCR_BOR_LEV_0 0x00000004U |
| #define FLASH_OPTCR_BOR_LEV_1 0x00000008U |
| #define FLASH_OPTCR_BOR_LEV_Pos (2U) |
| #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */ |
| #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk |
| #define FLASH_OPTCR_WDG_SW_Pos (5U) |
| #define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */ |
| #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk |
| #define FLASH_OPTCR_nRST_STOP_Pos (6U) |
| #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */ |
| #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk |
| #define FLASH_OPTCR_nRST_STDBY_Pos (7U) |
| #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */ |
| #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk |
| #define FLASH_OPTCR_RDP_Pos (8U) |
| #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */ |
| #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk |
| #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */ |
| #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */ |
| #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */ |
| #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */ |
| #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */ |
| #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */ |
| #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */ |
| #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */ |
| #define FLASH_OPTCR_nWRP_Pos (16U) |
| #define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */ |
| #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk |
| #define FLASH_OPTCR_nWRP_0 0x00010000U |
| #define FLASH_OPTCR_nWRP_1 0x00020000U |
| #define FLASH_OPTCR_nWRP_2 0x00040000U |
| #define FLASH_OPTCR_nWRP_3 0x00080000U |
| #define FLASH_OPTCR_nWRP_4 0x00100000U |
| #define FLASH_OPTCR_nWRP_5 0x00200000U |
| #define FLASH_OPTCR_nWRP_6 0x00400000U |
| #define FLASH_OPTCR_nWRP_7 0x00800000U |
| #define FLASH_OPTCR_nWRP_8 0x01000000U |
| #define FLASH_OPTCR_nWRP_9 0x02000000U |
| #define FLASH_OPTCR_nWRP_10 0x04000000U |
| #define FLASH_OPTCR_nWRP_11 0x08000000U |
| |
| /****************** Bits definition for FLASH_OPTCR1 register ***************/ |
| #define FLASH_OPTCR1_nWRP_Pos (16U) |
| #define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */ |
| #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk |
| #define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */ |
| #define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */ |
| #define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */ |
| #define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */ |
| #define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */ |
| #define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */ |
| #define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */ |
| #define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */ |
| #define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */ |
| #define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */ |
| #define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */ |
| #define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* General Purpose I/O */ |
| /* */ |
| /******************************************************************************/ |
| /****************** Bits definition for GPIO_MODER register *****************/ |
| #define GPIO_MODER_MODER0_Pos (0U) |
| #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ |
| #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk |
| #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ |
| #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ |
| #define GPIO_MODER_MODER1_Pos (2U) |
| #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ |
| #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk |
| #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ |
| #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ |
| #define GPIO_MODER_MODER2_Pos (4U) |
| #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ |
| #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk |
| #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ |
| #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ |
| #define GPIO_MODER_MODER3_Pos (6U) |
| #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ |
| #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk |
| #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ |
| #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ |
| #define GPIO_MODER_MODER4_Pos (8U) |
| #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ |
| #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk |
| #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ |
| #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ |
| #define GPIO_MODER_MODER5_Pos (10U) |
| #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ |
| #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk |
| #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ |
| #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ |
| #define GPIO_MODER_MODER6_Pos (12U) |
| #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ |
| #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk |
| #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ |
| #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ |
| #define GPIO_MODER_MODER7_Pos (14U) |
| #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ |
| #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk |
| #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ |
| #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ |
| #define GPIO_MODER_MODER8_Pos (16U) |
| #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ |
| #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk |
| #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ |
| #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ |
| #define GPIO_MODER_MODER9_Pos (18U) |
| #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ |
| #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk |
| #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ |
| #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ |
| #define GPIO_MODER_MODER10_Pos (20U) |
| #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ |
| #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk |
| #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ |
| #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ |
| #define GPIO_MODER_MODER11_Pos (22U) |
| #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ |
| #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk |
| #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ |
| #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ |
| #define GPIO_MODER_MODER12_Pos (24U) |
| #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ |
| #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk |
| #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ |
| #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ |
| #define GPIO_MODER_MODER13_Pos (26U) |
| #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ |
| #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk |
| #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ |
| #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ |
| #define GPIO_MODER_MODER14_Pos (28U) |
| #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ |
| #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk |
| #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ |
| #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ |
| #define GPIO_MODER_MODER15_Pos (30U) |
| #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ |
| #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk |
| #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ |
| #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ |
| |
| /* Legacy defines */ |
|