[CMSIS] Add missing SYSCFG_CFGR2_PVDL bit definition in STM32F412xx CMSIS headers
diff --git a/Include/stm32f412cx.h b/Include/stm32f412cx.h index bd7e265..5be3e10 100644 --- a/Include/stm32f412cx.h +++ b/Include/stm32f412cx.h
@@ -10687,7 +10687,7 @@ #define SYSCFG_CMPCR_READY_Pos (8U) #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */ #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */ -/****************** Bit definition for SYSCFG_CFGR register ****************/ +/****************** Bit definition for SYSCFG_CFGR register *****************/ #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U) #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */ #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */ @@ -10695,6 +10695,13 @@ #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */ #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */ +/****************** Bit definition for SYSCFG_CFGR2 register *****************/ +#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) +#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ +#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */ +#define SYSCFG_CFGR2_PVD_LOCK_Pos (2U) +#define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */ +#define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */ /******************************************************************************/ /* */
diff --git a/Include/stm32f412rx.h b/Include/stm32f412rx.h index 6e39916..47bb6ca 100644 --- a/Include/stm32f412rx.h +++ b/Include/stm32f412rx.h
@@ -11652,7 +11652,7 @@ #define SYSCFG_CMPCR_READY_Pos (8U) #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */ #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */ -/****************** Bit definition for SYSCFG_CFGR register ****************/ +/****************** Bit definition for SYSCFG_CFGR register *****************/ #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U) #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */ #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */ @@ -11660,6 +11660,13 @@ #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */ #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */ +/****************** Bit definition for SYSCFG_CFGR2 register *****************/ +#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) +#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ +#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */ +#define SYSCFG_CFGR2_PVD_LOCK_Pos (2U) +#define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */ +#define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */ /******************************************************************************/ /* */
diff --git a/Include/stm32f412vx.h b/Include/stm32f412vx.h index d41fe03..5b9324e 100644 --- a/Include/stm32f412vx.h +++ b/Include/stm32f412vx.h
@@ -11663,7 +11663,7 @@ #define SYSCFG_CMPCR_READY_Pos (8U) #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */ #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */ -/****************** Bit definition for SYSCFG_CFGR register ****************/ +/****************** Bit definition for SYSCFG_CFGR register *****************/ #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U) #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */ #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */ @@ -11671,6 +11671,13 @@ #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */ #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */ +/****************** Bit definition for SYSCFG_CFGR2 register *****************/ +#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) +#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ +#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */ +#define SYSCFG_CFGR2_PVD_LOCK_Pos (2U) +#define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */ +#define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */ /******************************************************************************/ /* */
diff --git a/Include/stm32f412zx.h b/Include/stm32f412zx.h index d47cda7..55e2750 100644 --- a/Include/stm32f412zx.h +++ b/Include/stm32f412zx.h
@@ -11685,7 +11685,7 @@ #define SYSCFG_CMPCR_READY_Pos (8U) #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */ #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */ -/****************** Bit definition for SYSCFG_CFGR register ****************/ +/****************** Bit definition for SYSCFG_CFGR register *****************/ #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U) #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */ #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */ @@ -11693,6 +11693,13 @@ #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */ #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */ +/****************** Bit definition for SYSCFG_CFGR2 register *****************/ +#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) +#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ +#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!<Core Lockup lock */ +#define SYSCFG_CFGR2_PVD_LOCK_Pos (2U) +#define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */ +#define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!<PVD Lock */ /******************************************************************************/ /* */