Release v1.4.4
diff --git a/Include/stm32g030xx.h b/Include/stm32g030xx.h index af20715..2d51ab5 100644 --- a/Include/stm32g030xx.h +++ b/Include/stm32g030xx.h
@@ -4045,6 +4045,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g031xx.h b/Include/stm32g031xx.h index 62f929b..941f888 100644 --- a/Include/stm32g031xx.h +++ b/Include/stm32g031xx.h
@@ -4225,6 +4225,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g041xx.h b/Include/stm32g041xx.h index d8ede70..23ce34d 100644 --- a/Include/stm32g041xx.h +++ b/Include/stm32g041xx.h
@@ -4461,6 +4461,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g050xx.h b/Include/stm32g050xx.h index 53490b7..2013094 100644 --- a/Include/stm32g050xx.h +++ b/Include/stm32g050xx.h
@@ -4064,6 +4064,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g051xx.h b/Include/stm32g051xx.h index dd3e7c9..dbf1d63 100644 --- a/Include/stm32g051xx.h +++ b/Include/stm32g051xx.h
@@ -4561,6 +4561,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g061xx.h b/Include/stm32g061xx.h index 4738a94..6e79739 100644 --- a/Include/stm32g061xx.h +++ b/Include/stm32g061xx.h
@@ -4797,6 +4797,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g070xx.h b/Include/stm32g070xx.h index 702c42a..2d79b25 100644 --- a/Include/stm32g070xx.h +++ b/Include/stm32g070xx.h
@@ -4193,6 +4193,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g071xx.h b/Include/stm32g071xx.h index b8b11b3..1ba7186 100644 --- a/Include/stm32g071xx.h +++ b/Include/stm32g071xx.h
@@ -4896,6 +4896,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g081xx.h b/Include/stm32g081xx.h index d6ebdd4..a552e1b 100644 --- a/Include/stm32g081xx.h +++ b/Include/stm32g081xx.h
@@ -5132,6 +5132,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g0b0xx.h b/Include/stm32g0b0xx.h index 0d609c0..c693338 100644 --- a/Include/stm32g0b0xx.h +++ b/Include/stm32g0b0xx.h
@@ -5165,6 +5165,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g0b1xx.h b/Include/stm32g0b1xx.h index 36e2cba..b97b009 100644 --- a/Include/stm32g0b1xx.h +++ b/Include/stm32g0b1xx.h
@@ -6146,6 +6146,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g0c1xx.h b/Include/stm32g0c1xx.h index 8ebf0a7..2c36f00 100644 --- a/Include/stm32g0c1xx.h +++ b/Include/stm32g0c1xx.h
@@ -6382,6 +6382,12 @@ #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_SWS_HSISYS (0x00000000UL) /*!< HSISYS used as system clock */ +#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */ +#define RCC_CFGR_SWS_PLLRCLK (0x00000010UL) /*!< PLLRCLK used as system clock */ +#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */ +#define RCC_CFGR_SWS_LSE (0x00000100UL) /*!< LSE used as system clock */ + /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
diff --git a/Include/stm32g0xx.h b/Include/stm32g0xx.h index 1749bdf..b10d5cf 100644 --- a/Include/stm32g0xx.h +++ b/Include/stm32g0xx.h
@@ -90,7 +90,7 @@ */ #define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ -#define __STM32G0_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ +#define __STM32G0_CMSIS_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ #define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\ |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
diff --git a/Release_Notes.html b/Release_Notes.html index 017db0e..f27e809 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
@@ -45,11 +45,14 @@ <div class="col-sm-12 col-lg-8"> <h1 id="update-history">Update History</h1> <div class="collapse"> -<input type="checkbox" id="collapse-section8" checked aria-hidden="true"> <label for="collapse-section8" area-hidden="true">V1.4.3 / 10-June-2022 </label> +<input type="checkbox" id="collapse-section9" checked aria-hidden="true"> <label for="collapse-section9" area-hidden="true">V1.4.4 / 15-December-2023 </label> <div> <h2 id="main-changes">Main Changes</h2> <ul> -<li>README.md update: Remove compatibility table from “Compatibility information” section.</li> +<li>Update USB RXBD count mask.</li> +<li>Add RCC_CFGR_SWS_HSE, HSI, PLL, LSI, LSE system clock definitions.</li> +<li>Update to support USB supply enable feature for STM32G0B0 devices.</li> +<li>Fix the location of .size directive in STM32CubeIDE’s startup code to allow proper size information of vector table.</li> </ul> <h2 id="contents">Contents</h2> <ul> @@ -65,20 +68,11 @@ </div> </div> <div class="collapse"> -<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" area-hidden="true">V1.4.2 / 01-April-2022 </label> +<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" area-hidden="true">V1.4.3 / 10-June-2023 </label> <div> <h2 id="main-changes-1">Main Changes</h2> <ul> -<li>Rename ADC TRx registers AWDxTR to be compliant with the reference manual.</li> -<li>Fix Doxygen grouping issues.</li> -<li>Update IRQ handler enumeration structure to be aligned with template CMSIS device.h file defined by ARM. -<ul> -<li>Rename SVC_IRQn to SVCall_IRQn:</li> -</ul></li> -<li>Add the following aliases for IRQ number definition to ensure compatibility across STM32 Series; -<ul> -<li>#define SVC_IRQn SVCall_IRQn</li> -</ul></li> +<li>README.md update: Remove compatibility table from “Compatibility information” section.</li> </ul> <h2 id="contents-1">Contents</h2> <ul> @@ -94,19 +88,19 @@ </div> </div> <div class="collapse"> -<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" area-hidden="true">V1.4.1 / 17-June-2021 </label> +<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" area-hidden="true">V1.4.2 / 01-April-2022 </label> <div> <h2 id="main-changes-2">Main Changes</h2> <ul> -<li>Update to remove wrong bits defined for DMAMUX Req ID.</li> -<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.</li> -<li>Add new atomic register access macros in stm32g0xx.h file.</li> -<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li> -<li>Update Licensing information and format +<li>Rename ADC TRx registers AWDxTR to be compliant with the reference manual.</li> +<li>Fix Doxygen grouping issues.</li> +<li>Update IRQ handler enumeration structure to be aligned with template CMSIS device.h file defined by ARM. <ul> -<li>Add LICENSE.txt file</li> -<li>Remove License message from Release_Notes.html</li> -<li>Update header files with new license format</li> +<li>Rename SVC_IRQn to SVCall_IRQn:</li> +</ul></li> +<li>Add the following aliases for IRQ number definition to ensure compatibility across STM32 Series; +<ul> +<li>#define SVC_IRQn SVCall_IRQn</li> </ul></li> </ul> <h2 id="contents-2">Contents</h2> @@ -123,9 +117,38 @@ </div> </div> <div class="collapse"> -<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" area-hidden="true">V1.4.0 / 29-October-2020 </label> +<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" area-hidden="true">V1.4.1 / 17-June-2021 </label> <div> <h2 id="main-changes-3">Main Changes</h2> +<ul> +<li>Update to remove wrong bits defined for DMAMUX Req ID.</li> +<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.</li> +<li>Add new atomic register access macros in stm32g0xx.h file.</li> +<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li> +<li>Update Licensing information and format +<ul> +<li>Add LICENSE.txt file</li> +<li>Remove License message from Release_Notes.html</li> +<li>Update header files with new license format</li> +</ul></li> +</ul> +<h2 id="contents-3">Contents</h2> +<ul> +<li>CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.</li> +<li>CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.</li> +<li>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</li> +<li>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</li> +</ul> +<h2 id="known-limitations-3">Known Limitations</h2> +<ul> +<li>None</li> +</ul> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" area-hidden="true">V1.4.0 / 29-October-2020 </label> +<div> +<h2 id="main-changes-4">Main Changes</h2> <h3 id="maintenance-release-and-product-update">Maintenance release and Product Update</h3> <p>Official release for STM32G0xx CMSIS introducing <strong>stm32g0b0xx, stm32g0b1xx, stm32g0c1xx devices</strong> and <strong>stm32g050xx, stm32g051xx, stm32g061xx devices.</strong></p> <p>Maintenance release for STM32G0xx CMSIS supporting stm32g030xx, stm32g031xx, stm32g041xx, stm32g070xx, stm32g071xx, stm32g081xx devices.</p> @@ -206,19 +229,19 @@ </tr> </tbody> </table> -<h2 id="contents-3">Contents</h2> +<h2 id="contents-4">Contents</h2> <p>-<strong>CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.</strong></p> <p>-<strong>CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.</strong></p> <p>-CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</p> <p>-CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p> -<h2 id="known-limitations-3">Known Limitations</h2> +<h2 id="known-limitations-4">Known Limitations</h2> <p>None</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.3.0 / 25-June-2019 </label> <div> -<h2 id="main-changes-4">Main Changes</h2> +<h2 id="main-changes-5">Main Changes</h2> <h3 id="maintenance-release">Maintenance release</h3> <p>Maintenance release for STM32G0xx CMSIS supporting stm32g030xx, stm32g031xx, stm32g041xx, stm32g070xx, stm32g071xx, stm32g081xx devices.</p> <p><strong>Fixed bugs list</strong></p> @@ -234,10 +257,10 @@ </tr> </tbody> </table> -<h2 id="contents-4">Contents</h2> +<h2 id="contents-5">Contents</h2> <p>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</p> <p>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p> -<h2 id="known-limitations-4">Known Limitations</h2> +<h2 id="known-limitations-5">Known Limitations</h2> <p><strong>Requirements not met or planned in a forthcoming release</strong></p> <table> <thead> @@ -267,7 +290,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 05-April-2019 </label> <div> -<h2 id="main-changes-5">Main Changes</h2> +<h2 id="main-changes-6">Main Changes</h2> <h3 id="maintenance-release-and-product-update-1">Maintenance release and Product Update</h3> <p>First release for STM32G0xx CMSIS introducing <strong>stm32g030xx, stm32g031xx, stm32g041xx</strong> devices.</p> <p><strong>Additional features</strong></p> @@ -299,10 +322,10 @@ </tr> </tbody> </table> -<h2 id="contents-5">Contents</h2> +<h2 id="contents-6">Contents</h2> <p>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</p> <p>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p> -<h2 id="known-limitations-5">Known Limitations</h2> +<h2 id="known-limitations-6">Known Limitations</h2> <p><strong>Requirements not met or planned in a forthcoming release</strong></p> <table> <thead> @@ -335,7 +358,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 06-February-2019 </label> <div> -<h2 id="main-changes-6">Main Changes</h2> +<h2 id="main-changes-7">Main Changes</h2> <h3 id="maintenance-release-1">Maintenance release</h3> <p>Maintenance release for <strong>STM32G0xx</strong> devices (stm32g070xx, stm32g071xx, stm32g081xx devices)</p> <p><strong>Fixed bugs list</strong></p> @@ -360,17 +383,17 @@ </tr> </tbody> </table> -<h2 id="contents-6">Contents</h2> +<h2 id="contents-7">Contents</h2> <p>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p> </div> </div> <div class="collapse"> <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"> V1.0.0 / 26-October-2018 </label> <div> -<h2 id="main-changes-7">Main Changes</h2> +<h2 id="main-changes-8">Main Changes</h2> <h3 id="first-release">First release</h3> <p>First official release for <strong>STM32G0xx</strong> devices</p> -<h2 id="contents-7">Contents</h2> +<h2 id="contents-8">Contents</h2> <ul> <li>CMSIS devices files for STM32G070xx, STM32G071xx and STM32G081xx</li> </ul>
diff --git a/Source/Templates/gcc/startup_stm32g030xx.s b/Source/Templates/gcc/startup_stm32g030xx.s index fd82f10..a168383 100644 --- a/Source/Templates/gcc/startup_stm32g030xx.s +++ b/Source/Templates/gcc/startup_stm32g030xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -177,6 +176,8 @@ .word USART2_IRQHandler /* USART2 */ .word 0 /* reserved */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g031xx.s b/Source/Templates/gcc/startup_stm32g031xx.s index 51c922b..473af2c 100644 --- a/Source/Templates/gcc/startup_stm32g031xx.s +++ b/Source/Templates/gcc/startup_stm32g031xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -178,6 +177,8 @@ .word LPUART1_IRQHandler /* LPUART1 */ .word 0 /* reserved */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g041xx.s b/Source/Templates/gcc/startup_stm32g041xx.s index af33433..dd8cb85 100644 --- a/Source/Templates/gcc/startup_stm32g041xx.s +++ b/Source/Templates/gcc/startup_stm32g041xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -179,6 +178,8 @@ .word 0 /* reserved */ .word AES_RNG_IRQHandler /* AES and RNG */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g050xx.s b/Source/Templates/gcc/startup_stm32g050xx.s index b117023..a73b8ea 100644 --- a/Source/Templates/gcc/startup_stm32g050xx.s +++ b/Source/Templates/gcc/startup_stm32g050xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -176,6 +175,8 @@ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g051xx.s b/Source/Templates/gcc/startup_stm32g051xx.s index 0247c61..1406f5e 100644 --- a/Source/Templates/gcc/startup_stm32g051xx.s +++ b/Source/Templates/gcc/startup_stm32g051xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -177,6 +176,8 @@ .word USART2_IRQHandler /* USART2 */ .word LPUART1_IRQHandler /* LPUART1 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g061xx.s b/Source/Templates/gcc/startup_stm32g061xx.s index 42f896b..e735253 100644 --- a/Source/Templates/gcc/startup_stm32g061xx.s +++ b/Source/Templates/gcc/startup_stm32g061xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -179,6 +178,8 @@ .word 0 /* reserved */ .word AES_RNG_IRQHandler /* AES and RNG */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g070xx.s b/Source/Templates/gcc/startup_stm32g070xx.s index 7dfdd84..83e6c3c 100644 --- a/Source/Templates/gcc/startup_stm32g070xx.s +++ b/Source/Templates/gcc/startup_stm32g070xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -177,6 +176,8 @@ .word USART2_IRQHandler /* USART2 */ .word USART3_4_IRQHandler /* USART3, USART4 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g071xx.s b/Source/Templates/gcc/startup_stm32g071xx.s index 5b4d4d8..ac01304 100644 --- a/Source/Templates/gcc/startup_stm32g071xx.s +++ b/Source/Templates/gcc/startup_stm32g071xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -178,6 +177,8 @@ .word USART3_4_LPUART1_IRQHandler /* USART3, USART4 and LPUART1 */ .word CEC_IRQHandler /* CEC */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g081xx.s b/Source/Templates/gcc/startup_stm32g081xx.s index e4ee41b..60f8caa 100644 --- a/Source/Templates/gcc/startup_stm32g081xx.s +++ b/Source/Templates/gcc/startup_stm32g081xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -179,6 +178,8 @@ .word CEC_IRQHandler /* CEC */ .word AES_RNG_IRQHandler /* AES and RNG */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g0b0xx.s b/Source/Templates/gcc/startup_stm32g0b0xx.s index a32177c..969d388 100644 --- a/Source/Templates/gcc/startup_stm32g0b0xx.s +++ b/Source/Templates/gcc/startup_stm32g0b0xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -177,6 +176,8 @@ .word USART2_IRQHandler /* USART2 */ .word USART3_4_5_6_IRQHandler /* USART3, USART4, USART5, USART6 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g0b1xx.s b/Source/Templates/gcc/startup_stm32g0b1xx.s index 7bf683a..88a1208 100644 --- a/Source/Templates/gcc/startup_stm32g0b1xx.s +++ b/Source/Templates/gcc/startup_stm32g0b1xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -178,6 +177,8 @@ .word USART3_4_5_6_LPUART1_IRQHandler /* USART3, USART4, USART5, USART6, LPUART1 */ .word CEC_IRQHandler /* CEC */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g0c1xx.s b/Source/Templates/gcc/startup_stm32g0c1xx.s index 0fd5896..6aaf18f 100644 --- a/Source/Templates/gcc/startup_stm32g0c1xx.s +++ b/Source/Templates/gcc/startup_stm32g0c1xx.s
@@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack @@ -179,6 +178,8 @@ .word CEC_IRQHandler /* CEC */ .word AES_RNG_IRQHandler /* AES and RNG */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.