Release v1.2.3
diff --git a/Include/stm32g431xx.h b/Include/stm32g431xx.h index 7be3c23..4d47482 100644 --- a/Include/stm32g431xx.h +++ b/Include/stm32g431xx.h
@@ -699,8 +699,7 @@ typedef struct { - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -1216,7 +1215,7 @@ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ @@ -1362,7 +1361,7 @@ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ @@ -4063,7 +4062,7 @@ /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */ /***************** Bit definition for FDCAN_DBTP register *******************/ #define FDCAN_DBTP_DSJW_Pos (0U) @@ -6372,7 +6371,7 @@ #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ #define OPAMP_CSR_OUTCAL_Pos (30U) #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ -#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ +#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ #define OPAMP_CSR_LOCK_Pos (31U) #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */ @@ -7225,7 +7224,7 @@ /* */ /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define RCC_HSI48_SUPPORT @@ -9050,19 +9049,6 @@ /* Serial Audio Interface */ /* */ /******************************************************************************/ -/******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) -#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ -#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ -#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ -#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ - -#define SAI_GCR_SYNCOUT_Pos (4U) -#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ -#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ -#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ -#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ - /******************* Bit definition for SAI_xCR1 register *******************/ #define SAI_xCR1_MODE_Pos (0U) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ @@ -9403,7 +9389,7 @@ /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */
diff --git a/Include/stm32g441xx.h b/Include/stm32g441xx.h index 5bc32fa..24ad9f7 100644 --- a/Include/stm32g441xx.h +++ b/Include/stm32g441xx.h
@@ -700,8 +700,7 @@ typedef struct { - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -1250,7 +1249,7 @@ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ @@ -1396,7 +1395,7 @@ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ @@ -4284,7 +4283,7 @@ /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */ /***************** Bit definition for FDCAN_DBTP register *******************/ #define FDCAN_DBTP_DSJW_Pos (0U) @@ -6593,7 +6592,7 @@ #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ #define OPAMP_CSR_OUTCAL_Pos (30U) #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ -#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ +#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ #define OPAMP_CSR_LOCK_Pos (31U) #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */ @@ -7446,7 +7445,7 @@ /* */ /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define RCC_HSI48_SUPPORT @@ -9280,19 +9279,6 @@ /* Serial Audio Interface */ /* */ /******************************************************************************/ -/******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) -#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ -#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ -#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ -#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ - -#define SAI_GCR_SYNCOUT_Pos (4U) -#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ -#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ -#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ -#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ - /******************* Bit definition for SAI_xCR1 register *******************/ #define SAI_xCR1_MODE_Pos (0U) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ @@ -9633,7 +9619,7 @@ /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */
diff --git a/Include/stm32g471xx.h b/Include/stm32g471xx.h index a9f3457..fef63a4 100644 --- a/Include/stm32g471xx.h +++ b/Include/stm32g471xx.h
@@ -757,8 +757,7 @@ typedef struct { - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -1307,7 +1306,7 @@ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ @@ -1453,7 +1452,7 @@ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ @@ -4245,7 +4244,7 @@ /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */ /***************** Bit definition for FDCAN_DBTP register *******************/ #define FDCAN_DBTP_DSJW_Pos (0U) @@ -6607,7 +6606,7 @@ #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ #define OPAMP_CSR_OUTCAL_Pos (30U) #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ -#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ +#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ #define OPAMP_CSR_LOCK_Pos (31U) #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */ @@ -7735,7 +7734,7 @@ /* */ /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define RCC_HSI48_SUPPORT @@ -9714,19 +9713,6 @@ /* Serial Audio Interface */ /* */ /******************************************************************************/ -/******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) -#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ -#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ -#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ -#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ - -#define SAI_GCR_SYNCOUT_Pos (4U) -#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ -#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ -#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ -#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ - /******************* Bit definition for SAI_xCR1 register *******************/ #define SAI_xCR1_MODE_Pos (0U) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ @@ -10067,7 +10053,7 @@ /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */
diff --git a/Include/stm32g473xx.h b/Include/stm32g473xx.h index 0b53c56..a79cde9 100644 --- a/Include/stm32g473xx.h +++ b/Include/stm32g473xx.h
@@ -796,8 +796,7 @@ typedef struct { - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -1385,7 +1384,7 @@ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ @@ -1531,7 +1530,7 @@ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ @@ -4380,7 +4379,7 @@ /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */ /***************** Bit definition for FDCAN_DBTP register *******************/ #define FDCAN_DBTP_DSJW_Pos (0U) @@ -5344,7 +5343,7 @@ /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */ #define FMC_BCR1_WFDIS_Pos (21U) #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */ #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */ @@ -7121,7 +7120,7 @@ #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ #define OPAMP_CSR_OUTCAL_Pos (30U) #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ -#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ +#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ #define OPAMP_CSR_LOCK_Pos (31U) #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */ @@ -8249,7 +8248,7 @@ /* */ /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define RCC_HSI48_SUPPORT @@ -10264,19 +10263,6 @@ /* Serial Audio Interface */ /* */ /******************************************************************************/ -/******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) -#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ -#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ -#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ -#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ - -#define SAI_GCR_SYNCOUT_Pos (4U) -#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ -#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ -#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ -#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ - /******************* Bit definition for SAI_xCR1 register *******************/ #define SAI_xCR1_MODE_Pos (0U) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ @@ -10617,7 +10603,7 @@ /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */
diff --git a/Include/stm32g474xx.h b/Include/stm32g474xx.h index e32fb9e..1899d0a 100644 --- a/Include/stm32g474xx.h +++ b/Include/stm32g474xx.h
@@ -804,8 +804,7 @@ typedef struct { - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -1026,7 +1025,7 @@ { __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ - __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */ + __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */ __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ @@ -1515,7 +1514,7 @@ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ @@ -1661,7 +1660,7 @@ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ @@ -4513,7 +4512,7 @@ /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */ /***************** Bit definition for FDCAN_DBTP register *******************/ #define FDCAN_DBTP_DSJW_Pos (0U) @@ -5477,7 +5476,7 @@ /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */ #define FMC_BCR1_WFDIS_Pos (21U) #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */ #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */ @@ -6949,7 +6948,7 @@ #define HRTIM_MCR_TFCEN HRTIM_MCR_TFCEN_Msk /*!< Timer F counter enable */ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_MCR_PREEN_Pos (27U) @@ -7166,7 +7165,7 @@ #define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -9079,7 +9078,7 @@ /**** Bit definition for Common HRTIM Timer Burst mode control register ********/ #define HRTIM_BMCR_BME_Pos (0U) #define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */ -#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */ +#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enable */ #define HRTIM_BMCR_BMOM_Pos (1U) #define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */ #define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */ @@ -10691,7 +10690,7 @@ #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ #define OPAMP_CSR_OUTCAL_Pos (30U) #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ -#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ +#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ #define OPAMP_CSR_LOCK_Pos (31U) #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */ @@ -11819,7 +11818,7 @@ /* */ /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define RCC_HSI48_SUPPORT @@ -13843,19 +13842,6 @@ /* Serial Audio Interface */ /* */ /******************************************************************************/ -/******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) -#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ -#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ -#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ -#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ - -#define SAI_GCR_SYNCOUT_Pos (4U) -#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ -#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ -#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ -#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ - /******************* Bit definition for SAI_xCR1 register *******************/ #define SAI_xCR1_MODE_Pos (0U) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ @@ -14196,7 +14182,7 @@ /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */
diff --git a/Include/stm32g483xx.h b/Include/stm32g483xx.h index 9300cf2..387008e 100644 --- a/Include/stm32g483xx.h +++ b/Include/stm32g483xx.h
@@ -797,8 +797,7 @@ typedef struct { - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -1419,7 +1418,7 @@ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ @@ -1565,7 +1564,7 @@ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ @@ -4601,7 +4600,7 @@ /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */ /***************** Bit definition for FDCAN_DBTP register *******************/ #define FDCAN_DBTP_DSJW_Pos (0U) @@ -5565,7 +5564,7 @@ /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */ #define FMC_BCR1_WFDIS_Pos (21U) #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */ #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */ @@ -7342,7 +7341,7 @@ #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ #define OPAMP_CSR_OUTCAL_Pos (30U) #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ -#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ +#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ #define OPAMP_CSR_LOCK_Pos (31U) #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */ @@ -8470,7 +8469,7 @@ /* */ /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define RCC_HSI48_SUPPORT @@ -10494,19 +10493,6 @@ /* Serial Audio Interface */ /* */ /******************************************************************************/ -/******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) -#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ -#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ -#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ -#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ - -#define SAI_GCR_SYNCOUT_Pos (4U) -#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ -#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ -#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ -#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ - /******************* Bit definition for SAI_xCR1 register *******************/ #define SAI_xCR1_MODE_Pos (0U) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ @@ -10847,7 +10833,7 @@ /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */
diff --git a/Include/stm32g484xx.h b/Include/stm32g484xx.h index 9687b01..905a640 100644 --- a/Include/stm32g484xx.h +++ b/Include/stm32g484xx.h
@@ -805,8 +805,7 @@ typedef struct { - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -1058,7 +1057,7 @@ { __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ - __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */ + __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */ __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ @@ -1549,7 +1548,7 @@ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ @@ -1695,7 +1694,7 @@ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ @@ -4734,7 +4733,7 @@ /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */ /***************** Bit definition for FDCAN_DBTP register *******************/ #define FDCAN_DBTP_DSJW_Pos (0U) @@ -5698,7 +5697,7 @@ /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */ #define FMC_BCR1_WFDIS_Pos (21U) #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */ #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */ @@ -7170,7 +7169,7 @@ #define HRTIM_MCR_TFCEN HRTIM_MCR_TFCEN_Msk /*!< Timer F counter enable */ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_MCR_PREEN_Pos (27U) @@ -7387,7 +7386,7 @@ #define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -9300,7 +9299,7 @@ /**** Bit definition for Common HRTIM Timer Burst mode control register ********/ #define HRTIM_BMCR_BME_Pos (0U) #define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */ -#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */ +#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enable */ #define HRTIM_BMCR_BMOM_Pos (1U) #define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */ #define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */ @@ -10912,7 +10911,7 @@ #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ #define OPAMP_CSR_OUTCAL_Pos (30U) #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ -#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ +#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ #define OPAMP_CSR_LOCK_Pos (31U) #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */ @@ -12040,7 +12039,7 @@ /* */ /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define RCC_HSI48_SUPPORT @@ -14073,19 +14072,6 @@ /* Serial Audio Interface */ /* */ /******************************************************************************/ -/******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) -#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ -#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ -#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ -#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ - -#define SAI_GCR_SYNCOUT_Pos (4U) -#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ -#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ -#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ -#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ - /******************* Bit definition for SAI_xCR1 register *******************/ #define SAI_xCR1_MODE_Pos (0U) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ @@ -14426,7 +14412,7 @@ /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */
diff --git a/Include/stm32g491xx.h b/Include/stm32g491xx.h index ca9874b..35889a9 100644 --- a/Include/stm32g491xx.h +++ b/Include/stm32g491xx.h
@@ -748,8 +748,7 @@ typedef struct { - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -1296,7 +1295,7 @@ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ @@ -1442,7 +1441,7 @@ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ @@ -4221,7 +4220,7 @@ /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */ /***************** Bit definition for FDCAN_DBTP register *******************/ #define FDCAN_DBTP_DSJW_Pos (0U) @@ -6536,7 +6535,7 @@ #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ #define OPAMP_CSR_OUTCAL_Pos (30U) #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ -#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ +#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ #define OPAMP_CSR_LOCK_Pos (31U) #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */ @@ -7586,7 +7585,7 @@ /* */ /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define RCC_HSI48_SUPPORT @@ -9542,19 +9541,6 @@ /* Serial Audio Interface */ /* */ /******************************************************************************/ -/******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) -#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ -#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ -#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ -#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ - -#define SAI_GCR_SYNCOUT_Pos (4U) -#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ -#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ -#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ -#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ - /******************* Bit definition for SAI_xCR1 register *******************/ #define SAI_xCR1_MODE_Pos (0U) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ @@ -9895,7 +9881,7 @@ /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -13694,8 +13680,12 @@ /******************************************************************************/ /* Aliases for __IRQn */ +#define TIM7_DAC_IRQn TIM7_IRQn +#define COMP4_5_6_IRQn COMP4_IRQn /* Aliases for __IRQHandler */ +#define TIM7_DAC_IRQHandler TIM7_IRQHandler +#define COMP4_5_6_IRQHandler COMP4_IRQHandler #ifdef __cplusplus }
diff --git a/Include/stm32g4a1xx.h b/Include/stm32g4a1xx.h index 2fb6e6f..ca49ede 100644 --- a/Include/stm32g4a1xx.h +++ b/Include/stm32g4a1xx.h
@@ -749,8 +749,7 @@ typedef struct { - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -1330,7 +1329,7 @@ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ @@ -1476,7 +1475,7 @@ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ @@ -4442,7 +4441,7 @@ /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */ /***************** Bit definition for FDCAN_DBTP register *******************/ #define FDCAN_DBTP_DSJW_Pos (0U) @@ -6757,7 +6756,7 @@ #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ #define OPAMP_CSR_OUTCAL_Pos (30U) #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ -#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ +#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ #define OPAMP_CSR_LOCK_Pos (31U) #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */ @@ -7807,7 +7806,7 @@ /* */ /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define RCC_HSI48_SUPPORT @@ -9772,19 +9771,6 @@ /* Serial Audio Interface */ /* */ /******************************************************************************/ -/******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) -#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ -#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ -#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ -#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ - -#define SAI_GCR_SYNCOUT_Pos (4U) -#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ -#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ -#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ -#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ - /******************* Bit definition for SAI_xCR1 register *******************/ #define SAI_xCR1_MODE_Pos (0U) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ @@ -10125,7 +10111,7 @@ /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */ @@ -13926,8 +13912,12 @@ /******************************************************************************/ /* Aliases for __IRQn */ +#define TIM7_DAC_IRQn TIM7_IRQn +#define COMP4_5_6_IRQn COMP4_IRQn /* Aliases for __IRQHandler */ +#define TIM7_DAC_IRQHandler TIM7_IRQHandler +#define COMP4_5_6_IRQHandler COMP4_IRQHandler #ifdef __cplusplus }
diff --git a/Include/stm32g4xx.h b/Include/stm32g4xx.h index 144aa60..55f8126 100644 --- a/Include/stm32g4xx.h +++ b/Include/stm32g4xx.h
@@ -84,11 +84,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.2.2 + * @brief CMSIS Device version number V1.2.3 */ #define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G4_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ -#define __STM32G4_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ +#define __STM32G4_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\ |(__STM32G4_CMSIS_VERSION_SUB1 << 16)\
diff --git a/Include/stm32gbk1cb.h b/Include/stm32gbk1cb.h index a9d8cf0..8b501cc 100644 --- a/Include/stm32gbk1cb.h +++ b/Include/stm32gbk1cb.h
@@ -698,8 +698,7 @@ typedef struct { - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; @@ -1202,7 +1201,7 @@ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ @@ -1348,7 +1347,7 @@ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ @@ -4049,7 +4048,7 @@ /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */ +#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */ /***************** Bit definition for FDCAN_DBTP register *******************/ #define FDCAN_DBTP_DSJW_Pos (0U) @@ -6358,7 +6357,7 @@ #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ #define OPAMP_CSR_OUTCAL_Pos (30U) #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ -#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ +#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */ #define OPAMP_CSR_LOCK_Pos (31U) #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */ @@ -7211,7 +7210,7 @@ /* */ /******************************************************************************/ /* -* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) +* @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define RCC_HSI48_SUPPORT @@ -9022,19 +9021,6 @@ /* Serial Audio Interface */ /* */ /******************************************************************************/ -/******************** Bit definition for SAI_GCR register *******************/ -#define SAI_GCR_SYNCIN_Pos (0U) -#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ -#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ -#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ -#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ - -#define SAI_GCR_SYNCOUT_Pos (4U) -#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ -#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ -#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ -#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ - /******************* Bit definition for SAI_xCR1 register *******************/ #define SAI_xCR1_MODE_Pos (0U) #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ @@ -9375,7 +9361,7 @@ /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define SPI_I2S_SUPPORT /*!< I2S support */
diff --git a/Release_Notes.html b/Release_Notes.html index 7ce5d11..bb000d3 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
@@ -11,24 +11,21 @@ span.underline{text-decoration: underline;} div.column{display: inline-block; vertical-align: top; width: 50%;} </style> - <link rel="stylesheet" href="_htmresc/mini-st.css" /> + <link rel="stylesheet" href="_htmresc/mini-st_2020.css" /> <!--[if lt IE 9]> <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script> <![endif]--> + <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" /> </head> <body> <div class="row"> <div class="col-sm-12 col-lg-4"> -<div class="card fluid"> -<div class="sectione dark"> <center> <h1 id="release-notes-for-stm32g4xx-cmsis"><small>Release Notes for</small> STM32G4xx CMSIS</h1> <p>Copyright © 2019 STMicroelectronics<br /> </p> -<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a> +<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a> </center> -</div> -</div> <h1 id="purpose">Purpose</h1> <p>This driver provides the CMSIS device for the stm32g4xx products. This covers following series :</p> <ul> @@ -41,14 +38,14 @@ <p>Various template file are provided to easily build an application. They can be adapted to fit applications requirements.</p> <ul> <li>Templates/system_stm32g4xx.c contains the initialization code referred as SystemInit.</li> -<li>Startup files are provided as example for IAR©, KEIL© and SW4STM32©.</li> -<li>Linker files are provided as example for IAR©, KEIL© and SW4STM32©.</li> +<li>Startup files are provided as example for IAR©, KEIL© and STM32CubeIDE©.</li> +<li>Linker files are provided as example for IAR©, KEIL© and STM32CubeIDE©.</li> </ul> </div> <div class="col-sm-12 col-lg-8"> <h1 id="update-history">Update History</h1> <div class="collapse"> -<input type="checkbox" id="collapse-section1_2_2" checked aria-hidden="true"> <label for="collapse-section1_2_2" aria-hidden="true">V1.2.2 / 10-November-2021</label> +<input type="checkbox" id="collapse-section1_2_3" checked aria-hidden="true"> <label for="collapse-section1_2_3" aria-hidden="true">V1.2.3 / 15-December-2023</label> <div> <h2 id="main-changes">Main Changes</h2> <h3 id="maintenance-release">Maintenance release</h3> @@ -57,6 +54,59 @@ </ul> <h2 id="contents">Contents</h2> <table> +<caption>Fixed bugs list<br /> +</caption> +<thead> +<tr class="header"> +<th>Headline</th> +</tr> +</thead> +<tbody> +<tr class="odd"> +<td>- Fix misalignment between reference manual and CMSIS driver: remove GCR register.</td> +</tr> +<tr class="even"> +<td>- Add missing __IRQn and __IRQHandler aliases, TIM7_DAC and COMP4_5_6 for STM32G491xx and STM32G4A1xx devices.</td> +</tr> +<tr class="odd"> +<td>- Update to call SystemInit first in startup/Reset_Handler, so GCC code is similar to IAR/Keil.</td> +</tr> +<tr class="even"> +<td>- Change the value of RAM end region in stm32g491xx IAR linker files.</td> +</tr> +<tr class="odd"> +<td>- Fix the location of .size directive in STM32CubeIDE’s startup code to allow proper size information of vector table.</td> +</tr> +</tbody> +</table> +<h2 id="known-limitations">Known Limitations</h2> +<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2> +<ul> +<li>IAR Embedded Workbench for ARM (EWARM) toolchain <strong>V8.50.9</strong> + ST-Link</li> +<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain <strong>V5.38</strong> + ST-Link</li> +<li>CubeIDE toolchain <strong>V1.14.0</strong></li> +</ul> +<h2 id="supported-devices-and-boards">Supported Devices and boards</h2> +<ul> +<li>STM32G431xx, STM32G441xx devices</li> +<li>STM32G471xx devices</li> +<li>STM32G473xx, STM32G483xx devices</li> +<li>STM32G474xx, STM32G484xx devices</li> +<li>STM32G491xx, STM32G4A1xx devices</li> +</ul> +<p>Note: in the section above, main changes are highlighted in <strong>bold</strong> since previous release.</p> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section1_2_2" aria-hidden="true"> <label for="collapse-section1_2_2" aria-hidden="true">V1.2.2 / 10-November-2021</label> +<div> +<h2 id="main-changes-1">Main Changes</h2> +<h3 id="maintenance-release-1">Maintenance release</h3> +<ul> +<li>General updates to fix known defects and enhancements implementation.</li> +</ul> +<h2 id="contents-1">Contents</h2> +<table> <caption>Additional features<br /> </caption> <thead> @@ -88,16 +138,14 @@ </tr> </tbody> </table> -<p>: Fixed bugs list<br /> -</p> -<h2 id="known-limitations">Known Limitations</h2> -<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2> +<h2 id="known-limitations-1">Known Limitations</h2> +<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2> <ul> <li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.4 + ST-Link</li> <li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 + ST-Link</li> <li>CubeIDE toolchain V1.6.0</li> </ul> -<h2 id="supported-devices-and-boards">Supported Devices and boards</h2> +<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2> <ul> <li>STM32G431xx, STM32G441xx devices</li> <li>STM32G471xx devices</li> @@ -111,12 +159,12 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1_2_1" aria-hidden="true"> <label for="collapse-section1_2_1" aria-hidden="true">V1.2.1 / 11-January-2021</label> <div> -<h2 id="main-changes-1">Main Changes</h2> -<h3 id="maintenance-release-1">Maintenance release</h3> +<h2 id="main-changes-2">Main Changes</h2> +<h3 id="maintenance-release-2">Maintenance release</h3> <ul> <li>General updates to fix known defects and enhancements implementation</li> </ul> -<h2 id="contents-1">Contents</h2> +<h2 id="contents-2">Contents</h2> <table> <caption>Additional features<br /> </caption> @@ -134,16 +182,14 @@ </tr> </tbody> </table> -<p>: Fixed bugs list<br /> -</p> -<h2 id="known-limitations-1">Known Limitations</h2> -<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2> +<h2 id="known-limitations-2">Known Limitations</h2> +<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2> <ul> <li>IAR Embedded Workbench for ARM (EWARM) toolchain <strong>V8.50.4</strong> + ST-Link</li> <li>RealView Microcontroller Development Kit (MDK-ARM) toolchain <strong>V5.31</strong> + ST-Link</li> <li>CubeIDE toolchain <strong>V1.6.0</strong></li> </ul> -<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2> +<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2> <ul> <li>STM32G431xx, STM32G441xx devices</li> <li>STM32G471xx devices</li> @@ -157,13 +203,13 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1_2_0" aria-hidden="true"> <label for="collapse-section1_2_0" aria-hidden="true">V1.2.0 / 26-June-2020</label> <div> -<h2 id="main-changes-2">Main Changes</h2> -<h3 id="maintenance-release-2">Maintenance release</h3> +<h2 id="main-changes-3">Main Changes</h2> +<h3 id="maintenance-release-3">Maintenance release</h3> <ul> <li>Add support for STM32G491xx and STM32G4A1 devices</li> <li>General updates to fix known defects and enhancements implementation</li> </ul> -<h2 id="contents-2">Contents</h2> +<h2 id="contents-3">Contents</h2> <table> <caption>Additional features<br /> </caption> @@ -187,16 +233,14 @@ </tr> </tbody> </table> -<p>: Fixed bugs list<br /> -</p> -<h2 id="known-limitations-2">Known Limitations</h2> -<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2> +<h2 id="known-limitations-3">Known Limitations</h2> +<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2> <ul> <li>IAR Embedded Workbench for ARM (EWARM) toolchain <strong>V8.40.1</strong></li> <li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li> <li>STM32CubeIDE toolchain V1.3.0</li> </ul> -<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2> +<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2> <ul> <li>STM32G431xx, STM32G441xx devices</li> <li>STM32G471xx devices</li> @@ -210,10 +254,10 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1_1_1" aria-hidden="true"> <label for="collapse-section1_1_1" aria-hidden="true">V1.1.1 / 14-February-2020</label> <div> -<h2 id="main-changes-3">Main Changes</h2> -<h3 id="maintenance-release-3">Maintenance release</h3> +<h2 id="main-changes-4">Main Changes</h2> +<h3 id="maintenance-release-4">Maintenance release</h3> <p>General updates to fix known defects and enhancements implementation</p> -<h2 id="contents-3">Contents</h2> +<h2 id="contents-4">Contents</h2> <table> <caption>Additional features<br /> </caption> @@ -238,21 +282,21 @@ </thead> <tbody> <tr class="odd"> -<td>Update STM32G473/483 startup files to support FDCAN2/3 intances</td> +<td>Update STM32G473/483 startup files to support FDCAN2/3 instances</td> </tr> <tr class="even"> <td>Remove IS_TIM_SYNCHRO_INSTANCE macro from device header files</td> </tr> </tbody> </table> -<h2 id="known-limitations-3">Known Limitations</h2> -<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2> +<h2 id="known-limitations-4">Known Limitations</h2> +<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2> <ul> <li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li> <li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li> <li>STM32CubeIDE toolchain V1.3.0</li> </ul> -<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2> +<h2 id="supported-devices-and-boards-4">Supported Devices and boards</h2> <ul> <li>STM32G431xx, STM32G441xx devices</li> <li>STM32G471xx devices</li> @@ -265,10 +309,10 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1_1_0" aria-hidden="true"> <label for="collapse-section1_1_0" aria-hidden="true">V1.1.0 / 28-June-2019</label> <div> -<h2 id="main-changes-4">Main Changes</h2> -<h3 id="maintenance-release-4">Maintenance release</h3> +<h2 id="main-changes-5">Main Changes</h2> +<h3 id="maintenance-release-5">Maintenance release</h3> <p>Maintenance release of CMSIS Devices drivers supporting STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, <strong>STM32G483xx</strong>, STM32G474xx and STM32G484xx devices</p> -<h2 id="contents-4">Contents</h2> +<h2 id="contents-5">Contents</h2> <table> <caption>Additional features<br /> </caption> @@ -309,14 +353,14 @@ </tr> </tbody> </table> -<h2 id="known-limitations-4">Known Limitations</h2> -<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2> +<h2 id="known-limitations-5">Known Limitations</h2> +<h2 id="development-toolchains-and-compilers-5">Development Toolchains and Compilers</h2> <ul> <li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li> <li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li> <li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li> </ul> -<h2 id="supported-devices-and-boards-4">Supported Devices and boards</h2> +<h2 id="supported-devices-and-boards-5">Supported Devices and boards</h2> <ul> <li>STM32G431xx, STM32G441xx devices</li> <li>STM32G471xx devices</li> @@ -329,12 +373,12 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1_0_0" aria-hidden="true"> <label for="collapse-section1_0_0" aria-hidden="true">V1.0.0 / 12-April-2019</label> <div> -<h2 id="main-changes-5">Main Changes</h2> +<h2 id="main-changes-6">Main Changes</h2> <h3 id="first-release">First release</h3> <p>First official release for STM32G4xx devices</p> -<h2 id="contents-5">Contents</h2> +<h2 id="contents-6">Contents</h2> <p>CMSIS devices files for STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, STM32G474xx and STM32G484xx.</p> -<h2 id="known-limitations-5">Known Limitations</h2> +<h2 id="known-limitations-6">Known Limitations</h2> <table> <thead> <tr class="header"> @@ -347,13 +391,13 @@ </tr> </tbody> </table> -<h2 id="development-toolchains-and-compilers-5">Development Toolchains and Compilers</h2> +<h2 id="development-toolchains-and-compilers-6">Development Toolchains and Compilers</h2> <ul> <li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li> <li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li> <li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li> </ul> -<h2 id="supported-devices-and-boards-5">Supported Devices and boards</h2> +<h2 id="supported-devices-and-boards-6">Supported Devices and boards</h2> <ul> <li>STM32G431xx, STM32G441xx devices</li> <li>STM32G471xx devices</li>
diff --git a/Source/Templates/gcc/startup_stm32g431xx.s b/Source/Templates/gcc/startup_stm32g431xx.s index 3397428..8c59237 100644 --- a/Source/Templates/gcc/startup_stm32g431xx.s +++ b/Source/Templates/gcc/startup_stm32g431xx.s
@@ -61,6 +61,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata @@ -92,9 +95,6 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +249,8 @@ .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g441xx.s b/Source/Templates/gcc/startup_stm32g441xx.s index 11c3af1..c15778c 100644 --- a/Source/Templates/gcc/startup_stm32g441xx.s +++ b/Source/Templates/gcc/startup_stm32g441xx.s
@@ -61,6 +61,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata @@ -93,8 +96,6 @@ cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g471xx.s b/Source/Templates/gcc/startup_stm32g471xx.s index b9aa6de..8dfaf51 100644 --- a/Source/Templates/gcc/startup_stm32g471xx.s +++ b/Source/Templates/gcc/startup_stm32g471xx.s
@@ -62,6 +62,9 @@ ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -93,8 +96,6 @@ cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g473xx.s b/Source/Templates/gcc/startup_stm32g473xx.s index 3d7d8d6..88b797f 100644 --- a/Source/Templates/gcc/startup_stm32g473xx.s +++ b/Source/Templates/gcc/startup_stm32g473xx.s
@@ -61,6 +61,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata @@ -93,8 +96,6 @@ cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g474xx.s b/Source/Templates/gcc/startup_stm32g474xx.s index a6add31..e7a2c61 100644 --- a/Source/Templates/gcc/startup_stm32g474xx.s +++ b/Source/Templates/gcc/startup_stm32g474xx.s
@@ -62,6 +62,9 @@ ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -93,8 +96,6 @@ cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g483xx.s b/Source/Templates/gcc/startup_stm32g483xx.s index 8690d34..ffae652 100644 --- a/Source/Templates/gcc/startup_stm32g483xx.s +++ b/Source/Templates/gcc/startup_stm32g483xx.s
@@ -62,6 +62,9 @@ ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -93,8 +96,7 @@ cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit + /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +129,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +251,8 @@ .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g484xx.s b/Source/Templates/gcc/startup_stm32g484xx.s index 9ec0f3c..f24aeb3 100644 --- a/Source/Templates/gcc/startup_stm32g484xx.s +++ b/Source/Templates/gcc/startup_stm32g484xx.s
@@ -61,6 +61,9 @@ ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -92,8 +95,6 @@ cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -126,7 +127,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -249,6 +249,8 @@ .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g491xx.s b/Source/Templates/gcc/startup_stm32g491xx.s index 9e3bf02..1a79404 100644 --- a/Source/Templates/gcc/startup_stm32g491xx.s +++ b/Source/Templates/gcc/startup_stm32g491xx.s
@@ -61,6 +61,9 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata @@ -93,8 +96,6 @@ cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32g4a1xx.s b/Source/Templates/gcc/startup_stm32g4a1xx.s index 163bf0b..2d565c5 100644 --- a/Source/Templates/gcc/startup_stm32g4a1xx.s +++ b/Source/Templates/gcc/startup_stm32g4a1xx.s
@@ -62,6 +62,9 @@ ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata @@ -93,8 +96,6 @@ cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -127,7 +128,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -250,6 +250,8 @@ .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32gbk1cb.s b/Source/Templates/gcc/startup_stm32gbk1cb.s index 778cb46..749f3e4 100644 --- a/Source/Templates/gcc/startup_stm32gbk1cb.s +++ b/Source/Templates/gcc/startup_stm32gbk1cb.s
@@ -60,6 +60,9 @@ .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 @@ -89,8 +92,7 @@ cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit + /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ @@ -123,7 +125,6 @@ ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: @@ -246,6 +247,8 @@ .word CORDIC_IRQHandler .word FMAC_IRQHandler + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/iar/linker/stm32g491xx_flash.icf b/Source/Templates/iar/linker/stm32g491xx_flash.icf index 4737115..23ca88e 100644 --- a/Source/Templates/iar/linker/stm32g491xx_flash.icf +++ b/Source/Templates/iar/linker/stm32g491xx_flash.icf
@@ -7,7 +7,7 @@ define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; define symbol __ICFEDIT_region_CCMSRAM_start__ = 0x10000000; define symbol __ICFEDIT_region_CCMSRAM_end__ = 0x10003FFF;
diff --git a/Source/Templates/iar/linker/stm32g491xx_sram.icf b/Source/Templates/iar/linker/stm32g491xx_sram.icf index 56b7381..9246b40 100644 --- a/Source/Templates/iar/linker/stm32g491xx_sram.icf +++ b/Source/Templates/iar/linker/stm32g491xx_sram.icf
@@ -7,7 +7,7 @@ define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; define symbol __ICFEDIT_region_ROM_end__ = 0x20009FFF; define symbol __ICFEDIT_region_RAM_start__ = 0x2000A000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; define symbol __ICFEDIT_region_CCMSRAM_start__ = 0x10000000; define symbol __ICFEDIT_region_CCMSRAM_end__ = 0x10003FFF;
diff --git a/_htmresc/favicon.png b/_htmresc/favicon.png new file mode 100644 index 0000000..06713ee --- /dev/null +++ b/_htmresc/favicon.png Binary files differ
diff --git a/_htmresc/mini-st.css b/_htmresc/mini-st_2020.css similarity index 77% rename from _htmresc/mini-st.css rename to _htmresc/mini-st_2020.css index 71fbc14..986f4d4 100644 --- a/_htmresc/mini-st.css +++ b/_htmresc/mini-st_2020.css
@@ -1,39 +1,39 @@ @charset "UTF-8"; /* - Flavor name: Default (mini-default) - Author: Angelos Chalaris (chalarangelo@gmail.com) - Maintainers: Angelos Chalaris - mini.css version: v3.0.0-alpha.3 + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 */ /* Browsers resets and base typography. */ /* Core module CSS variable definitions */ :root { - --fore-color: #111; - --secondary-fore-color: #444; - --back-color: #f8f8f8; - --secondary-back-color: #f0f0f0; - --blockquote-color: #f57c00; - --pre-color: #1565c0; - --border-color: #aaa; - --secondary-border-color: #ddd; - --heading-ratio: 1.19; + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; --universal-margin: 0.5rem; - --universal-padding: 0.125rem; - --universal-border-radius: 0.125rem; - --a-link-color: #0277bd; - --a-visited-color: #01579b; } + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } html { - font-size: 14px; } + font-size: 13.5px; } a, b, del, em, i, ins, q, span, strong, u { font-size: 1em; } html, * { - font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; - line-height: 1.4; + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; -webkit-text-size-adjust: 100%; } * { @@ -42,7 +42,10 @@ body { margin: 0; color: var(--fore-color); - background: var(--back-color); } + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } details { display: block; } @@ -62,9 +65,9 @@ height: auto; } h1, h2, h3, h4, h5, h6 { - line-height: 1.2; + line-height: 1.25; margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); - font-weight: 500; } + font-weight: 400; } h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { color: var(--secondary-fore-color); display: block; @@ -74,21 +77,15 @@ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } h2 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); - background: var(--mark-back-color); - font-weight: 600; - padding: 0.1em 0.5em 0.2em 0.5em; - color: var(--mark-fore-color); } - + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } h3 { - font-size: calc(1rem * var(--heading-ratio)); - padding-left: calc(2 * var(--universal-margin)); - /* background: var(--border-color); */ - } + font-size: calc(1rem * var(--heading-ratio) ); } h4 { - font-size: 1rem;); - padding-left: calc(4 * var(--universal-margin)); } + font-size: calc(1rem * var(--heading-ratio)); } h5 { font-size: 1rem; } @@ -101,7 +98,7 @@ ol, ul { margin: var(--universal-margin); - padding-left: calc(6 * var(--universal-margin)); } + padding-left: calc(3 * var(--universal-margin)); } b, strong { font-weight: 700; } @@ -111,7 +108,7 @@ border: 0; line-height: 1.25em; margin: var(--universal-margin); - height: 0.0625rem; + height: 0.0714285714rem; background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } blockquote { @@ -121,16 +118,16 @@ color: var(--secondary-fore-color); margin: var(--universal-margin); padding: calc(3 * var(--universal-padding)); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.375rem solid var(--blockquote-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } blockquote:before { position: absolute; top: calc(0rem - var(--universal-padding)); left: 0; font-family: sans-serif; - font-size: 3rem; - font-weight: 700; + font-size: 2rem; + font-weight: 800; content: "\201c"; color: var(--blockquote-color); } blockquote[cite]:after { @@ -160,8 +157,8 @@ background: var(--secondary-back-color); padding: calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.25rem solid var(--pre-color); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } sup, sub, code, kbd { @@ -204,7 +201,8 @@ box-sizing: border-box; display: flex; flex: 0 1 auto; - flex-flow: row wrap; } + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } .col-sm, [class^='col-sm-'], @@ -565,9 +563,9 @@ order: 999; } } /* Card component CSS variable definitions */ :root { - --card-back-color: #f8f8f8; - --card-fore-color: #111; - --card-border-color: #ddd; } + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } .card { display: flex; @@ -578,7 +576,7 @@ width: 100%; background: var(--card-back-color); color: var(--card-fore-color); - border: 0.0625rem solid var(--card-border-color); + border: 0.0714285714rem solid var(--card-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); overflow: hidden; } @@ -592,7 +590,7 @@ margin: 0; border: 0; border-radius: 0; - border-bottom: 0.0625rem solid var(--card-border-color); + border-bottom: 0.0714285714rem solid var(--card-border-color); padding: var(--universal-padding); width: 100%; } .card > .sectione.media { @@ -617,17 +615,18 @@ width: auto; } .card.warning { -/* --card-back-color: #ffca28; */ --card-back-color: #e5b8b7; - --card-border-color: #e8b825; } + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } .card.error { - --card-back-color: #b71c1c; - --card-fore-color: #f8f8f8; - --card-border-color: #a71a1a; } + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } .card > .sectione.dark { - --card-back-color: #e0e0e0; } + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } .card > .sectione.double-padded { padding: calc(1.5 * var(--universal-padding)); } @@ -637,12 +636,12 @@ */ /* Input_control module CSS variable definitions */ :root { - --form-back-color: #f0f0f0; - --form-fore-color: #111; - --form-border-color: #ddd; - --input-back-color: #f8f8f8; - --input-fore-color: #111; - --input-border-color: #ddd; + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; --input-focus-color: #0288d1; --input-invalid-color: #d32f2f; --button-back-color: #e2e2e2; @@ -655,13 +654,13 @@ form { background: var(--form-back-color); color: var(--form-fore-color); - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); padding: calc(2 * var(--universal-padding)) var(--universal-padding); } fieldset { - border: 0.0625rem solid var(--form-border-color); + border: 0.0714285714rem solid var(--form-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 4); padding: var(--universal-padding); } @@ -671,7 +670,7 @@ display: table; max-width: 100%; white-space: normal; - font-weight: 700; + font-weight: 500; padding: calc(var(--universal-padding) / 2); } label { @@ -716,7 +715,7 @@ box-sizing: border-box; background: var(--input-back-color); color: var(--input-fore-color); - border: 0.0625rem solid var(--input-border-color); + border: 0.0714285714rem solid var(--input-border-color); border-radius: var(--universal-border-radius); margin: calc(var(--universal-margin) / 2); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } @@ -763,8 +762,8 @@ [type="radio"]:checked:before { border-radius: 100%; content: ''; - top: calc(0.0625rem + var(--universal-padding) / 2); - left: calc(0.0625rem + var(--universal-padding) / 2); + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); background: var(--input-fore-color); width: 0.5rem; height: 0.5rem; } @@ -793,7 +792,7 @@ display: inline-block; background: var(--button-back-color); color: var(--button-fore-color); - border: 0.0625rem solid var(--button-border-color); + border: 0.0714285714rem solid var(--button-border-color); border-radius: var(--universal-border-radius); padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); margin: var(--universal-margin); @@ -814,7 +813,7 @@ .button-group { display: flex; - border: 0.0625rem solid var(--button-group-border-color); + border: 0.0714285714rem solid var(--button-group-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { @@ -826,13 +825,13 @@ border-radius: 0; box-shadow: none; } .button-group > :not(:first-child) { - border-left: 0.0625rem solid var(--button-group-border-color); } + border-left: 0.0714285714rem solid var(--button-group-border-color); } @media screen and (max-width: 499px) { .button-group { flex-direction: column; } .button-group > :not(:first-child) { border: 0; - border-top: 0.0625rem solid var(--button-group-border-color); } } + border-top: 0.0714285714rem solid var(--button-group-border-color); } } /* Custom elements for forms and input elements. @@ -874,29 +873,29 @@ */ /* Navigation module CSS variable definitions */ :root { - --header-back-color: #f8f8f8; - --header-hover-back-color: #f0f0f0; - --header-fore-color: #444; - --header-border-color: #ddd; - --nav-back-color: #f8f8f8; - --nav-hover-back-color: #f0f0f0; - --nav-fore-color: #444; - --nav-border-color: #ddd; - --nav-link-color: #0277bd; - --footer-fore-color: #444; - --footer-back-color: #f8f8f8; - --footer-border-color: #ddd; - --footer-link-color: #0277bd; - --drawer-back-color: #f8f8f8; - --drawer-hover-back-color: #f0f0f0; - --drawer-border-color: #ddd; - --drawer-close-color: #444; } + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } header { - height: 3.1875rem; + height: 2.75rem; background: var(--header-back-color); color: var(--header-fore-color); - border-bottom: 0.0625rem solid var(--header-border-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); padding: calc(var(--universal-padding) / 4) 0; white-space: nowrap; overflow-x: auto; @@ -927,7 +926,7 @@ nav { background: var(--nav-back-color); color: var(--nav-fore-color); - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-radius: var(--universal-border-radius); margin: var(--universal-margin); } nav * { @@ -946,10 +945,10 @@ nav .sublink-1:before { position: absolute; left: calc(var(--universal-padding) - 1 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } nav .sublink-2 { position: relative; @@ -957,16 +956,16 @@ nav .sublink-2:before { position: absolute; left: calc(var(--universal-padding) - 3 * var(--universal-padding)); - top: -0.0625rem; + top: -0.0714285714rem; content: ''; height: 100%; - border: 0.0625rem solid var(--nav-border-color); + border: 0.0714285714rem solid var(--nav-border-color); border-left: 0; } footer { background: var(--footer-back-color); color: var(--footer-fore-color); - border-top: 0.0625rem solid var(--footer-border-color); + border-top: 0.0714285714rem solid var(--footer-border-color); padding: calc(2 * var(--universal-padding)) var(--universal-padding); font-size: 0.875rem; } footer a, footer a:visited { @@ -1013,7 +1012,7 @@ height: 100vh; overflow-y: auto; background: var(--drawer-back-color); - border: 0.0625rem solid var(--drawer-border-color); + border: 0.0714285714rem solid var(--drawer-border-color); border-radius: 0; margin: 0; z-index: 1110; @@ -1060,38 +1059,36 @@ */ /* Table module CSS variable definitions. */ :root { - --table-border-color: #aaa; - --table-border-separator-color: #666; - --table-head-back-color: #e6e6e6; - --table-head-fore-color: #111; - --table-body-back-color: #f8f8f8; - --table-body-fore-color: #111; - --table-body-alt-back-color: #eee; } + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } table { border-collapse: separate; border-spacing: 0; - : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + margin: 0; display: flex; flex: 0 1 auto; flex-flow: row wrap; padding: var(--universal-padding); - padding-top: 0; - margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + padding-top: 0; } table caption { - font-size: 1.25 * rem; + font-size: 1rem; margin: calc(2 * var(--universal-margin)) 0; max-width: 100%; - flex: 0 0 100%; - text-align: left;} + flex: 0 0 100%; } table thead, table tbody { display: flex; flex-flow: row wrap; - border: 0.0625rem solid var(--table-border-color); } + border: 0.0714285714rem solid var(--table-border-color); } table thead { z-index: 999; border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; - border-bottom: 0.0625rem solid var(--table-border-separator-color); } + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } table tbody { border-top: 0; margin-top: calc(0 - var(--universal-margin)); @@ -1109,11 +1106,11 @@ table td { background: var(--table-body-back-color); color: var(--table-body-fore-color); - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table:not(.horizontal) { overflow: auto; - max-height: 850px; } + max-height: 100%; } table:not(.horizontal) thead, table:not(.horizontal) tbody { max-width: 100%; flex: 0 0 100%; } @@ -1134,32 +1131,33 @@ border: 0; } table.horizontal thead, table.horizontal tbody { border: 0; + flex: .2 0 0; flex-flow: row nowrap; } table.horizontal tbody { overflow: auto; justify-content: space-between; - flex: 1 0 0; - margin-left: calc( 4 * var(--universal-margin)); + flex: .8 0 0; + margin-left: 0; padding-bottom: calc(var(--universal-padding) / 4); } table.horizontal tr { flex-direction: column; flex: 1 0 auto; } table.horizontal th, table.horizontal td { - width: 100%; + width: auto; border: 0; - border-bottom: 0.0625rem solid var(--table-border-color); } + border-bottom: 0.0714285714rem solid var(--table-border-color); } table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { border-top: 0; } table.horizontal th { text-align: right; - border-left: 0.0625rem solid var(--table-border-color); - border-right: 0.0625rem solid var(--table-border-separator-color); } + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } table.horizontal thead tr:first-child { padding-left: 0; } table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0.0625rem solid var(--table-border-color); } + border-top: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td { - border-right: 0.0625rem solid var(--table-border-color); } + border-right: 0.0714285714rem solid var(--table-border-color); } table.horizontal tbody tr:last-child td:first-child { border-top-right-radius: 0.25rem; } table.horizontal tbody tr:last-child td:last-child { @@ -1191,12 +1189,12 @@ display: table-row-group; } table tr, table.horizontal tr { display: block; - border: 0.0625rem solid var(--table-border-color); + border: 0.0714285714rem solid var(--table-border-color); border-radius: var(--universal-border-radius); - background: #fafafa; + background: #ffffff; padding: var(--universal-padding); margin: var(--universal-margin); - margin-bottom: calc(2 * var(--universal-margin)); } + margin-bottom: calc(1 * var(--universal-margin)); } table th, table td, table.horizontal th, table.horizontal td { width: auto; } table td, table.horizontal td { @@ -1211,9 +1209,6 @@ border-top: 0; } table tbody tr:last-child td, table.horizontal tbody tr:last-child td { border-right: 0; } } -:root { - --table-body-alt-back-color: #eee; } - table tr:nth-of-type(2n) > td { background: var(--table-body-alt-back-color); } @@ -1234,8 +1229,8 @@ */ /* Contextual module CSS variable definitions */ :root { - --mark-back-color: #0277bd; - --mark-fore-color: #fafafa; } + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } mark { background: var(--mark-back-color); @@ -1243,11 +1238,11 @@ font-size: 0.95em; line-height: 1em; border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } mark.inline-block { display: inline-block; font-size: 1em; - line-height: 1.5; + line-height: 1.4; padding: calc(var(--universal-padding) / 2) var(--universal-padding); } :root { @@ -1314,8 +1309,8 @@ :root { --modal-overlay-color: rgba(0, 0, 0, 0.45); - --modal-close-color: #444; - --modal-close-hover-color: #f0f0f0; } + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } [type="checkbox"].modal { height: 1px; @@ -1368,13 +1363,14 @@ z-index: 1211; } :root { - --collapse-label-back-color: #e8e8e8; - --collapse-label-fore-color: #212121; - --collapse-label-hover-back-color: #f0f0f0; - --collapse-selected-label-back-color: #ececec; - --collapse-border-color: #ddd; - --collapse-content-back-color: #fafafa; - --collapse-selected-label-border-color: #0277bd; } + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } .collapse { width: calc(100% - 2 * var(--universal-margin)); @@ -1395,13 +1391,13 @@ .collapse > label { flex-grow: 1; display: inline-block; - height: 1.5rem; + height: 1.25rem; cursor: pointer; - transition: background 0.3s; + transition: background 0.2s; color: var(--collapse-label-fore-color); background: var(--collapse-label-back-color); - border: 0.0625rem solid var(--collapse-border-color); - padding: calc(1.5 * var(--universal-padding)); } + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } .collapse > label:hover, .collapse > label:focus { background: var(--collapse-label-hover-back-color); } .collapse > label + div { @@ -1418,7 +1414,7 @@ max-height: 1px; } .collapse > :checked + label { background: var(--collapse-selected-label-back-color); - border-bottom-color: var(--collapse-selected-label-border-color); } + border-color: var(--collapse-selected-label-border-color); } .collapse > :checked + label + div { box-sizing: border-box; position: relative; @@ -1427,13 +1423,13 @@ overflow: auto; margin: 0; background: var(--collapse-content-back-color); - border: 0.0625rem solid var(--collapse-border-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); border-top: 0; padding: var(--universal-padding); clip: auto; -webkit-clip-path: inset(0%); clip-path: inset(0%); - max-height: 850px; } + max-height: 100%; } .collapse > label:not(:first-of-type) { border-top: 0; } .collapse > label:first-of-type { @@ -1450,11 +1446,8 @@ /* Custom elements for contextual background elements, toasts and tooltips. */ -mark.secondary { - --mark-back-color: #d32f2f; } - mark.tertiary { - --mark-back-color: #308732; } + --mark-back-color: #3cb4e6; } mark.tag { padding: calc(var(--universal-padding)/2) var(--universal-padding); @@ -1463,9 +1456,9 @@ /* Definitions for progress elements and spinners. */ -/* Progess module CSS variable definitions */ +/* Progress module CSS variable definitions */ :root { - --progress-back-color: #ddd; + --progress-back-color: #3cb4e6; --progress-fore-color: #555; } progress { @@ -1558,45 +1551,53 @@ filter: invert(100%); } span.icon-alert { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } span.icon-bookmark { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-calendar { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-credit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } span.icon-edit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } span.icon-link { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } span.icon-help { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } span.icon-home { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-info { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } span.icon-lock { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } span.icon-mail { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } span.icon-location { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } span.icon-phone { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-rss { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } span.icon-search { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } span.icon-settings { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } span.icon-share { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } span.icon-cart { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } span.icon-upload { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } span.icon-user { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } /* Definitions for utilities and helper classes. @@ -1604,7 +1605,7 @@ /* Utility module CSS variable definitions */ :root { --generic-border-color: rgba(0, 0, 0, 0.3); - --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } .hidden { display: none !important; } @@ -1622,7 +1623,7 @@ overflow: hidden !important; } .bordered { - border: 0.0625rem solid var(--generic-border-color) !important; } + border: 0.0714285714rem solid var(--generic-border-color) !important; } .rounded { border-radius: var(--universal-border-radius) !important; } @@ -1697,4 +1698,14 @@ clip-path: inset(100%) !important; overflow: hidden !important; } } -/*# sourceMappingURL=mini-default.css.map */ +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file
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