Release v1.1.1
diff --git a/Include/stm32g431xx.h b/Include/stm32g431xx.h
index dd24805..34ffb02 100644
--- a/Include/stm32g431xx.h
+++ b/Include/stm32g431xx.h
@@ -8847,19 +8847,19 @@
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
-#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
-#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
-#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
+#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
+#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
+#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
-#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
+#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
+#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
-#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
+#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
+#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
@@ -9903,35 +9903,35 @@
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
-#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
+#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
-#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
+#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
-#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
+#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
-#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
+#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
-#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
+#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
-#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
+#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
-#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
+#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
-#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
+#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
-#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
+#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
-#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
+#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -12978,9 +12978,6 @@
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
diff --git a/Include/stm32g441xx.h b/Include/stm32g441xx.h
index b31bfdc..91d0007 100644
--- a/Include/stm32g441xx.h
+++ b/Include/stm32g441xx.h
@@ -9078,19 +9078,19 @@
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
-#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
-#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
-#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
+#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
+#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
+#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
-#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
+#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
+#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
-#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
+#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
+#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
@@ -10134,35 +10134,35 @@
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
-#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
+#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
-#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
+#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
-#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
+#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
-#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
+#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
-#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
+#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
-#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
+#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
-#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
+#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
-#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
+#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
-#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
+#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
-#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
+#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -13211,9 +13211,6 @@
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
diff --git a/Include/stm32g471xx.h b/Include/stm32g471xx.h
index dbd5df0..7671f95 100644
--- a/Include/stm32g471xx.h
+++ b/Include/stm32g471xx.h
@@ -9206,19 +9206,19 @@
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
-#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
-#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
-#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
+#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
+#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
+#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
-#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
+#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
+#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
-#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
+#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
+#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
@@ -10345,101 +10345,101 @@
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
-#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
+#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
-#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
+#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
-#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
+#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
-#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
+#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
-#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
+#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
-#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
+#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
-#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
+#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
-#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
+#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
-#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
+#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
-#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
+#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_SWPR_PAGE10_Pos (10U)
-#define SYSCFG_SWPR_PAGE10_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR_PAGE10 (uint32_t)(SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
+#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
#define SYSCFG_SWPR_PAGE11_Pos (11U)
-#define SYSCFG_SWPR_PAGE11_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR_PAGE11 (uint32_t)(SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
+#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
#define SYSCFG_SWPR_PAGE12_Pos (12U)
-#define SYSCFG_SWPR_PAGE12_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR_PAGE12 (uint32_t)(SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
+#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
#define SYSCFG_SWPR_PAGE13_Pos (13U)
-#define SYSCFG_SWPR_PAGE13_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR_PAGE13 (uint32_t)(SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
+#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
#define SYSCFG_SWPR_PAGE14_Pos (14U)
-#define SYSCFG_SWPR_PAGE14_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR_PAGE14 (uint32_t)(SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
+#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
#define SYSCFG_SWPR_PAGE15_Pos (15U)
-#define SYSCFG_SWPR_PAGE15_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR_PAGE15 (uint32_t)(SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
+#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
#define SYSCFG_SWPR_PAGE16_Pos (16U)
-#define SYSCFG_SWPR_PAGE16_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR_PAGE16 (uint32_t)(SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
+#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
#define SYSCFG_SWPR_PAGE17_Pos (17U)
-#define SYSCFG_SWPR_PAGE17_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR_PAGE17 (uint32_t)(SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
+#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
#define SYSCFG_SWPR_PAGE18_Pos (18U)
-#define SYSCFG_SWPR_PAGE18_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR_PAGE18 (uint32_t)(SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
+#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
#define SYSCFG_SWPR_PAGE19_Pos (19U)
-#define SYSCFG_SWPR_PAGE19_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR_PAGE19 (uint32_t)(SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
+#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
#define SYSCFG_SWPR_PAGE20_Pos (20U)
-#define SYSCFG_SWPR_PAGE20_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR_PAGE20 (uint32_t)(SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
+#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
#define SYSCFG_SWPR_PAGE21_Pos (21U)
-#define SYSCFG_SWPR_PAGE21_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR_PAGE21 (uint32_t)(SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
+#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
#define SYSCFG_SWPR_PAGE22_Pos (22U)
-#define SYSCFG_SWPR_PAGE22_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR_PAGE22 (uint32_t)(SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
+#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
#define SYSCFG_SWPR_PAGE23_Pos (23U)
-#define SYSCFG_SWPR_PAGE23_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR_PAGE23 (uint32_t)(SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
+#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
#define SYSCFG_SWPR_PAGE24_Pos (24U)
-#define SYSCFG_SWPR_PAGE24_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR_PAGE24 (uint32_t)(SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
+#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
#define SYSCFG_SWPR_PAGE25_Pos (25U)
-#define SYSCFG_SWPR_PAGE25_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR_PAGE25 (uint32_t)(SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
+#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
#define SYSCFG_SWPR_PAGE26_Pos (26U)
-#define SYSCFG_SWPR_PAGE26_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR_PAGE26 (uint32_t)(SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
+#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
#define SYSCFG_SWPR_PAGE27_Pos (27U)
-#define SYSCFG_SWPR_PAGE27_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR_PAGE27 (uint32_t)(SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
+#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
#define SYSCFG_SWPR_PAGE28_Pos (28U)
-#define SYSCFG_SWPR_PAGE28_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR_PAGE28 (uint32_t)(SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
+#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
#define SYSCFG_SWPR_PAGE29_Pos (29U)
-#define SYSCFG_SWPR_PAGE29_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR_PAGE29 (uint32_t)(SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
+#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
#define SYSCFG_SWPR_PAGE30_Pos (30U)
-#define SYSCFG_SWPR_PAGE30_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR_PAGE30 (uint32_t)(SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
+#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
#define SYSCFG_SWPR_PAGE31_Pos (31U)
-#define SYSCFG_SWPR_PAGE31_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR_PAGE31 (uint32_t)(SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
+#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -13525,9 +13525,6 @@
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
diff --git a/Include/stm32g473xx.h b/Include/stm32g473xx.h
index 777be3b..5928206 100644
--- a/Include/stm32g473xx.h
+++ b/Include/stm32g473xx.h
@@ -9980,19 +9980,19 @@
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
-#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
-#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
-#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
+#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
+#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
+#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
-#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
+#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
+#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
-#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
+#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
+#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
@@ -11119,101 +11119,101 @@
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
-#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
+#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
-#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
+#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
-#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
+#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
-#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
+#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
-#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
+#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
-#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
+#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
-#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
+#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
-#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
+#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
-#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
+#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
-#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
+#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_SWPR_PAGE10_Pos (10U)
-#define SYSCFG_SWPR_PAGE10_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR_PAGE10 (uint32_t)(SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
+#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
#define SYSCFG_SWPR_PAGE11_Pos (11U)
-#define SYSCFG_SWPR_PAGE11_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR_PAGE11 (uint32_t)(SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
+#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
#define SYSCFG_SWPR_PAGE12_Pos (12U)
-#define SYSCFG_SWPR_PAGE12_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR_PAGE12 (uint32_t)(SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
+#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
#define SYSCFG_SWPR_PAGE13_Pos (13U)
-#define SYSCFG_SWPR_PAGE13_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR_PAGE13 (uint32_t)(SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
+#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
#define SYSCFG_SWPR_PAGE14_Pos (14U)
-#define SYSCFG_SWPR_PAGE14_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR_PAGE14 (uint32_t)(SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
+#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
#define SYSCFG_SWPR_PAGE15_Pos (15U)
-#define SYSCFG_SWPR_PAGE15_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR_PAGE15 (uint32_t)(SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
+#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
#define SYSCFG_SWPR_PAGE16_Pos (16U)
-#define SYSCFG_SWPR_PAGE16_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR_PAGE16 (uint32_t)(SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
+#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
#define SYSCFG_SWPR_PAGE17_Pos (17U)
-#define SYSCFG_SWPR_PAGE17_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR_PAGE17 (uint32_t)(SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
+#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
#define SYSCFG_SWPR_PAGE18_Pos (18U)
-#define SYSCFG_SWPR_PAGE18_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR_PAGE18 (uint32_t)(SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
+#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
#define SYSCFG_SWPR_PAGE19_Pos (19U)
-#define SYSCFG_SWPR_PAGE19_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR_PAGE19 (uint32_t)(SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
+#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
#define SYSCFG_SWPR_PAGE20_Pos (20U)
-#define SYSCFG_SWPR_PAGE20_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR_PAGE20 (uint32_t)(SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
+#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
#define SYSCFG_SWPR_PAGE21_Pos (21U)
-#define SYSCFG_SWPR_PAGE21_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR_PAGE21 (uint32_t)(SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
+#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
#define SYSCFG_SWPR_PAGE22_Pos (22U)
-#define SYSCFG_SWPR_PAGE22_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR_PAGE22 (uint32_t)(SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
+#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
#define SYSCFG_SWPR_PAGE23_Pos (23U)
-#define SYSCFG_SWPR_PAGE23_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR_PAGE23 (uint32_t)(SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
+#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
#define SYSCFG_SWPR_PAGE24_Pos (24U)
-#define SYSCFG_SWPR_PAGE24_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR_PAGE24 (uint32_t)(SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
+#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
#define SYSCFG_SWPR_PAGE25_Pos (25U)
-#define SYSCFG_SWPR_PAGE25_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR_PAGE25 (uint32_t)(SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
+#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
#define SYSCFG_SWPR_PAGE26_Pos (26U)
-#define SYSCFG_SWPR_PAGE26_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR_PAGE26 (uint32_t)(SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
+#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
#define SYSCFG_SWPR_PAGE27_Pos (27U)
-#define SYSCFG_SWPR_PAGE27_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR_PAGE27 (uint32_t)(SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
+#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
#define SYSCFG_SWPR_PAGE28_Pos (28U)
-#define SYSCFG_SWPR_PAGE28_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR_PAGE28 (uint32_t)(SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
+#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
#define SYSCFG_SWPR_PAGE29_Pos (29U)
-#define SYSCFG_SWPR_PAGE29_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR_PAGE29 (uint32_t)(SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
+#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
#define SYSCFG_SWPR_PAGE30_Pos (30U)
-#define SYSCFG_SWPR_PAGE30_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR_PAGE30 (uint32_t)(SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
+#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
#define SYSCFG_SWPR_PAGE31_Pos (31U)
-#define SYSCFG_SWPR_PAGE31_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR_PAGE31 (uint32_t)(SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
+#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -14376,9 +14376,6 @@
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
diff --git a/Include/stm32g474xx.h b/Include/stm32g474xx.h
index bdba2c6..95303b2 100644
--- a/Include/stm32g474xx.h
+++ b/Include/stm32g474xx.h
@@ -13342,19 +13342,19 @@
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
-#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
-#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
-#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
+#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
+#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
+#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
-#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
+#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
+#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
-#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
+#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
+#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
@@ -14481,101 +14481,101 @@
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
-#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
+#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
-#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
+#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
-#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
+#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
-#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
+#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
-#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
+#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
-#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
+#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
-#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
+#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
-#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
+#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
-#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
+#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
-#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
+#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_SWPR_PAGE10_Pos (10U)
-#define SYSCFG_SWPR_PAGE10_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR_PAGE10 (uint32_t)(SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
+#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
#define SYSCFG_SWPR_PAGE11_Pos (11U)
-#define SYSCFG_SWPR_PAGE11_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR_PAGE11 (uint32_t)(SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
+#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
#define SYSCFG_SWPR_PAGE12_Pos (12U)
-#define SYSCFG_SWPR_PAGE12_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR_PAGE12 (uint32_t)(SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
+#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
#define SYSCFG_SWPR_PAGE13_Pos (13U)
-#define SYSCFG_SWPR_PAGE13_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR_PAGE13 (uint32_t)(SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
+#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
#define SYSCFG_SWPR_PAGE14_Pos (14U)
-#define SYSCFG_SWPR_PAGE14_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR_PAGE14 (uint32_t)(SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
+#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
#define SYSCFG_SWPR_PAGE15_Pos (15U)
-#define SYSCFG_SWPR_PAGE15_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR_PAGE15 (uint32_t)(SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
+#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
#define SYSCFG_SWPR_PAGE16_Pos (16U)
-#define SYSCFG_SWPR_PAGE16_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR_PAGE16 (uint32_t)(SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
+#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
#define SYSCFG_SWPR_PAGE17_Pos (17U)
-#define SYSCFG_SWPR_PAGE17_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR_PAGE17 (uint32_t)(SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
+#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
#define SYSCFG_SWPR_PAGE18_Pos (18U)
-#define SYSCFG_SWPR_PAGE18_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR_PAGE18 (uint32_t)(SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
+#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
#define SYSCFG_SWPR_PAGE19_Pos (19U)
-#define SYSCFG_SWPR_PAGE19_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR_PAGE19 (uint32_t)(SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
+#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
#define SYSCFG_SWPR_PAGE20_Pos (20U)
-#define SYSCFG_SWPR_PAGE20_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR_PAGE20 (uint32_t)(SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
+#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
#define SYSCFG_SWPR_PAGE21_Pos (21U)
-#define SYSCFG_SWPR_PAGE21_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR_PAGE21 (uint32_t)(SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
+#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
#define SYSCFG_SWPR_PAGE22_Pos (22U)
-#define SYSCFG_SWPR_PAGE22_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR_PAGE22 (uint32_t)(SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
+#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
#define SYSCFG_SWPR_PAGE23_Pos (23U)
-#define SYSCFG_SWPR_PAGE23_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR_PAGE23 (uint32_t)(SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
+#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
#define SYSCFG_SWPR_PAGE24_Pos (24U)
-#define SYSCFG_SWPR_PAGE24_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR_PAGE24 (uint32_t)(SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
+#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
#define SYSCFG_SWPR_PAGE25_Pos (25U)
-#define SYSCFG_SWPR_PAGE25_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR_PAGE25 (uint32_t)(SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
+#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
#define SYSCFG_SWPR_PAGE26_Pos (26U)
-#define SYSCFG_SWPR_PAGE26_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR_PAGE26 (uint32_t)(SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
+#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
#define SYSCFG_SWPR_PAGE27_Pos (27U)
-#define SYSCFG_SWPR_PAGE27_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR_PAGE27 (uint32_t)(SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
+#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
#define SYSCFG_SWPR_PAGE28_Pos (28U)
-#define SYSCFG_SWPR_PAGE28_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR_PAGE28 (uint32_t)(SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
+#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
#define SYSCFG_SWPR_PAGE29_Pos (29U)
-#define SYSCFG_SWPR_PAGE29_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR_PAGE29 (uint32_t)(SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
+#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
#define SYSCFG_SWPR_PAGE30_Pos (30U)
-#define SYSCFG_SWPR_PAGE30_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR_PAGE30 (uint32_t)(SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
+#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
#define SYSCFG_SWPR_PAGE31_Pos (31U)
-#define SYSCFG_SWPR_PAGE31_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR_PAGE31 (uint32_t)(SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
+#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -17738,9 +17738,6 @@
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
diff --git a/Include/stm32g483xx.h b/Include/stm32g483xx.h
index b8f3050..9bd1b8e 100644
--- a/Include/stm32g483xx.h
+++ b/Include/stm32g483xx.h
@@ -10211,19 +10211,19 @@
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
-#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
-#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
-#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
+#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
+#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
+#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
-#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
+#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
+#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
-#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
+#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
+#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
@@ -11350,101 +11350,101 @@
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
-#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
+#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
-#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
+#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
-#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
+#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
-#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
+#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
-#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
+#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
-#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
+#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
-#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
+#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
-#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
+#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
-#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
+#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
-#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
+#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_SWPR_PAGE10_Pos (10U)
-#define SYSCFG_SWPR_PAGE10_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR_PAGE10 (uint32_t)(SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
+#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
#define SYSCFG_SWPR_PAGE11_Pos (11U)
-#define SYSCFG_SWPR_PAGE11_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR_PAGE11 (uint32_t)(SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
+#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
#define SYSCFG_SWPR_PAGE12_Pos (12U)
-#define SYSCFG_SWPR_PAGE12_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR_PAGE12 (uint32_t)(SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
+#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
#define SYSCFG_SWPR_PAGE13_Pos (13U)
-#define SYSCFG_SWPR_PAGE13_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR_PAGE13 (uint32_t)(SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
+#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
#define SYSCFG_SWPR_PAGE14_Pos (14U)
-#define SYSCFG_SWPR_PAGE14_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR_PAGE14 (uint32_t)(SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
+#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
#define SYSCFG_SWPR_PAGE15_Pos (15U)
-#define SYSCFG_SWPR_PAGE15_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR_PAGE15 (uint32_t)(SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
+#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
#define SYSCFG_SWPR_PAGE16_Pos (16U)
-#define SYSCFG_SWPR_PAGE16_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR_PAGE16 (uint32_t)(SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
+#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
#define SYSCFG_SWPR_PAGE17_Pos (17U)
-#define SYSCFG_SWPR_PAGE17_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR_PAGE17 (uint32_t)(SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
+#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
#define SYSCFG_SWPR_PAGE18_Pos (18U)
-#define SYSCFG_SWPR_PAGE18_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR_PAGE18 (uint32_t)(SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
+#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
#define SYSCFG_SWPR_PAGE19_Pos (19U)
-#define SYSCFG_SWPR_PAGE19_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR_PAGE19 (uint32_t)(SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
+#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
#define SYSCFG_SWPR_PAGE20_Pos (20U)
-#define SYSCFG_SWPR_PAGE20_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR_PAGE20 (uint32_t)(SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
+#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
#define SYSCFG_SWPR_PAGE21_Pos (21U)
-#define SYSCFG_SWPR_PAGE21_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR_PAGE21 (uint32_t)(SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
+#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
#define SYSCFG_SWPR_PAGE22_Pos (22U)
-#define SYSCFG_SWPR_PAGE22_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR_PAGE22 (uint32_t)(SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
+#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
#define SYSCFG_SWPR_PAGE23_Pos (23U)
-#define SYSCFG_SWPR_PAGE23_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR_PAGE23 (uint32_t)(SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
+#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
#define SYSCFG_SWPR_PAGE24_Pos (24U)
-#define SYSCFG_SWPR_PAGE24_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR_PAGE24 (uint32_t)(SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
+#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
#define SYSCFG_SWPR_PAGE25_Pos (25U)
-#define SYSCFG_SWPR_PAGE25_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR_PAGE25 (uint32_t)(SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
+#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
#define SYSCFG_SWPR_PAGE26_Pos (26U)
-#define SYSCFG_SWPR_PAGE26_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR_PAGE26 (uint32_t)(SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
+#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
#define SYSCFG_SWPR_PAGE27_Pos (27U)
-#define SYSCFG_SWPR_PAGE27_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR_PAGE27 (uint32_t)(SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
+#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
#define SYSCFG_SWPR_PAGE28_Pos (28U)
-#define SYSCFG_SWPR_PAGE28_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR_PAGE28 (uint32_t)(SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
+#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
#define SYSCFG_SWPR_PAGE29_Pos (29U)
-#define SYSCFG_SWPR_PAGE29_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR_PAGE29 (uint32_t)(SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
+#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
#define SYSCFG_SWPR_PAGE30_Pos (30U)
-#define SYSCFG_SWPR_PAGE30_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR_PAGE30 (uint32_t)(SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
+#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
#define SYSCFG_SWPR_PAGE31_Pos (31U)
-#define SYSCFG_SWPR_PAGE31_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR_PAGE31 (uint32_t)(SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
+#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -14609,9 +14609,6 @@
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
diff --git a/Include/stm32g484xx.h b/Include/stm32g484xx.h
index 8313767..f166637 100644
--- a/Include/stm32g484xx.h
+++ b/Include/stm32g484xx.h
@@ -13573,19 +13573,19 @@
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
-#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
-#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
-#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
+#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
+#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
+#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
-#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
+#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
+#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
-#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
+#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
+#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
@@ -14712,101 +14712,101 @@
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
-#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
+#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
-#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
+#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
-#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
+#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
-#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
+#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
-#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
+#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
-#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
+#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
-#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
+#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
-#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
+#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
-#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
+#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
-#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
+#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_SWPR_PAGE10_Pos (10U)
-#define SYSCFG_SWPR_PAGE10_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR_PAGE10 (uint32_t)(SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
+#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
#define SYSCFG_SWPR_PAGE11_Pos (11U)
-#define SYSCFG_SWPR_PAGE11_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR_PAGE11 (uint32_t)(SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
+#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
#define SYSCFG_SWPR_PAGE12_Pos (12U)
-#define SYSCFG_SWPR_PAGE12_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR_PAGE12 (uint32_t)(SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
+#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
#define SYSCFG_SWPR_PAGE13_Pos (13U)
-#define SYSCFG_SWPR_PAGE13_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR_PAGE13 (uint32_t)(SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
+#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
#define SYSCFG_SWPR_PAGE14_Pos (14U)
-#define SYSCFG_SWPR_PAGE14_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR_PAGE14 (uint32_t)(SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
+#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
#define SYSCFG_SWPR_PAGE15_Pos (15U)
-#define SYSCFG_SWPR_PAGE15_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR_PAGE15 (uint32_t)(SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
+#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
#define SYSCFG_SWPR_PAGE16_Pos (16U)
-#define SYSCFG_SWPR_PAGE16_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR_PAGE16 (uint32_t)(SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
+#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
#define SYSCFG_SWPR_PAGE17_Pos (17U)
-#define SYSCFG_SWPR_PAGE17_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR_PAGE17 (uint32_t)(SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
+#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
#define SYSCFG_SWPR_PAGE18_Pos (18U)
-#define SYSCFG_SWPR_PAGE18_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR_PAGE18 (uint32_t)(SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
+#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
#define SYSCFG_SWPR_PAGE19_Pos (19U)
-#define SYSCFG_SWPR_PAGE19_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR_PAGE19 (uint32_t)(SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
+#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
#define SYSCFG_SWPR_PAGE20_Pos (20U)
-#define SYSCFG_SWPR_PAGE20_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR_PAGE20 (uint32_t)(SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
+#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
#define SYSCFG_SWPR_PAGE21_Pos (21U)
-#define SYSCFG_SWPR_PAGE21_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR_PAGE21 (uint32_t)(SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
+#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
#define SYSCFG_SWPR_PAGE22_Pos (22U)
-#define SYSCFG_SWPR_PAGE22_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR_PAGE22 (uint32_t)(SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
+#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
#define SYSCFG_SWPR_PAGE23_Pos (23U)
-#define SYSCFG_SWPR_PAGE23_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR_PAGE23 (uint32_t)(SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
+#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
#define SYSCFG_SWPR_PAGE24_Pos (24U)
-#define SYSCFG_SWPR_PAGE24_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR_PAGE24 (uint32_t)(SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
+#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
#define SYSCFG_SWPR_PAGE25_Pos (25U)
-#define SYSCFG_SWPR_PAGE25_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR_PAGE25 (uint32_t)(SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
+#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
#define SYSCFG_SWPR_PAGE26_Pos (26U)
-#define SYSCFG_SWPR_PAGE26_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR_PAGE26 (uint32_t)(SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
+#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
#define SYSCFG_SWPR_PAGE27_Pos (27U)
-#define SYSCFG_SWPR_PAGE27_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR_PAGE27 (uint32_t)(SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
+#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
#define SYSCFG_SWPR_PAGE28_Pos (28U)
-#define SYSCFG_SWPR_PAGE28_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR_PAGE28 (uint32_t)(SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
+#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
#define SYSCFG_SWPR_PAGE29_Pos (29U)
-#define SYSCFG_SWPR_PAGE29_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR_PAGE29 (uint32_t)(SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
+#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
#define SYSCFG_SWPR_PAGE30_Pos (30U)
-#define SYSCFG_SWPR_PAGE30_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR_PAGE30 (uint32_t)(SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
+#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
#define SYSCFG_SWPR_PAGE31_Pos (31U)
-#define SYSCFG_SWPR_PAGE31_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR_PAGE31 (uint32_t)(SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
+#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -17971,9 +17971,6 @@
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
diff --git a/Include/stm32g4xx.h b/Include/stm32g4xx.h
index d72506d..3ff61d8 100644
--- a/Include/stm32g4xx.h
+++ b/Include/stm32g4xx.h
@@ -58,7 +58,7 @@
*/
#if !defined (STM32G431xx) && !defined (STM32G441xx) && \
- !defined (STM32G471xx) && !defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G483xx) && !defined (STM32G484xx) && !defined (STM32GBK1CB)
+ !defined (STM32G471xx) && !defined (STM32G473xx) && !defined (STM32G474xx) && !defined (STM32G484xx) && !defined (STM32GBK1CB)
/* #define STM32G431xx */ /*!< STM32G431xx Devices */
/* #define STM32G441xx */ /*!< STM32G441xx Devices */
/* #define STM32G471xx */ /*!< STM32G471xx Devices */
@@ -82,11 +82,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number $VERSION$
+ * @brief CMSIS Device version number V1.1.1
*/
#define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G4_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
-#define __STM32G4_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32G4_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\
|(__STM32G4_CMSIS_VERSION_SUB1 << 16)\
diff --git a/Include/stm32gbk1cb.h b/Include/stm32gbk1cb.h
index 1044bb2..53a0fad 100644
--- a/Include/stm32gbk1cb.h
+++ b/Include/stm32gbk1cb.h
@@ -8819,19 +8819,19 @@
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
-#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
-#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
-#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
+#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
+#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
+#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
-#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
+#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
+#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
-#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
+#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
+#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
@@ -9875,35 +9875,35 @@
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
-#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
+#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
-#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
+#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
-#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
+#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
-#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
+#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
-#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
+#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
-#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
+#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
-#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
+#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
-#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
+#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
-#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
+#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
-#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
+#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -12925,9 +12925,6 @@
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
diff --git a/README.md b/README.md
index 2119cdc..690c4d4 100644
--- a/README.md
+++ b/README.md
@@ -27,6 +27,9 @@
--------------- | ---------- | -------------------------------------
Tag v1.0.0 | Tag v5.4.0_cm4 | Tag v1.0.0
Tag v1.1.0 | Tag v5.4.0_cm4 | Tag v1.1.0
+Tag v1.1.1 | Tag v5.4.0_cm4 | Tag v1.2.0
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_g4/blob/master/Release_Notes.html).
The full **STM32CubeG4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeG4).
diff --git a/Release_Notes.html b/Release_Notes.html
index 48ff0c5..ed008af 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -51,11 +51,11 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 28-June-2019</label>
+<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.1.1 / 14-February-2020</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
-<p>Maintenance release of CMSIS Devices drivers supporting STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, <strong>STM32G483xx</strong>, STM32G474xx and STM32G484xx devices</p>
+<p>General updates to fix known defects and enhancements implementation</p>
<h2 id="contents">Contents</h2>
<table>
<caption>Additional features<br />
@@ -67,6 +67,61 @@
</thead>
<tbody>
<tr class="odd">
+<td style="text-align: left;">- General updates to fix known defects and enhancements implementation</td>
+</tr>
+</tbody>
+</table>
+<table>
+<caption>Fixed bugs list<br />
+</caption>
+<thead>
+<tr class="header">
+<th>Headline</th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
+<td>Update STM32G473/483 startup files to support FDCAN2/3 intances</td>
+</tr>
+<tr class="even">
+<td>Remove IS_TIM_SYNCHRO_INSTANCE macro from device header files</td>
+</tr>
+</tbody>
+</table>
+<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
+<li>STM32CubeIDE toolchain v1.3.0</li>
+</ul>
+<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<ul>
+<li>STM32G431xx, STM32G441xx devices</li>
+<li>STM32G471xx devices</li>
+<li>STM32G473xx, STM32G483xx devices</li>
+<li>STM32G474xx, STM32G484xx devices</li>
+</ul>
+<p>Note: in the section above, main changes are highlighted in <strong>bold</strong> since previous release.</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 28-June-2019</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3 id="maintenance-release-1">Maintenance release</h3>
+<p>Maintenance release of CMSIS Devices drivers supporting STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, <strong>STM32G483xx</strong>, STM32G474xx and STM32G484xx devices</p>
+<h2 id="contents-1">Contents</h2>
+<table>
+<caption>Additional features<br />
+</caption>
+<thead>
+<tr class="header">
+<th style="text-align: left;">Headline</th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
<td style="text-align: left;">[STM32G483xx} New CMSIS driver files to support STM32G483xx</td>
</tr>
<tr class="even">
@@ -97,14 +152,14 @@
</tr>
</tbody>
</table>
-<h2 id="known-limitations">Known Limitations</h2>
-<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
<ul>
<li>STM32G431xx, STM32G441xx devices</li>
<li>STM32G471xx devices</li>
@@ -115,14 +170,14 @@
</div>
</div>
<div class="collapse">
-<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 12-April-2019</label>
+<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.0.0 / 12-April-2019</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release for STM32G4xx devices</p>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
<p>CMSIS devices files for STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, STM32G474xx and STM32G484xx.</p>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
<table>
<thead>
<tr class="header">
@@ -135,13 +190,13 @@
</tr>
</tbody>
</table>
-<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
<ul>
<li>STM32G431xx, STM32G441xx devices</li>
<li>STM32G471xx devices</li>
diff --git a/Source/Templates/arm/startup_stm32g473xx.s b/Source/Templates/arm/startup_stm32g473xx.s
index 801ad59..6ed919b 100644
--- a/Source/Templates/arm/startup_stm32g473xx.s
+++ b/Source/Templates/arm/startup_stm32g473xx.s
@@ -100,8 +100,8 @@
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
@@ -165,10 +165,10 @@
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
@@ -267,6 +267,8 @@
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
@@ -321,6 +323,10 @@
EXPORT I2C4_EV_IRQHandler [WEAK]
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT1_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
@@ -355,6 +361,8 @@
ADC1_2_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
@@ -409,6 +417,10 @@
I2C4_EV_IRQHandler
I2C4_ER_IRQHandler
SPI4_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN2_IT1_IRQHandler
+FDCAN3_IT0_IRQHandler
+FDCAN3_IT1_IRQHandler
RNG_IRQHandler
LPUART1_IRQHandler
I2C3_EV_IRQHandler
diff --git a/Source/Templates/arm/startup_stm32g483xx.s b/Source/Templates/arm/startup_stm32g483xx.s
index b5b693b..7a123c8 100644
--- a/Source/Templates/arm/startup_stm32g483xx.s
+++ b/Source/Templates/arm/startup_stm32g483xx.s
@@ -164,11 +164,11 @@
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
- DCD AES_IRQHandler ; AES global interrupt DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD AES_IRQHandler ; AES global interrupt
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
@@ -267,6 +267,8 @@
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
@@ -322,6 +324,10 @@
EXPORT I2C4_ER_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT1_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
@@ -356,6 +362,8 @@
ADC1_2_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
@@ -411,6 +419,10 @@
I2C4_ER_IRQHandler
SPI4_IRQHandler
AES_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN2_IT1_IRQHandler
+FDCAN3_IT0_IRQHandler
+FDCAN3_IT1_IRQHandler
RNG_IRQHandler
LPUART1_IRQHandler
I2C3_EV_IRQHandler
diff --git a/Source/Templates/gcc/startup_stm32g473xx.s b/Source/Templates/gcc/startup_stm32g473xx.s
index 3b10aeb..f59f3fc 100644
--- a/Source/Templates/gcc/startup_stm32g473xx.s
+++ b/Source/Templates/gcc/startup_stm32g473xx.s
@@ -169,8 +169,8 @@
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
- .word 0
- .word 0
+ .word FDCAN1_IT0_IRQHandler
+ .word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
@@ -234,10 +234,10 @@
.word I2C4_ER_IRQHandler
.word SPI4_IRQHandler
.word 0
- .word 0
- .word 0
- .word 0
- .word 0
+ .word FDCAN2_IT0_IRQHandler
+ .word FDCAN2_IT1_IRQHandler
+ .word FDCAN3_IT0_IRQHandler
+ .word FDCAN3_IT1_IRQHandler
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
@@ -349,6 +349,12 @@
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
@@ -511,6 +517,18 @@
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT0_IRQHandler
+ .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT1_IRQHandler
+ .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
+
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
diff --git a/Source/Templates/gcc/startup_stm32g483xx.s b/Source/Templates/gcc/startup_stm32g483xx.s
index 15e3ca1..797f3c8 100644
--- a/Source/Templates/gcc/startup_stm32g483xx.s
+++ b/Source/Templates/gcc/startup_stm32g483xx.s
@@ -169,8 +169,8 @@
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
- .word 0
- .word 0
+ .word FDCAN1_IT0_IRQHandler
+ .word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
@@ -234,10 +234,10 @@
.word I2C4_ER_IRQHandler
.word SPI4_IRQHandler
.word AES_IRQHandler
- .word 0
- .word 0
- .word 0
- .word 0
+ .word FDCAN2_IT0_IRQHandler
+ .word FDCAN2_IT1_IRQHandler
+ .word FDCAN3_IT0_IRQHandler
+ .word FDCAN3_IT1_IRQHandler
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
@@ -349,6 +349,12 @@
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
@@ -514,6 +520,17 @@
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT0_IRQHandler
+ .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT1_IRQHandler
+ .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
diff --git a/Source/Templates/iar/startup_stm32g473xx.s b/Source/Templates/iar/startup_stm32g473xx.s
index 1ddbd42..7340942 100644
--- a/Source/Templates/iar/startup_stm32g473xx.s
+++ b/Source/Templates/iar/startup_stm32g473xx.s
@@ -94,8 +94,8 @@
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
@@ -159,10 +159,10 @@
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
@@ -339,6 +339,16 @@
USB_LP_IRQHandler
B USB_LP_IRQHandler
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
@@ -609,6 +619,26 @@
SPI4_IRQHandler
B SPI4_IRQHandler
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK FDCAN3_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT0_IRQHandler
+ B FDCAN3_IT0_IRQHandler
+
+ PUBWEAK FDCAN3_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT1_IRQHandler
+ B FDCAN3_IT1_IRQHandler
+
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
diff --git a/Source/Templates/iar/startup_stm32g483xx.s b/Source/Templates/iar/startup_stm32g483xx.s
index 6dbea05..05b1e5b 100644
--- a/Source/Templates/iar/startup_stm32g483xx.s
+++ b/Source/Templates/iar/startup_stm32g483xx.s
@@ -94,8 +94,8 @@
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_IRQHandler ; USB Device High Priority
DCD USB_LP_IRQHandler ; USB Device Low Priority
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
@@ -158,11 +158,11 @@
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD SPI4_IRQHandler ; SPI4
- DCD AES_IRQHandler ; AES global interrupt DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD AES_IRQHandler ; AES global interrupt
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
DCD RNG_IRQHandler ; RNG global interrupt
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD I2C3_EV_IRQHandler ; I2C3 Event
@@ -339,6 +339,16 @@
USB_LP_IRQHandler
B USB_LP_IRQHandler
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
@@ -614,6 +624,26 @@
AES_IRQHandler
B AES_IRQHandler
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK FDCAN3_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT0_IRQHandler
+ B FDCAN3_IT0_IRQHandler
+
+ PUBWEAK FDCAN3_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT1_IRQHandler
+ B FDCAN3_IT1_IRQHandler
+
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler