Release v1.10.0
diff --git a/Include/stm32h723xx.h b/Include/stm32h723xx.h
index 4e5a3e0..610abfd 100644
--- a/Include/stm32h723xx.h
+++ b/Include/stm32h723xx.h
@@ -674,7 +674,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -924,6 +924,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1950,6 +1959,96 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2304,6 +2403,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2588,6 +2690,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -2836,7 +2940,7 @@
#define ADC3_CFGR_ALIGN_Pos (15U)
#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */
-#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */
/******************** Bit definition for ADC_CFGR2 register ********************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
@@ -3125,7 +3229,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4061,7 +4165,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10687,10 +10791,13 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
-#define FLASH_SIZE 0x00100000UL /* 1 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x100000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x100000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 1 MB */
#define FLASH_BANK_SIZE FLASH_SIZE /* 1 MB */
-#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
+#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
@@ -11152,7 +11259,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11632,7 +11739,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -13160,7 +13267,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13169,7 +13276,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -13488,7 +13595,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -13553,13 +13660,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -13615,7 +13722,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -21340,7 +21447,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -23625,6 +23732,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM23) || \
((INSTANCE) == TIM24))
diff --git a/Include/stm32h725xx.h b/Include/stm32h725xx.h
index 7138ed0..d4d22d9 100644
--- a/Include/stm32h725xx.h
+++ b/Include/stm32h725xx.h
@@ -675,7 +675,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -925,6 +925,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1951,6 +1960,96 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2305,6 +2404,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2589,6 +2691,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -2837,7 +2941,7 @@
#define ADC3_CFGR_ALIGN_Pos (15U)
#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */
-#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */
/******************** Bit definition for ADC_CFGR2 register ********************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
@@ -3126,7 +3230,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4062,7 +4166,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10688,10 +10792,13 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
-#define FLASH_SIZE 0x00100000UL /* 1 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x100000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x100000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 1 MB */
#define FLASH_BANK_SIZE FLASH_SIZE /* 1 MB */
-#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
+#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
@@ -11153,7 +11260,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11633,7 +11740,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -13161,7 +13268,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13170,7 +13277,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -13489,7 +13596,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -13554,13 +13661,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -13616,7 +13723,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -21352,7 +21459,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -23637,6 +23744,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM23) || \
((INSTANCE) == TIM24))
diff --git a/Include/stm32h730xx.h b/Include/stm32h730xx.h
index 968688f..624714f 100644
--- a/Include/stm32h730xx.h
+++ b/Include/stm32h730xx.h
@@ -677,7 +677,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -927,6 +927,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -2056,6 +2065,96 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2424,6 +2523,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2723,6 +2825,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -2971,7 +3075,7 @@
#define ADC3_CFGR_ALIGN_Pos (15U)
#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */
-#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */
/******************** Bit definition for ADC_CFGR2 register ********************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
@@ -3260,7 +3364,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4196,7 +4300,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10941,9 +11045,12 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 1U /* 1 sector */
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
-#define FLASH_SIZE FLASH_SECTOR_SIZE /* 128 KB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x20000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x20000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 128 KB */
#define FLASH_BANK_SIZE FLASH_SIZE /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
@@ -11406,7 +11513,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11886,7 +11993,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -13490,7 +13597,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13499,7 +13606,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -13818,7 +13925,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -13883,13 +13990,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -13945,7 +14052,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -21827,7 +21934,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -24116,6 +24223,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM23) || \
((INSTANCE) == TIM24))
diff --git a/Include/stm32h730xxq.h b/Include/stm32h730xxq.h
index 1007c89..cac92b3 100644
--- a/Include/stm32h730xxq.h
+++ b/Include/stm32h730xxq.h
@@ -678,7 +678,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -928,6 +928,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -2057,6 +2066,96 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2425,6 +2524,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2724,6 +2826,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -2972,7 +3076,7 @@
#define ADC3_CFGR_ALIGN_Pos (15U)
#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */
-#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */
/******************** Bit definition for ADC_CFGR2 register ********************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
@@ -3261,7 +3365,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4197,7 +4301,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10942,9 +11046,12 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 1U /* 1 sector */
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
-#define FLASH_SIZE FLASH_SECTOR_SIZE /* 128 KB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x20000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x20000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 128 KB */
#define FLASH_BANK_SIZE FLASH_SIZE /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
@@ -11407,7 +11514,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11887,7 +11994,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -13491,7 +13598,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13500,7 +13607,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -13819,7 +13926,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -13884,13 +13991,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -13946,7 +14053,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -21839,7 +21946,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -24128,6 +24235,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM23) || \
((INSTANCE) == TIM24))
diff --git a/Include/stm32h733xx.h b/Include/stm32h733xx.h
index c2797e0..39404cb 100644
--- a/Include/stm32h733xx.h
+++ b/Include/stm32h733xx.h
@@ -677,7 +677,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -927,6 +927,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -2056,6 +2065,96 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2424,6 +2523,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2723,6 +2825,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -2971,7 +3075,7 @@
#define ADC3_CFGR_ALIGN_Pos (15U)
#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */
-#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */
/******************** Bit definition for ADC_CFGR2 register ********************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
@@ -3260,7 +3364,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4196,7 +4300,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10941,10 +11045,13 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
-#define FLASH_SIZE 0x00100000UL /* 1 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x100000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x100000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 1 MB */
#define FLASH_BANK_SIZE FLASH_SIZE /* 1 MB */
-#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
+#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
@@ -11406,7 +11513,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11886,7 +11993,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -13490,7 +13597,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13499,7 +13606,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -13818,7 +13925,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -13883,13 +13990,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -13945,7 +14052,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -21827,7 +21934,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -24116,6 +24223,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM23) || \
((INSTANCE) == TIM24))
diff --git a/Include/stm32h735xx.h b/Include/stm32h735xx.h
index 4293e44..e8272e8 100644
--- a/Include/stm32h735xx.h
+++ b/Include/stm32h735xx.h
@@ -678,7 +678,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -928,6 +928,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -2057,6 +2066,96 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2425,6 +2524,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2724,6 +2826,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -2972,7 +3076,7 @@
#define ADC3_CFGR_ALIGN_Pos (15U)
#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */
-#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */
/******************** Bit definition for ADC_CFGR2 register ********************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
@@ -3261,7 +3365,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4197,7 +4301,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10942,10 +11046,13 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
-#define FLASH_SIZE 0x00100000UL /* 1 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x100000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x100000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 1 MB */
#define FLASH_BANK_SIZE FLASH_SIZE /* 1 MB */
-#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
+#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
@@ -11407,7 +11514,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11887,7 +11994,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -13491,7 +13598,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13500,7 +13607,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -13819,7 +13926,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -13884,13 +13991,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -13946,7 +14053,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -21839,7 +21946,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -24128,6 +24235,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM23) || \
((INSTANCE) == TIM24))
diff --git a/Include/stm32h742xx.h b/Include/stm32h742xx.h
index 6a5dc08..5d67a52 100644
--- a/Include/stm32h742xx.h
+++ b/Include/stm32h742xx.h
@@ -631,7 +631,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -881,6 +881,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1571,7 +1580,7 @@
{
__IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
__IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
+ __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */
__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
__IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
__IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
@@ -1876,6 +1885,90 @@
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2226,6 +2319,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2512,6 +2608,8 @@
#define USB_OTG_FS USB2_OTG_FS
#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -2984,7 +3082,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -3864,7 +3962,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10457,8 +10555,11 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
-#define FLASH_SIZE 0x200000UL /* 2 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
@@ -10808,7 +10909,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11288,7 +11389,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -12861,7 +12962,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -12926,13 +13027,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -12988,7 +13089,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -17747,7 +17848,7 @@
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
-#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< Reserved: needed for softawre compatibility (DMA Enable) */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
@@ -20288,7 +20389,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -20375,12 +20476,6 @@
#define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
#define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
-#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
-#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
-#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
-#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
-#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
-#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
@@ -22243,7 +22338,7 @@
/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
#define HRTIM_BMCR_BME_Pos (0U)
#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
-#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
+#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enable */
#define HRTIM_BMCR_BMOM_Pos (1U)
#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
@@ -25188,6 +25283,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h743xx.h b/Include/stm32h743xx.h
index ddc887a..a9e5f4c 100644
--- a/Include/stm32h743xx.h
+++ b/Include/stm32h743xx.h
@@ -634,7 +634,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -884,6 +884,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1658,7 +1667,7 @@
{
__IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
__IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
+ __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */
__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
__IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
__IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
@@ -1963,6 +1972,90 @@
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2317,6 +2410,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2607,6 +2703,8 @@
#define USB_OTG_FS USB2_OTG_FS
#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -3079,7 +3177,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -3959,7 +4057,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10552,8 +10650,11 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
-#define FLASH_SIZE 0x200000UL /* 2 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
@@ -10903,7 +11004,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11383,7 +11484,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -13163,7 +13264,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13172,7 +13273,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -13491,7 +13592,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -13556,13 +13657,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -13618,7 +13719,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -18395,7 +18496,7 @@
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
-#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< Reserved: needed for softawre compatibility (DMA Enable) */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
@@ -20936,7 +21037,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -21023,12 +21124,6 @@
#define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
#define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
-#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
-#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
-#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
-#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
-#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
-#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
@@ -22891,7 +22986,7 @@
/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
#define HRTIM_BMCR_BME_Pos (0U)
#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
-#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
+#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enable */
#define HRTIM_BMCR_BMOM_Pos (1U)
#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
@@ -25838,6 +25933,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h745xx.h b/Include/stm32h745xx.h
index 443ed0c..56afb78 100644
--- a/Include/stm32h745xx.h
+++ b/Include/stm32h745xx.h
@@ -666,7 +666,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -929,6 +929,15 @@
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1733,7 +1742,7 @@
{
__IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
__IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
+ __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */
__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
__IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
__IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
@@ -2038,6 +2047,94 @@
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+ uint32_t RESERVED25[1021]; /*!< Reserved, Address offset: 0x4710C-0x480FC */
+ __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */
+ __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */
+ __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2397,6 +2494,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2697,6 +2797,8 @@
#define USB_OTG_FS USB2_OTG_FS
#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -3169,7 +3271,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4062,7 +4164,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10655,8 +10757,11 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
-#define FLASH_SIZE 0x200000UL /* 2 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
@@ -11028,7 +11133,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11508,7 +11613,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -13679,7 +13784,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13688,7 +13793,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -14007,7 +14112,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -14072,13 +14177,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -14134,7 +14239,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -19022,7 +19127,7 @@
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
-#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< Reserved: needed for softawre compatibility (DMA Enable) */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
@@ -21590,7 +21695,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -21686,12 +21791,6 @@
#define DBGMCU_CR_DBG_STANDBYD2_Pos (5U)
#define DBGMCU_CR_DBG_STANDBYD2_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */
#define DBGMCU_CR_DBG_STANDBYD2 DBGMCU_CR_DBG_STANDBYD2_Msk
-#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
-#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
-#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
-#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
-#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
-#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
@@ -23656,7 +23755,7 @@
/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
#define HRTIM_BMCR_BME_Pos (0U)
#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
-#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
+#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enable */
#define HRTIM_BMCR_BMOM_Pos (1U)
#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
@@ -26610,6 +26709,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h747xx.h b/Include/stm32h747xx.h
index f155966..ebc71c6 100644
--- a/Include/stm32h747xx.h
+++ b/Include/stm32h747xx.h
@@ -667,7 +667,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -761,7 +761,7 @@
uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
__IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
__IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
- __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */
__IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
__IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
__IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
@@ -1010,6 +1010,15 @@
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1814,7 +1823,7 @@
{
__IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
__IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
+ __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */
__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
__IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
__IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
@@ -2119,6 +2128,94 @@
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+ uint32_t RESERVED25[1021]; /*!< Reserved, Address offset: 0x4710C-0x480FC */
+ __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */
+ __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */
+ __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2479,6 +2576,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2780,6 +2880,8 @@
#define USB_OTG_FS USB2_OTG_FS
#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -3252,7 +3354,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4145,7 +4247,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -9711,7 +9813,7 @@
#define DSI_LCOLCR_LPE_Pos (8U)
#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
-#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
+#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosely Packet Enable */
/******************* Bit definition for DSI_LPCR register ***************/
#define DSI_LPCR_DEP_Pos (0U)
@@ -13812,8 +13914,11 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
-#define FLASH_SIZE 0x200000UL /* 2 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
@@ -14185,7 +14290,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -14665,7 +14770,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -16836,7 +16941,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -16845,7 +16950,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -17164,7 +17269,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -17229,13 +17334,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -17291,7 +17396,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -22195,7 +22300,7 @@
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
-#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< Reserved: needed for softawre compatibility (DMA Enable) */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
@@ -24763,7 +24868,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -24859,12 +24964,6 @@
#define DBGMCU_CR_DBG_STANDBYD2_Pos (5U)
#define DBGMCU_CR_DBG_STANDBYD2_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */
#define DBGMCU_CR_DBG_STANDBYD2 DBGMCU_CR_DBG_STANDBYD2_Msk
-#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
-#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
-#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
-#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
-#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
-#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
@@ -26829,7 +26928,7 @@
/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
#define HRTIM_BMCR_BME_Pos (0U)
#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
-#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
+#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enable */
#define HRTIM_BMCR_BMOM_Pos (1U)
#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
@@ -29783,6 +29882,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h750xx.h b/Include/stm32h750xx.h
index 55a8894..bbe8ba0 100644
--- a/Include/stm32h750xx.h
+++ b/Include/stm32h750xx.h
@@ -635,7 +635,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -885,6 +885,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1728,7 +1737,7 @@
{
__IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
__IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
+ __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */
__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
__IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
__IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
@@ -2033,6 +2042,90 @@
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2390,6 +2483,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2683,6 +2779,8 @@
#define USB_OTG_FS USB2_OTG_FS
#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -3155,7 +3253,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4035,7 +4133,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10745,13 +10843,17 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 1U /* 1 sector */
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
-#define FLASH_SIZE FLASH_SECTOR_SIZE /* 128 KB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x20000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x20000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 128 KB */
#define FLASH_BANK_SIZE FLASH_SIZE /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
+
/******************* Bits definition for FLASH_ACR register **********************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
@@ -10949,9 +11051,6 @@
#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */
-#define FLASH_OPTCR_SWAP_BANK_Pos (31U)
-#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
-#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */
/******************* Bits definition for FLASH_OPTSR register ***************/
#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
@@ -10994,9 +11093,6 @@
#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */
-#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
-#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
-#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */
/******************* Bits definition for FLASH_OPTCCR register *******************/
#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
@@ -11095,7 +11191,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11575,7 +11671,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -13431,7 +13527,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13440,7 +13536,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -13759,7 +13855,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -13824,13 +13920,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -13886,7 +13982,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -18681,7 +18777,7 @@
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
-#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< Reserved: needed for softawre compatibility (DMA Enable) */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
@@ -21222,7 +21318,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -21309,12 +21405,6 @@
#define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
#define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
-#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
-#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
-#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
-#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
-#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
-#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
@@ -23177,7 +23267,7 @@
/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
#define HRTIM_BMCR_BME_Pos (0U)
#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
-#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
+#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enable */
#define HRTIM_BMCR_BMOM_Pos (1U)
#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
@@ -26124,6 +26214,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h753xx.h b/Include/stm32h753xx.h
index 4c4955b..afd0d3a 100644
--- a/Include/stm32h753xx.h
+++ b/Include/stm32h753xx.h
@@ -635,7 +635,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -885,6 +885,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1728,7 +1737,7 @@
{
__IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
__IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
+ __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */
__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
__IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
__IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
@@ -2033,6 +2042,90 @@
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2390,6 +2483,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2683,6 +2779,8 @@
#define USB_OTG_FS USB2_OTG_FS
#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -3155,7 +3253,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4035,7 +4133,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10745,8 +10843,11 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
-#define FLASH_SIZE 0x200000UL /* 2 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
@@ -11096,7 +11197,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11576,7 +11677,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -13432,7 +13533,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13441,7 +13542,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -13760,7 +13861,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -13825,13 +13926,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -13887,7 +13988,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -18682,7 +18783,7 @@
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
-#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< Reserved: needed for softawre compatibility (DMA Enable) */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
@@ -21223,7 +21324,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -21310,12 +21411,6 @@
#define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
#define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
-#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
-#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
-#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
-#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
-#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
-#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
@@ -23178,7 +23273,7 @@
/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
#define HRTIM_BMCR_BME_Pos (0U)
#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
-#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
+#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enable */
#define HRTIM_BMCR_BMOM_Pos (1U)
#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
@@ -26125,6 +26220,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h755xx.h b/Include/stm32h755xx.h
index d5d61b3..41ffb30 100644
--- a/Include/stm32h755xx.h
+++ b/Include/stm32h755xx.h
@@ -667,7 +667,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -930,6 +930,15 @@
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1803,7 +1812,7 @@
{
__IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
__IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
+ __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */
__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
__IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
__IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
@@ -2108,6 +2117,94 @@
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+ uint32_t RESERVED25[1021]; /*!< Reserved, Address offset: 0x4710C-0x480FC */
+ __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */
+ __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */
+ __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2470,6 +2567,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2773,6 +2873,8 @@
#define USB_OTG_FS USB2_OTG_FS
#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -3245,7 +3347,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4138,7 +4240,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -10848,8 +10950,11 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
-#define FLASH_SIZE 0x200000UL /* 2 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
@@ -11221,7 +11326,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11701,7 +11806,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -13948,7 +14053,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13957,7 +14062,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -14276,7 +14381,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -14341,13 +14446,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -14403,7 +14508,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -19309,7 +19414,7 @@
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
-#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< Reserved: needed for softawre compatibility (DMA Enable) */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
@@ -21877,7 +21982,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -21973,12 +22078,6 @@
#define DBGMCU_CR_DBG_STANDBYD2_Pos (5U)
#define DBGMCU_CR_DBG_STANDBYD2_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */
#define DBGMCU_CR_DBG_STANDBYD2 DBGMCU_CR_DBG_STANDBYD2_Msk
-#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
-#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
-#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
-#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
-#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
-#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
@@ -23943,7 +24042,7 @@
/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
#define HRTIM_BMCR_BME_Pos (0U)
#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
-#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
+#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enable */
#define HRTIM_BMCR_BMOM_Pos (1U)
#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
@@ -26897,6 +26996,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h757xx.h b/Include/stm32h757xx.h
index c3e4028..d125e36 100644
--- a/Include/stm32h757xx.h
+++ b/Include/stm32h757xx.h
@@ -668,7 +668,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -762,7 +762,7 @@
uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
__IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
__IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
- __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */
__IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
__IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
__IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
@@ -1011,6 +1011,15 @@
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1884,7 +1893,7 @@
{
__IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
__IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
- __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
+ __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */
__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
__IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
__IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
@@ -2189,6 +2198,94 @@
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+ uint32_t RESERVED25[1021]; /*!< Reserved, Address offset: 0x4710C-0x480FC */
+ __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */
+ __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */
+ __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2552,6 +2649,9 @@
#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2856,6 +2956,8 @@
#define USB_OTG_FS USB2_OTG_FS
#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -3328,7 +3430,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -4221,7 +4323,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -9904,7 +10006,7 @@
#define DSI_LCOLCR_LPE_Pos (8U)
#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
-#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
+#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosely Packet Enable */
/******************* Bit definition for DSI_LPCR register ***************/
#define DSI_LPCR_DEP_Pos (0U)
@@ -14005,8 +14107,11 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
-#define FLASH_SIZE 0x200000UL /* 2 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
@@ -14378,7 +14483,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -14858,7 +14963,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -17105,7 +17210,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -17114,7 +17219,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -17433,7 +17538,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -17498,13 +17603,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -17560,7 +17665,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -22482,7 +22587,7 @@
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
-#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< Reserved: needed for softawre compatibility (DMA Enable) */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
@@ -25050,7 +25155,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -25146,12 +25251,6 @@
#define DBGMCU_CR_DBG_STANDBYD2_Pos (5U)
#define DBGMCU_CR_DBG_STANDBYD2_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */
#define DBGMCU_CR_DBG_STANDBYD2 DBGMCU_CR_DBG_STANDBYD2_Msk
-#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
-#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
-#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
-#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
-#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
-#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
@@ -27116,7 +27215,7 @@
/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
#define HRTIM_BMCR_BME_Pos (0U)
#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
-#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
+#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enable */
#define HRTIM_BMCR_BMOM_Pos (1U)
#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
@@ -30070,6 +30169,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h7a3xx.h b/Include/stm32h7a3xx.h
index 4e9445b..98214a9 100644
--- a/Include/stm32h7a3xx.h
+++ b/Include/stm32h7a3xx.h
@@ -651,7 +651,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -728,6 +728,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1824,6 +1833,117 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[959]; /*!< Reserved, Address offset: 0x910C-0xA004 */
+ __IO uint32_t AXI_TARG9_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 9 bus matrix issuing functionality register, Address offset: 0xA008 */
+ uint32_t RESERVED120[6]; /*!< Reserved, Address offset: 0xA00C-0xA020 */
+ __IO uint32_t AXI_TARG9_FN_MOD2; /*!< AXI interconnect - TARG 9 bus matrix functionality 2 register, Address offset: 0xA024 */
+ uint32_t RESERVED121[56]; /*!< Reserved, Address offset: 0xA028-0xA104 */
+ __IO uint32_t AXI_TARG9_FN_MOD; /*!< AXI interconnect - TARG 9 issuing functionality modification register, Address offset: 0xA108 */
+ uint32_t RESERVED122[959]; /*!< Reserved, Address offset: 0xA10C-0xB004 */
+ __IO uint32_t AXI_TARG10_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 10 bus matrix issuing functionality register, Address offset: 0xB008 */
+ uint32_t RESERVED123[6]; /*!< Reserved, Address offset: 0xB00C-0xB020 */
+ __IO uint32_t AXI_TARG10_FN_MOD2; /*!< AXI interconnect - TARG 10 bus matrix functionality 2 register, Address offset: 0xB024 */
+ uint32_t RESERVED124[56]; /*!< Reserved, Address offset: 0xB028-0xB104 */
+ __IO uint32_t AXI_TARG10_FN_MOD; /*!< AXI interconnect - TARG 10 issuing functionality modification register, Address offset: 0xB108 */
+ uint32_t RESERVED125[968]; /*!< Reserved, Address offset: 0xB10C-0xC028 */
+ __IO uint32_t AXI_TARG10_FN_MOD_LB; /*!< AXI interconnect - TARG 10 long burst functionality modification register, Address offset: 0xC02C */
+ uint32_t RESERVED126[55293]; /*!< Reserved, Address offset: 0xC030-0xC104 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+ uint32_t RESERVED25[966]; /*!< Reserved, Address offset: 0x4710C-0x48020 */
+ __IO uint32_t AXI_INI7_FN_MOD2; /*!< AXI interconnect - INI 7 functionality modification 2 register, Address offset: 0x48024 */
+ __IO uint32_t AXI_INI7_FN_MOD_AHB; /*!< AXI interconnect - INI 7 AHB functionality modification register, Address offset: 0x48028 */
+ uint32_t RESERVED26[53]; /*!< Reserved, Address offset: 0x4802C-0x480FC */
+ __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */
+ __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */
+ __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2181,6 +2301,9 @@
#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2463,6 +2586,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -2935,7 +3060,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -3815,7 +3940,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -8481,8 +8606,11 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x08FFF80CU
#define FLASH_SECTOR_TOTAL 128U /* 128 sectors */
-#define FLASH_SIZE 0x200000UL /* 2 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */
@@ -8836,7 +8964,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -9316,7 +9444,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -9378,10 +9506,10 @@
#define GFXMMU_CR_PD GFXMMU_CR_PD_Msk /*!< Prefetch Disable */
#define GFXMMU_CR_OC_Pos (16U)
#define GFXMMU_CR_OC_Msk (0x1UL << GFXMMU_CR_OC_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outter Cachability */
+#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outer Cachability */
#define GFXMMU_CR_OB_Pos (17U)
#define GFXMMU_CR_OB_Msk (0x1UL << GFXMMU_CR_OB_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outter Bufferability */
+#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outer Bufferability */
/****************** Bits definition for GFXMMU_SR register ********************/
#define GFXMMU_SR_B0OF_Pos (0U)
@@ -11239,7 +11367,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -11248,7 +11376,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -11567,7 +11695,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -11632,13 +11760,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -11694,7 +11822,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -19652,7 +19780,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -21881,6 +22009,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h7a3xxq.h b/Include/stm32h7a3xxq.h
index 5fa70bd..202ec04 100644
--- a/Include/stm32h7a3xxq.h
+++ b/Include/stm32h7a3xxq.h
@@ -652,7 +652,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -729,6 +729,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1825,6 +1834,117 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[959]; /*!< Reserved, Address offset: 0x910C-0xA004 */
+ __IO uint32_t AXI_TARG9_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 9 bus matrix issuing functionality register, Address offset: 0xA008 */
+ uint32_t RESERVED120[6]; /*!< Reserved, Address offset: 0xA00C-0xA020 */
+ __IO uint32_t AXI_TARG9_FN_MOD2; /*!< AXI interconnect - TARG 9 bus matrix functionality 2 register, Address offset: 0xA024 */
+ uint32_t RESERVED121[56]; /*!< Reserved, Address offset: 0xA028-0xA104 */
+ __IO uint32_t AXI_TARG9_FN_MOD; /*!< AXI interconnect - TARG 9 issuing functionality modification register, Address offset: 0xA108 */
+ uint32_t RESERVED122[959]; /*!< Reserved, Address offset: 0xA10C-0xB004 */
+ __IO uint32_t AXI_TARG10_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 10 bus matrix issuing functionality register, Address offset: 0xB008 */
+ uint32_t RESERVED123[6]; /*!< Reserved, Address offset: 0xB00C-0xB020 */
+ __IO uint32_t AXI_TARG10_FN_MOD2; /*!< AXI interconnect - TARG 10 bus matrix functionality 2 register, Address offset: 0xB024 */
+ uint32_t RESERVED124[56]; /*!< Reserved, Address offset: 0xB028-0xB104 */
+ __IO uint32_t AXI_TARG10_FN_MOD; /*!< AXI interconnect - TARG 10 issuing functionality modification register, Address offset: 0xB108 */
+ uint32_t RESERVED125[968]; /*!< Reserved, Address offset: 0xB10C-0xC028 */
+ __IO uint32_t AXI_TARG10_FN_MOD_LB; /*!< AXI interconnect - TARG 10 long burst functionality modification register, Address offset: 0xC02C */
+ uint32_t RESERVED126[55293]; /*!< Reserved, Address offset: 0xC030-0xC104 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+ uint32_t RESERVED25[966]; /*!< Reserved, Address offset: 0x4710C-0x48020 */
+ __IO uint32_t AXI_INI7_FN_MOD2; /*!< AXI interconnect - INI 7 functionality modification 2 register, Address offset: 0x48024 */
+ __IO uint32_t AXI_INI7_FN_MOD_AHB; /*!< AXI interconnect - INI 7 AHB functionality modification register, Address offset: 0x48028 */
+ uint32_t RESERVED26[53]; /*!< Reserved, Address offset: 0x4802C-0x480FC */
+ __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */
+ __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */
+ __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2182,6 +2302,9 @@
#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2464,6 +2587,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -2936,7 +3061,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -3816,7 +3941,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -8482,8 +8607,11 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x08FFF80CU
#define FLASH_SECTOR_TOTAL 128U /* 128 sectors */
-#define FLASH_SIZE 0x200000UL /* 2 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */
@@ -8837,7 +8965,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -9317,7 +9445,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -9379,10 +9507,10 @@
#define GFXMMU_CR_PD GFXMMU_CR_PD_Msk /*!< Prefetch Disable */
#define GFXMMU_CR_OC_Pos (16U)
#define GFXMMU_CR_OC_Msk (0x1UL << GFXMMU_CR_OC_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outter Cachability */
+#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outer Cachability */
#define GFXMMU_CR_OB_Pos (17U)
#define GFXMMU_CR_OB_Msk (0x1UL << GFXMMU_CR_OB_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outter Bufferability */
+#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outer Bufferability */
/****************** Bits definition for GFXMMU_SR register ********************/
#define GFXMMU_SR_B0OF_Pos (0U)
@@ -11240,7 +11368,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -11249,7 +11377,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -11568,7 +11696,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -11633,13 +11761,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -11695,7 +11823,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -19664,7 +19792,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -21893,6 +22021,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h7b0xx.h b/Include/stm32h7b0xx.h
index 3daaa17..790f0d8 100644
--- a/Include/stm32h7b0xx.h
+++ b/Include/stm32h7b0xx.h
@@ -654,7 +654,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -731,6 +731,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1930,6 +1939,117 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[959]; /*!< Reserved, Address offset: 0x910C-0xA004 */
+ __IO uint32_t AXI_TARG9_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 9 bus matrix issuing functionality register, Address offset: 0xA008 */
+ uint32_t RESERVED120[6]; /*!< Reserved, Address offset: 0xA00C-0xA020 */
+ __IO uint32_t AXI_TARG9_FN_MOD2; /*!< AXI interconnect - TARG 9 bus matrix functionality 2 register, Address offset: 0xA024 */
+ uint32_t RESERVED121[56]; /*!< Reserved, Address offset: 0xA028-0xA104 */
+ __IO uint32_t AXI_TARG9_FN_MOD; /*!< AXI interconnect - TARG 9 issuing functionality modification register, Address offset: 0xA108 */
+ uint32_t RESERVED122[959]; /*!< Reserved, Address offset: 0xA10C-0xB004 */
+ __IO uint32_t AXI_TARG10_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 10 bus matrix issuing functionality register, Address offset: 0xB008 */
+ uint32_t RESERVED123[6]; /*!< Reserved, Address offset: 0xB00C-0xB020 */
+ __IO uint32_t AXI_TARG10_FN_MOD2; /*!< AXI interconnect - TARG 10 bus matrix functionality 2 register, Address offset: 0xB024 */
+ uint32_t RESERVED124[56]; /*!< Reserved, Address offset: 0xB028-0xB104 */
+ __IO uint32_t AXI_TARG10_FN_MOD; /*!< AXI interconnect - TARG 10 issuing functionality modification register, Address offset: 0xB108 */
+ uint32_t RESERVED125[968]; /*!< Reserved, Address offset: 0xB10C-0xC028 */
+ __IO uint32_t AXI_TARG10_FN_MOD_LB; /*!< AXI interconnect - TARG 10 long burst functionality modification register, Address offset: 0xC02C */
+ uint32_t RESERVED126[55293]; /*!< Reserved, Address offset: 0xC030-0xC104 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+ uint32_t RESERVED25[966]; /*!< Reserved, Address offset: 0x4710C-0x48020 */
+ __IO uint32_t AXI_INI7_FN_MOD2; /*!< AXI interconnect - INI 7 functionality modification 2 register, Address offset: 0x48024 */
+ __IO uint32_t AXI_INI7_FN_MOD_AHB; /*!< AXI interconnect - INI 7 AHB functionality modification register, Address offset: 0x48028 */
+ uint32_t RESERVED26[53]; /*!< Reserved, Address offset: 0x4802C-0x480FC */
+ __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */
+ __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */
+ __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2301,6 +2421,9 @@
#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2598,6 +2721,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -3070,7 +3195,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -3950,7 +4075,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -8735,9 +8860,12 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x08FFF80CU
#define FLASH_SECTOR_TOTAL 16U /* 16 sectors */
#define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */
-#define FLASH_SIZE 0x00020000UL /* 128 KB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x20000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x20000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 128 KB */
#define FLASH_BANK_SIZE FLASH_SIZE /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */
#define FLASH_NB_32BITWORD_IN_FLASHWORD 4U /* 128 bits */
@@ -8932,9 +9060,6 @@
#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */
-#define FLASH_OPTCR_SWAP_BANK_Pos (31U)
-#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
-#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */
/******************* Bits definition for FLASH_OPTSR register ***************/
#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
@@ -8980,9 +9105,6 @@
#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */
-#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
-#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
-#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */
/******************* Bits definition for FLASH_OPTCCR register *******************/
#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
@@ -9089,7 +9211,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -9569,7 +9691,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -9631,10 +9753,10 @@
#define GFXMMU_CR_PD GFXMMU_CR_PD_Msk /*!< Prefetch Disable */
#define GFXMMU_CR_OC_Pos (16U)
#define GFXMMU_CR_OC_Msk (0x1UL << GFXMMU_CR_OC_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outter Cachability */
+#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outer Cachability */
#define GFXMMU_CR_OB_Pos (17U)
#define GFXMMU_CR_OB_Msk (0x1UL << GFXMMU_CR_OB_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outter Bufferability */
+#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outer Bufferability */
/****************** Bits definition for GFXMMU_SR register ********************/
#define GFXMMU_SR_B0OF_Pos (0U)
@@ -11568,7 +11690,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -11577,7 +11699,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -11896,7 +12018,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -11961,13 +12083,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -12023,7 +12145,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -20138,7 +20260,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -22371,6 +22493,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h7b0xxq.h b/Include/stm32h7b0xxq.h
index 6f3a329..f21a96a 100644
--- a/Include/stm32h7b0xxq.h
+++ b/Include/stm32h7b0xxq.h
@@ -655,7 +655,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -732,6 +732,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1931,6 +1940,117 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[959]; /*!< Reserved, Address offset: 0x910C-0xA004 */
+ __IO uint32_t AXI_TARG9_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 9 bus matrix issuing functionality register, Address offset: 0xA008 */
+ uint32_t RESERVED120[6]; /*!< Reserved, Address offset: 0xA00C-0xA020 */
+ __IO uint32_t AXI_TARG9_FN_MOD2; /*!< AXI interconnect - TARG 9 bus matrix functionality 2 register, Address offset: 0xA024 */
+ uint32_t RESERVED121[56]; /*!< Reserved, Address offset: 0xA028-0xA104 */
+ __IO uint32_t AXI_TARG9_FN_MOD; /*!< AXI interconnect - TARG 9 issuing functionality modification register, Address offset: 0xA108 */
+ uint32_t RESERVED122[959]; /*!< Reserved, Address offset: 0xA10C-0xB004 */
+ __IO uint32_t AXI_TARG10_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 10 bus matrix issuing functionality register, Address offset: 0xB008 */
+ uint32_t RESERVED123[6]; /*!< Reserved, Address offset: 0xB00C-0xB020 */
+ __IO uint32_t AXI_TARG10_FN_MOD2; /*!< AXI interconnect - TARG 10 bus matrix functionality 2 register, Address offset: 0xB024 */
+ uint32_t RESERVED124[56]; /*!< Reserved, Address offset: 0xB028-0xB104 */
+ __IO uint32_t AXI_TARG10_FN_MOD; /*!< AXI interconnect - TARG 10 issuing functionality modification register, Address offset: 0xB108 */
+ uint32_t RESERVED125[968]; /*!< Reserved, Address offset: 0xB10C-0xC028 */
+ __IO uint32_t AXI_TARG10_FN_MOD_LB; /*!< AXI interconnect - TARG 10 long burst functionality modification register, Address offset: 0xC02C */
+ uint32_t RESERVED126[55293]; /*!< Reserved, Address offset: 0xC030-0xC104 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+ uint32_t RESERVED25[966]; /*!< Reserved, Address offset: 0x4710C-0x48020 */
+ __IO uint32_t AXI_INI7_FN_MOD2; /*!< AXI interconnect - INI 7 functionality modification 2 register, Address offset: 0x48024 */
+ __IO uint32_t AXI_INI7_FN_MOD_AHB; /*!< AXI interconnect - INI 7 AHB functionality modification register, Address offset: 0x48028 */
+ uint32_t RESERVED26[53]; /*!< Reserved, Address offset: 0x4802C-0x480FC */
+ __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */
+ __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */
+ __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2302,6 +2422,9 @@
#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2599,6 +2722,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -3071,7 +3196,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -3951,7 +4076,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -8736,9 +8861,12 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x08FFF80CU
#define FLASH_SECTOR_TOTAL 16U /* 16 sectors */
#define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */
-#define FLASH_SIZE 0x00020000UL /* 128 KB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x20000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x20000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 128 KB */
#define FLASH_BANK_SIZE FLASH_SIZE /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */
#define FLASH_NB_32BITWORD_IN_FLASHWORD 4U /* 128 bits */
@@ -8933,9 +9061,6 @@
#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */
-#define FLASH_OPTCR_SWAP_BANK_Pos (31U)
-#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
-#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */
/******************* Bits definition for FLASH_OPTSR register ***************/
#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
@@ -8981,9 +9106,6 @@
#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */
-#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
-#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
-#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */
/******************* Bits definition for FLASH_OPTCCR register *******************/
#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
@@ -9090,7 +9212,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -9570,7 +9692,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -9632,10 +9754,10 @@
#define GFXMMU_CR_PD GFXMMU_CR_PD_Msk /*!< Prefetch Disable */
#define GFXMMU_CR_OC_Pos (16U)
#define GFXMMU_CR_OC_Msk (0x1UL << GFXMMU_CR_OC_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outter Cachability */
+#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outer Cachability */
#define GFXMMU_CR_OB_Pos (17U)
#define GFXMMU_CR_OB_Msk (0x1UL << GFXMMU_CR_OB_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outter Bufferability */
+#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outer Bufferability */
/****************** Bits definition for GFXMMU_SR register ********************/
#define GFXMMU_SR_B0OF_Pos (0U)
@@ -11569,7 +11691,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -11578,7 +11700,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -11897,7 +12019,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -11962,13 +12084,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -12024,7 +12146,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -20150,7 +20272,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -22383,6 +22505,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h7b3xx.h b/Include/stm32h7b3xx.h
index a30a727..5da94b3 100644
--- a/Include/stm32h7b3xx.h
+++ b/Include/stm32h7b3xx.h
@@ -654,7 +654,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -731,6 +731,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1930,6 +1939,117 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[959]; /*!< Reserved, Address offset: 0x910C-0xA004 */
+ __IO uint32_t AXI_TARG9_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 9 bus matrix issuing functionality register, Address offset: 0xA008 */
+ uint32_t RESERVED120[6]; /*!< Reserved, Address offset: 0xA00C-0xA020 */
+ __IO uint32_t AXI_TARG9_FN_MOD2; /*!< AXI interconnect - TARG 9 bus matrix functionality 2 register, Address offset: 0xA024 */
+ uint32_t RESERVED121[56]; /*!< Reserved, Address offset: 0xA028-0xA104 */
+ __IO uint32_t AXI_TARG9_FN_MOD; /*!< AXI interconnect - TARG 9 issuing functionality modification register, Address offset: 0xA108 */
+ uint32_t RESERVED122[959]; /*!< Reserved, Address offset: 0xA10C-0xB004 */
+ __IO uint32_t AXI_TARG10_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 10 bus matrix issuing functionality register, Address offset: 0xB008 */
+ uint32_t RESERVED123[6]; /*!< Reserved, Address offset: 0xB00C-0xB020 */
+ __IO uint32_t AXI_TARG10_FN_MOD2; /*!< AXI interconnect - TARG 10 bus matrix functionality 2 register, Address offset: 0xB024 */
+ uint32_t RESERVED124[56]; /*!< Reserved, Address offset: 0xB028-0xB104 */
+ __IO uint32_t AXI_TARG10_FN_MOD; /*!< AXI interconnect - TARG 10 issuing functionality modification register, Address offset: 0xB108 */
+ uint32_t RESERVED125[968]; /*!< Reserved, Address offset: 0xB10C-0xC028 */
+ __IO uint32_t AXI_TARG10_FN_MOD_LB; /*!< AXI interconnect - TARG 10 long burst functionality modification register, Address offset: 0xC02C */
+ uint32_t RESERVED126[55293]; /*!< Reserved, Address offset: 0xC030-0xC104 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+ uint32_t RESERVED25[966]; /*!< Reserved, Address offset: 0x4710C-0x48020 */
+ __IO uint32_t AXI_INI7_FN_MOD2; /*!< AXI interconnect - INI 7 functionality modification 2 register, Address offset: 0x48024 */
+ __IO uint32_t AXI_INI7_FN_MOD_AHB; /*!< AXI interconnect - INI 7 AHB functionality modification register, Address offset: 0x48028 */
+ uint32_t RESERVED26[53]; /*!< Reserved, Address offset: 0x4802C-0x480FC */
+ __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */
+ __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */
+ __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2301,6 +2421,9 @@
#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2598,6 +2721,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -3070,7 +3195,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -3950,7 +4075,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -8735,8 +8860,11 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x08FFF80CU
#define FLASH_SECTOR_TOTAL 128U /* 128 sectors */
-#define FLASH_SIZE 0x200000UL /* 2 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */
@@ -9090,7 +9218,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -9570,7 +9698,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -9632,10 +9760,10 @@
#define GFXMMU_CR_PD GFXMMU_CR_PD_Msk /*!< Prefetch Disable */
#define GFXMMU_CR_OC_Pos (16U)
#define GFXMMU_CR_OC_Msk (0x1UL << GFXMMU_CR_OC_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outter Cachability */
+#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outer Cachability */
#define GFXMMU_CR_OB_Pos (17U)
#define GFXMMU_CR_OB_Msk (0x1UL << GFXMMU_CR_OB_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outter Bufferability */
+#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outer Bufferability */
/****************** Bits definition for GFXMMU_SR register ********************/
#define GFXMMU_SR_B0OF_Pos (0U)
@@ -11569,7 +11697,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -11578,7 +11706,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -11897,7 +12025,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -11962,13 +12090,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -12024,7 +12152,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -20139,7 +20267,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -22372,6 +22500,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h7b3xxq.h b/Include/stm32h7b3xxq.h
index 3e7dba5..d1c015d 100644
--- a/Include/stm32h7b3xxq.h
+++ b/Include/stm32h7b3xxq.h
@@ -655,7 +655,7 @@
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
- uint32_t RESERVED0; /*!< Reserved, 0x68 */
+ uint32_t RESERVED0; /*!< Reserved, 0x6C */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
@@ -732,6 +732,15 @@
__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
}EXTI_TypeDef;
+/**
+ * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+ * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+ * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+ * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
+ * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+ * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+ */
+
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
@@ -1931,6 +1940,117 @@
* @}
*/
+/**
+ * @brief Global Programmer View
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
+ __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
+ uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
+ uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
+ uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
+ __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
+ __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
+ __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
+ __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
+ __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
+ __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
+ __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
+ __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
+ uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
+ __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
+ uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
+ __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
+ __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
+ uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
+ __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
+ uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
+ __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
+ uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
+ __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
+ __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
+ uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
+ __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
+ uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
+ __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
+ uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
+ __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
+ uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
+ __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
+ uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
+ __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
+ uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
+ __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
+ uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
+ __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
+ uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
+ __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
+ uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
+ __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
+ uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */
+ __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */
+ uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */
+ __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */
+ uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */
+ __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */
+ uint32_t RESERVED119[959]; /*!< Reserved, Address offset: 0x910C-0xA004 */
+ __IO uint32_t AXI_TARG9_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 9 bus matrix issuing functionality register, Address offset: 0xA008 */
+ uint32_t RESERVED120[6]; /*!< Reserved, Address offset: 0xA00C-0xA020 */
+ __IO uint32_t AXI_TARG9_FN_MOD2; /*!< AXI interconnect - TARG 9 bus matrix functionality 2 register, Address offset: 0xA024 */
+ uint32_t RESERVED121[56]; /*!< Reserved, Address offset: 0xA028-0xA104 */
+ __IO uint32_t AXI_TARG9_FN_MOD; /*!< AXI interconnect - TARG 9 issuing functionality modification register, Address offset: 0xA108 */
+ uint32_t RESERVED122[959]; /*!< Reserved, Address offset: 0xA10C-0xB004 */
+ __IO uint32_t AXI_TARG10_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 10 bus matrix issuing functionality register, Address offset: 0xB008 */
+ uint32_t RESERVED123[6]; /*!< Reserved, Address offset: 0xB00C-0xB020 */
+ __IO uint32_t AXI_TARG10_FN_MOD2; /*!< AXI interconnect - TARG 10 bus matrix functionality 2 register, Address offset: 0xB024 */
+ uint32_t RESERVED124[56]; /*!< Reserved, Address offset: 0xB028-0xB104 */
+ __IO uint32_t AXI_TARG10_FN_MOD; /*!< AXI interconnect - TARG 10 issuing functionality modification register, Address offset: 0xB108 */
+ uint32_t RESERVED125[968]; /*!< Reserved, Address offset: 0xB10C-0xC028 */
+ __IO uint32_t AXI_TARG10_FN_MOD_LB; /*!< AXI interconnect - TARG 10 long burst functionality modification register, Address offset: 0xC02C */
+ uint32_t RESERVED126[55293]; /*!< Reserved, Address offset: 0xC030-0xC104 */
+ __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
+ __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
+ uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
+ __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
+ __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
+ __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
+ uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
+ __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
+ __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
+ __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
+ uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
+ __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
+ __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
+ uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
+ __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
+ __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
+ __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
+ uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
+ __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
+ __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
+ __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
+ uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
+ __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
+ __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
+ __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
+ uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
+ __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
+ __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
+ __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
+ uint32_t RESERVED25[966]; /*!< Reserved, Address offset: 0x4710C-0x48020 */
+ __IO uint32_t AXI_INI7_FN_MOD2; /*!< AXI interconnect - INI 7 functionality modification 2 register, Address offset: 0x48024 */
+ __IO uint32_t AXI_INI7_FN_MOD_AHB; /*!< AXI interconnect - INI 7 AHB functionality modification register, Address offset: 0x48028 */
+ uint32_t RESERVED26[53]; /*!< Reserved, Address offset: 0x4802C-0x480FC */
+ __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */
+ __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */
+ __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */
+
+} GPV_TypeDef;
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -2302,6 +2422,9 @@
#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
+
+#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
+
/**
* @}
*/
@@ -2599,6 +2722,8 @@
#define USB_OTG_HS USB1_OTG_HS
#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
+#define GPV ((GPV_TypeDef *) GPV_BASE)
+
/**
* @}
*/
@@ -3071,7 +3196,7 @@
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
@@ -3951,7 +4076,7 @@
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -8736,8 +8861,11 @@
/*
* @brief FLASH Global Defines
*/
+#define FLASH_SIZE_DATA_REGISTER 0x08FFF80CU
#define FLASH_SECTOR_TOTAL 128U /* 128 sectors */
-#define FLASH_SIZE 0x200000UL /* 2 MB */
+#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */
@@ -9091,7 +9219,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -9571,7 +9699,7 @@
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
-#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ******************/
#define FMC_SDSR_RE_Pos (0U)
@@ -9633,10 +9761,10 @@
#define GFXMMU_CR_PD GFXMMU_CR_PD_Msk /*!< Prefetch Disable */
#define GFXMMU_CR_OC_Pos (16U)
#define GFXMMU_CR_OC_Msk (0x1UL << GFXMMU_CR_OC_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outter Cachability */
+#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outer Cachability */
#define GFXMMU_CR_OB_Pos (17U)
#define GFXMMU_CR_OB_Msk (0x1UL << GFXMMU_CR_OB_Pos) /*!< 0x00002000 */
-#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outter Bufferability */
+#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outer Bufferability */
/****************** Bits definition for GFXMMU_SR register ********************/
#define GFXMMU_SR_B0OF_Pos (0U)
@@ -11570,7 +11698,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -11579,7 +11707,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -11898,7 +12026,7 @@
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
-#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
+#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
@@ -11963,13 +12091,13 @@
#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
-#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
+#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
-#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
+#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
-#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
+#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
@@ -12025,7 +12153,7 @@
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
-#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
+#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
@@ -20151,7 +20279,7 @@
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
-#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
+#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
@@ -22384,6 +22512,7 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
diff --git a/Include/stm32h7xx.h b/Include/stm32h7xx.h
index d9896bc..f36b58f 100644
--- a/Include/stm32h7xx.h
+++ b/Include/stm32h7xx.h
@@ -101,16 +101,16 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.9.0
+ * @brief CMSIS Device version number V1.10.0
*/
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x09) /*!< [23:16] sub1 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
- |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
- |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
- |(__CMSIS_DEVICE_HAL_VERSION_RC))
+#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
+ |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
+ |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
+ |(__STM32H7xx_CMSIS_DEVICE_VERSION_RC))
/**
* @}
diff --git a/License.md b/License.md
index 64783f9..72fbf79 100644
--- a/License.md
+++ b/License.md
@@ -80,5 +80,4 @@
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
- limitations under the License.
-
+ limitations under the License.
\ No newline at end of file
diff --git a/README.md b/README.md
index c12e081..b2dabf0 100644
--- a/README.md
+++ b/README.md
@@ -1,19 +1,21 @@
# STM32CubeH7 CMSIS Device MCU Component
+
+
## Overview
-**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
+**STM32Cube** is an STMicroelectronics original initiative to ease developers' life by reducing efforts, time and cost.
-**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
- * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
- * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
- * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
- * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ...
- * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
+ * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+ * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
+ * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
+ * A consistent set of middleware components such as RTOS, USB, FatFS, graphics, touch sensing library...
+ * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
-Two models of publication are proposed for the STM32Cube embedded software :
- * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
- * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions.
+Two models of publication are proposed for the STM32Cube embedded software:
+ * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
+ * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
## Description
@@ -29,13 +31,16 @@
CMSIS Device H7 | CMSIS Core | Was delivered in the full MCU package
--------------- | ---------- | -------------------------------------
-Tag v1.6.0 | Tag v5.4.0 | Tag v1.5.0 (and following, if any, till next CMSIS tag)
-Tag v1.7.0 | Tag v5.4.0 | Tag v1.6.0 (and following, if any, till next CMSIS tag)
-Tag v1.8.0 | Tag v5.4.0 | Tag v1.7.0 (and following, if any, till next CMSIS tag)
+Tag v1.6.0 | Tag v5.4.0 | Tag v1.5.0 (and following, if any, till next CMSIS tag)
+Tag v1.7.0 | Tag v5.4.0 | Tag v1.6.0 (and following, if any, till next CMSIS tag)
+Tag v1.8.0 | Tag v5.4.0 | Tag v1.7.0 (and following, if any, till next CMSIS tag)
+Tag v1.9.0 | Tag v5.4.0 | Tag v1.8.0 (and following, if any, till next CMSIS tag)
+Tag v1.10.0 | Tag v5.6.0 | Tag v1.9.0 (and following, if any, till next CMSIS tag)
The full **STM32CubeH7** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH7).
## Troubleshooting
+
If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_h7/issues/new).
-For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
\ No newline at end of file
diff --git a/Release_Notes.html b/Release_Notes.html
index 7f1d1da..c429775 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -38,10 +38,28 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section11" checked aria-hidden="true"> <label for="collapse-section11" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
+<input type="checkbox" id="collapse-section12" checked aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
+<li>Fix minor issues related to English typo in comments of registers and fields description</li>
+<li>Update STM32H7 devices header files to add GPV registers definition, base address and instance</li>
+<li>Update “FLASH_SIZE” define in STM32H7 devices header files to retrieve the flash size from the dedicated FLASH_SIZE_DATA_REGISTER register</li>
+<li>Update “IS_TIM_MASTER_INSTANCE” define in STM32H7 devices header files to consider TIM12 that can be a master timer</li>
+<li>Remove extra fields defines related to Domain D3 in DBGMCU_CR_DBG register</li>
+<li>Remove “FLASH_OPTCR_SWAP_BANK” and “FLASH_OPTSR_SWAP_BANK_OPT” field definitions from STM32H750xx device header file (that is a value line single bank device)</li>
+<li>Fix "__STM32H7xx_CMSIS_DEVICE_VERSION" definition in stm32h7xx.h file by referring to the right “STM32H7xx_CMSIS_DEVICE” defines</li>
+<li>Update “SystemCoreClockUpdate” function implementation in system_stm32h7xx.c files with default system_clock and PLL source set to HIS instead of CSI (as per the product specification)</li>
+<li>Update and improve GCC startup files to reduce the number of loads inside of the .data copy</li>
+<li>Update MDK-ARM template scatter files for dual core devices to fix a typo within the IRAM1 section</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
<li>Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices:
<ul>
<li>Add “stm32h723xx.h” , “stm32h725xx.h”, “stm32h733xx.h”, “stm32h735xx.h”, “stm32h730xx.h” and “stm32h730xxq.h” files</li>
@@ -98,7 +116,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>General updates to align Bits and registers definitions with the STM32H7 reference manual</li>
<li>Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero</li>
@@ -119,7 +137,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li><p>General updates to align Bit and registers definition with the STM32H7 reference manual</p></li>
<li>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices:
@@ -142,14 +160,14 @@
</ul></li>
<li>Update USB_OTG_GAHBCFG bit definition: to be aligned with LL_USB usage</li>
<li><p>Add USB_OTG_DOEPMSK_AHBERRM, USB_OTG_DOEPMSK_BERRM, USB_OTG_DOEPMSK_NAKM, USB_OTG_DOEPMSK_NYETM, USB_OTG_DIEPINT_AHBERR, USB_OTG_DIEPINT_INEPNM, USB_OTG_DOEPINT_AHBERR, USB_OTG_DOEPINT_OUTPKTERR, USB_OTG_DOEPINT_BERR, USB_OTG_DOEPINT_NAK and USB_OTG_DOEPINT_STPKTRX bit definitions</p></li>
-<li><p>Update IS_TIM_REMAP_INSTANCE and IS_TIM_SYNCHRO_INSTANCE macro implemenation</p></li>
+<li><p>Update IS_TIM_REMAP_INSTANCE and IS_TIM_SYNCHRO_INSTANCE macro implementation</p></li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li>
<li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li>
@@ -164,7 +182,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
<li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li>
@@ -228,7 +246,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li><strong>Patch Release on top of V1.3.0</strong></li>
<li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:
@@ -241,7 +259,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>STM32H7xx include files:
<ul>
@@ -286,7 +304,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>Add support for stm32h750xx value line devices:
<ul>
@@ -299,7 +317,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>Update FDCAN bit definition</li>
<li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li>
@@ -309,7 +327,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li>Update USB OTG bit definition</li>
<li>Adjust PLL fractional computation</li>
@@ -319,7 +337,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li>First official release for <strong>STM32H743xx/753xx</strong> devices</li>
</ul>
diff --git a/Source/Templates/arm/linker/stm32h745xg_flash_CM4.sct b/Source/Templates/arm/linker/stm32h745xg_flash_CM4.sct
index 36c6cf9..d7925d2 100644
--- a/Source/Templates/arm/linker/stm32h745xg_flash_CM4.sct
+++ b/Source/Templates/arm/linker/stm32h745xg_flash_CM4.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x10000000 0x10048000{ ; RW data
+ RW_IRAM1 0x10000000 0x00048000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h745xg_flash_CM7.sct b/Source/Templates/arm/linker/stm32h745xg_flash_CM7.sct
index 76a91ad..b1ad9a8 100644
--- a/Source/Templates/arm/linker/stm32h745xg_flash_CM7.sct
+++ b/Source/Templates/arm/linker/stm32h745xg_flash_CM7.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x20000000 0x20020000{ ; RW data
+ RW_IRAM1 0x20000000 0x00020000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h745xx_flash_CM4.sct b/Source/Templates/arm/linker/stm32h745xx_flash_CM4.sct
index 0c0809d..ae5556b 100644
--- a/Source/Templates/arm/linker/stm32h745xx_flash_CM4.sct
+++ b/Source/Templates/arm/linker/stm32h745xx_flash_CM4.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x10000000 0x10048000{ ; RW data
+ RW_IRAM1 0x10000000 0x00048000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h745xx_flash_CM7.sct b/Source/Templates/arm/linker/stm32h745xx_flash_CM7.sct
index a652783..3c1ccf3 100644
--- a/Source/Templates/arm/linker/stm32h745xx_flash_CM7.sct
+++ b/Source/Templates/arm/linker/stm32h745xx_flash_CM7.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x20000000 0x20020000{ ; RW data
+ RW_IRAM1 0x20000000 0x00020000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h745xx_sram1_CM7.sct b/Source/Templates/arm/linker/stm32h745xx_sram1_CM7.sct
index 148edb4..e756dbc 100644
--- a/Source/Templates/arm/linker/stm32h745xx_sram1_CM7.sct
+++ b/Source/Templates/arm/linker/stm32h745xx_sram1_CM7.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x24040000 0x24080000{ ; RW data
+ RW_IRAM1 0x24040000 0x00040000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h745xx_sram2_CM4.sct b/Source/Templates/arm/linker/stm32h745xx_sram2_CM4.sct
index b156ac6..db51c42 100644
--- a/Source/Templates/arm/linker/stm32h745xx_sram2_CM4.sct
+++ b/Source/Templates/arm/linker/stm32h745xx_sram2_CM4.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x10020000 0x10048000{ ; RW data
+ RW_IRAM1 0x10020000 0x00028000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h747xg_flash_CM4.sct b/Source/Templates/arm/linker/stm32h747xg_flash_CM4.sct
index 36c6cf9..d7925d2 100644
--- a/Source/Templates/arm/linker/stm32h747xg_flash_CM4.sct
+++ b/Source/Templates/arm/linker/stm32h747xg_flash_CM4.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x10000000 0x10048000{ ; RW data
+ RW_IRAM1 0x10000000 0x00048000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h747xg_flash_CM7.sct b/Source/Templates/arm/linker/stm32h747xg_flash_CM7.sct
index 76a91ad..b1ad9a8 100644
--- a/Source/Templates/arm/linker/stm32h747xg_flash_CM7.sct
+++ b/Source/Templates/arm/linker/stm32h747xg_flash_CM7.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x20000000 0x20020000{ ; RW data
+ RW_IRAM1 0x20000000 0x00020000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h747xx_flash_CM4.sct b/Source/Templates/arm/linker/stm32h747xx_flash_CM4.sct
index 0c0809d..ae5556b 100644
--- a/Source/Templates/arm/linker/stm32h747xx_flash_CM4.sct
+++ b/Source/Templates/arm/linker/stm32h747xx_flash_CM4.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x10000000 0x10048000{ ; RW data
+ RW_IRAM1 0x10000000 0x00048000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h747xx_flash_CM7.sct b/Source/Templates/arm/linker/stm32h747xx_flash_CM7.sct
index a652783..3c1ccf3 100644
--- a/Source/Templates/arm/linker/stm32h747xx_flash_CM7.sct
+++ b/Source/Templates/arm/linker/stm32h747xx_flash_CM7.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x20000000 0x20020000{ ; RW data
+ RW_IRAM1 0x20000000 0x00020000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h747xx_sram1_CM7.sct b/Source/Templates/arm/linker/stm32h747xx_sram1_CM7.sct
index 148edb4..e756dbc 100644
--- a/Source/Templates/arm/linker/stm32h747xx_sram1_CM7.sct
+++ b/Source/Templates/arm/linker/stm32h747xx_sram1_CM7.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x24040000 0x24080000{ ; RW data
+ RW_IRAM1 0x24040000 0x00040000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h747xx_sram2_CM4.sct b/Source/Templates/arm/linker/stm32h747xx_sram2_CM4.sct
index b156ac6..db51c42 100644
--- a/Source/Templates/arm/linker/stm32h747xx_sram2_CM4.sct
+++ b/Source/Templates/arm/linker/stm32h747xx_sram2_CM4.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x10020000 0x10048000{ ; RW data
+ RW_IRAM1 0x10020000 0x00028000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h755xx_flash_CM4.sct b/Source/Templates/arm/linker/stm32h755xx_flash_CM4.sct
index 0c0809d..ae5556b 100644
--- a/Source/Templates/arm/linker/stm32h755xx_flash_CM4.sct
+++ b/Source/Templates/arm/linker/stm32h755xx_flash_CM4.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x10000000 0x10048000{ ; RW data
+ RW_IRAM1 0x10000000 0x00048000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h755xx_flash_CM7.sct b/Source/Templates/arm/linker/stm32h755xx_flash_CM7.sct
index a652783..3c1ccf3 100644
--- a/Source/Templates/arm/linker/stm32h755xx_flash_CM7.sct
+++ b/Source/Templates/arm/linker/stm32h755xx_flash_CM7.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x20000000 0x20020000{ ; RW data
+ RW_IRAM1 0x20000000 0x00020000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h755xx_sram1_CM7.sct b/Source/Templates/arm/linker/stm32h755xx_sram1_CM7.sct
index 148edb4..e756dbc 100644
--- a/Source/Templates/arm/linker/stm32h755xx_sram1_CM7.sct
+++ b/Source/Templates/arm/linker/stm32h755xx_sram1_CM7.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x24040000 0x24080000{ ; RW data
+ RW_IRAM1 0x24040000 0x00040000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h755xx_sram2_CM4.sct b/Source/Templates/arm/linker/stm32h755xx_sram2_CM4.sct
index b156ac6..db51c42 100644
--- a/Source/Templates/arm/linker/stm32h755xx_sram2_CM4.sct
+++ b/Source/Templates/arm/linker/stm32h755xx_sram2_CM4.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x10020000 0x10048000{ ; RW data
+ RW_IRAM1 0x10020000 0x00028000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h757xx_flash_CM4.sct b/Source/Templates/arm/linker/stm32h757xx_flash_CM4.sct
index 0c0809d..ae5556b 100644
--- a/Source/Templates/arm/linker/stm32h757xx_flash_CM4.sct
+++ b/Source/Templates/arm/linker/stm32h757xx_flash_CM4.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x10000000 0x10048000{ ; RW data
+ RW_IRAM1 0x10000000 0x00048000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h757xx_flash_CM7.sct b/Source/Templates/arm/linker/stm32h757xx_flash_CM7.sct
index a652783..3c1ccf3 100644
--- a/Source/Templates/arm/linker/stm32h757xx_flash_CM7.sct
+++ b/Source/Templates/arm/linker/stm32h757xx_flash_CM7.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x20000000 0x20020000{ ; RW data
+ RW_IRAM1 0x20000000 0x00020000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h757xx_sram1_CM7.sct b/Source/Templates/arm/linker/stm32h757xx_sram1_CM7.sct
index 148edb4..e756dbc 100644
--- a/Source/Templates/arm/linker/stm32h757xx_sram1_CM7.sct
+++ b/Source/Templates/arm/linker/stm32h757xx_sram1_CM7.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x24040000 0x24080000{ ; RW data
+ RW_IRAM1 0x24040000 0x00040000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/arm/linker/stm32h757xx_sram2_CM4.sct b/Source/Templates/arm/linker/stm32h757xx_sram2_CM4.sct
index b156ac6..db51c42 100644
--- a/Source/Templates/arm/linker/stm32h757xx_sram2_CM4.sct
+++ b/Source/Templates/arm/linker/stm32h757xx_sram2_CM4.sct
@@ -8,7 +8,7 @@
*(InRoot$$Sections)
.ANY (+RO)
}
- RW_IRAM1 0x10020000 0x10048000{ ; RW data
+ RW_IRAM1 0x10020000 0x00028000{ ; RW data
.ANY (+RW +ZI)
}
}
diff --git a/Source/Templates/gcc/startup_stm32h723xx.s b/Source/Templates/gcc/startup_stm32h723xx.s
index 1398aca..6e3d456 100644
--- a/Source/Templates/gcc/startup_stm32h723xx.s
+++ b/Source/Templates/gcc/startup_stm32h723xx.s
@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32h723xx.s
* @author MCD Application Team
- * @brief STM32H723xx Devices vector table for GCC based toolchain.
+ * @brief STM32H723xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
@@ -24,7 +24,7 @@
*
******************************************************************************
*/
-
+
.syntax unified
.cpu cortex-m7
.fpu softvfp
@@ -33,10 +33,10 @@
.global g_pfnVectors
.global Default_Handler
-/* start address for the initialization values of the .data section.
+/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
-/* start address for the .data section. defined in linker script */
+/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
@@ -50,7 +50,7 @@
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
- * supplied main() routine is called.
+ * supplied main() routine is called.
* @param None
* @retval : None
*/
@@ -58,53 +58,55 @@
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
-Reset_Handler:
+Reset_Handler:
ldr sp, =_estack /* set stack pointer */
-/* Call the clock system intitialization function.*/
+/* Call the clock system initialization function.*/
bl SystemInit
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
- * @brief This is the code that gets called when the processor receives an
+ * @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
- * @param None
- * @retval None
+ * @param None
+ * @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
@@ -116,13 +118,13 @@
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
-*
+*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
-
-
+
+
g_pfnVectors:
.word _estack
.word Reset_Handler
@@ -141,91 +143,91 @@
.word 0
.word PendSV_Handler
.word SysTick_Handler
-
+
/* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
- .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
- .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
- .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
- .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word 0 /* Reserved */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FMC_IRQHandler /* FMC */
- .word SDMMC1_IRQHandler /* SDMMC1 */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word ETH_IRQHandler /* Ethernet */
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
- .word 0 /* Reserved */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
- .word UART7_IRQHandler /* UART7 */
+ .word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
@@ -240,58 +242,58 @@
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
- .word SPDIF_RX_IRQHandler /* SPDIF_RX */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word 0 /* Reserved */
- .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
.word 0 /* Reserved */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
- .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
- .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
- .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
- .word 0 /* Reserved */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
- .word TIM15_IRQHandler /* TIM15 global Interrupt */
- .word TIM16_IRQHandler /* TIM16 global Interrupt */
- .word TIM17_IRQHandler /* TIM17 global Interrupt */
- .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
- .word MDIOS_IRQHandler /* MDIOS global Interrupt */
- .word 0 /* Reserved */
- .word MDMA_IRQHandler /* MDMA global Interrupt */
- .word 0 /* Reserved */
- .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
- .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
- .word 0 /* Reserved */
- .word ADC3_IRQHandler /* ADC3 global Interrupt */
- .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word 0 /* Reserved */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
- .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
- .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
- .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
- .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
- .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
- .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
- .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
- .word COMP1_IRQHandler /* COMP1 global Interrupt */
- .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
- .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
- .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
- .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
- .word LPUART1_IRQHandler /* LP UART1 interrupt */
- .word 0 /* Reserved */
- .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
- .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
- .word SAI4_IRQHandler /* SAI4 global interrupt */
- .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
- .word 0 /* Reserved */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
+ .word 0 /* Reserved */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
.word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
.word 0 /* Reserved */
@@ -309,20 +311,20 @@
/*******************************************************************************
*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
* this definition.
-*
+*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
-
+
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
-
+
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
-
+
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
@@ -339,418 +341,418 @@
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_AVD_IRQHandler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
+
+ .weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
+
+ .weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
+
+ .weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
+
+ .weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
+
+ .weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
+
+ .weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
+
+ .weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
+
+ .weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
+
+ .weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
+
+ .weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
+
+ .weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
+
+ .weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
+
+ .weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT0_IRQHandler
+
+ .weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT0_IRQHandler
+
+ .weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT1_IRQHandler
+
+ .weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT1_IRQHandler
+
+ .weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
+
+ .weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_IRQHandler
+
+ .weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
- .weak TIM1_UP_IRQHandler
+
+ .weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
- .weak TIM1_TRG_COM_IRQHandler
+ .weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
+
+ .weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
+
+ .weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
+
+ .weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
+
+ .weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
+
+ .weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
+
+ .weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
+
+ .weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
+
+ .weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
+
+ .weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
+
+ .weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
+
+ .weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
+
+ .weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
+
+ .weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
+
+ .weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
+
+ .weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
+
+ .weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
+
+ .weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
+
+ .weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FMC_IRQHandler
+
+ .weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
-
- .weak SDMMC1_IRQHandler
+
+ .weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
+
+ .weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
+
+ .weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
+
+ .weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
+
+ .weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
+
+ .weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
+
+ .weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
+
+ .weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
+
+ .weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
+
+ .weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
+
+ .weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
+
+ .weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak ETH_IRQHandler
+
+ .weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
-
- .weak ETH_WKUP_IRQHandler
+
+ .weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
- .weak FDCAN_CAL_IRQHandler
- .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
+
+ .weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
+
+ .weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
+
+ .weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
+
+ .weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
+
+ .weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
+
+ .weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
+
+ .weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak DCMI_PSSI_IRQHandler
+
+ .weak DCMI_PSSI_IRQHandler
.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
- .weak RNG_IRQHandler
- .thumb_set RNG_IRQHandler,Default_Handler
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
- .weak FPU_IRQHandler
+ .weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
- .weak UART7_IRQHandler
+ .weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
- .weak UART8_IRQHandler
- .thumb_set UART8_IRQHandler,Default_Handler
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
- .weak SPI4_IRQHandler
+ .weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
-
- .weak SPI5_IRQHandler
+
+ .weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
- .weak SPI6_IRQHandler
- .thumb_set SPI6_IRQHandler,Default_Handler
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
- .weak SAI1_IRQHandler
+ .weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
-
- .weak LTDC_IRQHandler
+
+ .weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
- .weak LTDC_ER_IRQHandler
+ .weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
- .weak DMA2D_IRQHandler
+ .weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
-
- .weak OCTOSPI1_IRQHandler
+
+ .weak OCTOSPI1_IRQHandler
.thumb_set OCTOSPI1_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
+
+ .weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
- .weak CEC_IRQHandler
+ .weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
-
- .weak I2C4_EV_IRQHandler
- .thumb_set I2C4_EV_IRQHandler,Default_Handler
-
- .weak I2C4_ER_IRQHandler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
-
- .weak SPDIF_RX_IRQHandler
+
+ .weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
-
- .weak DMAMUX1_OVR_IRQHandler
+
+ .weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
- .weak DFSDM1_FLT0_IRQHandler
- .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
- .weak DFSDM1_FLT1_IRQHandler
- .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
- .weak DFSDM1_FLT2_IRQHandler
- .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
- .weak DFSDM1_FLT3_IRQHandler
+ .weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
-
- .weak SWPMI1_IRQHandler
+
+ .weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
- .weak MDIOS_WKUP_IRQHandler
- .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
- .weak MDIOS_IRQHandler
+ .weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
- .weak MDMA_IRQHandler
- .thumb_set MDMA_IRQHandler,Default_Handler
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
- .weak SDMMC2_IRQHandler
- .thumb_set SDMMC2_IRQHandler,Default_Handler
-
- .weak HSEM1_IRQHandler
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
- .weak ADC3_IRQHandler
- .thumb_set ADC3_IRQHandler,Default_Handler
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
- .weak DMAMUX2_OVR_IRQHandler
- .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
- .weak BDMA_Channel0_IRQHandler
- .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
- .weak BDMA_Channel1_IRQHandler
- .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
- .weak BDMA_Channel2_IRQHandler
- .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
- .weak BDMA_Channel3_IRQHandler
- .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
- .weak BDMA_Channel4_IRQHandler
- .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
- .weak BDMA_Channel5_IRQHandler
- .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
- .weak BDMA_Channel6_IRQHandler
+ .weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
- .weak BDMA_Channel7_IRQHandler
- .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
- .weak COMP1_IRQHandler
- .thumb_set COMP1_IRQHandler,Default_Handler
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
- .weak LPTIM3_IRQHandler
- .thumb_set LPTIM3_IRQHandler,Default_Handler
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
- .weak LPTIM4_IRQHandler
- .thumb_set LPTIM4_IRQHandler,Default_Handler
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
- .weak LPTIM5_IRQHandler
- .thumb_set LPTIM5_IRQHandler,Default_Handler
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
- .weak LPUART1_IRQHandler
- .thumb_set LPUART1_IRQHandler,Default_Handler
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
- .weak CRS_IRQHandler
- .thumb_set CRS_IRQHandler,Default_Handler
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
- .weak ECC_IRQHandler
+ .weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
- .weak SAI4_IRQHandler
+ .weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
- .weak DTS_IRQHandler
- .thumb_set DTS_IRQHandler,Default_Handler
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
- .weak WAKEUP_PIN_IRQHandler
+ .weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
- .weak OCTOSPI2_IRQHandler
+ .weak OCTOSPI2_IRQHandler
.thumb_set OCTOSPI2_IRQHandler,Default_Handler
- .weak FMAC_IRQHandler
+ .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
- .weak CORDIC_IRQHandler
+ .weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
- .weak UART9_IRQHandler
+ .weak UART9_IRQHandler
.thumb_set UART9_IRQHandler,Default_Handler
- .weak USART10_IRQHandler
+ .weak USART10_IRQHandler
.thumb_set USART10_IRQHandler,Default_Handler
- .weak I2C5_EV_IRQHandler
+ .weak I2C5_EV_IRQHandler
.thumb_set I2C5_EV_IRQHandler,Default_Handler
- .weak I2C5_ER_IRQHandler
+ .weak I2C5_ER_IRQHandler
.thumb_set I2C5_ER_IRQHandler,Default_Handler
- .weak FDCAN3_IT0_IRQHandler
+ .weak FDCAN3_IT0_IRQHandler
.thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
- .weak FDCAN3_IT1_IRQHandler
+ .weak FDCAN3_IT1_IRQHandler
.thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
- .weak TIM23_IRQHandler
+ .weak TIM23_IRQHandler
.thumb_set TIM23_IRQHandler,Default_Handler
- .weak TIM24_IRQHandler
- .thumb_set TIM24_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
+ .weak TIM24_IRQHandler
+ .thumb_set TIM24_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32h725xx.s b/Source/Templates/gcc/startup_stm32h725xx.s
index 3958e7c..dc5c49f 100644
--- a/Source/Templates/gcc/startup_stm32h725xx.s
+++ b/Source/Templates/gcc/startup_stm32h725xx.s
@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32h725xx.s
* @author MCD Application Team
- * @brief STM32H725xx Devices vector table for GCC based toolchain.
+ * @brief STM32H725xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
@@ -24,7 +24,7 @@
*
******************************************************************************
*/
-
+
.syntax unified
.cpu cortex-m7
.fpu softvfp
@@ -33,10 +33,10 @@
.global g_pfnVectors
.global Default_Handler
-/* start address for the initialization values of the .data section.
+/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
-/* start address for the .data section. defined in linker script */
+/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
@@ -50,7 +50,7 @@
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
- * supplied main() routine is called.
+ * supplied main() routine is called.
* @param None
* @retval : None
*/
@@ -58,53 +58,55 @@
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
-Reset_Handler:
+Reset_Handler:
ldr sp, =_estack /* set stack pointer */
-/* Call the clock system intitialization function.*/
+/* Call the clock system initialization function.*/
bl SystemInit
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
- * @brief This is the code that gets called when the processor receives an
+ * @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
- * @param None
- * @retval None
+ * @param None
+ * @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
@@ -116,13 +118,13 @@
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
-*
+*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
-
-
+
+
g_pfnVectors:
.word _estack
.word Reset_Handler
@@ -141,91 +143,91 @@
.word 0
.word PendSV_Handler
.word SysTick_Handler
-
+
/* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
- .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
- .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
- .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
- .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word 0 /* Reserved */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FMC_IRQHandler /* FMC */
- .word SDMMC1_IRQHandler /* SDMMC1 */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word ETH_IRQHandler /* Ethernet */
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
- .word 0 /* Reserved */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word 0 /* Reserved */
.word RNG_IRQHandler /* Rng */
.word FPU_IRQHandler /* FPU */
- .word UART7_IRQHandler /* UART7 */
+ .word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
@@ -240,58 +242,58 @@
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
- .word SPDIF_RX_IRQHandler /* SPDIF_RX */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word 0 /* Reserved */
- .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
.word 0 /* Reserved */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
- .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
- .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
- .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
- .word 0 /* Reserved */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
- .word TIM15_IRQHandler /* TIM15 global Interrupt */
- .word TIM16_IRQHandler /* TIM16 global Interrupt */
- .word TIM17_IRQHandler /* TIM17 global Interrupt */
- .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
- .word MDIOS_IRQHandler /* MDIOS global Interrupt */
- .word 0 /* Reserved */
- .word MDMA_IRQHandler /* MDMA global Interrupt */
- .word 0 /* Reserved */
- .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
- .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
- .word 0 /* Reserved */
- .word ADC3_IRQHandler /* ADC3 global Interrupt */
- .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word 0 /* Reserved */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
- .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
- .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
- .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
- .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
- .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
- .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
- .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
- .word COMP1_IRQHandler /* COMP1 global Interrupt */
- .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
- .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
- .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
- .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
- .word LPUART1_IRQHandler /* LP UART1 interrupt */
- .word 0 /* Reserved */
- .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
- .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
- .word SAI4_IRQHandler /* SAI4 global interrupt */
- .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
- .word 0 /* Reserved */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
+ .word 0 /* Reserved */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
.word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
.word 0 /* Reserved */
@@ -309,20 +311,20 @@
/*******************************************************************************
*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
* this definition.
-*
+*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
-
+
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
-
+
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
-
+
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
@@ -339,418 +341,418 @@
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_AVD_IRQHandler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
+
+ .weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
+
+ .weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
+
+ .weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
+
+ .weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
+
+ .weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
+
+ .weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
+
+ .weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
+
+ .weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
+
+ .weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
+
+ .weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
+
+ .weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
+
+ .weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
+
+ .weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT0_IRQHandler
+
+ .weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT0_IRQHandler
+
+ .weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT1_IRQHandler
+
+ .weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT1_IRQHandler
+
+ .weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
+
+ .weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_IRQHandler
+
+ .weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
- .weak TIM1_UP_IRQHandler
+
+ .weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
- .weak TIM1_TRG_COM_IRQHandler
+ .weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
+
+ .weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
+
+ .weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
+
+ .weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
+
+ .weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
+
+ .weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
+
+ .weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
+
+ .weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
+
+ .weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
+
+ .weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
+
+ .weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
+
+ .weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
+
+ .weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
+
+ .weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
+
+ .weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
+
+ .weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
+
+ .weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
+
+ .weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
+
+ .weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FMC_IRQHandler
+
+ .weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
-
- .weak SDMMC1_IRQHandler
+
+ .weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
+
+ .weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
+
+ .weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
+
+ .weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
+
+ .weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
+
+ .weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
+
+ .weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
+
+ .weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
+
+ .weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
+
+ .weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
+
+ .weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
+
+ .weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak ETH_IRQHandler
+
+ .weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
-
- .weak ETH_WKUP_IRQHandler
+
+ .weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
- .weak FDCAN_CAL_IRQHandler
- .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
+
+ .weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
+
+ .weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
+
+ .weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
+
+ .weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
+
+ .weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
+
+ .weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
+
+ .weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak DCMI_PSSI_IRQHandler
+
+ .weak DCMI_PSSI_IRQHandler
.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
- .weak RNG_IRQHandler
- .thumb_set RNG_IRQHandler,Default_Handler
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
- .weak FPU_IRQHandler
+ .weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
- .weak UART7_IRQHandler
+ .weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
- .weak UART8_IRQHandler
- .thumb_set UART8_IRQHandler,Default_Handler
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
- .weak SPI4_IRQHandler
+ .weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
-
- .weak SPI5_IRQHandler
+
+ .weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
- .weak SPI6_IRQHandler
- .thumb_set SPI6_IRQHandler,Default_Handler
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
- .weak SAI1_IRQHandler
+ .weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
-
- .weak LTDC_IRQHandler
+
+ .weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
- .weak LTDC_ER_IRQHandler
+ .weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
- .weak DMA2D_IRQHandler
+ .weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
-
- .weak OCTOSPI1_IRQHandler
+
+ .weak OCTOSPI1_IRQHandler
.thumb_set OCTOSPI1_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
+
+ .weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
- .weak CEC_IRQHandler
+ .weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
-
- .weak I2C4_EV_IRQHandler
- .thumb_set I2C4_EV_IRQHandler,Default_Handler
-
- .weak I2C4_ER_IRQHandler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
-
- .weak SPDIF_RX_IRQHandler
+
+ .weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
-
- .weak DMAMUX1_OVR_IRQHandler
+
+ .weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
- .weak DFSDM1_FLT0_IRQHandler
- .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
- .weak DFSDM1_FLT1_IRQHandler
- .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
- .weak DFSDM1_FLT2_IRQHandler
- .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
- .weak DFSDM1_FLT3_IRQHandler
+ .weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
-
- .weak SWPMI1_IRQHandler
+
+ .weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
- .weak MDIOS_WKUP_IRQHandler
- .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
- .weak MDIOS_IRQHandler
+ .weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
- .weak MDMA_IRQHandler
- .thumb_set MDMA_IRQHandler,Default_Handler
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
- .weak SDMMC2_IRQHandler
- .thumb_set SDMMC2_IRQHandler,Default_Handler
-
- .weak HSEM1_IRQHandler
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
- .weak ADC3_IRQHandler
- .thumb_set ADC3_IRQHandler,Default_Handler
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
- .weak DMAMUX2_OVR_IRQHandler
- .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
- .weak BDMA_Channel0_IRQHandler
- .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
- .weak BDMA_Channel1_IRQHandler
- .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
- .weak BDMA_Channel2_IRQHandler
- .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
- .weak BDMA_Channel3_IRQHandler
- .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
- .weak BDMA_Channel4_IRQHandler
- .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
- .weak BDMA_Channel5_IRQHandler
- .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
- .weak BDMA_Channel6_IRQHandler
+ .weak BDMA_Channel6_IRQHandler
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
- .weak BDMA_Channel7_IRQHandler
- .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
- .weak COMP1_IRQHandler
- .thumb_set COMP1_IRQHandler,Default_Handler
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
- .weak LPTIM3_IRQHandler
- .thumb_set LPTIM3_IRQHandler,Default_Handler
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
- .weak LPTIM4_IRQHandler
- .thumb_set LPTIM4_IRQHandler,Default_Handler
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
- .weak LPTIM5_IRQHandler
- .thumb_set LPTIM5_IRQHandler,Default_Handler
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
- .weak LPUART1_IRQHandler
- .thumb_set LPUART1_IRQHandler,Default_Handler
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
- .weak CRS_IRQHandler
- .thumb_set CRS_IRQHandler,Default_Handler
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
- .weak ECC_IRQHandler
+ .weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
- .weak SAI4_IRQHandler
+ .weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
- .weak DTS_IRQHandler
- .thumb_set DTS_IRQHandler,Default_Handler
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
- .weak WAKEUP_PIN_IRQHandler
+ .weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
- .weak OCTOSPI2_IRQHandler
+ .weak OCTOSPI2_IRQHandler
.thumb_set OCTOSPI2_IRQHandler,Default_Handler
- .weak FMAC_IRQHandler
+ .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
- .weak CORDIC_IRQHandler
+ .weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
- .weak UART9_IRQHandler
+ .weak UART9_IRQHandler
.thumb_set UART9_IRQHandler,Default_Handler
- .weak USART10_IRQHandler
+ .weak USART10_IRQHandler
.thumb_set USART10_IRQHandler,Default_Handler
- .weak I2C5_EV_IRQHandler
+ .weak I2C5_EV_IRQHandler
.thumb_set I2C5_EV_IRQHandler,Default_Handler
- .weak I2C5_ER_IRQHandler
+ .weak I2C5_ER_IRQHandler
.thumb_set I2C5_ER_IRQHandler,Default_Handler
- .weak FDCAN3_IT0_IRQHandler
+ .weak FDCAN3_IT0_IRQHandler
.thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
- .weak FDCAN3_IT1_IRQHandler
+ .weak FDCAN3_IT1_IRQHandler
.thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
- .weak TIM23_IRQHandler
+ .weak TIM23_IRQHandler
.thumb_set TIM23_IRQHandler,Default_Handler
- .weak TIM24_IRQHandler
- .thumb_set TIM24_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
+ .weak TIM24_IRQHandler
+ .thumb_set TIM24_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32h730xx.s b/Source/Templates/gcc/startup_stm32h730xx.s
index b252312..f9c8ea0 100644
--- a/Source/Templates/gcc/startup_stm32h730xx.s
+++ b/Source/Templates/gcc/startup_stm32h730xx.s
@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32h730xx.s
* @author MCD Application Team
- * @brief STM32H730xx Devices vector table for GCC based toolchain.
+ * @brief STM32H730xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
@@ -24,7 +24,7 @@
*
******************************************************************************
*/
-
+
.syntax unified
.cpu cortex-m7
.fpu softvfp
@@ -33,10 +33,10 @@
.global g_pfnVectors
.global Default_Handler
-/* start address for the initialization values of the .data section.
+/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
-/* start address for the .data section. defined in linker script */
+/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
@@ -50,7 +50,7 @@
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
- * supplied main() routine is called.
+ * supplied main() routine is called.
* @param None
* @retval : None
*/
@@ -58,53 +58,55 @@
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
-Reset_Handler:
+Reset_Handler:
ldr sp, =_estack /* set stack pointer */
-/* Call the clock system intitialization function.*/
+/* Call the clock system initialization function.*/
bl SystemInit
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
+ str r3, [r2]
+ adds r2, r2, #4
+
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
- bx lr
+ bx lr
.size Reset_Handler, .-Reset_Handler
/**
- * @brief This is the code that gets called when the processor receives an
+ * @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
- * @param None
- * @retval None
+ * @param None
+ * @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
@@ -116,13 +118,13 @@
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
-*
+*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
-
-
+
+
g_pfnVectors:
.word _estack
.word Reset_Handler
@@ -141,91 +143,91 @@
.word 0
.word PendSV_Handler
.word SysTick_Handler
-
+
/* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
- .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
- .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
- .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
- .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word 0 /* Reserved */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FMC_IRQHandler /* FMC */
- .word SDMMC1_IRQHandler /* SDMMC1 */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word ETH_IRQHandler /* Ethernet */
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
- .word CRYP_IRQHandler /* CRYP */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word CRYP_IRQHandler /* CRYP */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
- .word UART7_IRQHandler /* UART7 */
+ .word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
@@ -240,58 +242,58 @@
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
- .word SPDIF_RX_IRQHandler /* SPDIF_RX */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word 0 /* Reserved */
- .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
.word 0 /* Reserved */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
- .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
- .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
- .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
- .word 0 /* Reserved */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
- .word TIM15_IRQHandler /* TIM15 global Interrupt */
- .word TIM16_IRQHandler /* TIM16 global Interrupt */
- .word TIM17_IRQHandler /* TIM17 global Interrupt */
- .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
- .word MDIOS_IRQHandler /* MDIOS global Interrupt */
- .word 0 /* Reserved */
- .word MDMA_IRQHandler /* MDMA global Interrupt */
- .word 0 /* Reserved */
- .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
- .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
- .word 0 /* Reserved */
- .word ADC3_IRQHandler /* ADC3 global Interrupt */
- .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word 0 /* Reserved */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
- .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
- .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
- .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
- .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
- .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
- .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
- .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
- .word COMP1_IRQHandler /* COMP1 global Interrupt */
- .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
- .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
- .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
- .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
- .word LPUART1_IRQHandler /* LP UART1 interrupt */
- .word 0 /* Reserved */
- .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
- .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
- .word SAI4_IRQHandler /* SAI4 global interrupt */
- .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
- .word 0 /* Reserved */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
+ .word 0 /* Reserved */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
.word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
.word OTFDEC1_IRQHandler /* OTFDEC1 Interrupt */
@@ -309,20 +311,20 @@
/*******************************************************************************
*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
* this definition.
-*
+*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
-
+
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
-
+
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
-
+
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
@@ -339,427 +341,427 @@
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_AVD_IRQHandler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
+
+ .weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
+
+ .weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
+
+ .weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
+
+ .weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
+
+ .weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
+
+ .weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
+
+ .weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
+
+ .weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
+
+ .weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
+
+ .weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
+
+ .weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
+
+ .weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
+
+ .weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT0_IRQHandler
+
+ .weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT0_IRQHandler
+
+ .weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
-
- .weak FDCAN1_IT1_IRQHandler
+
+ .weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
-
- .weak FDCAN2_IT1_IRQHandler
+
+ .weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
+
+ .weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_IRQHandler
+
+ .weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
- .weak TIM1_UP_IRQHandler
+
+ .weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
- .weak TIM1_TRG_COM_IRQHandler
+ .weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
+
+ .weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
+
+ .weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
+
+ .weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
+
+ .weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
+
+ .weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
+
+ .weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
+
+ .weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
+
+ .weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
+
+ .weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
+
+ .weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
+
+ .weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
+
+ .weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
+
+ .weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
+
+ .weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
+
+ .weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
+
+ .weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_