[CMSIS] Update the Cortex-M7 core revision
diff --git a/Include/stm32h723xx.h b/Include/stm32h723xx.h
index dfe7f0f..bf226aa 100644
--- a/Include/stm32h723xx.h
+++ b/Include/stm32h723xx.h
@@ -211,7 +211,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
diff --git a/Include/stm32h725xx.h b/Include/stm32h725xx.h
index 2a22964..e5ad735 100644
--- a/Include/stm32h725xx.h
+++ b/Include/stm32h725xx.h
@@ -212,7 +212,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
diff --git a/Include/stm32h730xx.h b/Include/stm32h730xx.h
index ede15c5..57dbeb4 100644
--- a/Include/stm32h730xx.h
+++ b/Include/stm32h730xx.h
@@ -214,7 +214,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
diff --git a/Include/stm32h730xxq.h b/Include/stm32h730xxq.h
index 5ff323e..1c7ac86 100644
--- a/Include/stm32h730xxq.h
+++ b/Include/stm32h730xxq.h
@@ -215,7 +215,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
diff --git a/Include/stm32h733xx.h b/Include/stm32h733xx.h
index ebc647f..be446b8 100644
--- a/Include/stm32h733xx.h
+++ b/Include/stm32h733xx.h
@@ -214,7 +214,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
diff --git a/Include/stm32h735xx.h b/Include/stm32h735xx.h
index 9e9515c..07d23ab 100644
--- a/Include/stm32h735xx.h
+++ b/Include/stm32h735xx.h
@@ -215,7 +215,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
diff --git a/Include/stm32h742xx.h b/Include/stm32h742xx.h
index 38d5905..cdef725 100644
--- a/Include/stm32h742xx.h
+++ b/Include/stm32h742xx.h
@@ -210,7 +210,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -225,7 +225,6 @@
-
#include "system_stm32h7xx.h"
#include <stdint.h>
diff --git a/Include/stm32h743xx.h b/Include/stm32h743xx.h
index 3802024..b31ef96 100644
--- a/Include/stm32h743xx.h
+++ b/Include/stm32h743xx.h
@@ -213,7 +213,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -228,7 +228,6 @@
-
#include "system_stm32h7xx.h"
#include <stdint.h>
diff --git a/Include/stm32h745xg.h b/Include/stm32h745xg.h
index d0d63dd..0205f42 100644
--- a/Include/stm32h745xg.h
+++ b/Include/stm32h745xg.h
@@ -230,7 +230,7 @@
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
#else /* CORE_CM7 */
#ifdef CORE_CM7
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -250,7 +250,6 @@
-
#include "system_stm32h7xx.h"
#include <stdint.h>
diff --git a/Include/stm32h745xx.h b/Include/stm32h745xx.h
index 08a6183..34e0a4e 100644
--- a/Include/stm32h745xx.h
+++ b/Include/stm32h745xx.h
@@ -230,7 +230,7 @@
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
#else /* CORE_CM7 */
#ifdef CORE_CM7
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -250,7 +250,6 @@
-
#include "system_stm32h7xx.h"
#include <stdint.h>
diff --git a/Include/stm32h747xg.h b/Include/stm32h747xg.h
index ba1e025..7471f7f 100644
--- a/Include/stm32h747xg.h
+++ b/Include/stm32h747xg.h
@@ -231,7 +231,7 @@
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
#else /* CORE_CM7 */
#ifdef CORE_CM7
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -251,7 +251,6 @@
-
#include "system_stm32h7xx.h"
#include <stdint.h>
diff --git a/Include/stm32h747xx.h b/Include/stm32h747xx.h
index dd052c6..e7874cd 100644
--- a/Include/stm32h747xx.h
+++ b/Include/stm32h747xx.h
@@ -231,7 +231,7 @@
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
#else /* CORE_CM7 */
#ifdef CORE_CM7
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -251,7 +251,6 @@
-
#include "system_stm32h7xx.h"
#include <stdint.h>
diff --git a/Include/stm32h750xx.h b/Include/stm32h750xx.h
index b117c13..27f9b90 100644
--- a/Include/stm32h750xx.h
+++ b/Include/stm32h750xx.h
@@ -214,7 +214,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -229,7 +229,6 @@
-
#include "system_stm32h7xx.h"
#include <stdint.h>
diff --git a/Include/stm32h753xx.h b/Include/stm32h753xx.h
index 1bb6955..64060c1 100644
--- a/Include/stm32h753xx.h
+++ b/Include/stm32h753xx.h
@@ -214,7 +214,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -229,7 +229,6 @@
-
#include "system_stm32h7xx.h"
#include <stdint.h>
diff --git a/Include/stm32h755xx.h b/Include/stm32h755xx.h
index ffe28c5..b9dd5fa 100644
--- a/Include/stm32h755xx.h
+++ b/Include/stm32h755xx.h
@@ -231,7 +231,7 @@
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
#else /* CORE_CM7 */
#ifdef CORE_CM7
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -251,7 +251,6 @@
-
#include "system_stm32h7xx.h"
#include <stdint.h>
diff --git a/Include/stm32h757xx.h b/Include/stm32h757xx.h
index 7cf9487..4e1b801 100644
--- a/Include/stm32h757xx.h
+++ b/Include/stm32h757xx.h
@@ -232,7 +232,7 @@
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
#else /* CORE_CM7 */
#ifdef CORE_CM7
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
@@ -252,7 +252,6 @@
-
#include "system_stm32h7xx.h"
#include <stdint.h>
diff --git a/Include/stm32h7a3xx.h b/Include/stm32h7a3xx.h
index 5491297..8d8cc6c 100644
--- a/Include/stm32h7a3xx.h
+++ b/Include/stm32h7a3xx.h
@@ -208,7 +208,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
diff --git a/Include/stm32h7a3xxq.h b/Include/stm32h7a3xxq.h
index 46da5de..db9d537 100644
--- a/Include/stm32h7a3xxq.h
+++ b/Include/stm32h7a3xxq.h
@@ -209,7 +209,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
diff --git a/Include/stm32h7b0xx.h b/Include/stm32h7b0xx.h
index d23db59..7cd00a4 100644
--- a/Include/stm32h7b0xx.h
+++ b/Include/stm32h7b0xx.h
@@ -211,7 +211,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
diff --git a/Include/stm32h7b0xxq.h b/Include/stm32h7b0xxq.h
index 1b59940..f58644a 100644
--- a/Include/stm32h7b0xxq.h
+++ b/Include/stm32h7b0xxq.h
@@ -212,7 +212,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
diff --git a/Include/stm32h7b3xx.h b/Include/stm32h7b3xx.h
index fcfdac6..46bd64e 100644
--- a/Include/stm32h7b3xx.h
+++ b/Include/stm32h7b3xx.h
@@ -211,7 +211,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
diff --git a/Include/stm32h7b3xxq.h b/Include/stm32h7b3xxq.h
index f0d1405..1c65cfa 100644
--- a/Include/stm32h7b3xxq.h
+++ b/Include/stm32h7b3xxq.h
@@ -212,7 +212,7 @@
/**
* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
*/
-#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
+#define __CM7_REV 0x0110U /*!< Cortex-M7 revision r1p2 */
#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
