Release v1.10.6
diff --git a/Include/stm32h723xx.h b/Include/stm32h723xx.h index b139a38..de1ce94 100644 --- a/Include/stm32h723xx.h +++ b/Include/stm32h723xx.h
@@ -1321,7 +1321,7 @@ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -16973,7 +16973,104 @@ #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -17001,49 +17098,12 @@ #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U)
diff --git a/Include/stm32h725xx.h b/Include/stm32h725xx.h index 02749c7..c99cb32 100644 --- a/Include/stm32h725xx.h +++ b/Include/stm32h725xx.h
@@ -1322,7 +1322,7 @@ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -16985,7 +16985,104 @@ #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -17013,49 +17110,12 @@ #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U)
diff --git a/Include/stm32h730xx.h b/Include/stm32h730xx.h index 6bab03e..241f231 100644 --- a/Include/stm32h730xx.h +++ b/Include/stm32h730xx.h
@@ -1324,7 +1324,7 @@ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -17460,7 +17460,104 @@ #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -17488,49 +17585,12 @@ #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U)
diff --git a/Include/stm32h730xxq.h b/Include/stm32h730xxq.h index 4601a20..bb2b158 100644 --- a/Include/stm32h730xxq.h +++ b/Include/stm32h730xxq.h
@@ -1325,7 +1325,7 @@ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -17472,7 +17472,104 @@ #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -17500,49 +17597,12 @@ #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U)
diff --git a/Include/stm32h733xx.h b/Include/stm32h733xx.h index 8d9f104..dea3481 100644 --- a/Include/stm32h733xx.h +++ b/Include/stm32h733xx.h
@@ -1324,7 +1324,7 @@ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -17460,7 +17460,104 @@ #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -17488,49 +17585,12 @@ #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U)
diff --git a/Include/stm32h735xx.h b/Include/stm32h735xx.h index 20b7efc..84a93d1 100644 --- a/Include/stm32h735xx.h +++ b/Include/stm32h735xx.h
@@ -1325,7 +1325,7 @@ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ @@ -17472,7 +17472,104 @@ #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ -/******************** Bits definition for RTC_TAMPCR register ***************/ +/******************** Bits definition for RTC_TAFCR register ***************/ +#define RTC_TAFCR_PC15MODE_Pos (23U) +#define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ +#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk +#define RTC_TAFCR_PC15VALUE_Pos (22U) +#define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ +#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk +#define RTC_TAFCR_PC14MODE_Pos (21U) +#define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ +#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk +#define RTC_TAFCR_PC14VALUE_Pos (20U) +#define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ +#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk +#define RTC_TAFCR_PC13MODE_Pos (19U) +#define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ +#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk +#define RTC_TAFCR_PC13VALUE_Pos (18U) +#define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ +#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk +#define RTC_TAFCR_TAMPPUDIS_Pos (15U) +#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ +#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAFCR_TAMPPRCH_Pos (13U) +#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ +#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ +#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ +#define RTC_TAFCR_TAMPFLT_Pos (11U) +#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ +#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ +#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ +#define RTC_TAFCR_TAMPFREQ_Pos (8U) +#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ +#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ +#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ +#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ +#define RTC_TAFCR_TAMPTS_Pos (7U) +#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ +#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk +#define RTC_TAFCR_TAMP3TRG_Pos (6U) +#define RTC_TAFCR_TAMP3TRG_Msk (0x1UL << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ +#define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAFCR_TAMP3E_Pos (5U) +#define RTC_TAFCR_TAMP3E_Msk (0x1UL << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ +#define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk +#define RTC_TAFCR_TAMPIE_Pos (2U) +#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ +#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk +#define RTC_TAFCR_TAMP1TRG_Pos (1U) +#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ +#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAFCR_TAMP1E_Pos (0U) +#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ +#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk + +/* Aliases for RTC TAFCR */ +#define TAMPCR TAFCR +#define RTC_TAMPCR_TAMPPUDIS_Pos RTC_TAFCR_TAMPPUDIS_Pos +#define RTC_TAMPCR_TAMPPUDIS_Msk RTC_TAFCR_TAMPPUDIS_Msk +#define RTC_TAMPCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS +#define RTC_TAMPCR_TAMPPRCH_Pos RTC_TAFCR_TAMPPRCH_Pos +#define RTC_TAMPCR_TAMPPRCH_Msk RTC_TAFCR_TAMPPRCH_Msk +#define RTC_TAMPCR_TAMPPRCH RTC_TAFCR_TAMPPRCH +#define RTC_TAMPCR_TAMPPRCH_0 RTC_TAFCR_TAMPPRCH_0 +#define RTC_TAMPCR_TAMPPRCH_1 RTC_TAFCR_TAMPPRCH_1 +#define RTC_TAMPCR_TAMPFLT_Pos RTC_TAFCR_TAMPFLT_Pos +#define RTC_TAMPCR_TAMPFLT_Msk RTC_TAFCR_TAMPFLT_Msk +#define RTC_TAMPCR_TAMPFLT RTC_TAFCR_TAMPFLT +#define RTC_TAMPCR_TAMPFLT_0 RTC_TAFCR_TAMPFLT_0 +#define RTC_TAMPCR_TAMPFLT_1 RTC_TAFCR_TAMPFLT_1 +#define RTC_TAMPCR_TAMPFREQ_Pos RTC_TAFCR_TAMPFREQ_Pos +#define RTC_TAMPCR_TAMPFREQ_Msk RTC_TAFCR_TAMPFREQ_Msk +#define RTC_TAMPCR_TAMPFREQ RTC_TAFCR_TAMPFREQ +#define RTC_TAMPCR_TAMPFREQ_0 RTC_TAFCR_TAMPFREQ_0 +#define RTC_TAMPCR_TAMPFREQ_1 RTC_TAFCR_TAMPFREQ_1 +#define RTC_TAMPCR_TAMPFREQ_2 RTC_TAFCR_TAMPFREQ_2 +#define RTC_TAMPCR_TAMPTS_Pos RTC_TAFCR_TAMPTS_Pos +#define RTC_TAMPCR_TAMPTS_Msk RTC_TAFCR_TAMPTS_Msk +#define RTC_TAMPCR_TAMPTS RTC_TAFCR_TAMPTS +#define RTC_TAMPCR_TAMP3TRG_Pos RTC_TAFCR_TAMP3TRG_Pos +#define RTC_TAMPCR_TAMP3TRG_Msk RTC_TAFCR_TAMP3TRG_Msk +#define RTC_TAMPCR_TAMP3TRG RTC_TAFCR_TAMP3TRG +#define RTC_TAMPCR_TAMP3E_Pos RTC_TAFCR_TAMP3E_Pos +#define RTC_TAMPCR_TAMP3E_Msk RTC_TAFCR_TAMP3E_Msk +#define RTC_TAMPCR_TAMP3E RTC_TAFCR_TAMP3E +#define RTC_TAMPCR_TAMPIE_Pos RTC_TAFCR_TAMPIE_Pos +#define RTC_TAMPCR_TAMPIE_Msk RTC_TAFCR_TAMPIE_Msk +#define RTC_TAMPCR_TAMPIE RTC_TAFCR_TAMPIE +#define RTC_TAMPCR_TAMP1TRG_Pos RTC_TAFCR_TAMP1TRG_Pos +#define RTC_TAMPCR_TAMP1TRG_Msk RTC_TAFCR_TAMP1TRG_Msk +#define RTC_TAMPCR_TAMP1TRG RTC_TAFCR_TAMP1TRG +#define RTC_TAMPCR_TAMP1E_Pos RTC_TAFCR_TAMP1E_Pos +#define RTC_TAMPCR_TAMP1E_Msk RTC_TAFCR_TAMP1E_Msk +#define RTC_TAMPCR_TAMP1E RTC_TAFCR_TAMP1E + +/* Legacy defines for backward compatibility */ #define RTC_TAMPCR_TAMP3MF_Pos (24U) #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk @@ -17500,49 +17597,12 @@ #define RTC_TAMPCR_TAMP1IE_Pos (16U) #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk -#define RTC_TAMPCR_TAMPPUDIS_Pos (15U) -#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ -#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk -#define RTC_TAMPCR_TAMPPRCH_Pos (13U) -#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ -#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk -#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ -#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ -#define RTC_TAMPCR_TAMPFLT_Pos (11U) -#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ -#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk -#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ -#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ -#define RTC_TAMPCR_TAMPFREQ_Pos (8U) -#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ -#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk -#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ -#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ -#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ -#define RTC_TAMPCR_TAMPTS_Pos (7U) -#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ -#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk -#define RTC_TAMPCR_TAMP3TRG_Pos (6U) -#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ -#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk -#define RTC_TAMPCR_TAMP3E_Pos (5U) -#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ -#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk #define RTC_TAMPCR_TAMP2TRG_Pos (4U) #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk #define RTC_TAMPCR_TAMP2E_Pos (3U) #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk -#define RTC_TAMPCR_TAMPIE_Pos (2U) -#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ -#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk -#define RTC_TAMPCR_TAMP1TRG_Pos (1U) -#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ -#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk -#define RTC_TAMPCR_TAMP1E_Pos (0U) -#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ -#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U)
diff --git a/Include/stm32h742xx.h b/Include/stm32h742xx.h index 6fa3bdb..d725cc1 100644 --- a/Include/stm32h742xx.h +++ b/Include/stm32h742xx.h
@@ -15769,6 +15769,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h743xx.h b/Include/stm32h743xx.h index 8c04ec4..cfdc8ae 100644 --- a/Include/stm32h743xx.h +++ b/Include/stm32h743xx.h
@@ -16417,6 +16417,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h745xg.h b/Include/stm32h745xg.h index d79b344..140efbf 100644 --- a/Include/stm32h745xg.h +++ b/Include/stm32h745xg.h
@@ -17052,6 +17052,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h745xx.h b/Include/stm32h745xx.h index a5025de..d9ec1e3 100644 --- a/Include/stm32h745xx.h +++ b/Include/stm32h745xx.h
@@ -17052,6 +17052,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h747xg.h b/Include/stm32h747xg.h index b31853a..2dac4ed 100644 --- a/Include/stm32h747xg.h +++ b/Include/stm32h747xg.h
@@ -20225,6 +20225,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h747xx.h b/Include/stm32h747xx.h index 9ba49d0..7338d75 100644 --- a/Include/stm32h747xx.h +++ b/Include/stm32h747xx.h
@@ -20225,6 +20225,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h750xx.h b/Include/stm32h750xx.h index c9fa51e..7064f72 100644 --- a/Include/stm32h750xx.h +++ b/Include/stm32h750xx.h
@@ -16698,6 +16698,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h753xx.h b/Include/stm32h753xx.h index 74a2e7a..322f5fd 100644 --- a/Include/stm32h753xx.h +++ b/Include/stm32h753xx.h
@@ -16704,6 +16704,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h755xx.h b/Include/stm32h755xx.h index 60b7112..696c4a0 100644 --- a/Include/stm32h755xx.h +++ b/Include/stm32h755xx.h
@@ -17339,6 +17339,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h757xx.h b/Include/stm32h757xx.h index 92ea305..7fc7222 100644 --- a/Include/stm32h757xx.h +++ b/Include/stm32h757xx.h
@@ -20512,6 +20512,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h7a3xx.h b/Include/stm32h7a3xx.h index 82fc1d9..f3421dc 100644 --- a/Include/stm32h7a3xx.h +++ b/Include/stm32h7a3xx.h
@@ -14664,6 +14664,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h7a3xxq.h b/Include/stm32h7a3xxq.h index 365b11f..f5a6b17 100644 --- a/Include/stm32h7a3xxq.h +++ b/Include/stm32h7a3xxq.h
@@ -14676,6 +14676,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h7b0xx.h b/Include/stm32h7b0xx.h index 0c8889c..7bf6d5c 100644 --- a/Include/stm32h7b0xx.h +++ b/Include/stm32h7b0xx.h
@@ -15144,6 +15144,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h7b0xxq.h b/Include/stm32h7b0xxq.h index 40ef88c..0cbaf5f 100644 --- a/Include/stm32h7b0xxq.h +++ b/Include/stm32h7b0xxq.h
@@ -15156,6 +15156,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h7b3xx.h b/Include/stm32h7b3xx.h index 70b3448..6fa5039 100644 --- a/Include/stm32h7b3xx.h +++ b/Include/stm32h7b3xx.h
@@ -15151,6 +15151,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h7b3xxq.h b/Include/stm32h7b3xxq.h index 8be28db..49d9f47 100644 --- a/Include/stm32h7b3xxq.h +++ b/Include/stm32h7b3xxq.h
@@ -15163,6 +15163,11 @@ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ +#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */ +#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */ +#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */ +#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */ + /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
diff --git a/Include/stm32h7xx.h b/Include/stm32h7xx.h index 12eade1..917a5b7 100644 --- a/Include/stm32h7xx.h +++ b/Include/stm32h7xx.h
@@ -103,11 +103,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.10.5 + * @brief CMSIS Device version number V1.10.6 */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */ -#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ +#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
diff --git a/Release_Notes.html b/Release_Notes.html index 508eb23..2d5aaa3 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
@@ -30,10 +30,37 @@ <div class="col-sm-12 col-lg-8"> <h1 id="update-history"><strong>Update History</strong></h1> <div class="collapse"> -<input type="checkbox" id="collapse-section17" checked aria-hidden="true"> <label for="collapse-section17" aria-hidden="true"><strong>V1.10.5 / 30-October-2024</strong></label> +<input type="checkbox" id="collapse-section18" checked aria-hidden="true"> <label for="collapse-section18" aria-hidden="true"><strong>V1.10.6 / 06-December-2024</strong></label> <div> <h2 id="main-changes">Main Changes</h2> <ul> +<li><strong>system_stm32h7xx.c template files</strong> +<ul> +<li>Fix computed frequencies returned by the HAL_RCC_GetHCLKFreq(), HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq() APIs.</li> +<li>Enable FMC clock to ensure effective write access to FMC Bank1 registers in the SystemInit() API.</li> +</ul></li> +<li><strong>STM32H723/H725/H730/H733/H735 devices header files</strong> +<ul> +<li>Align the RTC TAMPER register and bitfields naming with the terminology used in the Reference Manual (RM0468).</li> +</ul></li> +<li><strong>STM32H742/H743/H745/H747/H750/H753/H755/H757/H7A3/H7B0/H7B3 device header files</strong> +<ul> +<li>Define new RTC macros to manage specific supported Tamper features: +<ul> +<li>RTC_TAMPER2_SUPPORT to manage Tamper 2 support</li> +<li>RTC_TAMPMASKFLAG_SUPPORT to manage Tamper Event Masking support</li> +<li>RTC_TAMPNOERASE_SUPPORT to manage Backup Registers erasure upon Tamper Event support</li> +<li>RTC_TAMPxIE_SUPPORT to manage selective TAMPERx interrupt enable support.</li> +</ul></li> +</ul></li> +</ul> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section17" aria-hidden="true"> <label for="collapse-section17" aria-hidden="true"><strong>V1.10.5 / 30-October-2024</strong></label> +<div> +<h2 id="main-changes-1">Main Changes</h2> +<ul> <li>Update startup files to safely exit from Run* mode. <ul> <li>Deploy the recommended “how to exit from Run* mode” configuration sequence available within product documentation.</li> @@ -50,7 +77,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section16" aria-hidden="true"> <label for="collapse-section16" aria-hidden="true"><strong>V1.10.4 / 15-March-2024</strong></label> <div> -<h2 id="main-changes-1">Main Changes</h2> +<h2 id="main-changes-2">Main Changes</h2> <ul> <li>Update the values of the sensor calibration temperatures for H742, H743, and H753 part numbers.</li> <li>Remove the unsupported MDMA BASE channel.</li> @@ -65,7 +92,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true"><strong>V1.10.3 / 23-September-2022</strong></label> <div> -<h2 id="main-changes-2">Main Changes</h2> +<h2 id="main-changes-3">Main Changes</h2> <ul> <li>General updates to fix known defects and implementation enhancements</li> <li>Update system_stm32h7xx_*.c template files to fix typo in comment: the VTOR offset value is multiple of 0x400.</li> @@ -76,7 +103,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.2 / 12-February-2022</strong></label> <div> -<h2 id="main-changes-3">Main Changes</h2> +<h2 id="main-changes-4">Main Changes</h2> <ul> <li>General updates to fix known defects and implementation enhancements</li> <li>Add support for ADC LDO output voltage ready bit.</li> @@ -91,7 +118,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label> <div> -<h2 id="main-changes-4">Main Changes</h2> +<h2 id="main-changes-5">Main Changes</h2> <ul> <li>General updates to fix known defects and implementation enhancements</li> <li>All source files: update disclaimer to add reference to the new license agreement.</li> @@ -117,7 +144,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label> <div> -<h2 id="main-changes-5">Main Changes</h2> +<h2 id="main-changes-6">Main Changes</h2> <ul> <li>Fix minor issues related to English typo in comments of registers and fields description</li> <li>Update STM32H7 devices header files to add GPV registers definition, base address and instance</li> @@ -135,7 +162,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label> <div> -<h2 id="main-changes-6">Main Changes</h2> +<h2 id="main-changes-7">Main Changes</h2> <ul> <li>Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices: <ul> @@ -193,7 +220,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label> <div> -<h2 id="main-changes-7">Main Changes</h2> +<h2 id="main-changes-8">Main Changes</h2> <ul> <li>General updates to align Bits and registers definitions with the STM32H7 reference manual</li> <li>Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero</li> @@ -214,7 +241,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label> <div> -<h2 id="main-changes-8">Main Changes</h2> +<h2 id="main-changes-9">Main Changes</h2> <ul> <li><p>General updates to align Bit and registers definition with the STM32H7 reference manual</p></li> <li>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices: @@ -244,7 +271,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label> <div> -<h2 id="main-changes-9">Main Changes</h2> +<h2 id="main-changes-10">Main Changes</h2> <ul> <li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li> <li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li> @@ -259,7 +286,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label> <div> -<h2 id="main-changes-10">Main Changes</h2> +<h2 id="main-changes-11">Main Changes</h2> <ul> <li>General updates to align Bit and registers definition with the STM32H7 reference manual</li> <li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li> @@ -323,7 +350,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label> <div> -<h2 id="main-changes-11">Main Changes</h2> +<h2 id="main-changes-12">Main Changes</h2> <ul> <li><strong>Patch Release on top of V1.3.0</strong></li> <li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files: @@ -336,7 +363,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label> <div> -<h2 id="main-changes-12">Main Changes</h2> +<h2 id="main-changes-13">Main Changes</h2> <ul> <li>STM32H7xx include files: <ul> @@ -381,7 +408,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label> <div> -<h2 id="main-changes-13">Main Changes</h2> +<h2 id="main-changes-14">Main Changes</h2> <ul> <li>Add support for stm32h750xx value line devices: <ul> @@ -394,7 +421,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label> <div> -<h2 id="main-changes-14">Main Changes</h2> +<h2 id="main-changes-15">Main Changes</h2> <ul> <li>Update FDCAN bit definition</li> <li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li> @@ -404,7 +431,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label> <div> -<h2 id="main-changes-15">Main Changes</h2> +<h2 id="main-changes-16">Main Changes</h2> <ul> <li>Update USB OTG bit definition</li> <li>Adjust PLL fractional computation</li> @@ -414,7 +441,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label> <div> -<h2 id="main-changes-16">Main Changes</h2> +<h2 id="main-changes-17">Main Changes</h2> <ul> <li>First official release for <strong>STM32H743xx/753xx</strong> devices</li> </ul>
diff --git a/Source/Templates/system_stm32h7xx.c b/Source/Templates/system_stm32h7xx.c index 0ebabe6..197d15c 100644 --- a/Source/Templates/system_stm32h7xx.c +++ b/Source/Templates/system_stm32h7xx.c
@@ -152,7 +152,7 @@ */ uint32_t SystemCoreClock = 64000000; uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -290,12 +290,21 @@ #endif /* USER_VECT_TAB_ADDRESS */ #else - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS)
diff --git a/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c index 64af7e2..8641d8b 100644 --- a/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c +++ b/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c
@@ -154,7 +154,7 @@ */ uint32_t SystemCoreClock = 64000000; uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -271,12 +271,21 @@ #endif /* USER_VECT_TAB_ADDRESS */ #elif defined(CORE_CM7) - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS)
diff --git a/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c b/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c index 94f2021..fe008ab 100644 --- a/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c +++ b/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c
@@ -157,7 +157,7 @@ */ uint32_t SystemCoreClock = 64000000; uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -263,13 +263,21 @@ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; } + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS)
diff --git a/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c b/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c index 8cce902..241e937 100644 --- a/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c +++ b/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c
@@ -157,7 +157,7 @@ */ uint32_t SystemCoreClock = 64000000; uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -269,12 +269,21 @@ #endif /* USER_VECT_TAB_ADDRESS */ #elif defined(CORE_CM7) - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS)
diff --git a/Source/Templates/system_stm32h7xx_singlecore.c b/Source/Templates/system_stm32h7xx_singlecore.c index 5e701b0..9823d88 100644 --- a/Source/Templates/system_stm32h7xx_singlecore.c +++ b/Source/Templates/system_stm32h7xx_singlecore.c
@@ -137,7 +137,7 @@ */ uint32_t SystemCoreClock = 64000000; uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} @@ -267,13 +267,21 @@ tmpreg = RCC->AHB2ENR; (void) tmpreg; #endif /* DATA_IN_D2_SRAM */ + if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) + { + /* Enable the FMC interface clock */ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Disable the FMC interface clock */ + CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + } /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS)