Release_Notes.html - third_party/github/STMicroelectronics/cmsis_device_h7 - Git at Google

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 <h1 id="release-notes-for-stm32h7xx-cmsis"><strong>Release Notes for STM32H7xx CMSIS</strong></h1>
 <p>Copyright © 2017 STMicroelectronics<br />
 </p>
 <a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
 </center>
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 </div>
 <h1 id="license"><strong>License</strong></h1>
 This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
 <center>
 <a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
 </center>
 </div>
 <div class="col-sm-12 col-lg-8">
 <h1 id="update-history"><strong>Update History</strong></h1>
 <div class="collapse">
 <input type="checkbox" id="collapse-section10" checked aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <ul>
 <li>General updates to align Bits and registers definitions with the STM32H7 reference manual<br />
 </li>
 <li>Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero</li>
 <li>Add definition of DMA_SxCR_TRBUFF bit field of DMA SxCR register allowing to enabled/disable bufferable transfers</li>
 <li>Remove RCC_AHB2ENR_CRYPEN/RCC_AHB2RSTR_CRYPRST/RCC_AHB2LPENR_CRYPLPEN and RCC_AHB2ENR_HASHEN/RCC_AHB2RSTR_HASHRST/RCC_AHB2LPENR_HASHLPEN from H7 devices that doesn’t support CRYP/HASH (STM32H742/43/45/47/A3)</li>
 <li>Add STM32H7_DEV_ID define allowing to identfy the H7 Device ID</li>
 <li>Update OCTOSPIM_TypeDef structure definition with 3 PCR registers instead of 8 (on STM32H7A3/B3/B0 devices supporting OctoSPI)</li>
 <li>Add definition for OCTOSPIM_CR_MUXEN and OCTOSPIM_CR_REQ2ACK_TIME in order to support OctoSPI IO Manager multiplexed mode feature (on STM32H7A3/B3/B0 devices supporting OctoSPI)</li>
 <li>Update system_stm32h7xx.c to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)</li>
 <li>Add EWARM linker files for STM32H7A3 devices with reduced Flash size to 1MB:
 <ul>
 <li>stm32h7a3xg_flash.icf, stm32h7a3xg_flash_rw_sram1.icf, stm32h7a3xg_flash_rw_sram2.icf.</li>
 <li>stm32h7a3xgq_flash.icf, stm32h7a3xgq_flash_rw_sram1.icf, stm32h7a3xgq_flash_rw_sram2.icf.</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
 <div>
 <h2 id="main-changes-1">Main Changes</h2>
 <ul>
 <li><p>General updates to align Bit and registers definition with the STM32H7 reference manual</p></li>
 <li>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices:
 <ul>
 <li>Add “stm32h7a3xx.h”, “stm32h7a3xxq.h”, “stm32h7b3xx.h”, “stm32h7b3xxq.h”, “stm32h7b0xx.h” and “stm32h7b0xxq.h” files</li>
 <li>Add startup files “startup_stm32h7a3xx.s”, “startup_stm32h7a3xxq.s”, “startup_stm32h7b3xx.s”, “startup_stm32h7b3xxq.s”, “startup_stm32h7b0xx.s” and “startup_stm32h7b0xxq.s” for EWARM , MDK-ARM and STM32CubeIDE toolchains</li>
 <li>Add part numbers list to stm32h7xx.h header file:
 <ul>
 <li>STM32H7A3xx : STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6</li>
 <li>STM32H7A3xxQ : STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q</li>
 <li>STM32H7B3xx : STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6</li>
 <li>STM32H7B3xxQ : STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q</li>
 <li>STM32H7B0xx : STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ</li>
 </ul></li>
 </ul></li>
 <li>Update DMA2D bits definitions: Update to support Line offset mode and swap bytes features
 <ul>
 <li>Add CR_LOM (Line Ofset Mode) bit definition, Add OPFCCR_SB (Swap Bytes) bit definition</li>
 <li>Update CR_MODE, FGOR_LO, BGOR_LO and OOR_LO bit definition</li>
 </ul></li>
 <li>Update USB_OTG_GAHBCFG bit definition: to be aligned with LL_USB usage</li>
 <li><p>Add USB_OTG_DOEPMSK_AHBERRM, USB_OTG_DOEPMSK_BERRM, USB_OTG_DOEPMSK_NAKM, USB_OTG_DOEPMSK_NYETM, USB_OTG_DIEPINT_AHBERR, USB_OTG_DIEPINT_INEPNM, USB_OTG_DOEPINT_AHBERR, USB_OTG_DOEPINT_OUTPKTERR, USB_OTG_DOEPINT_BERR, USB_OTG_DOEPINT_NAK and USB_OTG_DOEPINT_STPKTRX bit definitions</p></li>
 <li><p>Update IS_TIM_REMAP_INSTANCE and IS_TIM_SYNCHRO_INSTANCE macro implemenation</p></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
 <div>
 <h2 id="main-changes-2">Main Changes</h2>
 <ul>
 <li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li>
 <li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li>
 <li>Add definition of “ART” bit fields: ART_CTR_EN and ART_CTR_PCACHEADDR<br />
 </li>
 <li>Update definitions of “HRTIM1_TIMA” to “HRTIM1_TIME” : pointer to HRTIM_Timerx_TypeDef structure instead of HRTIM_TIM_TypeDef</li>
 <li>Fix Typo in “ETH_TypeDef” definition: use uint32_t for “RESERVED16” registers instead of int32_t</li>
 <li>Remove useless definition of “SDMMC” instance (keep only definitions of “SDMMC1” and “SDMMC2”)</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
 <div>
 <h2 id="main-changes-3">Main Changes</h2>
 <ul>
 <li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
 <li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li>
 <li>Add support of stm32h745xx, stm32h747xx, stm32h755xx, stm32h757xx <strong>Dual Core</strong> devices and STM32H742xx (new single core device):
 <ul>
 <li>Add “stm32h745xx.h” , “stm32h747xx.h”, “stm32h755xx.h”, “stm32h757xx.h” and “stm32h742xx.h” files</li>
 <li>Add startup files “startup_stm32h745xx.s”, “startup_stm32h747xx.s”, “startup_stm32h755xx.s”, “startup_stm32h757xx.s” and “startup_stm32h742xx.s” for EWARM , MDK-ARM and SW4STM32 toolchains</li>
 <li>Add part numbers list to stm32h7xx.h header file:
 <ul>
 <li>STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI</li>
 <li>STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI</li>
 <li>STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI</li>
 <li>STM32H750xx: STM32H750V, STM32H750I, STM32H750X</li>
 <li>STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI</li>
 <li>STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI</li>
 <li>STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI</li>
 <li><p>STM32H755xx: STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI</p></li>
 <li>Add system_stm32h7xx_singlecore.c : system initialization template source file for single core lines (STM32H743xx, STM32H753xx, STM32H750xx and STM32H742xx)</li>
 <li>Add system initialization template source file for dual core lines:
 <ul>
 <li>system_stm32h7xx_dualcore_boot_cm4_cm7.c: template for the boot case where Cortex-M7 and Cortex-M4 are boot at once</li>
 <li>system_stm32h7xx_dualcore_bootcm7_cm4gated.c: template for the boot case where Cortex-M7 is booting and Cortex-M4 is gated using FLASH Option Bytes</li>
 <li>system_stm32h7xx_dualcore_bootcm4_cm7gated.c: template for the boot case where Cortex-M4 is booting and Cortex-M7 is gated using FLASH Option Bytes</li>
 </ul></li>
 <li>Add EWARM, MDK-ARM and SW4STM32 <strong>Dual Core</strong> devices linker files</li>
 <li><p>Add EWARM STM32H742xx devices linker files</p></li>
 </ul></li>
 </ul></li>
 <li><strong>Registers and bit field definitions updates</strong>:
 <ul>
 <li>Update SYSCFG_TypeDef structure to add
 <ul>
 <li>Add CFGR register: allowing to control connection between double ECC RAMs/Flash errors, PVD errors and CortexM7/M4 lockup to TIM1/8/15/16/17 and HRTIMER Break inputs</li>
 <li>Add definitions of SYSCFG_CFGR register bit fields</li>
 <li>PWRCR registers: allowing to control the PWR overdrive enable/disable for Voltage Scaling zero</li>
 <li>Add SYSCFG_PWRCR register bit fields</li>
 </ul></li>
 <li>Update RCC_TypeDef structure according to STM32H7xx <strong>Rev.V</strong> devices:
 <ul>
 <li>ICSCR: renamed to HSICFGR, HSI Clock Calibration Register</li>
 <li>Rename also RCC_ICSCR_XXX bit definitions RCC_HSICFGR_XXX according to the new register HSICFGR</li>
 <li>CSICFGR: New registers (on <strong>Rev.V</strong> devices), CSI Clock Calibration Register</li>
 <li>Add dedicated RCC_CSICFGR_XXX bit definitions</li>
 </ul></li>
 <li>Keep RCC_Core_TypeDef structure used for Dual Core lines devices only: allowing RCC clock enabling/allocation for each Core(Cortex-M7/M4)
 <ul>
 <li>RCC_Core_TypeDef structure and RCC_C1_BASE/RCC_C1 definition removed from STM32H743xx/53xx and STM32H750xx lines</li>
 </ul></li>
 <li>Add CRYP_CR_NPBLB bit field definition: upon refresh of the CRYP peripheral on the STM32H7 <strong>Rev.V</strong> devices</li>
 <li>Update ADC_CR_BOOST bot field definition for STM32H7 <strong>Rev.V</strong> devices: 2 bits instead of 1</li>
 <li>Remove useless I2C_CR1_SWRST definition: alignment with the reference manual</li>
 <li>Add SAI_xCR1_NODIV bit field definition upon SAI peripheral update for STM32H7 <strong>Rev.V</strong> devices</li>
 <li>Rename SPI_TXCRC_RXCRC to SPI_RXCRC_RXCRC: typo fix and alignment with the reference manual</li>
 <li>Fix QUADSPI_SR_FLEVEL bit field definition: Mask on 6 bits (0x3F mask) instead of 5 bits(0x1F mask) and add definition of QUADSPI_SR_FLEVEL_6</li>
 <li>Add definition of SYSCFG_EXTICR3_EXTI8_PK, SYSCFG_EXTICR3_EXTI9_PK, SYSCFG_EXTICR3_EXTI10_PK, SYSCFG_EXTICR3_EXTI11_PK and SYSCFG_EXTICR4_EXTI13_PK</li>
 <li>Add definition of FLASH_LATENCY_DEFAULT: default safe FLASH latency</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label>
 <div>
 <h2 id="main-changes-4">Main Changes</h2>
 <ul>
 <li><strong>Patch Release on top of V1.3.0</strong></li>
 <li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:
 <ul>
 <li>stm32h743xx.h, stm32h750xx.h and stm32h753xx.h</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
 <div>
 <h2 id="main-changes-5">Main Changes</h2>
 <ul>
 <li>STM32H7xx include files:
 <ul>
 <li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
 <li>Update "_Mask" bits definition using UL suffix for Misra-C 2012 compliance</li>
 <li>Add definition of <strong>RAMECC_MonitorTypeDef</strong> and <strong>RAMECC_TypeDef</strong> structure</li>
 <li>Add definition of <strong>RAMECC</strong> peripheral base addresses</li>
 <li>Add <strong>RAMECC</strong> peripheral registers bit definitions</li>
 <li>Add IS_RAMECC_MONITOR_ALL_INSTANCE macro</li>
 <li>Add <strong>EXTI</strong> SWIER3 bit definitions</li>
 <li>Update <strong>FLASH</strong> sector number to 8 instead of 16 (8 sectors for each bank)</li>
 <li>Remove extra bit definition : FLASH_CR_SNB_3 to FLASH_CR_SNB_7</li>
 <li>Update <strong>FLASH</strong> user option bytes bit definition</li>
 <li>Fix FLASH_BANK_SIZE definition: add parenthesis</li>
 <li>Remove <strong>PWR</strong> extra bit definition PWR_CR1_RLPSN</li>
 <li>Add <strong>PWR</strong> bit definition PWR_WKUPEPR_WKUPEN</li>
 <li>Fix typo in <strong>SDMMC</strong> bit definition: SDMMC_MASK_SDIOITIE_Pos, SDMMC_MASK_SDIOITIE_Msk and SDMMC_MASK_SDIOITIE</li>
 <li>Add <strong>SDMMC</strong> instance check macro: IS_SDMMC_ALL_INSTANCE</li>
 <li>Fix typo in <strong>SYSCFG</strong> bit definition: SYSCFG_PMCR_EPIS_SEL_Pos, SYSCFG_PMCR_EPIS_SEL_Msk, SYSCFG_PMCR_EPIS_SEL and SYSCFG_PMCR_EPIS_SEL_0 to SYSCFG_PMCR_EPIS_SEL_2</li>
 <li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR1_EXTI0_Msk, to SYSCFG_EXTICR1_EXTI3_Msk, 4 bits instead of 3</li>
 <li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR2_EXTI0_Msk, to SYSCFG_EXTICR2_EXTI3_Msk, 4 bits instead of 3</li>
 <li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR3_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI3_Msk, 4 bits instead of 3</li>
 <li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR4_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI4_Msk, 4 bits instead of 3</li>
 <li>Fix IS_ADC_COMMON_INSTANCE macro : add parenthesis</li>
 <li>Fix HSEM_CR_COREID_CURRENT and HSEM_CR_COREID_CURRENT: add parenthesis</li>
 <li>Update <strong>USART</strong> and <strong>SMARTCARD</strong> bits definition</li>
 <li>Update <strong>GPIO</strong> registers and bit definition (BSRR register)</li>
 <li>Add IS_GPIO_AF_INSTANCE macro</li>
 <li>Update <strong>DAC</strong> bits definition</li>
 <li>Update <strong>FDCAN</strong> bits definition</li>
 <li>Update <strong>USB</strong> bits definition (OTEPSPRM register)</li>
 <li>Fix <strong>CEC</strong> bit definition (RXDR register)</li>
 <li>Update <strong>TIM</strong> registers and bits definition naming</li>
 <li>Fix IS_TIM_CCX_INSTANCE macro : add TIM_CHANNEL_4 to TIM_CHANNEL_6</li>
 <li>Update <strong>SPI</strong> and <strong>I2S</strong> bits definition</li>
 <li>Update <strong>BDMA</strong> bits definition</li>
 <li>Update <strong>FMC</strong> bits definition</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
 <div>
 <h2 id="main-changes-6">Main Changes</h2>
 <ul>
 <li>Add support for stm32h750xx value line devices:
 <ul>
 <li>Add “stm32h750xx.h” file</li>
 <li>Add startup files startup_stm32h750xx.s for EWARM, MDK-ARM and SW4STM32</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section3"  aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
 <div>
 <h2 id="main-changes-7">Main Changes</h2>
 <ul>
 <li>Update FDCAN bit definition</li>
 <li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
 <div>
 <h2 id="main-changes-8">Main Changes</h2>
 <ul>
 <li>Update USB OTG bit definition</li>
 <li>Adjust PLL fractional computation</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
 <div>
 <h2 id="main-changes-9">Main Changes</h2>
 <ul>
 <li>First official release for <strong>STM32H743xx/753xx</strong> devices</li>
 </ul>
 </div>
 </div>
 </div>
 </div>
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	<h1 id="release-notes-for-stm32h7xx-cmsis"><strong>Release Notes for STM32H7xx CMSIS</strong></h1>
	<p>Copyright © 2017 STMicroelectronics<br />
	</p>
	<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
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	<h1 id="license"><strong>License</strong></h1>
	This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
	<center>
	<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
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	<h1 id="update-history"><strong>Update History</strong></h1>
	<div class="collapse">
	<input type="checkbox" id="collapse-section10" checked aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
	<div>
	<h2 id="main-changes">Main Changes</h2>
	<ul>
	<li>General updates to align Bits and registers definitions with the STM32H7 reference manual<br />
	</li>
	<li>Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero</li>
	<li>Add definition of DMA_SxCR_TRBUFF bit field of DMA SxCR register allowing to enabled/disable bufferable transfers</li>
	<li>Remove RCC_AHB2ENR_CRYPEN/RCC_AHB2RSTR_CRYPRST/RCC_AHB2LPENR_CRYPLPEN and RCC_AHB2ENR_HASHEN/RCC_AHB2RSTR_HASHRST/RCC_AHB2LPENR_HASHLPEN from H7 devices that doesn’t support CRYP/HASH (STM32H742/43/45/47/A3)</li>
	<li>Add STM32H7_DEV_ID define allowing to identfy the H7 Device ID</li>
	<li>Update OCTOSPIM_TypeDef structure definition with 3 PCR registers instead of 8 (on STM32H7A3/B3/B0 devices supporting OctoSPI)</li>
	<li>Add definition for OCTOSPIM_CR_MUXEN and OCTOSPIM_CR_REQ2ACK_TIME in order to support OctoSPI IO Manager multiplexed mode feature (on STM32H7A3/B3/B0 devices supporting OctoSPI)</li>
	<li>Update system_stm32h7xx.c to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)</li>
	<li>Add EWARM linker files for STM32H7A3 devices with reduced Flash size to 1MB:
	<ul>
	<li>stm32h7a3xg_flash.icf, stm32h7a3xg_flash_rw_sram1.icf, stm32h7a3xg_flash_rw_sram2.icf.</li>
	<li>stm32h7a3xgq_flash.icf, stm32h7a3xgq_flash_rw_sram1.icf, stm32h7a3xgq_flash_rw_sram2.icf.</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
	<div>
	<h2 id="main-changes-1">Main Changes</h2>
	<ul>
	<li><p>General updates to align Bit and registers definition with the STM32H7 reference manual</p></li>
	<li>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices:
	<ul>
	<li>Add “stm32h7a3xx.h”, “stm32h7a3xxq.h”, “stm32h7b3xx.h”, “stm32h7b3xxq.h”, “stm32h7b0xx.h” and “stm32h7b0xxq.h” files</li>
	<li>Add startup files “startup_stm32h7a3xx.s”, “startup_stm32h7a3xxq.s”, “startup_stm32h7b3xx.s”, “startup_stm32h7b3xxq.s”, “startup_stm32h7b0xx.s” and “startup_stm32h7b0xxq.s” for EWARM , MDK-ARM and STM32CubeIDE toolchains</li>
	<li>Add part numbers list to stm32h7xx.h header file:
	<ul>
	<li>STM32H7A3xx : STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6</li>
	<li>STM32H7A3xxQ : STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q</li>
	<li>STM32H7B3xx : STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6</li>
	<li>STM32H7B3xxQ : STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q</li>
	<li>STM32H7B0xx : STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ</li>
	</ul></li>
	</ul></li>
	<li>Update DMA2D bits definitions: Update to support Line offset mode and swap bytes features
	<ul>
	<li>Add CR_LOM (Line Ofset Mode) bit definition, Add OPFCCR_SB (Swap Bytes) bit definition</li>
	<li>Update CR_MODE, FGOR_LO, BGOR_LO and OOR_LO bit definition</li>
	</ul></li>
	<li>Update USB_OTG_GAHBCFG bit definition: to be aligned with LL_USB usage</li>
	<li><p>Add USB_OTG_DOEPMSK_AHBERRM, USB_OTG_DOEPMSK_BERRM, USB_OTG_DOEPMSK_NAKM, USB_OTG_DOEPMSK_NYETM, USB_OTG_DIEPINT_AHBERR, USB_OTG_DIEPINT_INEPNM, USB_OTG_DOEPINT_AHBERR, USB_OTG_DOEPINT_OUTPKTERR, USB_OTG_DOEPINT_BERR, USB_OTG_DOEPINT_NAK and USB_OTG_DOEPINT_STPKTRX bit definitions</p></li>
	<li><p>Update IS_TIM_REMAP_INSTANCE and IS_TIM_SYNCHRO_INSTANCE macro implemenation</p></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
	<div>
	<h2 id="main-changes-2">Main Changes</h2>
	<ul>
	<li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li>
	<li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li>
	<li>Add definition of “ART” bit fields: ART_CTR_EN and ART_CTR_PCACHEADDR<br />
	</li>
	<li>Update definitions of “HRTIM1_TIMA” to “HRTIM1_TIME” : pointer to HRTIM_Timerx_TypeDef structure instead of HRTIM_TIM_TypeDef</li>
	<li>Fix Typo in “ETH_TypeDef” definition: use uint32_t for “RESERVED16” registers instead of int32_t</li>
	<li>Remove useless definition of “SDMMC” instance (keep only definitions of “SDMMC1” and “SDMMC2”)</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
	<div>
	<h2 id="main-changes-3">Main Changes</h2>
	<ul>
	<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
	<li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li>
	<li>Add support of stm32h745xx, stm32h747xx, stm32h755xx, stm32h757xx <strong>Dual Core</strong> devices and STM32H742xx (new single core device):
	<ul>
	<li>Add “stm32h745xx.h” , “stm32h747xx.h”, “stm32h755xx.h”, “stm32h757xx.h” and “stm32h742xx.h” files</li>
	<li>Add startup files “startup_stm32h745xx.s”, “startup_stm32h747xx.s”, “startup_stm32h755xx.s”, “startup_stm32h757xx.s” and “startup_stm32h742xx.s” for EWARM , MDK-ARM and SW4STM32 toolchains</li>
	<li>Add part numbers list to stm32h7xx.h header file:
	<ul>
	<li>STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI</li>
	<li>STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI</li>
	<li>STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI</li>
	<li>STM32H750xx: STM32H750V, STM32H750I, STM32H750X</li>
	<li>STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI</li>
	<li>STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI</li>
	<li>STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI</li>
	<li><p>STM32H755xx: STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI</p></li>
	<li>Add system_stm32h7xx_singlecore.c : system initialization template source file for single core lines (STM32H743xx, STM32H753xx, STM32H750xx and STM32H742xx)</li>
	<li>Add system initialization template source file for dual core lines:
	<ul>
	<li>system_stm32h7xx_dualcore_boot_cm4_cm7.c: template for the boot case where Cortex-M7 and Cortex-M4 are boot at once</li>
	<li>system_stm32h7xx_dualcore_bootcm7_cm4gated.c: template for the boot case where Cortex-M7 is booting and Cortex-M4 is gated using FLASH Option Bytes</li>
	<li>system_stm32h7xx_dualcore_bootcm4_cm7gated.c: template for the boot case where Cortex-M4 is booting and Cortex-M7 is gated using FLASH Option Bytes</li>
	</ul></li>
	<li>Add EWARM, MDK-ARM and SW4STM32 <strong>Dual Core</strong> devices linker files</li>
	<li><p>Add EWARM STM32H742xx devices linker files</p></li>
	</ul></li>
	</ul></li>
	<li><strong>Registers and bit field definitions updates</strong>:
	<ul>
	<li>Update SYSCFG_TypeDef structure to add
	<ul>
	<li>Add CFGR register: allowing to control connection between double ECC RAMs/Flash errors, PVD errors and CortexM7/M4 lockup to TIM1/8/15/16/17 and HRTIMER Break inputs</li>
	<li>Add definitions of SYSCFG_CFGR register bit fields</li>
	<li>PWRCR registers: allowing to control the PWR overdrive enable/disable for Voltage Scaling zero</li>
	<li>Add SYSCFG_PWRCR register bit fields</li>
	</ul></li>
	<li>Update RCC_TypeDef structure according to STM32H7xx <strong>Rev.V</strong> devices:
	<ul>
	<li>ICSCR: renamed to HSICFGR, HSI Clock Calibration Register</li>
	<li>Rename also RCC_ICSCR_XXX bit definitions RCC_HSICFGR_XXX according to the new register HSICFGR</li>
	<li>CSICFGR: New registers (on <strong>Rev.V</strong> devices), CSI Clock Calibration Register</li>
	<li>Add dedicated RCC_CSICFGR_XXX bit definitions</li>
	</ul></li>
	<li>Keep RCC_Core_TypeDef structure used for Dual Core lines devices only: allowing RCC clock enabling/allocation for each Core(Cortex-M7/M4)
	<ul>
	<li>RCC_Core_TypeDef structure and RCC_C1_BASE/RCC_C1 definition removed from STM32H743xx/53xx and STM32H750xx lines</li>
	</ul></li>
	<li>Add CRYP_CR_NPBLB bit field definition: upon refresh of the CRYP peripheral on the STM32H7 <strong>Rev.V</strong> devices</li>
	<li>Update ADC_CR_BOOST bot field definition for STM32H7 <strong>Rev.V</strong> devices: 2 bits instead of 1</li>
	<li>Remove useless I2C_CR1_SWRST definition: alignment with the reference manual</li>
	<li>Add SAI_xCR1_NODIV bit field definition upon SAI peripheral update for STM32H7 <strong>Rev.V</strong> devices</li>
	<li>Rename SPI_TXCRC_RXCRC to SPI_RXCRC_RXCRC: typo fix and alignment with the reference manual</li>
	<li>Fix QUADSPI_SR_FLEVEL bit field definition: Mask on 6 bits (0x3F mask) instead of 5 bits(0x1F mask) and add definition of QUADSPI_SR_FLEVEL_6</li>
	<li>Add definition of SYSCFG_EXTICR3_EXTI8_PK, SYSCFG_EXTICR3_EXTI9_PK, SYSCFG_EXTICR3_EXTI10_PK, SYSCFG_EXTICR3_EXTI11_PK and SYSCFG_EXTICR4_EXTI13_PK</li>
	<li>Add definition of FLASH_LATENCY_DEFAULT: default safe FLASH latency</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label>
	<div>
	<h2 id="main-changes-4">Main Changes</h2>
	<ul>
	<li><strong>Patch Release on top of V1.3.0</strong></li>
	<li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:
	<ul>
	<li>stm32h743xx.h, stm32h750xx.h and stm32h753xx.h</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
	<div>
	<h2 id="main-changes-5">Main Changes</h2>
	<ul>
	<li>STM32H7xx include files:
	<ul>
	<li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
	<li>Update "_Mask" bits definition using UL suffix for Misra-C 2012 compliance</li>
	<li>Add definition of <strong>RAMECC_MonitorTypeDef</strong> and <strong>RAMECC_TypeDef</strong> structure</li>
	<li>Add definition of <strong>RAMECC</strong> peripheral base addresses</li>
	<li>Add <strong>RAMECC</strong> peripheral registers bit definitions</li>
	<li>Add IS_RAMECC_MONITOR_ALL_INSTANCE macro</li>
	<li>Add <strong>EXTI</strong> SWIER3 bit definitions</li>
	<li>Update <strong>FLASH</strong> sector number to 8 instead of 16 (8 sectors for each bank)</li>
	<li>Remove extra bit definition : FLASH_CR_SNB_3 to FLASH_CR_SNB_7</li>
	<li>Update <strong>FLASH</strong> user option bytes bit definition</li>
	<li>Fix FLASH_BANK_SIZE definition: add parenthesis</li>
	<li>Remove <strong>PWR</strong> extra bit definition PWR_CR1_RLPSN</li>
	<li>Add <strong>PWR</strong> bit definition PWR_WKUPEPR_WKUPEN</li>
	<li>Fix typo in <strong>SDMMC</strong> bit definition: SDMMC_MASK_SDIOITIE_Pos, SDMMC_MASK_SDIOITIE_Msk and SDMMC_MASK_SDIOITIE</li>
	<li>Add <strong>SDMMC</strong> instance check macro: IS_SDMMC_ALL_INSTANCE</li>
	<li>Fix typo in <strong>SYSCFG</strong> bit definition: SYSCFG_PMCR_EPIS_SEL_Pos, SYSCFG_PMCR_EPIS_SEL_Msk, SYSCFG_PMCR_EPIS_SEL and SYSCFG_PMCR_EPIS_SEL_0 to SYSCFG_PMCR_EPIS_SEL_2</li>
	<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR1_EXTI0_Msk, to SYSCFG_EXTICR1_EXTI3_Msk, 4 bits instead of 3</li>
	<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR2_EXTI0_Msk, to SYSCFG_EXTICR2_EXTI3_Msk, 4 bits instead of 3</li>
	<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR3_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI3_Msk, 4 bits instead of 3</li>
	<li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR4_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI4_Msk, 4 bits instead of 3</li>
	<li>Fix IS_ADC_COMMON_INSTANCE macro : add parenthesis</li>
	<li>Fix HSEM_CR_COREID_CURRENT and HSEM_CR_COREID_CURRENT: add parenthesis</li>
	<li>Update <strong>USART</strong> and <strong>SMARTCARD</strong> bits definition</li>
	<li>Update <strong>GPIO</strong> registers and bit definition (BSRR register)</li>
	<li>Add IS_GPIO_AF_INSTANCE macro</li>
	<li>Update <strong>DAC</strong> bits definition</li>
	<li>Update <strong>FDCAN</strong> bits definition</li>
	<li>Update <strong>USB</strong> bits definition (OTEPSPRM register)</li>
	<li>Fix <strong>CEC</strong> bit definition (RXDR register)</li>
	<li>Update <strong>TIM</strong> registers and bits definition naming</li>
	<li>Fix IS_TIM_CCX_INSTANCE macro : add TIM_CHANNEL_4 to TIM_CHANNEL_6</li>
	<li>Update <strong>SPI</strong> and <strong>I2S</strong> bits definition</li>
	<li>Update <strong>BDMA</strong> bits definition</li>
	<li>Update <strong>FMC</strong> bits definition</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
	<div>
	<h2 id="main-changes-6">Main Changes</h2>
	<ul>
	<li>Add support for stm32h750xx value line devices:
	<ul>
	<li>Add “stm32h750xx.h” file</li>
	<li>Add startup files startup_stm32h750xx.s for EWARM, MDK-ARM and SW4STM32</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
	<div>
	<h2 id="main-changes-7">Main Changes</h2>
	<ul>
	<li>Update FDCAN bit definition</li>
	<li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
	<div>
	<h2 id="main-changes-8">Main Changes</h2>
	<ul>
	<li>Update USB OTG bit definition</li>
	<li>Adjust PLL fractional computation</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
	<div>
	<h2 id="main-changes-9">Main Changes</h2>
	<ul>
	<li>First official release for <strong>STM32H743xx/753xx</strong> devices</li>
	</ul>
	</div>
	</div>
	</div>
	</div>
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