Release v1.10.4
diff --git a/Include/stm32h723xx.h b/Include/stm32h723xx.h index bf226aa..4c8a9d0 100644 --- a/Include/stm32h723xx.h +++ b/Include/stm32h723xx.h
@@ -3864,6 +3864,10 @@ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD2CR_AWD2CH_Pos (0U) +#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ + /******************** Bit definition for ADC_AWD3CR register ********************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ @@ -3889,6 +3893,10 @@ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD3CR_AWD3CH_Pos (0U) +#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */ + /******************** Bit definition for ADC_DIFSEL register ********************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ @@ -11719,7 +11727,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -18200,6 +18208,7 @@ /* Serial Peripheral Interface (SPI/I2S) */ /* */ /******************************************************************************/ +#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */ /******************* Bit definition for SPI_CR1 register ********************/ #define SPI_CR1_SPE_Pos (0U) #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */ @@ -21903,6 +21912,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -21928,7 +21940,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -21939,13 +21951,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -22015,6 +22035,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -22132,7 +22158,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h725xx.h b/Include/stm32h725xx.h index e5ad735..56eb393 100644 --- a/Include/stm32h725xx.h +++ b/Include/stm32h725xx.h
@@ -3865,6 +3865,10 @@ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD2CR_AWD2CH_Pos (0U) +#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ + /******************** Bit definition for ADC_AWD3CR register ********************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ @@ -3890,6 +3894,10 @@ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD3CR_AWD3CH_Pos (0U) +#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */ + /******************** Bit definition for ADC_DIFSEL register ********************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ @@ -11720,7 +11728,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -18212,6 +18220,7 @@ /* Serial Peripheral Interface (SPI/I2S) */ /* */ /******************************************************************************/ +#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */ /******************* Bit definition for SPI_CR1 register ********************/ #define SPI_CR1_SPE_Pos (0U) #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */ @@ -21915,6 +21924,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -21940,7 +21952,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -21951,13 +21963,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -22027,6 +22047,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -22144,7 +22170,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h730xx.h b/Include/stm32h730xx.h index 57dbeb4..2b2cea2 100644 --- a/Include/stm32h730xx.h +++ b/Include/stm32h730xx.h
@@ -3999,6 +3999,10 @@ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD2CR_AWD2CH_Pos (0U) +#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ + /******************** Bit definition for ADC_AWD3CR register ********************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ @@ -4024,6 +4028,10 @@ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD3CR_AWD3CH_Pos (0U) +#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */ + /******************** Bit definition for ADC_DIFSEL register ********************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ @@ -11973,7 +11981,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -18687,6 +18695,7 @@ /* Serial Peripheral Interface (SPI/I2S) */ /* */ /******************************************************************************/ +#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */ /******************* Bit definition for SPI_CR1 register ********************/ #define SPI_CR1_SPE_Pos (0U) #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */ @@ -22390,6 +22399,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -22415,7 +22427,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -22426,13 +22438,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -22502,6 +22522,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -22619,7 +22645,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h730xxq.h b/Include/stm32h730xxq.h index 1c7ac86..01c6a27 100644 --- a/Include/stm32h730xxq.h +++ b/Include/stm32h730xxq.h
@@ -4000,6 +4000,10 @@ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD2CR_AWD2CH_Pos (0U) +#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ + /******************** Bit definition for ADC_AWD3CR register ********************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ @@ -4025,6 +4029,10 @@ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD3CR_AWD3CH_Pos (0U) +#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */ + /******************** Bit definition for ADC_DIFSEL register ********************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ @@ -11974,7 +11982,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -18699,6 +18707,7 @@ /* Serial Peripheral Interface (SPI/I2S) */ /* */ /******************************************************************************/ +#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */ /******************* Bit definition for SPI_CR1 register ********************/ #define SPI_CR1_SPE_Pos (0U) #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */ @@ -22402,6 +22411,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -22427,7 +22439,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -22438,13 +22450,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -22514,6 +22534,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -22631,7 +22657,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h733xx.h b/Include/stm32h733xx.h index be446b8..2182327 100644 --- a/Include/stm32h733xx.h +++ b/Include/stm32h733xx.h
@@ -3999,6 +3999,10 @@ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD2CR_AWD2CH_Pos (0U) +#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ + /******************** Bit definition for ADC_AWD3CR register ********************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ @@ -4024,6 +4028,10 @@ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD3CR_AWD3CH_Pos (0U) +#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */ + /******************** Bit definition for ADC_DIFSEL register ********************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ @@ -18687,6 +18695,7 @@ /* Serial Peripheral Interface (SPI/I2S) */ /* */ /******************************************************************************/ +#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */ /******************* Bit definition for SPI_CR1 register ********************/ #define SPI_CR1_SPE_Pos (0U) #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */ @@ -22390,6 +22399,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -22415,7 +22427,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -22426,13 +22438,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -22502,6 +22522,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -22619,7 +22645,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h735xx.h b/Include/stm32h735xx.h index 07d23ab..bc5cd0d 100644 --- a/Include/stm32h735xx.h +++ b/Include/stm32h735xx.h
@@ -4000,6 +4000,10 @@ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD2CR_AWD2CH_Pos (0U) +#define ADC3_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD2CR_AWD2CH ADC3_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ + /******************** Bit definition for ADC_AWD3CR register ********************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ @@ -4025,6 +4029,10 @@ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC3_AWD3CR_AWD3CH_Pos (0U) +#define ADC3_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC3_AWD3CR_AWD3CH ADC3_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */ + /******************** Bit definition for ADC_DIFSEL register ********************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ @@ -11974,7 +11982,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -18699,6 +18707,7 @@ /* Serial Peripheral Interface (SPI/I2S) */ /* */ /******************************************************************************/ +#define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */ /******************* Bit definition for SPI_CR1 register ********************/ #define SPI_CR1_SPE_Pos (0U) #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */ @@ -22402,6 +22411,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -22427,7 +22439,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -22438,13 +22450,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -22514,6 +22534,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -22631,7 +22657,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h742xx.h b/Include/stm32h742xx.h index cdef725..de01dee 100644 --- a/Include/stm32h742xx.h +++ b/Include/stm32h742xx.h
@@ -11368,7 +11368,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -20659,7 +20659,7 @@ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ @@ -20868,7 +20868,7 @@ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -23643,6 +23643,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -23668,7 +23671,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -23679,13 +23682,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -23755,6 +23766,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -23872,7 +23889,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h743xx.h b/Include/stm32h743xx.h index b31ef96..ec21ef9 100644 --- a/Include/stm32h743xx.h +++ b/Include/stm32h743xx.h
@@ -11463,7 +11463,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -13210,7 +13210,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -21307,7 +21307,7 @@ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ @@ -21516,7 +21516,7 @@ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -24291,6 +24291,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -24316,7 +24319,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -24327,13 +24330,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -24403,6 +24414,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -24520,7 +24537,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h745xg.h b/Include/stm32h745xg.h index 0205f42..fa504d2 100644 --- a/Include/stm32h745xg.h +++ b/Include/stm32h745xg.h
@@ -11596,7 +11596,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -13734,7 +13734,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -22080,7 +22080,7 @@ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ @@ -22289,7 +22289,7 @@ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -25064,6 +25064,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -25089,7 +25092,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -25100,13 +25103,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -25176,6 +25187,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -25293,7 +25310,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h745xx.h b/Include/stm32h745xx.h index 34e0a4e..0c4fc03 100644 --- a/Include/stm32h745xx.h +++ b/Include/stm32h745xx.h
@@ -11596,7 +11596,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -13734,7 +13734,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -22080,7 +22080,7 @@ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ @@ -22289,7 +22289,7 @@ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -25064,6 +25064,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -25089,7 +25092,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -25100,13 +25103,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -25176,6 +25187,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -25293,7 +25310,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h747xg.h b/Include/stm32h747xg.h index 7471f7f..dab35c4 100644 --- a/Include/stm32h747xg.h +++ b/Include/stm32h747xg.h
@@ -14753,7 +14753,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -16891,7 +16891,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -25253,7 +25253,7 @@ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ @@ -25462,7 +25462,7 @@ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -28237,6 +28237,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -28262,7 +28265,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -28273,13 +28276,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -28349,6 +28360,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -28466,7 +28483,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h747xx.h b/Include/stm32h747xx.h index e7874cd..dc32f93 100644 --- a/Include/stm32h747xx.h +++ b/Include/stm32h747xx.h
@@ -14753,7 +14753,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -16891,7 +16891,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -25253,7 +25253,7 @@ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ @@ -25462,7 +25462,7 @@ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -28237,6 +28237,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -28262,7 +28265,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -28273,13 +28276,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -28349,6 +28360,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -28466,7 +28483,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h750xx.h b/Include/stm32h750xx.h index 27f9b90..8fce634 100644 --- a/Include/stm32h750xx.h +++ b/Include/stm32h750xx.h
@@ -11650,7 +11650,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -13473,7 +13473,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -21588,7 +21588,7 @@ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ @@ -21797,7 +21797,7 @@ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -24572,6 +24572,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -24597,7 +24600,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -24608,13 +24611,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -24684,6 +24695,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -24801,7 +24818,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h753xx.h b/Include/stm32h753xx.h index 64060c1..40a4bb2 100644 --- a/Include/stm32h753xx.h +++ b/Include/stm32h753xx.h
@@ -11656,7 +11656,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -13479,7 +13479,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -21594,7 +21594,7 @@ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ @@ -21803,7 +21803,7 @@ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -24578,6 +24578,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -24603,7 +24606,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -24614,13 +24617,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -24690,6 +24701,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -24807,7 +24824,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h755xx.h b/Include/stm32h755xx.h index b9dd5fa..b191b8e 100644 --- a/Include/stm32h755xx.h +++ b/Include/stm32h755xx.h
@@ -11789,7 +11789,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -14003,7 +14003,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -22367,7 +22367,7 @@ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ @@ -22576,7 +22576,7 @@ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -25351,6 +25351,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -25376,7 +25379,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -25387,13 +25390,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -25463,6 +25474,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -25580,7 +25597,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h757xx.h b/Include/stm32h757xx.h index 4e1b801..339fb95 100644 --- a/Include/stm32h757xx.h +++ b/Include/stm32h757xx.h
@@ -14946,7 +14946,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -17160,7 +17160,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -25540,7 +25540,7 @@ #define HRTIM_MCR_DACSYNC_Pos (25U) #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */ @@ -25749,7 +25749,7 @@ #define HRTIM_TIMCR_DACSYNC_Pos (25U) #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */ -#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */ +#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */ #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */ #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */ #define HRTIM_TIMCR_PREEN_Pos (27U) @@ -28524,6 +28524,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -28549,7 +28552,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -28560,13 +28563,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -28636,6 +28647,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -28753,7 +28770,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h7a3xx.h b/Include/stm32h7a3xx.h index 9c20602..998e8dd 100644 --- a/Include/stm32h7a3xx.h +++ b/Include/stm32h7a3xx.h
@@ -9423,7 +9423,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -11313,7 +11313,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -20194,6 +20194,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -20219,7 +20222,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -20230,13 +20233,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -20306,6 +20317,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -20423,7 +20440,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h7a3xxq.h b/Include/stm32h7a3xxq.h index e5a4710..dad5eef 100644 --- a/Include/stm32h7a3xxq.h +++ b/Include/stm32h7a3xxq.h
@@ -9424,7 +9424,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -11314,7 +11314,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -20206,6 +20206,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -20231,7 +20234,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -20242,13 +20245,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -20318,6 +20329,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -20435,7 +20452,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h7b0xx.h b/Include/stm32h7b0xx.h index 03ad90e..29e03e6 100644 --- a/Include/stm32h7b0xx.h +++ b/Include/stm32h7b0xx.h
@@ -9670,7 +9670,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -11636,7 +11636,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -20674,6 +20674,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -20699,7 +20702,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -20710,13 +20713,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -20786,6 +20797,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -20903,7 +20920,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h7b0xxq.h b/Include/stm32h7b0xxq.h index 9082828..7b84cf6 100644 --- a/Include/stm32h7b0xxq.h +++ b/Include/stm32h7b0xxq.h
@@ -9671,7 +9671,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -11637,7 +11637,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -20686,6 +20686,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -20711,7 +20714,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -20722,13 +20725,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -20798,6 +20809,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -20915,7 +20932,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h7b3xx.h b/Include/stm32h7b3xx.h index 9631e90..6210aa5 100644 --- a/Include/stm32h7b3xx.h +++ b/Include/stm32h7b3xx.h
@@ -9677,7 +9677,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -11643,7 +11643,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -20681,6 +20681,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -20706,7 +20709,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -20717,13 +20720,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -20793,6 +20804,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -20910,7 +20927,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h7b3xxq.h b/Include/stm32h7b3xxq.h index bf7344c..1242559 100644 --- a/Include/stm32h7b3xxq.h +++ b/Include/stm32h7b3xxq.h
@@ -9678,7 +9678,7 @@ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ -#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */ +#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ @@ -11644,7 +11644,7 @@ /******************** Bit definition for SR register ********************/ #define JPEG_SR_IFTF_Pos (1U) #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */ -#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */ #define JPEG_SR_IFNFF_Pos (2U) #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */ #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */ @@ -20693,6 +20693,9 @@ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ @@ -20718,7 +20721,7 @@ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ @@ -20729,13 +20732,21 @@ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ @@ -20805,6 +20816,12 @@ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U) +#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */ +#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition forUSB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) @@ -20922,7 +20939,7 @@ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */ /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
diff --git a/Include/stm32h7xx.h b/Include/stm32h7xx.h index c1fcad2..b0473a2 100644 --- a/Include/stm32h7xx.h +++ b/Include/stm32h7xx.h
@@ -102,11 +102,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.10.3 + * @brief CMSIS Device version number V1.10.4 */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */ -#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
diff --git a/Release_Notes.html b/Release_Notes.html index ad4b20b..9ee4c65 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
@@ -11,7 +11,7 @@ span.underline{text-decoration: underline;} div.column{display: inline-block; vertical-align: top; width: 50%;} </style> - <link rel="stylesheet" href="_htmresc/mini-st.css" /> + <link rel="stylesheet" href="_htmresc/mini-st_2020.css" /> <!--[if lt IE 9]> <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script> <![endif]--> @@ -30,10 +30,25 @@ <div class="col-sm-12 col-lg-8"> <h1 id="update-history"><strong>Update History</strong></h1> <div class="collapse"> -<input type="checkbox" id="collapse-section15" checked aria-hidden="true"> <label for="collapse-section15" aria-hidden="true"><strong>V1.10.3 / 04-November-2022</strong></label> +<input type="checkbox" id="collapse-section16" checked aria-hidden="true"> <label for="collapse-section16" aria-hidden="true"><strong>V1.10.4 / 15-March-2024</strong></label> <div> <h2 id="main-changes">Main Changes</h2> <ul> +<li>Update the values of the sensor calibration temperatures for H742, H743, and H753 part numbers.</li> +<li>Remove the unsupported MDMA BASE channel.</li> +<li>Align CMSIS with IP spec and product reference manual by adding missing bit fields definition.</li> +<li>Update STM32CubeIDE projects to fix the location of .size directive in startup code to allow proper size information of vector table.</li> +<li>Update the Cortex-M7 core revision.</li> +<li>Set FMC_SDCMR_MODE_2 bit field definition to 0x4.</li> +<li>Update to support I2S feature on SPI6 instance available on STM32H723xx, STM32H725xx, STM32H730xx, STM32H730xxQ, STM32H733xx and STM32H735xx devices.</li> +</ul> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true"><strong>V1.10.3 / 23-September-2022</strong></label> +<div> +<h2 id="main-changes-1">Main Changes</h2> +<ul> <li>General updates to fix known defects and implementation enhancements</li> <li>Update system_stm32h7xx_*.c template files to fix typo in comment: the VTOR offset value is multiple of 0x400.</li> <li>Adjust QUADSPI FIFO level threshold bits mask definition on 5 bits instead of 4bits.</li> @@ -43,7 +58,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.2 / 12-February-2022</strong></label> <div> -<h2 id="main-changes-1">Main Changes</h2> +<h2 id="main-changes-2">Main Changes</h2> <ul> <li>General updates to fix known defects and implementation enhancements</li> <li>Add support for ADC LDO output voltage ready bit.</li> @@ -58,7 +73,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label> <div> -<h2 id="main-changes-2">Main Changes</h2> +<h2 id="main-changes-3">Main Changes</h2> <ul> <li>General updates to fix known defects and implementation enhancements</li> <li>All source files: update disclaimer to add reference to the new license agreement.</li> @@ -84,7 +99,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label> <div> -<h2 id="main-changes-3">Main Changes</h2> +<h2 id="main-changes-4">Main Changes</h2> <ul> <li>Fix minor issues related to English typo in comments of registers and fields description</li> <li>Update STM32H7 devices header files to add GPV registers definition, base address and instance</li> @@ -102,7 +117,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label> <div> -<h2 id="main-changes-4">Main Changes</h2> +<h2 id="main-changes-5">Main Changes</h2> <ul> <li>Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices: <ul> @@ -160,7 +175,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label> <div> -<h2 id="main-changes-5">Main Changes</h2> +<h2 id="main-changes-6">Main Changes</h2> <ul> <li>General updates to align Bits and registers definitions with the STM32H7 reference manual</li> <li>Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero</li> @@ -181,7 +196,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label> <div> -<h2 id="main-changes-6">Main Changes</h2> +<h2 id="main-changes-7">Main Changes</h2> <ul> <li><p>General updates to align Bit and registers definition with the STM32H7 reference manual</p></li> <li>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices: @@ -211,7 +226,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label> <div> -<h2 id="main-changes-7">Main Changes</h2> +<h2 id="main-changes-8">Main Changes</h2> <ul> <li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li> <li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li> @@ -226,7 +241,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label> <div> -<h2 id="main-changes-8">Main Changes</h2> +<h2 id="main-changes-9">Main Changes</h2> <ul> <li>General updates to align Bit and registers definition with the STM32H7 reference manual</li> <li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li> @@ -290,7 +305,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label> <div> -<h2 id="main-changes-9">Main Changes</h2> +<h2 id="main-changes-10">Main Changes</h2> <ul> <li><strong>Patch Release on top of V1.3.0</strong></li> <li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files: @@ -303,7 +318,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label> <div> -<h2 id="main-changes-10">Main Changes</h2> +<h2 id="main-changes-11">Main Changes</h2> <ul> <li>STM32H7xx include files: <ul> @@ -348,7 +363,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label> <div> -<h2 id="main-changes-11">Main Changes</h2> +<h2 id="main-changes-12">Main Changes</h2> <ul> <li>Add support for stm32h750xx value line devices: <ul> @@ -361,7 +376,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label> <div> -<h2 id="main-changes-12">Main Changes</h2> +<h2 id="main-changes-13">Main Changes</h2> <ul> <li>Update FDCAN bit definition</li> <li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li> @@ -371,7 +386,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label> <div> -<h2 id="main-changes-13">Main Changes</h2> +<h2 id="main-changes-14">Main Changes</h2> <ul> <li>Update USB OTG bit definition</li> <li>Adjust PLL fractional computation</li> @@ -381,7 +396,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label> <div> -<h2 id="main-changes-14">Main Changes</h2> +<h2 id="main-changes-15">Main Changes</h2> <ul> <li>First official release for <strong>STM32H743xx/753xx</strong> devices</li> </ul>
diff --git a/Source/Templates/gcc/linker/stm32h745xg_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h745xg_flash_CM4.ld index 332776f..b72b837 100644 --- a/Source/Templates/gcc/linker/stm32h745xg_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h745xg_flash_CM4.ld
@@ -84,27 +84,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld index 3303fdb..4dfeb02 100644 --- a/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld
@@ -85,27 +85,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h745xx_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h745xx_flash_CM4.ld index 0def732..88243c9 100644 --- a/Source/Templates/gcc/linker/stm32h745xx_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h745xx_flash_CM4.ld
@@ -84,27 +84,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld index 956771b..a6efc45 100644 --- a/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld
@@ -85,27 +85,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h745xx_sram1_CM7.ld b/Source/Templates/gcc/linker/stm32h745xx_sram1_CM7.ld index 33c3dc7..78282a4 100644 --- a/Source/Templates/gcc/linker/stm32h745xx_sram1_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h745xx_sram1_CM7.ld
@@ -84,27 +84,31 @@ . = ALIGN(4); } >RAM_EXEC - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM_EXEC + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM_EXEC - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM_EXEC - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >RAM_EXEC - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h745xx_sram2_CM4.ld b/Source/Templates/gcc/linker/stm32h745xx_sram2_CM4.ld index 9b40dbf..1f3e588 100644 --- a/Source/Templates/gcc/linker/stm32h745xx_sram2_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h745xx_sram2_CM4.ld
@@ -84,27 +84,31 @@ . = ALIGN(4); } >RAM_EXEC - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM_EXEC + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM_EXEC - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM_EXEC - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >RAM_EXEC - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h747xg_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h747xg_flash_CM4.ld index 332776f..b72b837 100644 --- a/Source/Templates/gcc/linker/stm32h747xg_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h747xg_flash_CM4.ld
@@ -84,27 +84,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld index 3303fdb..4dfeb02 100644 --- a/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld
@@ -85,27 +85,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h747xx_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h747xx_flash_CM4.ld index 0def732..88243c9 100644 --- a/Source/Templates/gcc/linker/stm32h747xx_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h747xx_flash_CM4.ld
@@ -84,27 +84,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld index 956771b..a6efc45 100644 --- a/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld
@@ -85,27 +85,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h747xx_sram1_CM7.ld b/Source/Templates/gcc/linker/stm32h747xx_sram1_CM7.ld index 1704cea..709f0c7 100644 --- a/Source/Templates/gcc/linker/stm32h747xx_sram1_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h747xx_sram1_CM7.ld
@@ -83,27 +83,31 @@ . = ALIGN(4); } >RAM_EXEC - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM_EXEC + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM_EXEC - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM_EXEC - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >RAM_EXEC - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h747xx_sram2_CM4.ld b/Source/Templates/gcc/linker/stm32h747xx_sram2_CM4.ld index 9b40dbf..1f3e588 100644 --- a/Source/Templates/gcc/linker/stm32h747xx_sram2_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h747xx_sram2_CM4.ld
@@ -84,27 +84,31 @@ . = ALIGN(4); } >RAM_EXEC - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM_EXEC + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM_EXEC - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM_EXEC - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >RAM_EXEC - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h755xx_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h755xx_flash_CM4.ld index bb37506..a34e143 100644 --- a/Source/Templates/gcc/linker/stm32h755xx_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h755xx_flash_CM4.ld
@@ -83,27 +83,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld index 9383036..176419e 100644 --- a/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld
@@ -84,27 +84,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h755xx_sram1_CM7.ld b/Source/Templates/gcc/linker/stm32h755xx_sram1_CM7.ld index 1704cea..709f0c7 100644 --- a/Source/Templates/gcc/linker/stm32h755xx_sram1_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h755xx_sram1_CM7.ld
@@ -83,27 +83,31 @@ . = ALIGN(4); } >RAM_EXEC - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM_EXEC + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM_EXEC - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM_EXEC - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >RAM_EXEC - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h755xx_sram2_CM4.ld b/Source/Templates/gcc/linker/stm32h755xx_sram2_CM4.ld index 521b55b..5708151 100644 --- a/Source/Templates/gcc/linker/stm32h755xx_sram2_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h755xx_sram2_CM4.ld
@@ -85,27 +85,31 @@ . = ALIGN(4); } >RAM_EXEC - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM_EXEC + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM_EXEC - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM_EXEC - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >RAM_EXEC - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h757xx_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h757xx_flash_CM4.ld index bb37506..a34e143 100644 --- a/Source/Templates/gcc/linker/stm32h757xx_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h757xx_flash_CM4.ld
@@ -83,27 +83,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld index 9383036..176419e 100644 --- a/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld
@@ -84,27 +84,31 @@ . = ALIGN(4); } >FLASH - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >FLASH - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h757xx_sram1_CM7.ld b/Source/Templates/gcc/linker/stm32h757xx_sram1_CM7.ld index 1704cea..709f0c7 100644 --- a/Source/Templates/gcc/linker/stm32h757xx_sram1_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h757xx_sram1_CM7.ld
@@ -83,27 +83,31 @@ . = ALIGN(4); } >RAM_EXEC - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM_EXEC + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM_EXEC - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM_EXEC - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >RAM_EXEC - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/linker/stm32h757xx_sram2_CM4.ld b/Source/Templates/gcc/linker/stm32h757xx_sram2_CM4.ld index 3b7012e..fdf1128 100644 --- a/Source/Templates/gcc/linker/stm32h757xx_sram2_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h757xx_sram2_CM4.ld
@@ -83,27 +83,31 @@ . = ALIGN(4); } >RAM_EXEC - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC - .ARM : { + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM_EXEC + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; } >RAM_EXEC - .preinit_array : + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); } >RAM_EXEC - .init_array : + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); } >RAM_EXEC - .fini_array : + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*)))
diff --git a/Source/Templates/gcc/startup_stm32h723xx.s b/Source/Templates/gcc/startup_stm32h723xx.s index 8ca5ddc..1b11e21 100644 --- a/Source/Templates/gcc/startup_stm32h723xx.s +++ b/Source/Templates/gcc/startup_stm32h723xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -309,6 +307,8 @@ .word TIM23_IRQHandler /* TIM23 global interrupt */ .word TIM24_IRQHandler /* TIM24 global interrupt */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h725xx.s b/Source/Templates/gcc/startup_stm32h725xx.s index f299b28..67e8c3b 100644 --- a/Source/Templates/gcc/startup_stm32h725xx.s +++ b/Source/Templates/gcc/startup_stm32h725xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -309,6 +307,8 @@ .word TIM23_IRQHandler /* TIM23 global interrupt */ .word TIM24_IRQHandler /* TIM24 global interrupt */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h730xx.s b/Source/Templates/gcc/startup_stm32h730xx.s index 1dcce49..cb72ff2 100644 --- a/Source/Templates/gcc/startup_stm32h730xx.s +++ b/Source/Templates/gcc/startup_stm32h730xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -309,6 +307,8 @@ .word TIM23_IRQHandler /* TIM23 global interrupt */ .word TIM24_IRQHandler /* TIM24 global interrupt */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h730xxq.s b/Source/Templates/gcc/startup_stm32h730xxq.s index 2eda302..af8cb46 100644 --- a/Source/Templates/gcc/startup_stm32h730xxq.s +++ b/Source/Templates/gcc/startup_stm32h730xxq.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -309,6 +307,8 @@ .word TIM23_IRQHandler /* TIM23 global interrupt */ .word TIM24_IRQHandler /* TIM24 global interrupt */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h733xx.s b/Source/Templates/gcc/startup_stm32h733xx.s index c0a50eb..674fc67 100644 --- a/Source/Templates/gcc/startup_stm32h733xx.s +++ b/Source/Templates/gcc/startup_stm32h733xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -309,6 +307,8 @@ .word TIM23_IRQHandler /* TIM23 global interrupt */ .word TIM24_IRQHandler /* TIM24 global interrupt */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h735xx.s b/Source/Templates/gcc/startup_stm32h735xx.s index 3f72238..ec88982 100644 --- a/Source/Templates/gcc/startup_stm32h735xx.s +++ b/Source/Templates/gcc/startup_stm32h735xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -309,6 +307,8 @@ .word TIM23_IRQHandler /* TIM23 global interrupt */ .word TIM24_IRQHandler /* TIM24 global interrupt */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h742xx.s b/Source/Templates/gcc/startup_stm32h742xx.s index 8046e44..e4c4df3 100644 --- a/Source/Templates/gcc/startup_stm32h742xx.s +++ b/Source/Templates/gcc/startup_stm32h742xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -296,6 +294,8 @@ .word 0 /* Reserved */ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h743xx.s b/Source/Templates/gcc/startup_stm32h743xx.s index 480136b..26eb214 100644 --- a/Source/Templates/gcc/startup_stm32h743xx.s +++ b/Source/Templates/gcc/startup_stm32h743xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -296,6 +294,8 @@ .word 0 /* Reserved */ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h745xg.s b/Source/Templates/gcc/startup_stm32h745xg.s index 881a25f..98cd733 100644 --- a/Source/Templates/gcc/startup_stm32h745xg.s +++ b/Source/Templates/gcc/startup_stm32h745xg.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -296,6 +294,8 @@ .word HOLD_CORE_IRQHandler /* Hold core interrupt */ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h745xx.s b/Source/Templates/gcc/startup_stm32h745xx.s index 881a25f..98cd733 100644 --- a/Source/Templates/gcc/startup_stm32h745xx.s +++ b/Source/Templates/gcc/startup_stm32h745xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -296,6 +294,8 @@ .word HOLD_CORE_IRQHandler /* Hold core interrupt */ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h747xg.s b/Source/Templates/gcc/startup_stm32h747xg.s index 0cabab3..283540b 100644 --- a/Source/Templates/gcc/startup_stm32h747xg.s +++ b/Source/Templates/gcc/startup_stm32h747xg.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -296,6 +294,8 @@ .word HOLD_CORE_IRQHandler /* Hold core interrupt */ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h747xx.s b/Source/Templates/gcc/startup_stm32h747xx.s index d6f7741..4c55c05 100644 --- a/Source/Templates/gcc/startup_stm32h747xx.s +++ b/Source/Templates/gcc/startup_stm32h747xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -296,6 +294,8 @@ .word HOLD_CORE_IRQHandler /* Hold core interrupt */ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h750xx.s b/Source/Templates/gcc/startup_stm32h750xx.s index 3cdcc4f..dc7c0fd 100644 --- a/Source/Templates/gcc/startup_stm32h750xx.s +++ b/Source/Templates/gcc/startup_stm32h750xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -296,6 +294,8 @@ .word 0 /* Reserved */ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h753xx.s b/Source/Templates/gcc/startup_stm32h753xx.s index bf9c67c..3dec8ae 100644 --- a/Source/Templates/gcc/startup_stm32h753xx.s +++ b/Source/Templates/gcc/startup_stm32h753xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -296,6 +294,8 @@ .word 0 /* Reserved */ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h755xx.s b/Source/Templates/gcc/startup_stm32h755xx.s index 705b6c5..6779078 100644 --- a/Source/Templates/gcc/startup_stm32h755xx.s +++ b/Source/Templates/gcc/startup_stm32h755xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -296,6 +294,8 @@ .word HOLD_CORE_IRQHandler /* Hold core interrupt */ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h757xx.s b/Source/Templates/gcc/startup_stm32h757xx.s index c86ecef..7f03e9a 100644 --- a/Source/Templates/gcc/startup_stm32h757xx.s +++ b/Source/Templates/gcc/startup_stm32h757xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ @@ -296,6 +294,8 @@ .word HOLD_CORE_IRQHandler /* Hold core interrupt */ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h7a3xx.s b/Source/Templates/gcc/startup_stm32h7a3xx.s index ff47a1a..c5f259f 100644 --- a/Source/Templates/gcc/startup_stm32h7a3xx.s +++ b/Source/Templates/gcc/startup_stm32h7a3xx.s
@@ -142,8 +142,6 @@ .word PendSV_Handler .word SysTick_Handler - .size g_pfnVectors, .-g_pfnVectors - /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */ @@ -301,6 +299,8 @@ .word GFXMMU_IRQHandler /* GFXMMU */ .word BDMA1_IRQHandler /* BDMA1 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h7a3xxq.s b/Source/Templates/gcc/startup_stm32h7a3xxq.s index c749ba8..ab96718 100644 --- a/Source/Templates/gcc/startup_stm32h7a3xxq.s +++ b/Source/Templates/gcc/startup_stm32h7a3xxq.s
@@ -141,8 +141,6 @@ .word 0 .word PendSV_Handler .word SysTick_Handler - - .size g_pfnVectors, .-g_pfnVectors /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ @@ -301,6 +299,8 @@ .word GFXMMU_IRQHandler /* GFXMMU */ .word BDMA1_IRQHandler /* BDMA1 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h7b0xx.s b/Source/Templates/gcc/startup_stm32h7b0xx.s index 1764f80..ac3c9ca 100644 --- a/Source/Templates/gcc/startup_stm32h7b0xx.s +++ b/Source/Templates/gcc/startup_stm32h7b0xx.s
@@ -141,8 +141,6 @@ .word 0 .word PendSV_Handler .word SysTick_Handler - - .size g_pfnVectors, .-g_pfnVectors /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ @@ -301,6 +299,8 @@ .word GFXMMU_IRQHandler /* GFXMMU */ .word BDMA1_IRQHandler /* BDMA1 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h7b0xxq.s b/Source/Templates/gcc/startup_stm32h7b0xxq.s index 2e70d27..c14e62c 100644 --- a/Source/Templates/gcc/startup_stm32h7b0xxq.s +++ b/Source/Templates/gcc/startup_stm32h7b0xxq.s
@@ -141,8 +141,6 @@ .word 0 .word PendSV_Handler .word SysTick_Handler - - .size g_pfnVectors, .-g_pfnVectors /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ @@ -301,6 +299,8 @@ .word GFXMMU_IRQHandler /* GFXMMU */ .word BDMA1_IRQHandler /* BDMA1 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h7b3xx.s b/Source/Templates/gcc/startup_stm32h7b3xx.s index 4457714..c990644 100644 --- a/Source/Templates/gcc/startup_stm32h7b3xx.s +++ b/Source/Templates/gcc/startup_stm32h7b3xx.s
@@ -141,8 +141,6 @@ .word 0 .word PendSV_Handler .word SysTick_Handler - - .size g_pfnVectors, .-g_pfnVectors /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ @@ -301,6 +299,8 @@ .word GFXMMU_IRQHandler /* GFXMMU */ .word BDMA1_IRQHandler /* BDMA1 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/Source/Templates/gcc/startup_stm32h7b3xxq.s b/Source/Templates/gcc/startup_stm32h7b3xxq.s index fcff30e..bdf46c1 100644 --- a/Source/Templates/gcc/startup_stm32h7b3xxq.s +++ b/Source/Templates/gcc/startup_stm32h7b3xxq.s
@@ -141,8 +141,6 @@ .word 0 .word PendSV_Handler .word SysTick_Handler - - .size g_pfnVectors, .-g_pfnVectors /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ @@ -301,6 +299,8 @@ .word GFXMMU_IRQHandler /* GFXMMU */ .word BDMA1_IRQHandler /* BDMA1 */ + .size g_pfnVectors, .-g_pfnVectors + /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler.
diff --git a/_htmresc/mini-st.css b/_htmresc/mini-st.css deleted file mode 100644 index eb41d56..0000000 --- a/_htmresc/mini-st.css +++ /dev/null
@@ -1,1700 +0,0 @@ -@charset "UTF-8"; -/* - Flavor name: Default (mini-default) - Author: Angelos Chalaris (chalarangelo@gmail.com) - Maintainers: Angelos Chalaris - mini.css version: v3.0.0-alpha.3 -*/ -/* - Browsers resets and base typography. -*/ -/* Core module CSS variable definitions */ -:root { - --fore-color: #111; - --secondary-fore-color: #444; - --back-color: #f8f8f8; - --secondary-back-color: #f0f0f0; - --blockquote-color: #f57c00; - --pre-color: #1565c0; - --border-color: #aaa; - --secondary-border-color: #ddd; - --heading-ratio: 1.19; - --universal-margin: 0.5rem; - --universal-padding: 0.125rem; - --universal-border-radius: 0.125rem; - --a-link-color: #0277bd; - --a-visited-color: #01579b; } - -html { - font-size: 14px; } - -a, b, del, em, i, ins, q, span, strong, u { - font-size: 1em; } - -html, * { - font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; - line-height: 1.4; - -webkit-text-size-adjust: 100%; } - -* { - font-size: 1rem; } - -body { - margin: 0; - color: var(--fore-color); - background: var(--back-color); } - -details { - display: block; } - -summary { - display: list-item; } - -abbr[title] { - border-bottom: none; - text-decoration: underline dotted; } - -input { - overflow: visible; } - -img { - max-width: 100%; - height: auto; } - -h1, h2, h3, h4, h5, h6 { - line-height: 1.2; - margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); - font-weight: 500; } - h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { - color: var(--secondary-fore-color); - display: block; - margin-top: -0.25rem; } - -h1 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } - -h2 { - font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); - background: var(--mark-back-color); - font-weight: 600; - padding: 0.1em 0.5em 0.2em 0.5em; - color: var(--mark-fore-color); } - -h3 { - font-size: calc(1rem * var(--heading-ratio)); - padding-left: calc(2 * var(--universal-margin)); - /* background: var(--border-color); */ - } - -h4 { - font-size: 1rem;); - padding-left: calc(4 * var(--universal-margin)); } - -h5 { - font-size: 1rem; } - -h6 { - font-size: calc(1rem / var(--heading-ratio)); } - -p { - margin: var(--universal-margin); } - -ol, ul { - margin: var(--universal-margin); - padding-left: calc(6 * var(--universal-margin)); } - -b, strong { - font-weight: 700; } - -hr { - box-sizing: content-box; - border: 0; - line-height: 1.25em; - margin: var(--universal-margin); - height: 0.0625rem; - background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } - -blockquote { - display: block; - position: relative; - font-style: italic; - color: var(--secondary-fore-color); - margin: var(--universal-margin); - padding: calc(3 * var(--universal-padding)); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.375rem solid var(--blockquote-color); - border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } - blockquote:before { - position: absolute; - top: calc(0rem - var(--universal-padding)); - left: 0; - font-family: sans-serif; - font-size: 3rem; - font-weight: 700; - content: "\201c"; - color: var(--blockquote-color); } - blockquote[cite]:after { - font-style: normal; - font-size: 0.75em; - font-weight: 700; - content: "\a— " attr(cite); - white-space: pre; } - -code, kbd, pre, samp { - font-family: Menlo, Consolas, monospace; - font-size: 0.85em; } - -code { - background: var(--secondary-back-color); - border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } - -kbd { - background: var(--fore-color); - color: var(--back-color); - border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } - -pre { - overflow: auto; - background: var(--secondary-back-color); - padding: calc(1.5 * var(--universal-padding)); - margin: var(--universal-margin); - border: 0.0625rem solid var(--secondary-border-color); - border-left: 0.25rem solid var(--pre-color); - border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } - -sup, sub, code, kbd { - line-height: 0; - position: relative; - vertical-align: baseline; } - -small, sup, sub, figcaption { - font-size: 0.75em; } - -sup { - top: -0.5em; } - -sub { - bottom: -0.25em; } - -figure { - margin: var(--universal-margin); } - -figcaption { - color: var(--secondary-fore-color); } - -a { - text-decoration: none; } - a:link { - color: var(--a-link-color); } - a:visited { - color: var(--a-visited-color); } - a:hover, a:focus { - text-decoration: underline; } - -/* - Definitions for the grid system, cards and containers. -*/ -.container { - margin: 0 auto; - padding: 0 calc(1.5 * var(--universal-padding)); } - -.row { - box-sizing: border-box; - display: flex; - flex: 0 1 auto; - flex-flow: row wrap; } - -.col-sm, -[class^='col-sm-'], -[class^='col-sm-offset-'], -.row[class*='cols-sm-'] > * { - box-sizing: border-box; - flex: 0 0 auto; - padding: 0 calc(var(--universal-padding) / 2); } - -.col-sm, -.row.cols-sm > * { - max-width: 100%; - flex-grow: 1; - flex-basis: 0; } - -.col-sm-1, -.row.cols-sm-1 > * { - max-width: 8.3333333333%; - flex-basis: 8.3333333333%; } - -.col-sm-offset-0 { - margin-left: 0; } - -.col-sm-2, -.row.cols-sm-2 > * { - max-width: 16.6666666667%; - flex-basis: 16.6666666667%; } - -.col-sm-offset-1 { - margin-left: 8.3333333333%; } - -.col-sm-3, -.row.cols-sm-3 > * { - max-width: 25%; - flex-basis: 25%; } - -.col-sm-offset-2 { - margin-left: 16.6666666667%; } - -.col-sm-4, -.row.cols-sm-4 > * { - max-width: 33.3333333333%; - flex-basis: 33.3333333333%; } - -.col-sm-offset-3 { - margin-left: 25%; } - -.col-sm-5, -.row.cols-sm-5 > * { - max-width: 41.6666666667%; - flex-basis: 41.6666666667%; } - -.col-sm-offset-4 { - margin-left: 33.3333333333%; } - -.col-sm-6, -.row.cols-sm-6 > * { - max-width: 50%; - flex-basis: 50%; } - -.col-sm-offset-5 { - margin-left: 41.6666666667%; } - -.col-sm-7, -.row.cols-sm-7 > * { - max-width: 58.3333333333%; - flex-basis: 58.3333333333%; } - -.col-sm-offset-6 { - margin-left: 50%; } - -.col-sm-8, -.row.cols-sm-8 > * { - max-width: 66.6666666667%; - flex-basis: 66.6666666667%; } - -.col-sm-offset-7 { - margin-left: 58.3333333333%; } - -.col-sm-9, -.row.cols-sm-9 > * { - max-width: 75%; - flex-basis: 75%; } - -.col-sm-offset-8 { - margin-left: 66.6666666667%; } - -.col-sm-10, -.row.cols-sm-10 > * { - max-width: 83.3333333333%; - flex-basis: 83.3333333333%; } - -.col-sm-offset-9 { - margin-left: 75%; } - -.col-sm-11, -.row.cols-sm-11 > * { - max-width: 91.6666666667%; - flex-basis: 91.6666666667%; } - -.col-sm-offset-10 { - margin-left: 83.3333333333%; } - -.col-sm-12, -.row.cols-sm-12 > * { - max-width: 100%; - flex-basis: 100%; } - -.col-sm-offset-11 { - margin-left: 91.6666666667%; } - -.col-sm-normal { - order: initial; } - -.col-sm-first { - order: -999; } - -.col-sm-last { - order: 999; } - -@media screen and (min-width: 500px) { - .col-md, - [class^='col-md-'], - [class^='col-md-offset-'], - .row[class*='cols-md-'] > * { - box-sizing: border-box; - flex: 0 0 auto; - padding: 0 calc(var(--universal-padding) / 2); } - - .col-md, - .row.cols-md > * { - max-width: 100%; - flex-grow: 1; - flex-basis: 0; } - - .col-md-1, - .row.cols-md-1 > * { - max-width: 8.3333333333%; - flex-basis: 8.3333333333%; } - - .col-md-offset-0 { - margin-left: 0; } - - .col-md-2, - .row.cols-md-2 > * { - max-width: 16.6666666667%; - flex-basis: 16.6666666667%; } - - .col-md-offset-1 { - margin-left: 8.3333333333%; } - - .col-md-3, - .row.cols-md-3 > * { - max-width: 25%; - flex-basis: 25%; } - - .col-md-offset-2 { - margin-left: 16.6666666667%; } - - .col-md-4, - .row.cols-md-4 > * { - max-width: 33.3333333333%; - flex-basis: 33.3333333333%; } - - .col-md-offset-3 { - margin-left: 25%; } - - .col-md-5, - .row.cols-md-5 > * { - max-width: 41.6666666667%; - flex-basis: 41.6666666667%; } - - .col-md-offset-4 { - margin-left: 33.3333333333%; } - - .col-md-6, - .row.cols-md-6 > * { - max-width: 50%; - flex-basis: 50%; } - - .col-md-offset-5 { - margin-left: 41.6666666667%; } - - .col-md-7, - .row.cols-md-7 > * { - max-width: 58.3333333333%; - flex-basis: 58.3333333333%; } - - .col-md-offset-6 { - margin-left: 50%; } - - .col-md-8, - .row.cols-md-8 > * { - max-width: 66.6666666667%; - flex-basis: 66.6666666667%; } - - .col-md-offset-7 { - margin-left: 58.3333333333%; } - - .col-md-9, - .row.cols-md-9 > * { - max-width: 75%; - flex-basis: 75%; } - - .col-md-offset-8 { - margin-left: 66.6666666667%; } - - .col-md-10, - .row.cols-md-10 > * { - max-width: 83.3333333333%; - flex-basis: 83.3333333333%; } - - .col-md-offset-9 { - margin-left: 75%; } - - .col-md-11, - .row.cols-md-11 > * { - max-width: 91.6666666667%; - flex-basis: 91.6666666667%; } - - .col-md-offset-10 { - margin-left: 83.3333333333%; } - - .col-md-12, - .row.cols-md-12 > * { - max-width: 100%; - flex-basis: 100%; } - - .col-md-offset-11 { - margin-left: 91.6666666667%; } - - .col-md-normal { - order: initial; } - - .col-md-first { - order: -999; } - - .col-md-last { - order: 999; } } -@media screen and (min-width: 1280px) { - .col-lg, - [class^='col-lg-'], - [class^='col-lg-offset-'], - .row[class*='cols-lg-'] > * { - box-sizing: border-box; - flex: 0 0 auto; - padding: 0 calc(var(--universal-padding) / 2); } - - .col-lg, - .row.cols-lg > * { - max-width: 100%; - flex-grow: 1; - flex-basis: 0; } - - .col-lg-1, - .row.cols-lg-1 > * { - max-width: 8.3333333333%; - flex-basis: 8.3333333333%; } - - .col-lg-offset-0 { - margin-left: 0; } - - .col-lg-2, - .row.cols-lg-2 > * { - max-width: 16.6666666667%; - flex-basis: 16.6666666667%; } - - .col-lg-offset-1 { - margin-left: 8.3333333333%; } - - .col-lg-3, - .row.cols-lg-3 > * { - max-width: 25%; - flex-basis: 25%; } - - .col-lg-offset-2 { - margin-left: 16.6666666667%; } - - .col-lg-4, - .row.cols-lg-4 > * { - max-width: 33.3333333333%; - flex-basis: 33.3333333333%; } - - .col-lg-offset-3 { - margin-left: 25%; } - - .col-lg-5, - .row.cols-lg-5 > * { - max-width: 41.6666666667%; - flex-basis: 41.6666666667%; } - - .col-lg-offset-4 { - margin-left: 33.3333333333%; } - - .col-lg-6, - .row.cols-lg-6 > * { - max-width: 50%; - flex-basis: 50%; } - - .col-lg-offset-5 { - margin-left: 41.6666666667%; } - - .col-lg-7, - .row.cols-lg-7 > * { - max-width: 58.3333333333%; - flex-basis: 58.3333333333%; } - - .col-lg-offset-6 { - margin-left: 50%; } - - .col-lg-8, - .row.cols-lg-8 > * { - max-width: 66.6666666667%; - flex-basis: 66.6666666667%; } - - .col-lg-offset-7 { - margin-left: 58.3333333333%; } - - .col-lg-9, - .row.cols-lg-9 > * { - max-width: 75%; - flex-basis: 75%; } - - .col-lg-offset-8 { - margin-left: 66.6666666667%; } - - .col-lg-10, - .row.cols-lg-10 > * { - max-width: 83.3333333333%; - flex-basis: 83.3333333333%; } - - .col-lg-offset-9 { - margin-left: 75%; } - - .col-lg-11, - .row.cols-lg-11 > * { - max-width: 91.6666666667%; - flex-basis: 91.6666666667%; } - - .col-lg-offset-10 { - margin-left: 83.3333333333%; } - - .col-lg-12, - .row.cols-lg-12 > * { - max-width: 100%; - flex-basis: 100%; } - - .col-lg-offset-11 { - margin-left: 91.6666666667%; } - - .col-lg-normal { - order: initial; } - - .col-lg-first { - order: -999; } - - .col-lg-last { - order: 999; } } -/* Card component CSS variable definitions */ -:root { - --card-back-color: #f8f8f8; - --card-fore-color: #111; - --card-border-color: #ddd; } - -.card { - display: flex; - flex-direction: column; - justify-content: space-between; - align-self: center; - position: relative; - width: 100%; - background: var(--card-back-color); - color: var(--card-fore-color); - border: 0.0625rem solid var(--card-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); - overflow: hidden; } - @media screen and (min-width: 320px) { - .card { - max-width: 320px; } } - .card > .sectione { - background: var(--card-back-color); - color: var(--card-fore-color); - box-sizing: border-box; - margin: 0; - border: 0; - border-radius: 0; - border-bottom: 0.0625rem solid var(--card-border-color); - padding: var(--universal-padding); - width: 100%; } - .card > .sectione.media { - height: 200px; - padding: 0; - -o-object-fit: cover; - object-fit: cover; } - .card > .sectione:last-child { - border-bottom: 0; } - -/* - Custom elements for card elements. -*/ -@media screen and (min-width: 240px) { - .card.small { - max-width: 240px; } } -@media screen and (min-width: 480px) { - .card.large { - max-width: 480px; } } -.card.fluid { - max-width: 100%; - width: auto; } - -.card.warning { -/* --card-back-color: #ffca28; */ - --card-back-color: #e5b8b7; - --card-border-color: #e8b825; } - -.card.error { - --card-back-color: #b71c1c; - --card-fore-color: #f8f8f8; - --card-border-color: #a71a1a; } - -.card > .sectione.dark { - --card-back-color: #e0e0e0; } - -.card > .sectione.double-padded { - padding: calc(1.5 * var(--universal-padding)); } - -/* - Definitions for forms and input elements. -*/ -/* Input_control module CSS variable definitions */ -:root { - --form-back-color: #f0f0f0; - --form-fore-color: #111; - --form-border-color: #ddd; - --input-back-color: #f8f8f8; - --input-fore-color: #111; - --input-border-color: #ddd; - --input-focus-color: #0288d1; - --input-invalid-color: #d32f2f; - --button-back-color: #e2e2e2; - --button-hover-back-color: #dcdcdc; - --button-fore-color: #212121; - --button-border-color: transparent; - --button-hover-border-color: transparent; - --button-group-border-color: rgba(124, 124, 124, 0.54); } - -form { - background: var(--form-back-color); - color: var(--form-fore-color); - border: 0.0625rem solid var(--form-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); - padding: calc(2 * var(--universal-padding)) var(--universal-padding); } - -fieldset { - border: 0.0625rem solid var(--form-border-color); - border-radius: var(--universal-border-radius); - margin: calc(var(--universal-margin) / 4); - padding: var(--universal-padding); } - -legend { - box-sizing: border-box; - display: table; - max-width: 100%; - white-space: normal; - font-weight: 700; - padding: calc(var(--universal-padding) / 2); } - -label { - padding: calc(var(--universal-padding) / 2) var(--universal-padding); } - -.input-group { - display: inline-block; } - .input-group.fluid { - display: flex; - align-items: center; - justify-content: center; } - .input-group.fluid > input { - max-width: 100%; - flex-grow: 1; - flex-basis: 0px; } - @media screen and (max-width: 499px) { - .input-group.fluid { - align-items: stretch; - flex-direction: column; } } - .input-group.vertical { - display: flex; - align-items: stretch; - flex-direction: column; } - .input-group.vertical > input { - max-width: 100%; - flex-grow: 1; - flex-basis: 0px; } - -[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { - height: auto; } - -[type="search"] { - -webkit-appearance: textfield; - outline-offset: -2px; } - -[type="search"]::-webkit-search-cancel-button, -[type="search"]::-webkit-search-decoration { - -webkit-appearance: none; } - -input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], -[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { - box-sizing: border-box; - background: var(--input-back-color); - color: var(--input-fore-color); - border: 0.0625rem solid var(--input-border-color); - border-radius: var(--universal-border-radius); - margin: calc(var(--universal-margin) / 2); - padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } - -input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { - border-color: var(--input-focus-color); - box-shadow: none; } -input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { - border-color: var(--input-invalid-color); - box-shadow: none; } -input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { - background: var(--secondary-back-color); } - -select { - max-width: 100%; } - -option { - overflow: hidden; - text-overflow: ellipsis; } - -[type="checkbox"], [type="radio"] { - -webkit-appearance: none; - -moz-appearance: none; - appearance: none; - position: relative; - height: calc(1rem + var(--universal-padding) / 2); - width: calc(1rem + var(--universal-padding) / 2); - vertical-align: text-bottom; - padding: 0; - flex-basis: calc(1rem + var(--universal-padding) / 2) !important; - flex-grow: 0 !important; } - [type="checkbox"]:checked:before, [type="radio"]:checked:before { - position: absolute; } - -[type="checkbox"]:checked:before { - content: '\2713'; - font-family: sans-serif; - font-size: calc(1rem + var(--universal-padding) / 2); - top: calc(0rem - var(--universal-padding)); - left: calc(var(--universal-padding) / 4); } - -[type="radio"] { - border-radius: 100%; } - [type="radio"]:checked:before { - border-radius: 100%; - content: ''; - top: calc(0.0625rem + var(--universal-padding) / 2); - left: calc(0.0625rem + var(--universal-padding) / 2); - background: var(--input-fore-color); - width: 0.5rem; - height: 0.5rem; } - -:placeholder-shown { - color: var(--input-fore-color); } - -::-ms-placeholder { - color: var(--input-fore-color); - opacity: 0.54; } - -button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { - border-style: none; - padding: 0; } - -button, html [type="button"], [type="reset"], [type="submit"] { - -webkit-appearance: button; } - -button { - overflow: visible; - text-transform: none; } - -button, [type="button"], [type="submit"], [type="reset"], -a.button, label.button, .button, -a[role="button"], label[role="button"], [role="button"] { - display: inline-block; - background: var(--button-back-color); - color: var(--button-fore-color); - border: 0.0625rem solid var(--button-border-color); - border-radius: var(--universal-border-radius); - padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); - margin: var(--universal-margin); - text-decoration: none; - cursor: pointer; - transition: background 0.3s; } - button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, - a.button:hover, - a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, - a[role="button"]:hover, - a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { - background: var(--button-hover-back-color); - border-color: var(--button-hover-border-color); } - -input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { - cursor: not-allowed; - opacity: 0.75; } - -.button-group { - display: flex; - border: 0.0625rem solid var(--button-group-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); } - .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { - margin: 0; - max-width: 100%; - flex: 1 1 auto; - text-align: center; - border: 0; - border-radius: 0; - box-shadow: none; } - .button-group > :not(:first-child) { - border-left: 0.0625rem solid var(--button-group-border-color); } - @media screen and (max-width: 499px) { - .button-group { - flex-direction: column; } - .button-group > :not(:first-child) { - border: 0; - border-top: 0.0625rem solid var(--button-group-border-color); } } - -/* - Custom elements for forms and input elements. -*/ -button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { - --button-back-color: #1976d2; - --button-fore-color: #f8f8f8; } - button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { - --button-hover-back-color: #1565c0; } - -button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { - --button-back-color: #d32f2f; - --button-fore-color: #f8f8f8; } - button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { - --button-hover-back-color: #c62828; } - -button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { - --button-back-color: #308732; - --button-fore-color: #f8f8f8; } - button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { - --button-hover-back-color: #277529; } - -button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { - --button-back-color: #212121; - --button-fore-color: #f8f8f8; } - button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { - --button-hover-back-color: #111; } - -button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { - padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); - margin: var(--universal-margin); } - -button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { - padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); - margin: var(--universal-margin); } - -/* - Definitions for navigation elements. -*/ -/* Navigation module CSS variable definitions */ -:root { - --header-back-color: #f8f8f8; - --header-hover-back-color: #f0f0f0; - --header-fore-color: #444; - --header-border-color: #ddd; - --nav-back-color: #f8f8f8; - --nav-hover-back-color: #f0f0f0; - --nav-fore-color: #444; - --nav-border-color: #ddd; - --nav-link-color: #0277bd; - --footer-fore-color: #444; - --footer-back-color: #f8f8f8; - --footer-border-color: #ddd; - --footer-link-color: #0277bd; - --drawer-back-color: #f8f8f8; - --drawer-hover-back-color: #f0f0f0; - --drawer-border-color: #ddd; - --drawer-close-color: #444; } - -header { - height: 3.1875rem; - background: var(--header-back-color); - color: var(--header-fore-color); - border-bottom: 0.0625rem solid var(--header-border-color); - padding: calc(var(--universal-padding) / 4) 0; - white-space: nowrap; - overflow-x: auto; - overflow-y: hidden; } - header.row { - box-sizing: content-box; } - header .logo { - color: var(--header-fore-color); - font-size: 1.75rem; - padding: var(--universal-padding) calc(2 * var(--universal-padding)); - text-decoration: none; } - header button, header [type="button"], header .button, header [role="button"] { - box-sizing: border-box; - position: relative; - top: calc(0rem - var(--universal-padding) / 4); - height: calc(3.1875rem + var(--universal-padding) / 2); - background: var(--header-back-color); - line-height: calc(3.1875rem - var(--universal-padding) * 1.5); - text-align: center; - color: var(--header-fore-color); - border: 0; - border-radius: 0; - margin: 0; - text-transform: uppercase; } - header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { - background: var(--header-hover-back-color); } - -nav { - background: var(--nav-back-color); - color: var(--nav-fore-color); - border: 0.0625rem solid var(--nav-border-color); - border-radius: var(--universal-border-radius); - margin: var(--universal-margin); } - nav * { - padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } - nav a, nav a:visited { - display: block; - color: var(--nav-link-color); - border-radius: var(--universal-border-radius); - transition: background 0.3s; } - nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { - text-decoration: none; - background: var(--nav-hover-back-color); } - nav .sublink-1 { - position: relative; - margin-left: calc(2 * var(--universal-padding)); } - nav .sublink-1:before { - position: absolute; - left: calc(var(--universal-padding) - 1 * var(--universal-padding)); - top: -0.0625rem; - content: ''; - height: 100%; - border: 0.0625rem solid var(--nav-border-color); - border-left: 0; } - nav .sublink-2 { - position: relative; - margin-left: calc(4 * var(--universal-padding)); } - nav .sublink-2:before { - position: absolute; - left: calc(var(--universal-padding) - 3 * var(--universal-padding)); - top: -0.0625rem; - content: ''; - height: 100%; - border: 0.0625rem solid var(--nav-border-color); - border-left: 0; } - -footer { - background: var(--footer-back-color); - color: var(--footer-fore-color); - border-top: 0.0625rem solid var(--footer-border-color); - padding: calc(2 * var(--universal-padding)) var(--universal-padding); - font-size: 0.875rem; } - footer a, footer a:visited { - color: var(--footer-link-color); } - -header.sticky { - position: -webkit-sticky; - position: sticky; - z-index: 1101; - top: 0; } - -footer.sticky { - position: -webkit-sticky; - position: sticky; - z-index: 1101; - bottom: 0; } - -.drawer-toggle:before { - display: inline-block; - position: relative; - vertical-align: bottom; - content: '\00a0\2261\00a0'; - font-family: sans-serif; - font-size: 1.5em; } -@media screen and (min-width: 500px) { - .drawer-toggle:not(.persistent) { - display: none; } } - -[type="checkbox"].drawer { - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - [type="checkbox"].drawer + * { - display: block; - box-sizing: border-box; - position: fixed; - top: 0; - width: 320px; - height: 100vh; - overflow-y: auto; - background: var(--drawer-back-color); - border: 0.0625rem solid var(--drawer-border-color); - border-radius: 0; - margin: 0; - z-index: 1110; - right: -320px; - transition: right 0.3s; } - [type="checkbox"].drawer + * .drawer-close { - position: absolute; - top: var(--universal-margin); - right: var(--universal-margin); - z-index: 1111; - width: 2rem; - height: 2rem; - border-radius: var(--universal-border-radius); - padding: var(--universal-padding); - margin: 0; - cursor: pointer; - transition: background 0.3s; } - [type="checkbox"].drawer + * .drawer-close:before { - display: block; - content: '\00D7'; - color: var(--drawer-close-color); - position: relative; - font-family: sans-serif; - font-size: 2rem; - line-height: 1; - text-align: center; } - [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { - background: var(--drawer-hover-back-color); } - @media screen and (max-width: 320px) { - [type="checkbox"].drawer + * { - width: 100%; } } - [type="checkbox"].drawer:checked + * { - right: 0; } - @media screen and (min-width: 500px) { - [type="checkbox"].drawer:not(.persistent) + * { - position: static; - height: 100%; - z-index: 1100; } - [type="checkbox"].drawer:not(.persistent) + * .drawer-close { - display: none; } } - -/* - Definitions for the responsive table component. -*/ -/* Table module CSS variable definitions. */ -:root { - --table-border-color: #aaa; - --table-border-separator-color: #666; - --table-head-back-color: #e6e6e6; - --table-head-fore-color: #111; - --table-body-back-color: #f8f8f8; - --table-body-fore-color: #111; - --table-body-alt-back-color: #eee; } - -table { - border-collapse: separate; - border-spacing: 0; - : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); - display: flex; - flex: 0 1 auto; - flex-flow: row wrap; - padding: var(--universal-padding); - padding-top: 0; - margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } - table caption { - font-size: 1.25 * rem; - margin: calc(2 * var(--universal-margin)) 0; - max-width: 100%; - flex: 0 0 100%; - text-align: left;} - table thead, table tbody { - display: flex; - flex-flow: row wrap; - border: 0.0625rem solid var(--table-border-color); } - table thead { - z-index: 999; - border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; - border-bottom: 0.0625rem solid var(--table-border-separator-color); } - table tbody { - border-top: 0; - margin-top: calc(0 - var(--universal-margin)); - border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } - table tr { - display: flex; - padding: 0; } - table th, table td { - padding: calc(0.5 * var(--universal-padding)); - font-size: 0.9rem; } - table th { - text-align: left; - background: var(--table-head-back-color); - color: var(--table-head-fore-color); } - table td { - background: var(--table-body-back-color); - color: var(--table-body-fore-color); - border-top: 0.0625rem solid var(--table-border-color); } - -table:not(.horizontal) { - overflow: auto; - max-height: 850px; } - table:not(.horizontal) thead, table:not(.horizontal) tbody { - max-width: 100%; - flex: 0 0 100%; } - table:not(.horizontal) tr { - flex-flow: row wrap; - flex: 0 0 100%; } - table:not(.horizontal) th, table:not(.horizontal) td { - flex: 1 0 0%; - overflow: hidden; - text-overflow: ellipsis; } - table:not(.horizontal) thead { - position: sticky; - top: 0; } - table:not(.horizontal) tbody tr:first-child td { - border-top: 0; } - -table.horizontal { - border: 0; } - table.horizontal thead, table.horizontal tbody { - border: 0; - flex-flow: row nowrap; } - table.horizontal tbody { - overflow: auto; - justify-content: space-between; - flex: 1 0 0; - margin-left: calc( 4 * var(--universal-margin)); - padding-bottom: calc(var(--universal-padding) / 4); } - table.horizontal tr { - flex-direction: column; - flex: 1 0 auto; } - table.horizontal th, table.horizontal td { - width: 100%; - border: 0; - border-bottom: 0.0625rem solid var(--table-border-color); } - table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { - border-top: 0; } - table.horizontal th { - text-align: right; - border-left: 0.0625rem solid var(--table-border-color); - border-right: 0.0625rem solid var(--table-border-separator-color); } - table.horizontal thead tr:first-child { - padding-left: 0; } - table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0.0625rem solid var(--table-border-color); } - table.horizontal tbody tr:last-child td { - border-right: 0.0625rem solid var(--table-border-color); } - table.horizontal tbody tr:last-child td:first-child { - border-top-right-radius: 0.25rem; } - table.horizontal tbody tr:last-child td:last-child { - border-bottom-right-radius: 0.25rem; } - table.horizontal thead tr:first-child th:first-child { - border-top-left-radius: 0.25rem; } - table.horizontal thead tr:first-child th:last-child { - border-bottom-left-radius: 0.25rem; } - -@media screen and (max-width: 499px) { - table, table.horizontal { - border-collapse: collapse; - border: 0; - width: 100%; - display: table; } - table thead, table th, table.horizontal thead, table.horizontal th { - border: 0; - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - padding: 0; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - table tbody, table.horizontal tbody { - border: 0; - display: table-row-group; } - table tr, table.horizontal tr { - display: block; - border: 0.0625rem solid var(--table-border-color); - border-radius: var(--universal-border-radius); - background: #fafafa; - padding: var(--universal-padding); - margin: var(--universal-margin); - margin-bottom: calc(2 * var(--universal-margin)); } - table th, table td, table.horizontal th, table.horizontal td { - width: auto; } - table td, table.horizontal td { - display: block; - border: 0; - text-align: right; } - table td:before, table.horizontal td:before { - content: attr(data-label); - float: left; - font-weight: 600; } - table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { - border-top: 0; } - table tbody tr:last-child td, table.horizontal tbody tr:last-child td { - border-right: 0; } } -:root { - --table-body-alt-back-color: #eee; } - -table tr:nth-of-type(2n) > td { - background: var(--table-body-alt-back-color); } - -@media screen and (max-width: 500px) { - table tr:nth-of-type(2n) { - background: var(--table-body-alt-back-color); } } -:root { - --table-body-hover-back-color: #90caf9; } - -table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { - background: var(--table-body-hover-back-color); } - -@media screen and (max-width: 500px) { - table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { - background: var(--table-body-hover-back-color); } } -/* - Definitions for contextual background elements, toasts and tooltips. -*/ -/* Contextual module CSS variable definitions */ -:root { - --mark-back-color: #0277bd; - --mark-fore-color: #fafafa; } - -mark { - background: var(--mark-back-color); - color: var(--mark-fore-color); - font-size: 0.95em; - line-height: 1em; - border-radius: var(--universal-border-radius); - padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } - mark.inline-block { - display: inline-block; - font-size: 1em; - line-height: 1.5; - padding: calc(var(--universal-padding) / 2) var(--universal-padding); } - -:root { - --toast-back-color: #424242; - --toast-fore-color: #fafafa; } - -.toast { - position: fixed; - bottom: calc(var(--universal-margin) * 3); - left: 50%; - transform: translate(-50%, -50%); - z-index: 1111; - color: var(--toast-fore-color); - background: var(--toast-back-color); - border-radius: calc(var(--universal-border-radius) * 16); - padding: var(--universal-padding) calc(var(--universal-padding) * 3); } - -:root { - --tooltip-back-color: #212121; - --tooltip-fore-color: #fafafa; } - -.tooltip { - position: relative; - display: inline-block; } - .tooltip:before, .tooltip:after { - position: absolute; - opacity: 0; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); - transition: all 0.3s; - z-index: 1010; - left: 50%; } - .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { - bottom: 75%; } - .tooltip.bottom:before, .tooltip.bottom:after { - top: 75%; } - .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { - opacity: 1; - clip: auto; - -webkit-clip-path: inset(0%); - clip-path: inset(0%); } - .tooltip:before { - content: ''; - background: transparent; - border: var(--universal-margin) solid transparent; - left: calc(50% - var(--universal-margin)); } - .tooltip:not(.bottom):before { - border-top-color: #212121; } - .tooltip.bottom:before { - border-bottom-color: #212121; } - .tooltip:after { - content: attr(aria-label); - color: var(--tooltip-fore-color); - background: var(--tooltip-back-color); - border-radius: var(--universal-border-radius); - padding: var(--universal-padding); - white-space: nowrap; - transform: translateX(-50%); } - .tooltip:not(.bottom):after { - margin-bottom: calc(2 * var(--universal-margin)); } - .tooltip.bottom:after { - margin-top: calc(2 * var(--universal-margin)); } - -:root { - --modal-overlay-color: rgba(0, 0, 0, 0.45); - --modal-close-color: #444; - --modal-close-hover-color: #f0f0f0; } - -[type="checkbox"].modal { - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - [type="checkbox"].modal + div { - position: fixed; - top: 0; - left: 0; - display: none; - width: 100vw; - height: 100vh; - background: var(--modal-overlay-color); } - [type="checkbox"].modal + div .card { - margin: 0 auto; - max-height: 50vh; - overflow: auto; } - [type="checkbox"].modal + div .card .modal-close { - position: absolute; - top: 0; - right: 0; - width: 1.75rem; - height: 1.75rem; - border-radius: var(--universal-border-radius); - padding: var(--universal-padding); - margin: 0; - cursor: pointer; - transition: background 0.3s; } - [type="checkbox"].modal + div .card .modal-close:before { - display: block; - content: '\00D7'; - color: var(--modal-close-color); - position: relative; - font-family: sans-serif; - font-size: 1.75rem; - line-height: 1; - text-align: center; } - [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { - background: var(--modal-close-hover-color); } - [type="checkbox"].modal:checked + div { - display: flex; - flex: 0 1 auto; - z-index: 1200; } - [type="checkbox"].modal:checked + div .card .modal-close { - z-index: 1211; } - -:root { - --collapse-label-back-color: #e8e8e8; - --collapse-label-fore-color: #212121; - --collapse-label-hover-back-color: #f0f0f0; - --collapse-selected-label-back-color: #ececec; - --collapse-border-color: #ddd; - --collapse-content-back-color: #fafafa; - --collapse-selected-label-border-color: #0277bd; } - -.collapse { - width: calc(100% - 2 * var(--universal-margin)); - opacity: 1; - display: flex; - flex-direction: column; - margin: var(--universal-margin); - border-radius: var(--universal-border-radius); } - .collapse > [type="radio"], .collapse > [type="checkbox"] { - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); } - .collapse > label { - flex-grow: 1; - display: inline-block; - height: 1.5rem; - cursor: pointer; - transition: background 0.3s; - color: var(--collapse-label-fore-color); - background: var(--collapse-label-back-color); - border: 0.0625rem solid var(--collapse-border-color); - padding: calc(1.5 * var(--universal-padding)); } - .collapse > label:hover, .collapse > label:focus { - background: var(--collapse-label-hover-back-color); } - .collapse > label + div { - flex-basis: auto; - height: 1px; - width: 1px; - margin: -1px; - overflow: hidden; - position: absolute; - clip: rect(0 0 0 0); - -webkit-clip-path: inset(100%); - clip-path: inset(100%); - transition: max-height 0.3s; - max-height: 1px; } - .collapse > :checked + label { - background: var(--collapse-selected-label-back-color); - border-bottom-color: var(--collapse-selected-label-border-color); } - .collapse > :checked + label + div { - box-sizing: border-box; - position: relative; - width: 100%; - height: auto; - overflow: auto; - margin: 0; - background: var(--collapse-content-back-color); - border: 0.0625rem solid var(--collapse-border-color); - border-top: 0; - padding: var(--universal-padding); - clip: auto; - -webkit-clip-path: inset(0%); - clip-path: inset(0%); - max-height: 850px; } - .collapse > label:not(:first-of-type) { - border-top: 0; } - .collapse > label:first-of-type { - border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } - .collapse > label:last-of-type:not(:first-of-type) { - border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } - .collapse > label:last-of-type:first-of-type { - border-radius: var(--universal-border-radius); } - .collapse > :checked:last-of-type:not(:first-of-type) + label { - border-radius: 0; } - .collapse > :checked:last-of-type + label + div { - border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } - -/* - Custom elements for contextual background elements, toasts and tooltips. -*/ -mark.secondary { - --mark-back-color: #d32f2f; } - -mark.tertiary { - --mark-back-color: #308732; } - -mark.tag { - padding: calc(var(--universal-padding)/2) var(--universal-padding); - border-radius: 1em; } - -/* - Definitions for progress elements and spinners. -*/ -/* Progress module CSS variable definitions */ -:root { - --progress-back-color: #ddd; - --progress-fore-color: #555; } - -progress { - display: block; - vertical-align: baseline; - -webkit-appearance: none; - -moz-appearance: none; - appearance: none; - height: 0.75rem; - width: calc(100% - 2 * var(--universal-margin)); - margin: var(--universal-margin); - border: 0; - border-radius: calc(2 * var(--universal-border-radius)); - background: var(--progress-back-color); - color: var(--progress-fore-color); } - progress::-webkit-progress-value { - background: var(--progress-fore-color); - border-top-left-radius: calc(2 * var(--universal-border-radius)); - border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } - progress::-webkit-progress-bar { - background: var(--progress-back-color); } - progress::-moz-progress-bar { - background: var(--progress-fore-color); - border-top-left-radius: calc(2 * var(--universal-border-radius)); - border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } - progress[value="1000"]::-webkit-progress-value { - border-radius: calc(2 * var(--universal-border-radius)); } - progress[value="1000"]::-moz-progress-bar { - border-radius: calc(2 * var(--universal-border-radius)); } - progress.inline { - display: inline-block; - vertical-align: middle; - width: 60%; } - -:root { - --spinner-back-color: #ddd; - --spinner-fore-color: #555; } - -@keyframes spinner-donut-anim { - 0% { - transform: rotate(0deg); } - 100% { - transform: rotate(360deg); } } -.spinner { - display: inline-block; - margin: var(--universal-margin); - border: 0.25rem solid var(--spinner-back-color); - border-left: 0.25rem solid var(--spinner-fore-color); - border-radius: 50%; - width: 1.25rem; - height: 1.25rem; - animation: spinner-donut-anim 1.2s linear infinite; } - -/* - Custom elements for progress bars and spinners. -*/ -progress.primary { - --progress-fore-color: #1976d2; } - -progress.secondary { - --progress-fore-color: #d32f2f; } - -progress.tertiary { - --progress-fore-color: #308732; } - -.spinner.primary { - --spinner-fore-color: #1976d2; } - -.spinner.secondary { - --spinner-fore-color: #d32f2f; } - -.spinner.tertiary { - --spinner-fore-color: #308732; } - -/* - Definitions for icons - powered by Feather (https://feathericons.com/). -*/ -span[class^='icon-'] { - display: inline-block; - height: 1em; - width: 1em; - vertical-align: -0.125em; - background-size: contain; - margin: 0 calc(var(--universal-margin) / 4); } - span[class^='icon-'].secondary { - -webkit-filter: invert(25%); - filter: invert(25%); } - span[class^='icon-'].inverse { - -webkit-filter: invert(100%); - filter: invert(100%); } - -span.icon-alert { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-bookmark { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } -span.icon-calendar { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-credit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-edit { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } -span.icon-link { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-help { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-home { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } -span.icon-info { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-lock { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } -span.icon-mail { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } -span.icon-location { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } -span.icon-phone { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } -span.icon-rss { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } -span.icon-search { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-settings { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } -span.icon-share { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-cart { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } -span.icon-upload { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } -span.icon-user { - background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } - -/* - Definitions for utilities and helper classes. -*/ -/* Utility module CSS variable definitions */ -:root { - --generic-border-color: rgba(0, 0, 0, 0.3); - --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } - -.hidden { - display: none !important; } - -.visually-hidden { - position: absolute !important; - width: 1px !important; - height: 1px !important; - margin: -1px !important; - border: 0 !important; - padding: 0 !important; - clip: rect(0 0 0 0) !important; - -webkit-clip-path: inset(100%) !important; - clip-path: inset(100%) !important; - overflow: hidden !important; } - -.bordered { - border: 0.0625rem solid var(--generic-border-color) !important; } - -.rounded { - border-radius: var(--universal-border-radius) !important; } - -.circular { - border-radius: 50% !important; } - -.shadowed { - box-shadow: var(--generic-box-shadow) !important; } - -.responsive-margin { - margin: calc(var(--universal-margin) / 4) !important; } - @media screen and (min-width: 500px) { - .responsive-margin { - margin: calc(var(--universal-margin) / 2) !important; } } - @media screen and (min-width: 1280px) { - .responsive-margin { - margin: var(--universal-margin) !important; } } - -.responsive-padding { - padding: calc(var(--universal-padding) / 4) !important; } - @media screen and (min-width: 500px) { - .responsive-padding { - padding: calc(var(--universal-padding) / 2) !important; } } - @media screen and (min-width: 1280px) { - .responsive-padding { - padding: var(--universal-padding) !important; } } - -@media screen and (max-width: 499px) { - .hidden-sm { - display: none !important; } } -@media screen and (min-width: 500px) and (max-width: 1279px) { - .hidden-md { - display: none !important; } } -@media screen and (min-width: 1280px) { - .hidden-lg { - display: none !important; } } -@media screen and (max-width: 499px) { - .visually-hidden-sm { - position: absolute !important; - width: 1px !important; - height: 1px !important; - margin: -1px !important; - border: 0 !important; - padding: 0 !important; - clip: rect(0 0 0 0) !important; - -webkit-clip-path: inset(100%) !important; - clip-path: inset(100%) !important; - overflow: hidden !important; } } -@media screen and (min-width: 500px) and (max-width: 1279px) { - .visually-hidden-md { - position: absolute !important; - width: 1px !important; - height: 1px !important; - margin: -1px !important; - border: 0 !important; - padding: 0 !important; - clip: rect(0 0 0 0) !important; - -webkit-clip-path: inset(100%) !important; - clip-path: inset(100%) !important; - overflow: hidden !important; } } -@media screen and (min-width: 1280px) { - .visually-hidden-lg { - position: absolute !important; - width: 1px !important; - height: 1px !important; - margin: -1px !important; - border: 0 !important; - padding: 0 !important; - clip: rect(0 0 0 0) !important; - -webkit-clip-path: inset(100%) !important; - clip-path: inset(100%) !important; - overflow: hidden !important; } } - -/*# sourceMappingURL=mini-default.css.map */
diff --git a/_htmresc/st_logo.png b/_htmresc/st_logo.png deleted file mode 100644 index 8b80057..0000000 --- a/_htmresc/st_logo.png +++ /dev/null Binary files differ
