Release_Notes.html - third_party/github/STMicroelectronics/cmsis_device_l0 - Git at Google

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 <h1 id="release-notes-for-stm32l0xx-cmsis"><small>Release Notes for</small> <mark>STM32L0xx CMSIS</mark></h1>
 <p>Copyright © 2009-2018 ARM Limited - STMicroelectronics<br />
 </p>
 <a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
 </center>
 </div>
 </div>
 <h1 id="license">License</h1>
 <p>Licensed by ST under Apache-2.0 license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
 <p><a href="../../../LICENSE.txt">Apache License v2.0</a></p>
 <h1 id="purpose">Purpose</h1>
 <p>This driver provides the CMSIS device for the stm32l1xx products. This covers:</p>
 <ul>
 <li>STM32L010xx devices</li>
 <li>STM32L011xx and STM32L021xx devices</li>
 <li>STM32L031xx and STM32L041xx devices</li>
 <li>STM32L051xx, STM32L052xx, STM32L053xx, STM32L062xx and STM32L063xx devices</li>
 <li>STM32L071xx, STM32L072xx, STM32L073xx, STM32L082xx and STM32L083xx devices</li>
 </ul>
 <p>This driver is composed of the descriptions of the registers under “Include” directory.</p>
 <p>Various template file are provided to easily build an application. They can be adapted to fit applications requirements.</p>
 <ul>
 <li>Templates/system_stm32l0xx.c contains the initialization code referred as SystemInit.</li>
 <li>Startup files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
 <li>Linker files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
 </ul>
 </div>
 <div class="col-sm-12 col-lg-8">
 <h1 id="update-history">Update History</h1>
 <div class="collapse">
 <input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.9.1 / 28-October-2020</label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <h3 id="maintenance-release">Maintenance release</h3>
 <h2 id="contents">Contents</h2>
 <ul>
 <li>system_stm32l0xx.c
 <ul>
 <li>SystemInit(): update to don’t reset RCC registers to its reset values.</li>
 <li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive: USER_VECT_TAB_ADDRESS.</li>
 </ul></li>
 <li>All header files
 <ul>
 <li>Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro.</li>
 </ul></li>
 <li>Remove stm32l061xx.h header file.</li>
 <li>Add License.md and Readme.md files required for GitHub publication</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.9.0 / 26-October-2018</label>
 <div>
 <h2 id="main-changes-1">Main Changes</h2>
 <h3 id="maintenance-release-1">Maintenance release</h3>
 <h3 id="first-release-supporting-l0-value-lines">First release supporting L0 Value Lines</h3>
 <h2 id="contents-1">Contents</h2>
 <ul>
 <li>Add the support of STM32L010xx devices
 <ul>
 <li>Add stm32l010xb.h, stm32l010x8.h, stm32l010x6.h and stm32l010x4.h device description files</li>
 <li>Add startup_stm32l010xb.s, startup_stm32l010x8.s, startup_stm32l010x6.s and startup_stm32l010x4.s startup files for EWARM, MDK-ARM and SW4STM32 toolchains</li>
 <li>Add EWARM associated linker files for execution from internal RAM or internal FLASH</li>
 </ul></li>
 <li>stm32l0xx.h
 <ul>
 <li>Add the following device defines:
 <ul>
 <li>“#define STM32L010xB” for all STM32L010xB devices</li>
 <li>“#define STM32L010x8” for all STM32L010x8 devices</li>
 <li>“#define STM32L010x6” for all STM32L010x6 devices</li>
 <li>“#define STM32L010x4” for all STM32L010x4 devices</li>
 </ul></li>
 <li>Align ErrorStatus typedef to common error handling.</li>
 </ul></li>
 <li>All stm32l0xxxx.h device description files.h
 <ul>
 <li>[MISRAC2012-Rule-10.6] Use ‘UL’ postfix for _Msk definitions and memory/peripheral base addresses</li>
 <li>Correct comments in the bit definition of RCC_AHBRST, RCC_APB2RSTR and RCC_APB1RSTR registers.</li>
 <li>Rename RTC_CR_BCK bit to RTC_CR_BKP to be aligned with reference manual.</li>
 <li>Add missing definition of IS_TSC_ALL_INSTANCE after TSC driver update.</li>
 <li>Add back the bit definition of SYSCFG_CFGR3_EN_VREFINT in SYSCFG_CFGR3 register.</li>
 <li>Rename GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit definitions (from GPIO_AFRL/AFRH registers) to GPIO_AFRL_AFSELx.</li>
 <li>Align IS_TIM_XXX_INSTANCE definitions with other series.</li>
 <li>Remove cast (uint8_t) in CRC_IDR_IDR definition.</li>
 <li>Add missing definition of IS_PCD_ALL_INSTANCE macro after USB driver update.</li>
 <li>Add definition of IS_UART_DRIVER_ENABLE_INSTANCE macro after UART driver update.</li>
 <li>Add compatibility definition of USART_ICR_NECF / USART_ICR_NCF with others series.</li>
 <li>Update IS_UART_INSTANCE macro definition.</li>
 <li>Add definition of IS_LPTIM_ENCODER_INTERFACE_INSTANCE macro after LPTIM driver update.</li>
 <li>Move definition of FLASH_BANK2_BASE start address to stm32l0xx_hal_flash.h to be dependant on Memory Size register.</li>
 <li>Update interrupt definition to use DMA1_Channel4_5_IRQn for STM32L011xx and STM32L021xx devices.</li>
 <li>Correct PWR_WAKEUP_PIN definitions for L011xx and L021xx devices.</li>
 </ul></li>
 <li>system_stm32l0xx.c
 <ul>
 <li>Update file to correct comments for VECT_TAB_OFFSET definition.</li>
 <li>Update default MSI_VALUE reset value set in SystemCoreClock.</li>
 <li>Update SystemCoreClockUpdate() function to check HSI16DIVF for HSI divided by 4.</li>
 </ul></li>
 <li>startup_stm32l0xxxx.s
 <ul>
 <li>Update startup files to use DMA1_Channel4_5_IRQn/IRQHandler for STM32L011xx and STM32L01xx devices.</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.8.0 / 12-January-2018</label>
 <div>
 <h2 id="main-changes-2">Main Changes</h2>
 <h3 id="internal-release">Internal release</h3>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.7.2 / 25-August-2017</label>
 <div>
 <h2 id="main-changes-3">Main Changes</h2>
 <h3 id="maintenance-release-2">Maintenance release</h3>
 <h2 id="contents-2">Contents</h2>
 <ul>
 <li>Removed DATE and VERSION fields from header files.</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.7.1 / 25-November-2016</label>
 <div>
 <h2 id="main-changes-4">Main Changes</h2>
 <h3 id="maintenance-release-3">Maintenance release</h3>
 <h2 id="contents-3">Contents</h2>
 <ul>
 <li>Updated IS_COMP_COMMON_INSTANCE() macro.</li>
 <li>Corrected ADC_CFGR2_TOVS bit and mask definitions.</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.7.0 / 31-May-2016</label>
 <div>
 <h2 id="main-changes-5">Main Changes</h2>
 <h3 id="maintenance-release-4">Maintenance release</h3>
 <h2 id="contents-4">Contents</h2>
 <ul>
 <li>Added Pos and Msk macros missing within the CMSIS stm32l083xx.h file.</li>
 <li>Added LCD_CR_BUFEN bit definition in LCD CR register for stm32l053xx, stm32l063xx, stm32l073xx, stm32l083xx devices.</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.6.0 / 15-April-2016</label>
 <div>
 <h2 id="main-changes-6">Main Changes</h2>
 <h3 id="maintenance-release-5">Maintenance release</h3>
 <h2 id="contents-5">Contents</h2>
 <ul>
 <li>Add Pos and Msk macros within the CMSIS files.
 <ul>
 <li>For example, on the previous CMSIS version (V1.5.0), the constant ADC_IER_EOCALIE was defined as follow :
 <ul>
 <li>#define ADC_IER_EOCALIE ((uint32_t)0x00000800U)</li>
 </ul></li>
 <li>On this new CMSIS version (V1.6.0), the constant ADC_IER_EOCALIE is now defined as follow :
 <ul>
 <li>#define ADC_IER_EOCALIE_Pos (11U)</li>
 <li>#define ADC_IER_EOCALIE_Msk (0x1U &lt;&lt; ADC_IER_EOCALIE_Pos)</li>
 <li>#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk</li>
 </ul></li>
 <li>The same rule applies on all the other constants present inside the CMSIS files.</li>
 </ul></li>
 <li><p>MISRA C 2004 rule 10.6 compliancy. (A ‘U’ suffix shall be applied to all constants of unisgned type).</p></li>
 <li>Several SYSCFG definition changes :</li>
 <li>SYSCFG_CFGR3_EN_VREFINT enable bit suppressed. (no more needed and must not be used).</li>
 <li>SYSCFG_CFGR3_EN_BGAP define suppressed.</li>
 <li>SYSCFG_CFGR3_REF_HSI48_RDYF, SYSCFG_CFGR3_SENSOR_ADC_RDYF, SYSCFG_CFGR3_VREFINT_ADC_RDYF, SYSCFG_CFGR3_VREFINT_COMP_RDYF flags suppressed, SYSCFG_CFGR3_VREFINT_RDYF must be used instead (this flag is a combination of the 4 suppressed flags).</li>
 <li><p>Added SYSCFG_CFGR3_REF_RC48MHz_RDYF, SYSCFG_CFGR3_REF_HSI48_RDYF, SYSCFG_VREFINT_ADC_RDYF, SYSCFG_CFGR3_SENSOR_ADC_RDYF, SYSCFG_CFGR3_VREFINT_ADC_RDYF and SYSCFG_CFGR3_VREFINT_COMP_RDYF defines.</p></li>
 <li>Aligned register namings with the different L0 Reference Manual (For STM32L0x1 : RM0377 Rev5, for STM32L0x2 : RM0367 Rev2, for STM32L0x3 : RM0367 Rev4). The list of the modification is listed hereafter :
 <ul>
 <li>Introduced new masks in EXTI bit definitions in order to simplify LL source code.</li>
 <li>Renamed RCC_CFGR_MCO_x into RCC_CFGR_MCOSEL_x</li>
 <li>Added FLASHSIZE_BASE, UID_BASE and SRAM_SIZE_MAX defines.</li>
 <li>Renamed macro IS_DMA_ALL_INSTANCE() to IS_DMA_STREAM_ALL_INSTANCE().</li>
 <li>Added new macros: IS_I2C_WAKEUP_FROMSTOP_INSTANCE(), IS_ADC_COMMON_INSTANCE() and IS_LPUART_INSTANCE().</li>
 <li>Added new defines PWR_PVD_SUPPORT to handle the PVD feature.</li>
 <li>Corrected the value of FLASH_END for STM32L011xx or STM32L021xx devices.</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.5.0 / 8-January-2016</label>
 <div>
 <h2 id="main-changes-7">Main Changes</h2>
 <h3 id="maintenance-release-6">Maintenance release</h3>
 <h2 id="contents-6">Contents</h2>
 <ul>
 <li>MISRA C 2004 rule 5.1 and rule 10.6 compliancy.</li>
 <li>Several renaming in order to be aligned with the Reference Manual.The list of the modification is listed hereafter :
 <ul>
 <li>Adding of a new COMP_Common_TypeDef structure.</li>
 <li>Removal of the RCR field inside the TIM_TypeDef structure.</li>
 <li>Adding of a new define COMP12_COMMON</li>
 <li>Adding of a new define DAC1 (same as DAC)</li>
 <li>Adding of a new define ADC1_COMMON</li>
 <li>Adding of a new define ADC_CHSELR_CHSEL</li>
 <li>Adding of a new define COMP_CSR_WINMODE</li>
 <li>Adding of a new define DAC_CHANNEL2_SUPPORT</li>
 <li>Renaming of EXTI_RTSR_TRx into EXTI_RTSR_RTx with x = {0,..22}</li>
 <li>Renaming of EXTI_FTSR_TRx into EXTI_FTSR_FTx with x = {0,..22}</li>
 <li>Renaming of EXTI_SWIER_SWIERx into EXTI_SWIER_SWIx with x = {0,..22}</li>
 <li>Renaming of EXTI_PR_PRx into EXTI_PR_PIFx with x = {0,..22}</li>
 <li>Renaming of RCC_IOPRSTR_GPIOxRST into RCC_IOPRSTR_IOPxRST with x = {A,B,C,D,E,H}</li>
 <li>Add a new define RCC_AHBRSTR_DMA1RST</li>
 <li>Add a new define RCC_APB2RSTR_ADC1RST</li>
 <li>Add a new define RCC_APB2RSTR_DBGMCURST</li>
 <li>Renaming of RCC_IOPENR_GPIOxEN into RCC_IOPENR_IOPxEN with x = {A,B,C,D,E,H}</li>
 <li>Add a new define RCC_AHBENR_DMA1EN</li>
 <li>Rename RCC_APB2ENR_MIFIEN into RCC_APB2ENR_FWEN</li>
 <li>Rename RCC_APB2ENR_ADC1EN into RCC_APB2ENR_ADCEN</li>
 <li>Rename RCC_APB2ENR_DBGMCUEN into RCC_APB2ENR_DBGEN</li>
 <li>Rename RCC_IOPSMENR_GPIOxSMEN into RCC_IOPSMENR_IOPxSMEN with x = {A,B,C,D,E,H}</li>
 <li>Add a new define RCC_AHBSMENR_DMA1SMEN</li>
 <li>Rename RCC_APB2SMENR_ADC1SMEN into RCC_APB2SMENR_ADCSMEN</li>
 <li>Rename RCC_APB2SMENR_DBGMCUSMEN into RCC_APB2SMENR_DBGSMEN</li>
 <li>Add new defines TIM_TIM2_REMAP_HSI_SUPPORT and TIM_TIM2_REMAP_HSI48_SUPPORT</li>
 <li>Remove the following defines : TIM_CR2_CCPC, TIM_CR2_CCUS, TIM_CR2_OIS1, TIM_CR2_OIS1N, TIM_CR2_OIS2,TIM_CR2_OIS2N, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_CR2_OIS4</li>
 <li>Remove TIM_SR_COMIF and TIM_SR_BIF</li>
 <li>Remove TIM_EGR_COMG and TIM_EGR_BG</li>
 <li>Remove TIM_CCER_CC1NE, TIM_CCER_CC2NE and TIM_CCER_CC3NE</li>
 <li>Remove TIM_RCR_REP</li>
 <li>Rename USART_ISR_LBD into USART_ISR_LBDF</li>
 <li>Rename WWDG_CR_Tx into WWDG_CR_T_x with x = {0,..6}</li>
 <li>Rename WWDG_CFR_WDGTBx into WWDG_CFR_WDGTB_x with x = {0,1}</li>
 <li>Add several macros to check Timer instances (IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(), IS_TIM_CLOCK_DIVISION_INSTANCE(), …)</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.4.0 / 16-October-2015</label>
 <div>
 <h2 id="main-changes-8">Main Changes</h2>
 <h3 id="maintenance-release-7">Maintenance release</h3>
 <ul>
 <li>Update all the files to support STM32L011xx and STM32L021xx.</li>
 </ul>
 <h2 id="contents-7">Contents</h2>
 <ul>
 <li>Remove the Debug Monitor handler from the startup files (not supported on L0).</li>
 <li>Renamings and usage of some aliases in order to be compliant with the RefManuals.</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.3.0 / 9-Sept-2015</label>
 <div>
 <h2 id="main-changes-9">Main Changes</h2>
 <h3 id="maintenance-release-8">Maintenance release</h3>
 <ul>
 <li>Update all the files to support <strong>STM32L031xx</strong> and <strong>STM32L041xx</strong>.</li>
 </ul>
 <h2 id="contents-8">Contents</h2>
 <ul>
 <li>Several renamings in order to be compliant with the specifications.</li>
 <li>Adding of new bit definitions (COMP_CSR_COMP2LPTIM1IN1, SYSCFG_CFGR1_UFB, I2C_OAR2_x, LCD_CR_MUX_SEG, RTC_BKP_NUMBER)</li>
 <li>Update of several registers and structures (CRC_TypeDef, TIM_TypeDef)</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.2.0 / 6-February-2015</label>
 <div>
 <h2 id="main-changes-10">Main Changes</h2>
 <h3 id="maintenance-release-9">Maintenance release</h3>
 <ul>
 <li>Added the set of CMSIS files for the <strong>STM32L07xx</strong> and <strong>STM32L08xx</strong> family</li>
 </ul>
 <h2 id="contents-9">Contents</h2>
 <ul>
 <li>Add IAR set of files STM32L073xx - STM32L072xx - STM32L071xx - STM32L083xx - STM32L082xx - STM32L081xx</li>
 <li>Added MDK-ARM startup files for L071xx, L072xx, L073xx, L081xx, L082xx, L083xx</li>
 <li>Added Atollic startup files for L071xx, L072xx, L073xx, L081xx, L082xx, L083xx</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.1.0 / 18-June-2014</label>
 <div>
 <h2 id="main-changes-11">Main Changes</h2>
 <h3 id="maintenance-release-10">Maintenance release</h3>
 <h2 id="contents-10">Contents</h2>
 <ul>
 <li><strong>Header files</strong>
 <ul>
 <li>Add defines for memories base and end addresses:
 <ul>
 <li>FLASH_END, DATA_EEPROM_BASE and DATA_EEPROM_END (instead of having them in stm32l0xx_hal_flash.h file)</li>
 </ul></li>
 <li>Peripheral register structures definition is aligned on 32 bit</li>
 <li>FLASH_SR_FWWER value fixed to 0x00020000 instead of 0x00010000</li>
 <li>Add missing EXTI register bits definition
 <ul>
 <li>IMR and EMR registers: bits 18, 20, 26, 28, 29</li>
 <li>FTSR, RTSR, PR and SWIER registers: bits 20, 21, 22</li>
 </ul></li>
 <li>Update some bits definition to be in line with latest version of the Reference Manual
 <ul>
 <li>Rename FLASH_SR_ENHV into FLASH_SR_ENDHV</li>
 <li>Rename SYSCFG_VREFINT_ADC_RDYF into SYSCFG_CFGR3_VREFINT_ADC_RDYF</li>
 <li>Rename ADC_SMPR_SMPR_xxx into ADC_SMPR_SMP_xxx</li>
 <li>Rename SYSCFG_CFGR3_VREFINT_ADC_RDYF into SYSCFG_VREFINT_ADC_RDYF Note: aliases has been added to keep compatibility with previous version</li>
 </ul></li>
 </ul></li>
 <li><strong>system_stm32l0xx.c</strong>
 <ul>
 <li>Use "__IO const" instead of "__I", to avoid any compilation issue when __cplusplus switch is defined</li>
 </ul></li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.0.1 / 24-April-2014</label>
 <div>
 <h2 id="main-changes-12">Main Changes</h2>
 <h3 id="first-official-release">First official release</h3>
 <h2 id="contents-11">Contents</h2>
 <ul>
 <li>Update gcc startup files</li>
 </ul>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 22-April-2014</label>
 <div>
 <h2 id="main-changes-13">Main Changes</h2>
 <h3 id="first-official-release-1">First official release</h3>
 </div>
 </div>
 </div>
 </div>
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	<h1 id="release-notes-for-stm32l0xx-cmsis"><small>Release Notes for</small> <mark>STM32L0xx CMSIS</mark></h1>
	<p>Copyright © 2009-2018 ARM Limited - STMicroelectronics<br />
	</p>
	<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
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	<h1 id="license">License</h1>
	<p>Licensed by ST under Apache-2.0 license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
	<p><a href="../../../LICENSE.txt">Apache License v2.0</a></p>
	<h1 id="purpose">Purpose</h1>
	<p>This driver provides the CMSIS device for the stm32l1xx products. This covers:</p>
	<ul>
	<li>STM32L010xx devices</li>
	<li>STM32L011xx and STM32L021xx devices</li>
	<li>STM32L031xx and STM32L041xx devices</li>
	<li>STM32L051xx, STM32L052xx, STM32L053xx, STM32L062xx and STM32L063xx devices</li>
	<li>STM32L071xx, STM32L072xx, STM32L073xx, STM32L082xx and STM32L083xx devices</li>
	</ul>
	<p>This driver is composed of the descriptions of the registers under “Include” directory.</p>
	<p>Various template file are provided to easily build an application. They can be adapted to fit applications requirements.</p>
	<ul>
	<li>Templates/system_stm32l0xx.c contains the initialization code referred as SystemInit.</li>
	<li>Startup files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
	<li>Linker files are provided as example for IAR©, KEIL© and SW4STM32©.</li>
	</ul>
	</div>
	<div class="col-sm-12 col-lg-8">
	<h1 id="update-history">Update History</h1>
	<div class="collapse">
	<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.9.1 / 28-October-2020</label>
	<div>
	<h2 id="main-changes">Main Changes</h2>
	<h3 id="maintenance-release">Maintenance release</h3>
	<h2 id="contents">Contents</h2>
	<ul>
	<li>system_stm32l0xx.c
	<ul>
	<li>SystemInit(): update to don’t reset RCC registers to its reset values.</li>
	<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive: USER_VECT_TAB_ADDRESS.</li>
	</ul></li>
	<li>All header files
	<ul>
	<li>Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro.</li>
	</ul></li>
	<li>Remove stm32l061xx.h header file.</li>
	<li>Add License.md and Readme.md files required for GitHub publication</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.9.0 / 26-October-2018</label>
	<div>
	<h2 id="main-changes-1">Main Changes</h2>
	<h3 id="maintenance-release-1">Maintenance release</h3>
	<h3 id="first-release-supporting-l0-value-lines">First release supporting L0 Value Lines</h3>
	<h2 id="contents-1">Contents</h2>
	<ul>
	<li>Add the support of STM32L010xx devices
	<ul>
	<li>Add stm32l010xb.h, stm32l010x8.h, stm32l010x6.h and stm32l010x4.h device description files</li>
	<li>Add startup_stm32l010xb.s, startup_stm32l010x8.s, startup_stm32l010x6.s and startup_stm32l010x4.s startup files for EWARM, MDK-ARM and SW4STM32 toolchains</li>
	<li>Add EWARM associated linker files for execution from internal RAM or internal FLASH</li>
	</ul></li>
	<li>stm32l0xx.h
	<ul>
	<li>Add the following device defines:
	<ul>
	<li>“#define STM32L010xB” for all STM32L010xB devices</li>
	<li>“#define STM32L010x8” for all STM32L010x8 devices</li>
	<li>“#define STM32L010x6” for all STM32L010x6 devices</li>
	<li>“#define STM32L010x4” for all STM32L010x4 devices</li>
	</ul></li>
	<li>Align ErrorStatus typedef to common error handling.</li>
	</ul></li>
	<li>All stm32l0xxxx.h device description files.h
	<ul>
	<li>[MISRAC2012-Rule-10.6] Use ‘UL’ postfix for _Msk definitions and memory/peripheral base addresses</li>
	<li>Correct comments in the bit definition of RCC_AHBRST, RCC_APB2RSTR and RCC_APB1RSTR registers.</li>
	<li>Rename RTC_CR_BCK bit to RTC_CR_BKP to be aligned with reference manual.</li>
	<li>Add missing definition of IS_TSC_ALL_INSTANCE after TSC driver update.</li>
	<li>Add back the bit definition of SYSCFG_CFGR3_EN_VREFINT in SYSCFG_CFGR3 register.</li>
	<li>Rename GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit definitions (from GPIO_AFRL/AFRH registers) to GPIO_AFRL_AFSELx.</li>
	<li>Align IS_TIM_XXX_INSTANCE definitions with other series.</li>
	<li>Remove cast (uint8_t) in CRC_IDR_IDR definition.</li>
	<li>Add missing definition of IS_PCD_ALL_INSTANCE macro after USB driver update.</li>
	<li>Add definition of IS_UART_DRIVER_ENABLE_INSTANCE macro after UART driver update.</li>
	<li>Add compatibility definition of USART_ICR_NECF / USART_ICR_NCF with others series.</li>
	<li>Update IS_UART_INSTANCE macro definition.</li>
	<li>Add definition of IS_LPTIM_ENCODER_INTERFACE_INSTANCE macro after LPTIM driver update.</li>
	<li>Move definition of FLASH_BANK2_BASE start address to stm32l0xx_hal_flash.h to be dependant on Memory Size register.</li>
	<li>Update interrupt definition to use DMA1_Channel4_5_IRQn for STM32L011xx and STM32L021xx devices.</li>
	<li>Correct PWR_WAKEUP_PIN definitions for L011xx and L021xx devices.</li>
	</ul></li>
	<li>system_stm32l0xx.c
	<ul>
	<li>Update file to correct comments for VECT_TAB_OFFSET definition.</li>
	<li>Update default MSI_VALUE reset value set in SystemCoreClock.</li>
	<li>Update SystemCoreClockUpdate() function to check HSI16DIVF for HSI divided by 4.</li>
	</ul></li>
	<li>startup_stm32l0xxxx.s
	<ul>
	<li>Update startup files to use DMA1_Channel4_5_IRQn/IRQHandler for STM32L011xx and STM32L01xx devices.</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.8.0 / 12-January-2018</label>
	<div>
	<h2 id="main-changes-2">Main Changes</h2>
	<h3 id="internal-release">Internal release</h3>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.7.2 / 25-August-2017</label>
	<div>
	<h2 id="main-changes-3">Main Changes</h2>
	<h3 id="maintenance-release-2">Maintenance release</h3>
	<h2 id="contents-2">Contents</h2>
	<ul>
	<li>Removed DATE and VERSION fields from header files.</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.7.1 / 25-November-2016</label>
	<div>
	<h2 id="main-changes-4">Main Changes</h2>
	<h3 id="maintenance-release-3">Maintenance release</h3>
	<h2 id="contents-3">Contents</h2>
	<ul>
	<li>Updated IS_COMP_COMMON_INSTANCE() macro.</li>
	<li>Corrected ADC_CFGR2_TOVS bit and mask definitions.</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.7.0 / 31-May-2016</label>
	<div>
	<h2 id="main-changes-5">Main Changes</h2>
	<h3 id="maintenance-release-4">Maintenance release</h3>
	<h2 id="contents-4">Contents</h2>
	<ul>
	<li>Added Pos and Msk macros missing within the CMSIS stm32l083xx.h file.</li>
	<li>Added LCD_CR_BUFEN bit definition in LCD CR register for stm32l053xx, stm32l063xx, stm32l073xx, stm32l083xx devices.</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.6.0 / 15-April-2016</label>
	<div>
	<h2 id="main-changes-6">Main Changes</h2>
	<h3 id="maintenance-release-5">Maintenance release</h3>
	<h2 id="contents-5">Contents</h2>
	<ul>
	<li>Add Pos and Msk macros within the CMSIS files.
	<ul>
	<li>For example, on the previous CMSIS version (V1.5.0), the constant ADC_IER_EOCALIE was defined as follow :
	<ul>
	<li>#define ADC_IER_EOCALIE ((uint32_t)0x00000800U)</li>
	</ul></li>
	<li>On this new CMSIS version (V1.6.0), the constant ADC_IER_EOCALIE is now defined as follow :
	<ul>
	<li>#define ADC_IER_EOCALIE_Pos (11U)</li>
	<li>#define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos)</li>
	<li>#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk</li>
	</ul></li>
	<li>The same rule applies on all the other constants present inside the CMSIS files.</li>
	</ul></li>
	<li><p>MISRA C 2004 rule 10.6 compliancy. (A ‘U’ suffix shall be applied to all constants of unisgned type).</p></li>
	<li>Several SYSCFG definition changes :</li>
	<li>SYSCFG_CFGR3_EN_VREFINT enable bit suppressed. (no more needed and must not be used).</li>
	<li>SYSCFG_CFGR3_EN_BGAP define suppressed.</li>
	<li>SYSCFG_CFGR3_REF_HSI48_RDYF, SYSCFG_CFGR3_SENSOR_ADC_RDYF, SYSCFG_CFGR3_VREFINT_ADC_RDYF, SYSCFG_CFGR3_VREFINT_COMP_RDYF flags suppressed, SYSCFG_CFGR3_VREFINT_RDYF must be used instead (this flag is a combination of the 4 suppressed flags).</li>
	<li><p>Added SYSCFG_CFGR3_REF_RC48MHz_RDYF, SYSCFG_CFGR3_REF_HSI48_RDYF, SYSCFG_VREFINT_ADC_RDYF, SYSCFG_CFGR3_SENSOR_ADC_RDYF, SYSCFG_CFGR3_VREFINT_ADC_RDYF and SYSCFG_CFGR3_VREFINT_COMP_RDYF defines.</p></li>
	<li>Aligned register namings with the different L0 Reference Manual (For STM32L0x1 : RM0377 Rev5, for STM32L0x2 : RM0367 Rev2, for STM32L0x3 : RM0367 Rev4). The list of the modification is listed hereafter :
	<ul>
	<li>Introduced new masks in EXTI bit definitions in order to simplify LL source code.</li>
	<li>Renamed RCC_CFGR_MCO_x into RCC_CFGR_MCOSEL_x</li>
	<li>Added FLASHSIZE_BASE, UID_BASE and SRAM_SIZE_MAX defines.</li>
	<li>Renamed macro IS_DMA_ALL_INSTANCE() to IS_DMA_STREAM_ALL_INSTANCE().</li>
	<li>Added new macros: IS_I2C_WAKEUP_FROMSTOP_INSTANCE(), IS_ADC_COMMON_INSTANCE() and IS_LPUART_INSTANCE().</li>
	<li>Added new defines PWR_PVD_SUPPORT to handle the PVD feature.</li>
	<li>Corrected the value of FLASH_END for STM32L011xx or STM32L021xx devices.</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.5.0 / 8-January-2016</label>
	<div>
	<h2 id="main-changes-7">Main Changes</h2>
	<h3 id="maintenance-release-6">Maintenance release</h3>
	<h2 id="contents-6">Contents</h2>
	<ul>
	<li>MISRA C 2004 rule 5.1 and rule 10.6 compliancy.</li>
	<li>Several renaming in order to be aligned with the Reference Manual.The list of the modification is listed hereafter :
	<ul>
	<li>Adding of a new COMP_Common_TypeDef structure.</li>
	<li>Removal of the RCR field inside the TIM_TypeDef structure.</li>
	<li>Adding of a new define COMP12_COMMON</li>
	<li>Adding of a new define DAC1 (same as DAC)</li>
	<li>Adding of a new define ADC1_COMMON</li>
	<li>Adding of a new define ADC_CHSELR_CHSEL</li>
	<li>Adding of a new define COMP_CSR_WINMODE</li>
	<li>Adding of a new define DAC_CHANNEL2_SUPPORT</li>
	<li>Renaming of EXTI_RTSR_TRx into EXTI_RTSR_RTx with x = {0,..22}</li>
	<li>Renaming of EXTI_FTSR_TRx into EXTI_FTSR_FTx with x = {0,..22}</li>
	<li>Renaming of EXTI_SWIER_SWIERx into EXTI_SWIER_SWIx with x = {0,..22}</li>
	<li>Renaming of EXTI_PR_PRx into EXTI_PR_PIFx with x = {0,..22}</li>
	<li>Renaming of RCC_IOPRSTR_GPIOxRST into RCC_IOPRSTR_IOPxRST with x = {A,B,C,D,E,H}</li>
	<li>Add a new define RCC_AHBRSTR_DMA1RST</li>
	<li>Add a new define RCC_APB2RSTR_ADC1RST</li>
	<li>Add a new define RCC_APB2RSTR_DBGMCURST</li>
	<li>Renaming of RCC_IOPENR_GPIOxEN into RCC_IOPENR_IOPxEN with x = {A,B,C,D,E,H}</li>
	<li>Add a new define RCC_AHBENR_DMA1EN</li>
	<li>Rename RCC_APB2ENR_MIFIEN into RCC_APB2ENR_FWEN</li>
	<li>Rename RCC_APB2ENR_ADC1EN into RCC_APB2ENR_ADCEN</li>
	<li>Rename RCC_APB2ENR_DBGMCUEN into RCC_APB2ENR_DBGEN</li>
	<li>Rename RCC_IOPSMENR_GPIOxSMEN into RCC_IOPSMENR_IOPxSMEN with x = {A,B,C,D,E,H}</li>
	<li>Add a new define RCC_AHBSMENR_DMA1SMEN</li>
	<li>Rename RCC_APB2SMENR_ADC1SMEN into RCC_APB2SMENR_ADCSMEN</li>
	<li>Rename RCC_APB2SMENR_DBGMCUSMEN into RCC_APB2SMENR_DBGSMEN</li>
	<li>Add new defines TIM_TIM2_REMAP_HSI_SUPPORT and TIM_TIM2_REMAP_HSI48_SUPPORT</li>
	<li>Remove the following defines : TIM_CR2_CCPC, TIM_CR2_CCUS, TIM_CR2_OIS1, TIM_CR2_OIS1N, TIM_CR2_OIS2,TIM_CR2_OIS2N, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_CR2_OIS4</li>
	<li>Remove TIM_SR_COMIF and TIM_SR_BIF</li>
	<li>Remove TIM_EGR_COMG and TIM_EGR_BG</li>
	<li>Remove TIM_CCER_CC1NE, TIM_CCER_CC2NE and TIM_CCER_CC3NE</li>
	<li>Remove TIM_RCR_REP</li>
	<li>Rename USART_ISR_LBD into USART_ISR_LBDF</li>
	<li>Rename WWDG_CR_Tx into WWDG_CR_T_x with x = {0,..6}</li>
	<li>Rename WWDG_CFR_WDGTBx into WWDG_CFR_WDGTB_x with x = {0,1}</li>
	<li>Add several macros to check Timer instances (IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(), IS_TIM_CLOCK_DIVISION_INSTANCE(), …)</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.4.0 / 16-October-2015</label>
	<div>
	<h2 id="main-changes-8">Main Changes</h2>
	<h3 id="maintenance-release-7">Maintenance release</h3>
	<ul>
	<li>Update all the files to support STM32L011xx and STM32L021xx.</li>
	</ul>
	<h2 id="contents-7">Contents</h2>
	<ul>
	<li>Remove the Debug Monitor handler from the startup files (not supported on L0).</li>
	<li>Renamings and usage of some aliases in order to be compliant with the RefManuals.</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.3.0 / 9-Sept-2015</label>
	<div>
	<h2 id="main-changes-9">Main Changes</h2>
	<h3 id="maintenance-release-8">Maintenance release</h3>
	<ul>
	<li>Update all the files to support <strong>STM32L031xx</strong> and <strong>STM32L041xx</strong>.</li>
	</ul>
	<h2 id="contents-8">Contents</h2>
	<ul>
	<li>Several renamings in order to be compliant with the specifications.</li>
	<li>Adding of new bit definitions (COMP_CSR_COMP2LPTIM1IN1, SYSCFG_CFGR1_UFB, I2C_OAR2_x, LCD_CR_MUX_SEG, RTC_BKP_NUMBER)</li>
	<li>Update of several registers and structures (CRC_TypeDef, TIM_TypeDef)</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.2.0 / 6-February-2015</label>
	<div>
	<h2 id="main-changes-10">Main Changes</h2>
	<h3 id="maintenance-release-9">Maintenance release</h3>
	<ul>
	<li>Added the set of CMSIS files for the <strong>STM32L07xx</strong> and <strong>STM32L08xx</strong> family</li>
	</ul>
	<h2 id="contents-9">Contents</h2>
	<ul>
	<li>Add IAR set of files STM32L073xx - STM32L072xx - STM32L071xx - STM32L083xx - STM32L082xx - STM32L081xx</li>
	<li>Added MDK-ARM startup files for L071xx, L072xx, L073xx, L081xx, L082xx, L083xx</li>
	<li>Added Atollic startup files for L071xx, L072xx, L073xx, L081xx, L082xx, L083xx</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.1.0 / 18-June-2014</label>
	<div>
	<h2 id="main-changes-11">Main Changes</h2>
	<h3 id="maintenance-release-10">Maintenance release</h3>
	<h2 id="contents-10">Contents</h2>
	<ul>
	<li><strong>Header files</strong>
	<ul>
	<li>Add defines for memories base and end addresses:
	<ul>
	<li>FLASH_END, DATA_EEPROM_BASE and DATA_EEPROM_END (instead of having them in stm32l0xx_hal_flash.h file)</li>
	</ul></li>
	<li>Peripheral register structures definition is aligned on 32 bit</li>
	<li>FLASH_SR_FWWER value fixed to 0x00020000 instead of 0x00010000</li>
	<li>Add missing EXTI register bits definition
	<ul>
	<li>IMR and EMR registers: bits 18, 20, 26, 28, 29</li>
	<li>FTSR, RTSR, PR and SWIER registers: bits 20, 21, 22</li>
	</ul></li>
	<li>Update some bits definition to be in line with latest version of the Reference Manual
	<ul>
	<li>Rename FLASH_SR_ENHV into FLASH_SR_ENDHV</li>
	<li>Rename SYSCFG_VREFINT_ADC_RDYF into SYSCFG_CFGR3_VREFINT_ADC_RDYF</li>
	<li>Rename ADC_SMPR_SMPR_xxx into ADC_SMPR_SMP_xxx</li>
	<li>Rename SYSCFG_CFGR3_VREFINT_ADC_RDYF into SYSCFG_VREFINT_ADC_RDYF Note: aliases has been added to keep compatibility with previous version</li>
	</ul></li>
	</ul></li>
	<li><strong>system_stm32l0xx.c</strong>
	<ul>
	<li>Use "__IO const" instead of "__I", to avoid any compilation issue when __cplusplus switch is defined</li>
	</ul></li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.0.1 / 24-April-2014</label>
	<div>
	<h2 id="main-changes-12">Main Changes</h2>
	<h3 id="first-official-release">First official release</h3>
	<h2 id="contents-11">Contents</h2>
	<ul>
	<li>Update gcc startup files</li>
	</ul>
	</div>
	</div>
	<div class="collapse">
	<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 22-April-2014</label>
	<div>
	<h2 id="main-changes-13">Main Changes</h2>
	<h3 id="first-official-release-1">First official release</h3>
	</div>
	</div>
	</div>
	</div>
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