| /** |
| ****************************************************************************** |
| * @file stm32l010x8.h |
| * @author MCD Application Team |
| * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. |
| * This file contains all the peripheral register's definitions, bits |
| * definitions and memory mapping for stm32l010x8 devices. |
| * |
| * This file contains: |
| * - Data structures and the address mapping for all peripherals |
| * - Peripheral's registers declarations and bits definition |
| * - Macros to access peripheral's registers hardware |
| * |
| ****************************************************************************** |
| * @attention |
| * |
| * <h2><center>© Copyright(c) 2018 STMicroelectronics. |
| * All rights reserved.</center></h2> |
| * |
| * This software component is licensed by ST under BSD 3-Clause license, |
| * the "License"; You may not use this file except in compliance with the |
| * License. You may obtain a copy of the License at: |
| * opensource.org/licenses/BSD-3-Clause |
| * |
| ****************************************************************************** |
| */ |
| |
| /** @addtogroup CMSIS |
| * @{ |
| */ |
| |
| /** @addtogroup stm32l010x8 |
| * @{ |
| */ |
| |
| #ifndef __STM32L010x8_H |
| #define __STM32L010x8_H |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| |
| /** @addtogroup Configuration_section_for_CMSIS |
| * @{ |
| */ |
| /** |
| * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals |
| */ |
| #define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */ |
| #define __MPU_PRESENT 0U /*!< STM32L0xx provides no MPU */ |
| #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ |
| #define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */ |
| #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_interrupt_number_definition |
| * @{ |
| */ |
| |
| /** |
| * @brief stm32l010x8 Interrupt Number Definition, according to the selected device |
| * in @ref Library_configuration_section |
| */ |
| |
| /*!< Interrupt Number Definition */ |
| typedef enum |
| { |
| /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ |
| NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ |
| SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ |
| PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ |
| SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ |
| |
| /****** STM32L-0 specific Interrupt Numbers *********************************************************/ |
| WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ |
| FLASH_IRQn = 3, /*!< FLASH Interrupt */ |
| RCC_IRQn = 4, /*!< RCC Interrupt */ |
| EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ |
| EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ |
| EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ |
| DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ |
| DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ |
| DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ |
| ADC1_IRQn = 12, /*!< ADC1 Interrupt */ |
| LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ |
| TIM2_IRQn = 15, /*!< TIM2 Interrupt */ |
| TIM21_IRQn = 20, /*!< TIM21 Interrupt */ |
| I2C1_IRQn = 23, /*!< I2C1 Interrupt */ |
| SPI1_IRQn = 25, /*!< SPI1 Interrupt */ |
| USART2_IRQn = 28, /*!< USART2 Interrupt */ |
| LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */ |
| } IRQn_Type; |
| |
| /** |
| * @} |
| */ |
| |
| #include "core_cm0plus.h" |
| #include "system_stm32l0xx.h" |
| #include <stdint.h> |
| |
| /** @addtogroup Peripheral_registers_structures |
| * @{ |
| */ |
| |
| /** |
| * @brief Analog to Digital Converter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ |
| __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ |
| __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ |
| __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ |
| __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ |
| __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ |
| uint32_t RESERVED1; /*!< Reserved, 0x18 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x1C */ |
| __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ |
| uint32_t RESERVED3; /*!< Reserved, 0x24 */ |
| __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ |
| uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ |
| __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ |
| uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ |
| __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ |
| } ADC_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CCR; |
| } ADC_Common_TypeDef; |
| |
| |
| |
| /** |
| * @brief CRC calculation unit |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| uint8_t RESERVED0; /*!< Reserved, 0x05 */ |
| uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x0C */ |
| __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ |
| __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ |
| } CRC_TypeDef; |
| |
| /** |
| * @brief Debug MCU |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ |
| __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ |
| }DBGMCU_TypeDef; |
| |
| /** |
| * @brief DMA Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CCR; /*!< DMA channel x configuration register */ |
| __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ |
| __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ |
| __IO uint32_t CMAR; /*!< DMA channel x memory address register */ |
| } DMA_Channel_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ |
| __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ |
| } DMA_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ |
| } DMA_Request_TypeDef; |
| |
| /** |
| * @brief External Interrupt/Event Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ |
| __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ |
| __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ |
| __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ |
| __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ |
| __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ |
| }EXTI_TypeDef; |
| |
| /** |
| * @brief FLASH Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ |
| __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ |
| __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ |
| __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ |
| __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ |
| __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ |
| __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ |
| __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */ |
| __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */ |
| } FLASH_TypeDef; |
| |
| |
| /** |
| * @brief Option Bytes Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ |
| __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ |
| __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */ |
| } OB_TypeDef; |
| |
| |
| /** |
| * @brief General Purpose IO |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ |
| __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ |
| __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ |
| }GPIO_TypeDef; |
| |
| /** |
| * @brief LPTIMIMER |
| */ |
| typedef struct |
| { |
| __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ |
| __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ |
| __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ |
| __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ |
| __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ |
| __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ |
| __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ |
| __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ |
| } LPTIM_TypeDef; |
| |
| /** |
| * @brief SysTem Configuration |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ |
| __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */ |
| __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ |
| uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ |
| __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */ |
| } SYSCFG_TypeDef; |
| |
| |
| |
| /** |
| * @brief Inter-integrated Circuit Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ |
| __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ |
| __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ |
| __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ |
| __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ |
| __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ |
| __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ |
| __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ |
| __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ |
| }I2C_TypeDef; |
| |
| |
| /** |
| * @brief Independent WATCHDOG |
| */ |
| typedef struct |
| { |
| __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
| __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
| __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
| __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
| __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ |
| } IWDG_TypeDef; |
| |
| /** |
| * @brief Power Control |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ |
| __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ |
| } PWR_TypeDef; |
| |
| /** |
| * @brief Reset and Clock Control |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
| __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ |
| __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */ |
| __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */ |
| __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */ |
| __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */ |
| __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */ |
| __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */ |
| __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */ |
| __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ |
| __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */ |
| __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */ |
| __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */ |
| __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */ |
| __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */ |
| __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */ |
| __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */ |
| __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */ |
| __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */ |
| __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */ |
| __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */ |
| } RCC_TypeDef; |
| |
| /** |
| * @brief Real-Time Clock |
| */ |
| typedef struct |
| { |
| __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
| __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
| __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
| __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
| __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
| __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
| uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ |
| __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
| __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ |
| __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
| __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
| __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
| __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
| __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
| __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
| __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
| __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ |
| __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ |
| __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ |
| __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */ |
| __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ |
| __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
| __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
| __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
| __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
| } RTC_TypeDef; |
| |
| |
| /** |
| * @brief Serial Peripheral Interface |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ |
| __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ |
| __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ |
| __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ |
| } SPI_TypeDef; |
| |
| /** |
| * @brief TIM |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ |
| __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ |
| __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */ |
| __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */ |
| __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ |
| __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
| } TIM_TypeDef; |
| |
| /** |
| * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ |
| __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ |
| __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ |
| __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ |
| __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ |
| __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ |
| __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ |
| __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ |
| __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ |
| __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ |
| } USART_TypeDef; |
| |
| /** |
| * @brief Window WATCHDOG |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| } WWDG_TypeDef; |
| |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_memory_map |
| * @{ |
| */ |
| #define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */ |
| |
| #define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */ |
| #define DATA_EEPROM_END (0x080800FFUL) /*!< DATA EEPROM end address in the alias region */ |
| #define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */ |
| #define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */ |
| |
| #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */ |
| |
| /*!< Peripheral memory map */ |
| #define APBPERIPH_BASE PERIPH_BASE |
| #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
| #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL) |
| |
| #define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL) |
| #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) |
| #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) |
| #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) |
| #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) |
| #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL) |
| #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) |
| #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) |
| #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL) |
| |
| #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) |
| #define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL) |
| #define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL) |
| #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) |
| #define ADC_BASE (APBPERIPH_BASE + 0x00012708UL) |
| #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) |
| #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) |
| |
| #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) |
| #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) |
| #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) |
| #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) |
| #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) |
| #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) |
| #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) |
| #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) |
| #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL) |
| |
| |
| #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) |
| #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ |
| #define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */ |
| #define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */ |
| #define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */ |
| #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) |
| |
| #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL) |
| #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL) |
| #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL) |
| #define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL) |
| #define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL) |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_declaration |
| * @{ |
| */ |
| |
| #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| #define RTC ((RTC_TypeDef *) RTC_BASE) |
| #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| #define USART2 ((USART_TypeDef *) USART2_BASE) |
| #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) |
| #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| #define PWR ((PWR_TypeDef *) PWR_BASE) |
| #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) |
| |
| #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
| #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| #define TIM21 ((TIM_TypeDef *) TIM21_BASE) |
| #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) |
| /* Legacy defines */ |
| #define ADC ADC1_COMMON |
| #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| |
| #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
| #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
| #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
| #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
| #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
| #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
| #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
| #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) |
| |
| |
| #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| #define OB ((OB_TypeDef *) OB_BASE) |
| #define RCC ((RCC_TypeDef *) RCC_BASE) |
| #define CRC ((CRC_TypeDef *) CRC_BASE) |
| |
| #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
| #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Exported_constants |
| * @{ |
| */ |
| |
| /** @addtogroup Peripheral_Registers_Bits_Definition |
| * @{ |
| */ |
| |
| /******************************************************************************/ |
| /* Peripheral Registers Bits Definition */ |
| /******************************************************************************/ |
| /******************************************************************************/ |
| /* */ |
| /* Analog to Digital Converter (ADC) */ |
| /* */ |
| /******************************************************************************/ |
| /******************** Bits definition for ADC_ISR register ******************/ |
| #define ADC_ISR_EOCAL_Pos (11U) |
| #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ |
| #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */ |
| #define ADC_ISR_AWD_Pos (7U) |
| #define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */ |
| #define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */ |
| #define ADC_ISR_OVR_Pos (4U) |
| #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ |
| #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */ |
| #define ADC_ISR_EOSEQ_Pos (3U) |
| #define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */ |
| #define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */ |
| #define ADC_ISR_EOC_Pos (2U) |
| #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ |
| #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */ |
| #define ADC_ISR_EOSMP_Pos (1U) |
| #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ |
| #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ |
| #define ADC_ISR_ADRDY_Pos (0U) |
| #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ |
| #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */ |
| |
| /* Old EOSEQ bit definition, maintained for legacy purpose */ |
| #define ADC_ISR_EOS ADC_ISR_EOSEQ |
| |
| /******************** Bits definition for ADC_IER register ******************/ |
| #define ADC_IER_EOCALIE_Pos (11U) |
| #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ |
| #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */ |
| #define ADC_IER_AWDIE_Pos (7U) |
| #define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */ |
| #define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */ |
| #define ADC_IER_OVRIE_Pos (4U) |
| #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ |
| #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ |
| #define ADC_IER_EOSEQIE_Pos (3U) |
| #define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */ |
| #define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */ |
| #define ADC_IER_EOCIE_Pos (2U) |
| #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ |
| #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */ |
| #define ADC_IER_EOSMPIE_Pos (1U) |
| #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ |
| #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */ |
| #define ADC_IER_ADRDYIE_Pos (0U) |
| #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ |
| #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */ |
| |
| /* Old EOSEQIE bit definition, maintained for legacy purpose */ |
| #define ADC_IER_EOSIE ADC_IER_EOSEQIE |
| |
| /******************** Bits definition for ADC_CR register *******************/ |
| #define ADC_CR_ADCAL_Pos (31U) |
| #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ |
| #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ |
| #define ADC_CR_ADVREGEN_Pos (28U) |
| #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ |
| #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */ |
| #define ADC_CR_ADSTP_Pos (4U) |
| #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ |
| #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */ |
| #define ADC_CR_ADSTART_Pos (2U) |
| #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ |
| #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */ |
| #define ADC_CR_ADDIS_Pos (1U) |
| #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ |
| #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ |
| #define ADC_CR_ADEN_Pos (0U) |
| #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ |
| #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */ |
| |
| /******************* Bits definition for ADC_CFGR1 register *****************/ |
| #define ADC_CFGR1_AWDCH_Pos (26U) |
| #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ |
| #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ |
| #define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */ |
| #define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */ |
| #define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */ |
| #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ |
| #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ |
| #define ADC_CFGR1_AWDEN_Pos (23U) |
| #define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */ |
| #define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */ |
| #define ADC_CFGR1_AWDSGL_Pos (22U) |
| #define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */ |
| #define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */ |
| #define ADC_CFGR1_DISCEN_Pos (16U) |
| #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ |
| #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */ |
| #define ADC_CFGR1_AUTOFF_Pos (15U) |
| #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ |
| #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */ |
| #define ADC_CFGR1_WAIT_Pos (14U) |
| #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ |
| #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */ |
| #define ADC_CFGR1_CONT_Pos (13U) |
| #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ |
| #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */ |
| #define ADC_CFGR1_OVRMOD_Pos (12U) |
| #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ |
| #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ |
| #define ADC_CFGR1_EXTEN_Pos (10U) |
| #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ |
| #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ |
| #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ |
| #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ |
| #define ADC_CFGR1_EXTSEL_Pos (6U) |
| #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ |
| #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ |
| #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ |
| #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ |
| #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ |
| #define ADC_CFGR1_ALIGN_Pos (5U) |
| #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ |
| #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */ |
| #define ADC_CFGR1_RES_Pos (3U) |
| #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ |
| #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */ |
| #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ |
| #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ |
| #define ADC_CFGR1_SCANDIR_Pos (2U) |
| #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ |
| #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */ |
| #define ADC_CFGR1_DMACFG_Pos (1U) |
| #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ |
| #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */ |
| #define ADC_CFGR1_DMAEN_Pos (0U) |
| #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ |
| #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */ |
| |
| /* Old WAIT bit definition, maintained for legacy purpose */ |
| #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT |
| |
| /******************* Bits definition for ADC_CFGR2 register *****************/ |
| #define ADC_CFGR2_TOVS_Pos (9U) |
| #define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */ |
| #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */ |
| #define ADC_CFGR2_OVSS_Pos (5U) |
| #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ |
| #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */ |
| #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ |
| #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ |
| #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ |
| #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ |
| #define ADC_CFGR2_OVSR_Pos (2U) |
| #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ |
| #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */ |
| #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ |
| #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ |
| #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ |
| #define ADC_CFGR2_OVSE_Pos (0U) |
| #define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ |
| #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */ |
| #define ADC_CFGR2_CKMODE_Pos (30U) |
| #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ |
| #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */ |
| #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ |
| #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ |
| |
| |
| /****************** Bit definition for ADC_SMPR register ********************/ |
| #define ADC_SMPR_SMP_Pos (0U) |
| #define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ |
| #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */ |
| #define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ |
| #define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ |
| #define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ |
| |
| /* Legacy defines */ |
| #define ADC_SMPR_SMPR ADC_SMPR_SMP |
| #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0 |
| #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1 |
| #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2 |
| |
| /******************* Bit definition for ADC_TR register ********************/ |
| #define ADC_TR_HT_Pos (16U) |
| #define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */ |
| #define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */ |
| #define ADC_TR_LT_Pos (0U) |
| #define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */ |
| #define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */ |
| |
| /****************** Bit definition for ADC_CHSELR register ******************/ |
| #define ADC_CHSELR_CHSEL_Pos (0U) |
| #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ |
| #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */ |
| #define ADC_CHSELR_CHSEL18_Pos (18U) |
| #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ |
| #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */ |
| #define ADC_CHSELR_CHSEL17_Pos (17U) |
| #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ |
| #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */ |
| #define ADC_CHSELR_CHSEL15_Pos (15U) |
| #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ |
| #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */ |
| #define ADC_CHSELR_CHSEL14_Pos (14U) |
| #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ |
| #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */ |
| #define ADC_CHSELR_CHSEL13_Pos (13U) |
| #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ |
| #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */ |
| #define ADC_CHSELR_CHSEL12_Pos (12U) |
| #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ |
| #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */ |
| #define ADC_CHSELR_CHSEL11_Pos (11U) |
| #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ |
| #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */ |
| #define ADC_CHSELR_CHSEL10_Pos (10U) |
| #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ |
| #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */ |
| #define ADC_CHSELR_CHSEL9_Pos (9U) |
| #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ |
| #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */ |
| #define ADC_CHSELR_CHSEL8_Pos (8U) |
| #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ |
| #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */ |
| #define ADC_CHSELR_CHSEL7_Pos (7U) |
| #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ |
| #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */ |
| #define ADC_CHSELR_CHSEL6_Pos (6U) |
| #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ |
| #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */ |
| #define ADC_CHSELR_CHSEL5_Pos (5U) |
| #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ |
| #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */ |
| #define ADC_CHSELR_CHSEL4_Pos (4U) |
| #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ |
| #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */ |
| #define ADC_CHSELR_CHSEL3_Pos (3U) |
| #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ |
| #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */ |
| #define ADC_CHSELR_CHSEL2_Pos (2U) |
| #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ |
| #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */ |
| #define ADC_CHSELR_CHSEL1_Pos (1U) |
| #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ |
| #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */ |
| #define ADC_CHSELR_CHSEL0_Pos (0U) |
| #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ |
| #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */ |
| |
| /******************** Bit definition for ADC_DR register ********************/ |
| #define ADC_DR_DATA_Pos (0U) |
| #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */ |
| |
| /******************** Bit definition for ADC_CALFACT register ********************/ |
| #define ADC_CALFACT_CALFACT_Pos (0U) |
| #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ |
| #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */ |
| |
| /******************* Bit definition for ADC_CCR register ********************/ |
| #define ADC_CCR_LFMEN_Pos (25U) |
| #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ |
| #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */ |
| #define ADC_CCR_VREFEN_Pos (22U) |
| #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ |
| #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */ |
| #define ADC_CCR_PRESC_Pos (18U) |
| #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ |
| #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */ |
| #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ |
| #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ |
| #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ |
| #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* CRC calculation unit (CRC) */ |
| /* */ |
| /******************************************************************************/ |
| /******************* Bit definition for CRC_DR register *********************/ |
| #define CRC_DR_DR_Pos (0U) |
| #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ |
| #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ |
| |
| /******************* Bit definition for CRC_IDR register ********************/ |
| #define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */ |
| |
| /******************** Bit definition for CRC_CR register ********************/ |
| #define CRC_CR_RESET_Pos (0U) |
| #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ |
| #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ |
| #define CRC_CR_POLYSIZE_Pos (3U) |
| #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ |
| #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ |
| #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ |
| #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ |
| #define CRC_CR_REV_IN_Pos (5U) |
| #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ |
| #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ |
| #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ |
| #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ |
| #define CRC_CR_REV_OUT_Pos (7U) |
| #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ |
| #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ |
| |
| /******************* Bit definition for CRC_INIT register *******************/ |
| #define CRC_INIT_INIT_Pos (0U) |
| #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ |
| #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ |
| |
| /******************* Bit definition for CRC_POL register ********************/ |
| #define CRC_POL_POL_Pos (0U) |
| #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ |
| #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* Debug MCU (DBGMCU) */ |
| /* */ |
| /******************************************************************************/ |
| |
| /**************** Bit definition for DBGMCU_IDCODE register *****************/ |
| #define DBGMCU_IDCODE_DEV_ID_Pos (0U) |
| #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ |
| #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ |
| |
| #define DBGMCU_IDCODE_REV_ID_Pos (16U) |
| #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ |
| #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ |
| #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ |
| #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ |
| #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ |
| #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ |
| #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ |
| #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ |
| #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ |
| #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ |
| #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ |
| #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ |
| #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ |
| #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ |
| #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ |
| #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ |
| #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ |
| #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ |
| |
| /****************** Bit definition for DBGMCU_CR register *******************/ |
| #define DBGMCU_CR_DBG_Pos (0U) |
| #define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */ |
| #define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */ |
| #define DBGMCU_CR_DBG_SLEEP_Pos (0U) |
| #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ |
| #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ |
| #define DBGMCU_CR_DBG_STOP_Pos (1U) |
| #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ |
| #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ |
| #define DBGMCU_CR_DBG_STANDBY_Pos (2U) |
| #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ |
| #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ |
| |
| /****************** Bit definition for DBGMCU_APB1_FZ register **************/ |
| #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) |
| #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ |
| #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ |
| #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) |
| #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ |
| #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ |
| #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) |
| #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ |
| #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ |
| #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) |
| #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ |
| #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ |
| #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U) |
| #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ |
| #define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ |
| #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U) |
| #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */ |
| #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */ |
| /****************** Bit definition for DBGMCU_APB2_FZ register **************/ |
| #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U) |
| #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */ |
| #define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* DMA Controller (DMA) */ |
| /* */ |
| /******************************************************************************/ |
| |
| /******************* Bit definition for DMA_ISR register ********************/ |
| #define DMA_ISR_GIF1_Pos (0U) |
| #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ |
| #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ |
| #define DMA_ISR_TCIF1_Pos (1U) |
| #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ |
| #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ |
| #define DMA_ISR_HTIF1_Pos (2U) |
| #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ |
| #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ |
| #define DMA_ISR_TEIF1_Pos (3U) |
| #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ |
| #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ |
| #define DMA_ISR_GIF2_Pos (4U) |
| #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ |
| #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ |
| #define DMA_ISR_TCIF2_Pos (5U) |
| #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ |
| #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ |
| #define DMA_ISR_HTIF2_Pos (6U) |
| #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ |
| #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ |
| #define DMA_ISR_TEIF2_Pos (7U) |
| #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ |
| #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ |
| #define DMA_ISR_GIF3_Pos (8U) |
| #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ |
| #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ |
| #define DMA_ISR_TCIF3_Pos (9U) |
| #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ |
| #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ |
| #define DMA_ISR_HTIF3_Pos (10U) |
| #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ |
| #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ |
| #define DMA_ISR_TEIF3_Pos (11U) |
| #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ |
| #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ |
| #define DMA_ISR_GIF4_Pos (12U) |
| #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ |
| #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ |
| #define DMA_ISR_TCIF4_Pos (13U) |
| #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ |
| #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ |
| #define DMA_ISR_HTIF4_Pos (14U) |
| #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ |
| #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ |
| #define DMA_ISR_TEIF4_Pos (15U) |
| #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ |
| #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ |
| #define DMA_ISR_GIF5_Pos (16U) |
| #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ |
| #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ |
| #define DMA_ISR_TCIF5_Pos (17U) |
| #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ |
| #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ |
| #define DMA_ISR_HTIF5_Pos (18U) |
| #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ |
| #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ |
| #define DMA_ISR_TEIF5_Pos (19U) |
| #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ |
| #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ |
| #define DMA_ISR_GIF6_Pos (20U) |
| #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ |
| #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ |
| #define DMA_ISR_TCIF6_Pos (21U) |
| #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ |
| #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ |
| #define DMA_ISR_HTIF6_Pos (22U) |
| #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ |
| #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ |
| #define DMA_ISR_TEIF6_Pos (23U) |
| #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ |
| #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ |
| #define DMA_ISR_GIF7_Pos (24U) |
| #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ |
| #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ |
| #define DMA_ISR_TCIF7_Pos (25U) |
| #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ |
| #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ |
| #define DMA_ISR_HTIF7_Pos (26U) |
| #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ |
| #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ |
| #define DMA_ISR_TEIF7_Pos (27U) |
| #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ |
| #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ |
| |
| /******************* Bit definition for DMA_IFCR register *******************/ |
| #define DMA_IFCR_CGIF1_Pos (0U) |
| #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ |
| #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF1_Pos (1U) |
| #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ |
| #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF1_Pos (2U) |
| #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ |
| #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF1_Pos (3U) |
| #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ |
| #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ |
| #define DMA_IFCR_CGIF2_Pos (4U) |
| #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ |
| #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF2_Pos (5U) |
| #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ |
| #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF2_Pos (6U) |
| #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ |
| #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF2_Pos (7U) |
| #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ |
| #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ |
| #define DMA_IFCR_CGIF3_Pos (8U) |
| #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ |
| #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF3_Pos (9U) |
| #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ |
| #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF3_Pos (10U) |
| #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ |
| #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF3_Pos (11U) |
| #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ |
| #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ |
| #define DMA_IFCR_CGIF4_Pos (12U) |
| #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ |
| #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF4_Pos (13U) |
| #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ |
| #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF4_Pos (14U) |
| #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ |
| #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF4_Pos (15U) |
| #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ |
| #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ |
| #define DMA_IFCR_CGIF5_Pos (16U) |
| #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ |
| #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF5_Pos (17U) |
| #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ |
| #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF5_Pos (18U) |
| #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ |
| #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF5_Pos (19U) |
| #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ |
| #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ |
| #define DMA_IFCR_CGIF6_Pos (20U) |
| #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ |
| #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF6_Pos (21U) |
| #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ |
| #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF6_Pos (22U) |
| #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ |
| #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF6_Pos (23U) |
| #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ |
| #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ |
| #define DMA_IFCR_CGIF7_Pos (24U) |
| #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ |
| #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ |
| #define DMA_IFCR_CTCIF7_Pos (25U) |
| #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ |
| #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ |
| #define DMA_IFCR_CHTIF7_Pos (26U) |
| #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ |
| #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ |
| #define DMA_IFCR_CTEIF7_Pos (27U) |
| #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ |
| #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ |
| |
| /******************* Bit definition for DMA_CCR register ********************/ |
| #define DMA_CCR_EN_Pos (0U) |
| #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ |
| #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ |
| #define DMA_CCR_TCIE_Pos (1U) |
| #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ |
| #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ |
| #define DMA_CCR_HTIE_Pos (2U) |
| #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ |
| #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ |
| #define DMA_CCR_TEIE_Pos (3U) |
| #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ |
| #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ |
| #define DMA_CCR_DIR_Pos (4U) |
| #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ |
| #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ |
| #define DMA_CCR_CIRC_Pos (5U) |
| #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ |
| #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ |
| #define DMA_CCR_PINC_Pos (6U) |
| #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ |
| #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ |
| #define DMA_CCR_MINC_Pos (7U) |
| #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ |
| #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ |
| |
| #define DMA_CCR_PSIZE_Pos (8U) |
| #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ |
| #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ |
| #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ |
| #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ |
| |
| #define DMA_CCR_MSIZE_Pos (10U) |
| #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ |
| #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ |
| #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ |
| #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ |
| |
| #define DMA_CCR_PL_Pos (12U) |
| #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ |
| #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ |
| #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ |
| #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ |
| |
| #define DMA_CCR_MEM2MEM_Pos (14U) |
| #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ |
| #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ |
| |
| /****************** Bit definition for DMA_CNDTR register *******************/ |
| #define DMA_CNDTR_NDT_Pos (0U) |
| #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ |
| #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ |
| |
| /****************** Bit definition for DMA_CPAR register ********************/ |
| #define DMA_CPAR_PA_Pos (0U) |
| #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ |
| #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ |
| |
| /****************** Bit definition for DMA_CMAR register ********************/ |
| #define DMA_CMAR_MA_Pos (0U) |
| #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ |
| |
| |
| /******************* Bit definition for DMA_CSELR register *******************/ |
| #define DMA_CSELR_C1S_Pos (0U) |
| #define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ |
| #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ |
| #define DMA_CSELR_C2S_Pos (4U) |
| #define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ |
| #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ |
| #define DMA_CSELR_C3S_Pos (8U) |
| #define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ |
| #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ |
| #define DMA_CSELR_C4S_Pos (12U) |
| #define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ |
| #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ |
| #define DMA_CSELR_C5S_Pos (16U) |
| #define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ |
| #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ |
| #define DMA_CSELR_C6S_Pos (20U) |
| #define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */ |
| #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */ |
| #define DMA_CSELR_C7S_Pos (24U) |
| #define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */ |
| #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* External Interrupt/Event Controller (EXTI) */ |
| /* */ |
| /******************************************************************************/ |
| |
| /******************* Bit definition for EXTI_IMR register *******************/ |
| #define EXTI_IMR_IM0_Pos (0U) |
| #define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */ |
| #define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */ |
| #define EXTI_IMR_IM1_Pos (1U) |
| #define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */ |
| #define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */ |
| #define EXTI_IMR_IM2_Pos (2U) |
| #define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */ |
| #define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */ |
| #define EXTI_IMR_IM3_Pos (3U) |
| #define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */ |
| #define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */ |
| #define EXTI_IMR_IM4_Pos (4U) |
| #define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */ |
| #define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */ |
| #define EXTI_IMR_IM5_Pos (5U) |
| #define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */ |
| #define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */ |
| #define EXTI_IMR_IM6_Pos (6U) |
| #define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */ |
| #define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */ |
| #define EXTI_IMR_IM7_Pos (7U) |
| #define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */ |
| #define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */ |
| #define EXTI_IMR_IM8_Pos (8U) |
| #define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */ |
| #define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */ |
| #define EXTI_IMR_IM9_Pos (9U) |
| #define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */ |
| #define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */ |
| #define EXTI_IMR_IM10_Pos (10U) |
| #define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */ |
| #define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */ |
| #define EXTI_IMR_IM11_Pos (11U) |
| #define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */ |
| #define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */ |
| #define EXTI_IMR_IM12_Pos (12U) |
| #define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */ |
| #define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */ |
| #define EXTI_IMR_IM13_Pos (13U) |
| #define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */ |
| #define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */ |
| #define EXTI_IMR_IM14_Pos (14U) |
| #define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */ |
| #define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */ |
| #define EXTI_IMR_IM15_Pos (15U) |
| #define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */ |
| #define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */ |
| #define EXTI_IMR_IM17_Pos (17U) |
| #define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */ |
| #define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */ |
| #define EXTI_IMR_IM19_Pos (19U) |
| #define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */ |
| #define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */ |
| #define EXTI_IMR_IM20_Pos (20U) |
| #define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */ |
| #define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */ |
| #define EXTI_IMR_IM23_Pos (23U) |
| #define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */ |
| #define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */ |
| #define EXTI_IMR_IM26_Pos (26U) |
| #define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */ |
| #define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */ |
| #define EXTI_IMR_IM28_Pos (28U) |
| #define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */ |
| #define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */ |
| #define EXTI_IMR_IM29_Pos (29U) |
| #define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */ |
| #define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */ |
| |
| #define EXTI_IMR_IM_Pos (0U) |
| #define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */ |
| #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ |
| |
| /****************** Bit definition for EXTI_EMR register ********************/ |
| #define EXTI_EMR_EM0_Pos (0U) |
| #define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */ |
| #define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */ |
| #define EXTI_EMR_EM1_Pos (1U) |
| #define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */ |
| #define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */ |
| #define EXTI_EMR_EM2_Pos (2U) |
| #define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */ |
| #define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */ |
| #define EXTI_EMR_EM3_Pos (3U) |
| #define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */ |
| #define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */ |
| #define EXTI_EMR_EM4_Pos (4U) |
| #define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */ |
| #define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */ |
| #define EXTI_EMR_EM5_Pos (5U) |
| #define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */ |
| #define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */ |
| #define EXTI_EMR_EM6_Pos (6U) |
| #define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */ |
| #define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */ |
| #define EXTI_EMR_EM7_Pos (7U) |
| #define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */ |
| #define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */ |
| #define EXTI_EMR_EM8_Pos (8U) |
| #define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */ |
| #define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */ |
| #define EXTI_EMR_EM9_Pos (9U) |
| #define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */ |
| #define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */ |
| #define EXTI_EMR_EM10_Pos (10U) |
| #define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */ |
| #define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */ |
| #define EXTI_EMR_EM11_Pos (11U) |
| #define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */ |
| #define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */ |
| #define EXTI_EMR_EM12_Pos (12U) |
| #define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */ |
| #define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */ |
| #define EXTI_EMR_EM13_Pos (13U) |
| #define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */ |
| #define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */ |
| #define EXTI_EMR_EM14_Pos (14U) |
| #define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */ |
| #define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */ |
| #define EXTI_EMR_EM15_Pos (15U) |
| #define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */ |
| #define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */ |
| #define EXTI_EMR_EM17_Pos (17U) |
| #define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */ |
| #define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */ |
| #define EXTI_EMR_EM19_Pos (19U) |
| #define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */ |
| #define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */ |
| #define EXTI_EMR_EM20_Pos (20U) |
| #define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */ |
| #define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */ |
| #define EXTI_EMR_EM23_Pos (23U) |
| #define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */ |
| #define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */ |
| #define EXTI_EMR_EM26_Pos (26U) |
| #define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */ |
| #define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */ |
| #define EXTI_EMR_EM28_Pos (28U) |
| #define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */ |
| #define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */ |
| #define EXTI_EMR_EM29_Pos (29U) |
| #define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */ |
| #define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */ |
| |
| /******************* Bit definition for EXTI_RTSR register ******************/ |
| #define EXTI_RTSR_RT0_Pos (0U) |
| #define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ |
| #define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ |
| #define EXTI_RTSR_RT1_Pos (1U) |
| #define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ |
| #define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ |
| #define EXTI_RTSR_RT2_Pos (2U) |
| #define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ |
| #define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ |
| #define EXTI_RTSR_RT3_Pos (3U) |
| #define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ |
| #define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ |
| #define EXTI_RTSR_RT4_Pos (4U) |
| #define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ |
| #define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ |
| #define EXTI_RTSR_RT5_Pos (5U) |
| #define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ |
| #define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ |
| #define EXTI_RTSR_RT6_Pos (6U) |
| #define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ |
| #define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ |
| #define EXTI_RTSR_RT7_Pos (7U) |
| #define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ |
| #define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ |
| #define EXTI_RTSR_RT8_Pos (8U) |
| #define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */ |
| #define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ |
| #define EXTI_RTSR_RT9_Pos (9U) |
| #define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */ |
| #define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ |
| #define EXTI_RTSR_RT10_Pos (10U) |
| #define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */ |
| #define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ |
| #define EXTI_RTSR_RT11_Pos (11U) |
| #define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */ |
| #define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ |
| #define EXTI_RTSR_RT12_Pos (12U) |
| #define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */ |
| #define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ |
| #define EXTI_RTSR_RT13_Pos (13U) |
| #define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */ |
| #define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ |
| #define EXTI_RTSR_RT14_Pos (14U) |
| #define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */ |
| #define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ |
| #define EXTI_RTSR_RT15_Pos (15U) |
| #define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */ |
| #define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ |
| #define EXTI_RTSR_RT16_Pos (16U) |
| #define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */ |
| #define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ |
| #define EXTI_RTSR_RT17_Pos (17U) |
| #define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */ |
| #define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ |
| #define EXTI_RTSR_RT19_Pos (19U) |
| #define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */ |
| #define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ |
| #define EXTI_RTSR_RT20_Pos (20U) |
| #define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */ |
| #define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ |
| #define EXTI_RTSR_RT21_Pos (21U) |
| #define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */ |
| #define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ |
| #define EXTI_RTSR_RT22_Pos (22U) |
| #define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */ |
| #define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ |
| |
| /* Legacy defines */ |
| #define EXTI_RTSR_TR0 EXTI_RTSR_RT0 |
| #define EXTI_RTSR_TR1 EXTI_RTSR_RT1 |
| #define EXTI_RTSR_TR2 EXTI_RTSR_RT2 |
| #define EXTI_RTSR_TR3 EXTI_RTSR_RT3 |
| #define EXTI_RTSR_TR4 EXTI_RTSR_RT4 |
| #define EXTI_RTSR_TR5 EXTI_RTSR_RT5 |
| #define EXTI_RTSR_TR6 EXTI_RTSR_RT6 |
| #define EXTI_RTSR_TR7 EXTI_RTSR_RT7 |
| #define EXTI_RTSR_TR8 EXTI_RTSR_RT8 |
| #define EXTI_RTSR_TR9 EXTI_RTSR_RT9 |
| #define EXTI_RTSR_TR10 EXTI_RTSR_RT10 |
| #define EXTI_RTSR_TR11 EXTI_RTSR_RT11 |
| #define EXTI_RTSR_TR12 EXTI_RTSR_RT12 |
| #define EXTI_RTSR_TR13 EXTI_RTSR_RT13 |
| #define EXTI_RTSR_TR14 EXTI_RTSR_RT14 |
| #define EXTI_RTSR_TR15 EXTI_RTSR_RT15 |
| #define EXTI_RTSR_TR16 EXTI_RTSR_RT16 |
| #define EXTI_RTSR_TR17 EXTI_RTSR_RT17 |
| #define EXTI_RTSR_TR19 EXTI_RTSR_RT19 |
| #define EXTI_RTSR_TR20 EXTI_RTSR_RT20 |
| #define EXTI_RTSR_TR21 EXTI_RTSR_RT21 |
| #define EXTI_RTSR_TR22 EXTI_RTSR_RT22 |
| |
| /******************* Bit definition for EXTI_FTSR register *******************/ |
| #define EXTI_FTSR_FT0_Pos (0U) |
| #define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ |
| #define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ |
| #define EXTI_FTSR_FT1_Pos (1U) |
| #define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ |
| #define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ |
| #define EXTI_FTSR_FT2_Pos (2U) |
| #define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ |
| #define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ |
| #define EXTI_FTSR_FT3_Pos (3U) |
| #define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ |
| #define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ |
| #define EXTI_FTSR_FT4_Pos (4U) |
| #define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ |
| #define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ |
| #define EXTI_FTSR_FT5_Pos (5U) |
| #define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ |
| #define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ |
| #define EXTI_FTSR_FT6_Pos (6U) |
| #define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ |
| #define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ |
| #define EXTI_FTSR_FT7_Pos (7U) |
| #define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ |
| #define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ |
| #define EXTI_FTSR_FT8_Pos (8U) |
| #define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */ |
| #define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ |
| #define EXTI_FTSR_FT9_Pos (9U) |
| #define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */ |
| #define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ |
| #define EXTI_FTSR_FT10_Pos (10U) |
| #define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */ |
| #define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ |
| #define EXTI_FTSR_FT11_Pos (11U) |
| #define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */ |
| #define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ |
| #define EXTI_FTSR_FT12_Pos (12U) |
| #define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */ |
| #define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ |
| #define EXTI_FTSR_FT13_Pos (13U) |
| #define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */ |
| #define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ |
| #define EXTI_FTSR_FT14_Pos (14U) |
| #define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */ |
| #define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ |
| #define EXTI_FTSR_FT15_Pos (15U) |
| #define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */ |
| #define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ |
| #define EXTI_FTSR_FT16_Pos (16U) |
| #define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */ |
| #define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ |
| #define EXTI_FTSR_FT17_Pos (17U) |
| #define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */ |
| #define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ |
| #define EXTI_FTSR_FT19_Pos (19U) |
| #define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */ |
| #define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ |
| #define EXTI_FTSR_FT20_Pos (20U) |
| #define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */ |
| #define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ |
| #define EXTI_FTSR_FT21_Pos (21U) |
| #define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */ |
| #define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ |
| #define EXTI_FTSR_FT22_Pos (22U) |
| #define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */ |
| #define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ |
| |
| /* Legacy defines */ |
| #define EXTI_FTSR_TR0 EXTI_FTSR_FT0 |
| #define EXTI_FTSR_TR1 EXTI_FTSR_FT1 |
| #define EXTI_FTSR_TR2 EXTI_FTSR_FT2 |
| #define EXTI_FTSR_TR3 EXTI_FTSR_FT3 |
| #define EXTI_FTSR_TR4 EXTI_FTSR_FT4 |
| #define EXTI_FTSR_TR5 EXTI_FTSR_FT5 |
| #define EXTI_FTSR_TR6 EXTI_FTSR_FT6 |
| #define EXTI_FTSR_TR7 EXTI_FTSR_FT7 |
| #define EXTI_FTSR_TR8 EXTI_FTSR_FT8 |
| #define EXTI_FTSR_TR9 EXTI_FTSR_FT9 |
| #define EXTI_FTSR_TR10 EXTI_FTSR_FT10 |
| #define EXTI_FTSR_TR11 EXTI_FTSR_FT11 |
| #define EXTI_FTSR_TR12 EXTI_FTSR_FT12 |
| #define EXTI_FTSR_TR13 EXTI_FTSR_FT13 |
| #define EXTI_FTSR_TR14 EXTI_FTSR_FT14 |
| #define EXTI_FTSR_TR15 EXTI_FTSR_FT15 |
| #define EXTI_FTSR_TR16 EXTI_FTSR_FT16 |
| #define EXTI_FTSR_TR17 EXTI_FTSR_FT17 |
| #define EXTI_FTSR_TR19 EXTI_FTSR_FT19 |
| #define EXTI_FTSR_TR20 EXTI_FTSR_FT20 |
| #define EXTI_FTSR_TR21 EXTI_FTSR_FT21 |
| #define EXTI_FTSR_TR22 EXTI_FTSR_FT22 |
| |
| /******************* Bit definition for EXTI_SWIER register *******************/ |
| #define EXTI_SWIER_SWI0_Pos (0U) |
| #define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ |
| #define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ |
| #define EXTI_SWIER_SWI1_Pos (1U) |
| #define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ |
| #define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ |
| #define EXTI_SWIER_SWI2_Pos (2U) |
| #define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ |
| #define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ |
| #define EXTI_SWIER_SWI3_Pos (3U) |
| #define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ |
| #define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ |
| #define EXTI_SWIER_SWI4_Pos (4U) |
| #define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ |
| #define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ |
| #define EXTI_SWIER_SWI5_Pos (5U) |
| #define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ |
| #define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ |
| #define EXTI_SWIER_SWI6_Pos (6U) |
| #define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ |
| #define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ |
| #define EXTI_SWIER_SWI7_Pos (7U) |
| #define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ |
| #define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ |
| #define EXTI_SWIER_SWI8_Pos (8U) |
| #define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */ |
| #define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */ |
| #define EXTI_SWIER_SWI9_Pos (9U) |
| #define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */ |
| #define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */ |
| #define EXTI_SWIER_SWI10_Pos (10U) |
| #define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */ |
| #define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */ |
| #define EXTI_SWIER_SWI11_Pos (11U) |
| #define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */ |
| #define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */ |
| #define EXTI_SWIER_SWI12_Pos (12U) |
| #define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */ |
| #define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */ |
| #define EXTI_SWIER_SWI13_Pos (13U) |
| #define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */ |
| #define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */ |
| #define EXTI_SWIER_SWI14_Pos (14U) |
| #define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */ |
| #define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */ |
| #define EXTI_SWIER_SWI15_Pos (15U) |
| #define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */ |
| #define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */ |
| #define EXTI_SWIER_SWI16_Pos (16U) |
| #define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */ |
| #define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */ |
| #define EXTI_SWIER_SWI17_Pos (17U) |
| #define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */ |
| #define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */ |
| #define EXTI_SWIER_SWI19_Pos (19U) |
| #define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */ |
| #define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */ |
| #define EXTI_SWIER_SWI20_Pos (20U) |
| #define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */ |
| #define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */ |
| #define EXTI_SWIER_SWI21_Pos (21U) |
| #define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */ |
| #define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */ |
| #define EXTI_SWIER_SWI22_Pos (22U) |
| #define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */ |
| #define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */ |
| |
| /* Legacy defines */ |
| #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0 |
| #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1 |
| #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2 |
| #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3 |
| #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4 |
| #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5 |
| #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6 |
| #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7 |
| #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8 |
| #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9 |
| #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10 |
| #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11 |
| #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12 |
| #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13 |
| #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14 |
| #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15 |
| #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16 |
| #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17 |
| #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19 |
| #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20 |
| #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21 |
| #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22 |
| |
| /****************** Bit definition for EXTI_PR register *********************/ |
| #define EXTI_PR_PIF0_Pos (0U) |
| #define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */ |
| #define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */ |
| #define EXTI_PR_PIF1_Pos (1U) |
| #define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */ |
| #define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */ |
| #define EXTI_PR_PIF2_Pos (2U) |
| #define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */ |
| #define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */ |
| #define EXTI_PR_PIF3_Pos (3U) |
| #define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */ |
| #define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */ |
| #define EXTI_PR_PIF4_Pos (4U) |
| #define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */ |
| #define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */ |
| #define EXTI_PR_PIF5_Pos (5U) |
| #define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */ |
| #define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */ |
| #define EXTI_PR_PIF6_Pos (6U) |
| #define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */ |
| #define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */ |
| #define EXTI_PR_PIF7_Pos (7U) |
| #define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */ |
| #define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */ |
| #define EXTI_PR_PIF8_Pos (8U) |
| #define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */ |
| #define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */ |
| #define EXTI_PR_PIF9_Pos (9U) |
| #define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */ |
| #define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */ |
| #define EXTI_PR_PIF10_Pos (10U) |
| #define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */ |
| #define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */ |
| #define EXTI_PR_PIF11_Pos (11U) |
| #define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */ |
| #define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */ |
| #define EXTI_PR_PIF12_Pos (12U) |
| #define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */ |
| #define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */ |
| #define EXTI_PR_PIF13_Pos (13U) |
| #define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */ |
| #define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */ |
| #define EXTI_PR_PIF14_Pos (14U) |
| #define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */ |
| #define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */ |
| #define EXTI_PR_PIF15_Pos (15U) |
| #define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */ |
| #define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */ |
| #define EXTI_PR_PIF16_Pos (16U) |
| #define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */ |
| #define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */ |
| #define EXTI_PR_PIF17_Pos (17U) |
| #define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */ |
| #define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */ |
| #define EXTI_PR_PIF19_Pos (19U) |
| #define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */ |
| #define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */ |
| #define EXTI_PR_PIF20_Pos (20U) |
| #define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */ |
| #define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */ |
| #define EXTI_PR_PIF21_Pos (21U) |
| #define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */ |
| #define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */ |
| #define EXTI_PR_PIF22_Pos (22U) |
| #define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */ |
| #define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */ |
| |
| /* Legacy defines */ |
| #define EXTI_PR_PR0 EXTI_PR_PIF0 |
| #define EXTI_PR_PR1 EXTI_PR_PIF1 |
| #define EXTI_PR_PR2 EXTI_PR_PIF2 |
| #define EXTI_PR_PR3 EXTI_PR_PIF3 |
| #define EXTI_PR_PR4 EXTI_PR_PIF4 |
| #define EXTI_PR_PR5 EXTI_PR_PIF5 |
| #define EXTI_PR_PR6 EXTI_PR_PIF6 |
| #define EXTI_PR_PR7 EXTI_PR_PIF7 |
| #define EXTI_PR_PR8 EXTI_PR_PIF8 |
| #define EXTI_PR_PR9 EXTI_PR_PIF9 |
| #define EXTI_PR_PR10 EXTI_PR_PIF10 |
| #define EXTI_PR_PR11 EXTI_PR_PIF11 |
| #define EXTI_PR_PR12 EXTI_PR_PIF12 |
| #define EXTI_PR_PR13 EXTI_PR_PIF13 |
| #define EXTI_PR_PR14 EXTI_PR_PIF14 |
| #define EXTI_PR_PR15 EXTI_PR_PIF15 |
| #define EXTI_PR_PR16 EXTI_PR_PIF16 |
| #define EXTI_PR_PR17 EXTI_PR_PIF17 |
| #define EXTI_PR_PR19 EXTI_PR_PIF19 |
| #define EXTI_PR_PR20 EXTI_PR_PIF20 |
| #define EXTI_PR_PR21 EXTI_PR_PIF21 |
| #define EXTI_PR_PR22 EXTI_PR_PIF22 |
| |
| /******************************************************************************/ |
| /* */ |
| /* FLASH and Option Bytes Registers */ |
| /* */ |
| /******************************************************************************/ |
| |
| /******************* Bit definition for FLASH_ACR register ******************/ |
| #define FLASH_ACR_LATENCY_Pos (0U) |
| #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
| #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ |
| #define FLASH_ACR_PRFTEN_Pos (1U) |
| #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ |
| #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ |
| #define FLASH_ACR_SLEEP_PD_Pos (3U) |
| #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ |
| #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ |
| #define FLASH_ACR_RUN_PD_Pos (4U) |
| #define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ |
| #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ |
| #define FLASH_ACR_DISAB_BUF_Pos (5U) |
| #define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */ |
| #define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */ |
| #define FLASH_ACR_PRE_READ_Pos (6U) |
| #define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */ |
| #define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */ |
| |
| /******************* Bit definition for FLASH_PECR register ******************/ |
| #define FLASH_PECR_PELOCK_Pos (0U) |
| #define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ |
| #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ |
| #define FLASH_PECR_PRGLOCK_Pos (1U) |
| #define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ |
| #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ |
| #define FLASH_PECR_OPTLOCK_Pos (2U) |
| #define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ |
| #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ |
| #define FLASH_PECR_PROG_Pos (3U) |
| #define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ |
| #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ |
| #define FLASH_PECR_DATA_Pos (4U) |
| #define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ |
| #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ |
| #define FLASH_PECR_FIX_Pos (8U) |
| #define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */ |
| #define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ |
| #define FLASH_PECR_ERASE_Pos (9U) |
| #define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ |
| #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ |
| #define FLASH_PECR_FPRG_Pos (10U) |
| #define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ |
| #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ |
| #define FLASH_PECR_EOPIE_Pos (16U) |
| #define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ |
| #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ |
| #define FLASH_PECR_ERRIE_Pos (17U) |
| #define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ |
| #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ |
| #define FLASH_PECR_OBL_LAUNCH_Pos (18U) |
| #define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ |
| #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ |
| #define FLASH_PECR_HALF_ARRAY_Pos (19U) |
| #define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */ |
| #define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */ |
| |
| /****************** Bit definition for FLASH_PDKEYR register ******************/ |
| #define FLASH_PDKEYR_PDKEYR_Pos (0U) |
| #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ |
| #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ |
| |
| /****************** Bit definition for FLASH_PEKEYR register ******************/ |
| #define FLASH_PEKEYR_PEKEYR_Pos (0U) |
| #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ |
| #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ |
| |
| /****************** Bit definition for FLASH_PRGKEYR register ******************/ |
| #define FLASH_PRGKEYR_PRGKEYR_Pos (0U) |
| #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ |
| #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ |
| |
| /****************** Bit definition for FLASH_OPTKEYR register ******************/ |
| #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) |
| #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ |
| #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ |
| |
| /****************** Bit definition for FLASH_SR register *******************/ |
| #define FLASH_SR_BSY_Pos (0U) |
| #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ |
| #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ |
| #define FLASH_SR_EOP_Pos (1U) |
| #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ |
| #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ |
| #define FLASH_SR_HVOFF_Pos (2U) |
| #define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */ |
| #define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */ |
| #define FLASH_SR_READY_Pos (3U) |
| #define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */ |
| #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ |
| |
| #define FLASH_SR_WRPERR_Pos (8U) |
| #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ |
| #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ |
| #define FLASH_SR_PGAERR_Pos (9U) |
| #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ |
| #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ |
| #define FLASH_SR_SIZERR_Pos (10U) |
| #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ |
| #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ |
| #define FLASH_SR_OPTVERR_Pos (11U) |
| #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ |
| #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */ |
| #define FLASH_SR_RDERR_Pos (13U) |
| #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */ |
| #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */ |
| #define FLASH_SR_NOTZEROERR_Pos (16U) |
| #define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */ |
| #define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */ |
| #define FLASH_SR_FWWERR_Pos (17U) |
| #define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */ |
| #define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */ |
| |
| /* Legacy defines */ |
| #define FLASH_SR_FWWER FLASH_SR_FWWERR |
| #define FLASH_SR_ENHV FLASH_SR_HVOFF |
| #define FLASH_SR_ENDHV FLASH_SR_HVOFF |
| |
| /****************** Bit definition for FLASH_OPTR register *******************/ |
| #define FLASH_OPTR_RDPROT_Pos (0U) |
| #define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */ |
| #define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */ |
| #define FLASH_OPTR_WPRMOD_Pos (8U) |
| #define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */ |
| #define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */ |
| #define FLASH_OPTR_BOR_LEV_Pos (16U) |
| #define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */ |
| #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ |
| #define FLASH_OPTR_IWDG_SW_Pos (20U) |
| #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */ |
| #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */ |
| #define FLASH_OPTR_nRST_STOP_Pos (21U) |
| #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */ |
| #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ |
| #define FLASH_OPTR_nRST_STDBY_Pos (22U) |
| #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */ |
| #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ |
| #define FLASH_OPTR_USER_Pos (20U) |
| #define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */ |
| #define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */ |
| #define FLASH_OPTR_BOOT1_Pos (31U) |
| #define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */ |
| #define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */ |
| |
| /****************** Bit definition for FLASH_WRPR register ******************/ |
| #define FLASH_WRPR_WRP_Pos (0U) |
| #define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ |
| #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */ |
| |
| /******************************************************************************/ |
| /* */ |
| /* General Purpose IOs (GPIO) */ |
| /* */ |
| /******************************************************************************/ |
| /******************* Bit definition for GPIO_MODER register *****************/ |
| #define GPIO_MODER_MODE0_Pos (0U) |
| #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ |
| #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk |
| #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ |
| #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ |
| #define GPIO_MODER_MODE1_Pos (2U) |
| #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ |
| #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk |
| #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ |
| #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ |
| #define GPIO_MODER_MODE2_Pos (4U) |
| #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ |
| #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk |
| #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ |
| #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ |
| #define GPIO_MODER_MODE3_Pos (6U) |
| #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ |
| #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk |
| #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ |
| #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ |
| #define GPIO_MODER_MODE4_Pos (8U) |
| #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ |
| #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk |
| #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ |
| #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ |
| #define GPIO_MODER_MODE5_Pos (10U) |
| #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ |
| #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk |
| #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ |
| #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ |
| #define GPIO_MODER_MODE6_Pos (12U) |
| #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ |
| #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk |
| #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ |
| #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ |
| #define GPIO_MODER_MODE7_Pos (14U) |
| #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ |
| #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk |
| #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ |
| #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ |
| #define GPIO_MODER_MODE8_Pos (16U) |
| #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ |
| #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk |
| #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ |
| #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ |
| #define GPIO_MODER_MODE9_Pos (18U) |
| #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ |
| #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk |
| #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ |
| #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ |
| #define GPIO_MODER_MODE10_Pos (20U) |
| #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ |
| #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk |
| #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ |
| #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ |
| #define GPIO_MODER_MODE11_Pos (22U) |
| #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ |
| #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk |
| #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ |
| #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ |
| #define GPIO_MODER_MODE12_Pos (24U) |
| #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ |
| #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk |
| #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ |
| #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ |
| #define GPIO_MODER_MODE13_Pos (26U) |
| #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ |
| #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk |
| #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ |
| #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ |
| #define GPIO_MODER_MODE14_Pos (28U) |
| #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ |
| #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk |
| #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ |
| #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ |
| #define GPIO_MODER_MODE15_Pos (30U) |
| #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ |
| #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk |
| #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ |
| #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ |
| |
| /****************** Bit definition for GPIO_OTYPER register *****************/ |
| #define GPIO_OTYPER_OT_0 (0x00000001U) |
| #define GPIO_OTYPER_OT_1 (0x00000002U) |
| #define GPIO_OTYPER_OT_2 (0x00000004U) |
| #define GPIO_OTYPER_OT_3 (0x00000008U) |
| #define GPIO_OTYPER_OT_4 (0x00000010U) |
| #define GPIO_OTYPER_OT_5 (0x00000020U) |
| #define GPIO_OTYPER_OT_6 (0x00000040U) |
| #define GPIO_OTYPER_OT_7 (0x00000080U) |
| #define GPIO_OTYPER_OT_8 (0x00000100U) |
| #define GPIO_OTYPER_OT_9 (0x00000200U) |
| #define GPIO_OTYPER_OT_10 (0x00000400U) |
| #define GPIO_OTYPER_OT_11 (0x00000800U) |
| #define GPIO_OTYPER_OT_12 (0x00001000U) |
| #define GPIO_OTYPER_OT_13 (0x00002000U) |
| #define GPIO_OTYPER_OT_14 (0x00004000U) |
| #define GPIO_OTYPER_OT_15 (0x00008000U) |
| |
| /**************** Bit definition for GPIO_OSPEEDR register ******************/ |
| #define GPIO_OSPEEDER_OSPEED0_Pos (0U) |
| #define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ |
| #define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk |
| #define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ |
| #define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ |
| #define GPIO_OSPEEDER_OSPEED1_Pos (2U) |
| #define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ |
| #define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk |
| #define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ |
| #define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ |
| #define GPIO_OSPEEDER_OSPEED2_Pos (4U) |
| #define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ |
| #define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk |
| #define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ |
| #define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ |
| #define GPIO_OSPEEDER_OSPEED3_Pos (6U) |
| #define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ |
| #define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk |
| #define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ |
| #define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ |
| #define GPIO_OSPEEDER_OSPEED4_Pos (8U) |
| #define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ |
| #define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk |
| #define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ |
| #define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ |
| #define GPIO_OSPEEDER_OSPEED5_Pos (10U) |
| #define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ |
| #define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk |
| #define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ |
| #define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ |
| #define GPIO_OSPEEDER_OSPEED6_Pos (12U) |
| #define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ |
| #define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk |
| #define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ |
| #define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ |
| #define GPIO_OSPEEDER_OSPEED7_Pos (14U) |
| #define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ |
| #define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk |
| #define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ |
| #define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ |
| #define GPIO_OSPEEDER_OSPEED8_Pos (16U) |
| #define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ |
| #define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk |
| #define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ |
| #define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ |
| #define GPIO_OSPEEDER_OSPEED9_Pos (18U) |
| #define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ |
| #define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk |
| #define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ |
| #define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ |
| #define GPIO_OSPEEDER_OSPEED10_Pos (20U) |
| #define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ |
| #define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk |
| #define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ |
| #define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ |
| #define GPIO_OSPEEDER_OSPEED11_Pos (22U) |
| #define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ |
| #define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk |
| #define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ |
| #define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ |
| #define GPIO_OSPEEDER_OSPEED12_Pos (24U) |
| #define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ |
| #define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk |
| #define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ |
| #define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ |
| #define GPIO_OSPEEDER_OSPEED13_Pos (26U) |
| #define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ |
| #define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk |
| #define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ |
| #define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ |
| #define GPIO_OSPEEDER_OSPEED14_Pos (28U) |
| #define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ |
| #define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk |
| #define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ |
| #define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ |
| #define GPIO_OSPEEDER_OSPEED15_Pos (30U) |
| #define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ |
| #define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk |
| #define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ |
| #define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ |
| |
| /******************* Bit definition for GPIO_PUPDR register ******************/ |
| #define GPIO_PUPDR_PUPD0_Pos (0U) |
| #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ |
| #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk |
| #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ |
| #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ |
| #define GPIO_PUPDR_PUPD1_Pos (2U) |
| #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ |
| #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk |
| #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ |
| #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ |
| #define GPIO_PUPDR_PUPD2_Pos (4U) |
| #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ |
| #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk |
| #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ |
| #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ |
| #define GPIO_PUPDR_PUPD3_Pos (6U) |
| #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ |
| #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk |
| #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ |
| #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ |
| #define GPIO_PUPDR_PUPD4_Pos (8U) |
| #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ |
| #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk |
| #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ |
| #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ |
| #define GPIO_PUPDR_PUPD5_Pos (10U) |
| #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ |
| #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk |
| #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ |
| #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ |
| #define GPIO_PUPDR_PUPD6_Pos (12U) |
| #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ |
| #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk |
| #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ |
| #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ |
| #define GPIO_PUPDR_PUPD7_Pos (14U) |
| #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ |
| #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk |
| #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ |
| #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ |
| #define GPIO_PUPDR_PUPD8_Pos (16U) |
| #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ |
| #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk |
| #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ |
| #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ |
| #define GPIO_PUPDR_PUPD9_Pos (18U) |
| #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ |
| #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk |
| #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ |
| #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ |
| #define GPIO_PUPDR_PUPD10_Pos (20U) |
| #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ |
| #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk |
| #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ |
| #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ |
| #define GPIO_PUPDR_PUPD11_Pos (22U) |
| #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ |
| #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk |
| #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ |
| #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ |
| #define GPIO_PUPDR_PUPD12_Pos (24U) |
| #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ |
| #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk |
| #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ |
| #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ |
| #define GPIO_PUPDR_PUPD13_Pos (26U) |
| #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ |
| #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk |
| #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ |
| #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ |
| #define GPIO_PUPDR_PUPD14_Pos (28U) |
| #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ |
| #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk |
| #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ |
| #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ |
| #define GPIO_PUPDR_PUPD15_Pos (30U) |
| #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ |
| #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk |
| #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ |
| #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ |
| |
| /******************* Bit definition for GPIO_IDR register *******************/ |
| #define GPIO_IDR_ID0_Pos (0U) |
| #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ |
| #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk |
| #define GPIO_IDR_ID1_Pos (1U) |
| #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ |
| #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk |
| #define GPIO_IDR_ID2_Pos (2U) |
| #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ |
| #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk |
| #define GPIO_IDR_ID3_Pos (3U) |
| #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ |
| #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk |
| #define GPIO_IDR_ID4_Pos (4U) |
| #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ |
| #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk |
| #define GPIO_IDR_ID5_Pos (5U) |
| #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ |
| #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk |
| #define GPIO_IDR_ID6_Pos (6U) |
| #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ |
| #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk |
| #define GPIO_IDR_ID7_Pos (7U) |
| #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ |
| #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk |
| #define GPIO_IDR_ID8_Pos (8U) |
| #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ |
| #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk |
| #define GPIO_IDR_ID9_Pos (9U) |
| #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ |
| #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk |
| #define GPIO_IDR_ID10_Pos (10U) |
| #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ |
| #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk |
| #define GPIO_IDR_ID11_Pos (11U) |
| #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ |
| #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk |
| #define GPIO_IDR_ID12_Pos (12U) |
| #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ |
| #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk |
| #define GPIO_IDR_ID13_Pos (13U) |
| #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ |
| #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk |
| #define GPIO_IDR_ID14_Pos (14U) |
| #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ |
| #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk |
| #define GPIO_IDR_ID15_Pos (15U) |
| #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ |
| #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk |
| |
| /****************** Bit definition for GPIO_ODR register ********************/ |
| #define GPIO_ODR_OD0_Pos (0U) |
| #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ |
| #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk |
| #define GPIO_ODR_OD1_Pos (1U) |
| #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ |
| #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk |
| #define GPIO_ODR_OD2_Pos (2U) |
| #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ |
| #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk |
| #define GPIO_ODR_OD3_Pos (3U) |
| #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ |
| #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk |
| #define GPIO_ODR_OD4_Pos (4U) |
| #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ |
| #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk |
| #define GPIO_ODR_OD5_Pos (5U) |
| #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ |
| #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk |
| #define GPIO_ODR_OD6_Pos (6U) |
| #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ |
| #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk |
| #define GPIO_ODR_OD7_Pos (7U) |
| #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ |
| #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk |
| #define GPIO_ODR_OD8_Pos (8U) |
| #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ |
| #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk |
| #define GPIO_ODR_OD9_Pos (9U) |
| #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ |
| #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk |
| #define GPIO_ODR_OD10_Pos (10U) |
| #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ |
| #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk |
| #define GPIO_ODR_OD11_Pos (11U) |
| #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ |
| #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk |
| #define GPIO_ODR_OD12_Pos (12U) |
| #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ |
| #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk |
| #define GPIO_ODR_OD13_Pos (13U) |
| #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ |
| #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk |
| #define GPIO_ODR_OD14_Pos (14U) |
| #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ |
| #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk |
| #define GPIO_ODR_OD15_Pos (15U) |
| #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ |
| #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk |
| |
| /****************** Bit definition for GPIO_BSRR register ********************/ |
| #define GPIO_BSRR_BS_0 (0x00000001U) |
| #define GPIO_BSRR_BS_1 (0x00000002U) |
| #define GPIO_BSRR_BS_2 (0x00000004U) |
| #define GPIO_BSRR_BS_3 (0x00000008U) |
| #define GPIO_BSRR_BS_4 (0x00000010U) |
| #define GPIO_BSRR_BS_5 (0x00000020U) |
| #define GPIO_BSRR_BS_6 (0x00000040U) |
| #define GPIO_BSRR_BS_7 (0x00000080U) |
| #define GPIO_BSRR_BS_8 (0x00000100U) |
| #define GPIO_BSRR_BS_9 (0x00000200U) |
| #define GPIO_BSRR_BS_10 (0x00000400U) |
| #define GPIO_BSRR_BS_11 (0x00000800U) |
| #define GPIO_BSRR_BS_12 (0x00001000U) |
| #define GPIO_BSRR_BS_13 (0x00002000U) |
| #define GPIO_BSRR_BS_14 (0x00004000U) |
| #define GPIO_BSRR_BS_15 (0x00008000U) |
| #define GPIO_BSRR_BR_0 (0x00010000U) |
| #define GPIO_BSRR_BR_1 (0x00020000U) |
| #define GPIO_BSRR_BR_2 (0x00040000U) |
| #define GPIO_BSRR_BR_3 (0x00080000U) |
| #define GPIO_BSRR_BR_4 (0x00100000U) |
| #define GPIO_BSRR_BR_5 (0x00200000U) |
| #define GPIO_BSRR_BR_6 (0x00400000U) |
| #define GPIO_BSRR_BR_7 (0x00800000U) |
| #define GPIO_BSRR_BR_8 (0x01000000U) |
| #define GPIO_BSRR_BR_9 (0x02000000U) |
| #define GPIO_BSRR_BR_10 (0x04000000U) |
| #define GPIO_BSRR_BR_11 (0x08000000U) |
| #define GPIO_BSRR_BR_12 (0x10000000U) |
| #define GPIO_BSRR_BR_13 (0x20000000U) |
| #define GPIO_BSRR_BR_14 (0x40000000U) |
| #define GPIO_BSRR_BR_15 (0x80000000U) |
| |
| /****************** Bit definition for GPIO_LCKR register ********************/ |
| #define GPIO_LCKR_LCK0_Pos (0U) |
| #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ |
| #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk |
| #define GPIO_LCKR_LCK1_Pos (1U) |
| #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ |
| #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk |
| #define GPIO_LCKR_LCK2_Pos (2U) |
| #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ |
| #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk |
| #define GPIO_LCKR_LCK3_Pos (3U) |
| #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ |
| #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk |
| #define GPIO_LCKR_LCK4_Pos (4U) |
| #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ |
| #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk |
| #define GPIO_LCKR_LCK5_Pos (5U) |
| #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ |
| #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk |
| #define GPIO_LCKR_LCK6_Pos (6U) |
| #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ |
| #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk |
| #define GPIO_LCKR_LCK7_Pos (7U) |
| #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ |
| #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk |
| #define GPIO_LCKR_LCK8_Pos (8U) |
| #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ |
| #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk |
| #define GPIO_LCKR_LCK9_Pos (9U) |
| #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ |
| #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk |
| #define GPIO_LCKR_LCK10_Pos (10U) |
| #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ |
| #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk |
| #define GPIO_LCKR_LCK11_Pos (11U) |
| #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ |
| #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk |
| #define GPIO_LCKR_LCK12_Pos (12U) |
| #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ |
| #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk |
| #define GPIO_LCKR_LCK13_Pos (13U) |
| #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ |
| #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk |
| #define GPIO_LCKR_LCK14_Pos (14U) |
| #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ |
| #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk |
| #define GPIO_LCKR_LCK15_Pos (15U) |
| #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ |
| #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk |
| #define GPIO_LCKR_LCKK_Pos (16U) |
| #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ |
| #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk |
| |
| /****************** Bit definition for GPIO_AFRL register ********************/ |
| #define GPIO_AFRL_AFSEL0_Pos (0U) |
| #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ |
| #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk |
| #define GPIO_AFRL_AFSEL1_Pos (4U) |
| #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ |
| #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk |
| #define GPIO_AFRL_AFSEL2_Pos (8U) |
| #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ |
| #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk |
| #define GPIO_AFRL_AFSEL3_Pos (12U) |
| #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ |
| #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk |
| #define GPIO_AFRL_AFSEL4_Pos (16U) |
| #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ |
| #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk |
| #define GPIO_AFRL_AFSEL5_Pos (20U) |
| #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ |
| #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk |
| #define GPIO_AFRL_AFSEL6_Pos (24U) |
| #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ |
| #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
| #define GPIO_AFRL_AFSEL7_Pos (28U) |
| #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
| #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
| |
| /****************** Bit definition for GPIO_AFRH register ********************/ |
| #define GPIO_AFRH_AFSEL8_Pos (0U) |
| #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ |
| #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk |
| #define GPIO_AFRH_AFSEL9_Pos (4U) |
| #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ |
| #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk |
| #define GPIO_AFRH_AFSEL10_Pos (8U) |
| #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ |
| #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk |
| #define GPIO_AFRH_AFSEL11_Pos (12U) |
| #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ |
| #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk |
| #define GPIO_AFRH_AFSEL12_Pos (16U) |
| #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ |
| #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk |
| #define GPIO_AFRH_AFSEL13_Pos (20U) |
| #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ |
| #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk |
| #define GPIO_AFRH_AFSEL14_Pos (24U) |
| #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ |
| #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk |
| #define GPIO_AFRH_AFSEL15_Pos (28U) |
| #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ |
| #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk |
| |
| /****************** Bit definition for GPIO_BRR register *********************/ |
| #define GPIO_BRR_BR_0 (0x00000001U) |
| #define GPIO_BRR_BR_1 (0x00000002U) |
| #define GPIO_BRR_BR_2 (0x00000004U) |
| #define GPIO_BRR_BR_3 (0x00000008U) |
| #define GPIO_BRR_BR_4 (0x00000010U) |
| #define GPIO_BRR_BR_5 (0x00000020U) |
| #define GPIO_BRR_BR_6 (0x00000040U) |
| #define GPIO_BRR_BR_7 (0x00000080U) |
| #define GPIO_BRR_BR_8 (0x00000100U) |
| #define GPIO_BRR_BR_9 (0x00000200U) |
| #define GPIO_BRR_BR_10 (0x00000400U) |
| #define GPIO_BRR_BR_11 (0x00000800U) |
| #define GPIO_BRR_BR_12 (0x00001000U) |
| #define GPIO_BRR_BR_13 (0x00002000U) |
| #define GPIO_BRR_BR_14 (0x00004000U) |
| #define GPIO_BRR_BR_15 (0x00008000U) |
| |
| /******************************************************************************/ |
| /* */ |
| /* Inter-integrated Circuit Interface (I2C) */ |
| /* */ |
| /******************************************************************************/ |
| |
| /******************* Bit definition for I2C_CR1 register *******************/ |
| #define I2C_CR1_PE_Pos (0U) |
| #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ |
| #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ |
| #define I2C_CR1_TXIE_Pos (1U) |
| #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ |
| #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ |
| #define I2C_CR1_RXIE_Pos (2U) |
| #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ |
| #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ |
| #define I2C_CR1_ADDRIE_Pos (3U) |
| #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ |
| #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ |
| #define I2C_CR1_NACKIE_Pos (4U) |
| #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ |
| #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ |
| #define I2C_CR1_STOPIE_Pos (5U) |
| #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ |
| #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ |
| #define I2C_CR1_TCIE_Pos (6U) |
| #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ |
| #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ |
| #define I2C_CR1_ERRIE_Pos (7U) |
| #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ |
| #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ |
| #define I2C_CR1_DNF_Pos (8U) |
| #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ |
| #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ |
| #define I2C_CR1_ANFOFF_Pos (12U) |
| #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ |
| #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ |
| #define I2C_CR1_TXDMAEN_Pos (14U) |
| #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ |
| #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ |
| #define I2C_CR1_RXDMAEN_Pos (15U) |
| #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ |
| #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ |
| #define I2C_CR1_SBC_Pos (16U) |
| #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ |
| #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ |
| #define I2C_CR1_NOSTRETCH_Pos (17U) |
| #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ |
| #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ |
| #define I2C_CR1_WUPEN_Pos (18U) |
| #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ |
| #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ |
| #define I2C_CR1_GCEN_Pos (19U) |
| #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ |
| #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ |
| #define I2C_CR1_SMBHEN_Pos (20U) |
| #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ |
| #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ |
| #define I2C_CR1_SMBDEN_Pos (21U) |
| #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ |
| #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ |
| #define I2C_CR1_ALERTEN_Pos (22U) |
| #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ |
| #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ |
| #define I2C_CR1_PECEN_Pos (23U) |
| #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ |
| #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ |
| |
| /****************** Bit definition for I2C_CR2 register ********************/ |
| #define I2C_CR2_SADD_Pos (0U) |
| #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ |
| #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ |
| #define I2C_CR2_RD_WRN_Pos (10U) |
| #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ |
| #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ |
| #define I2C_CR2_ADD10_Pos (11U) |
| #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ |
| #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ |
| #define I2C_CR2_HEAD10R_Pos (12U) |
| #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ |
| #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ |
| #define I2C_CR2_START_Pos (13U) |
| #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ |
| #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ |
| #define I2C_CR2_STOP_Pos (14U) |
| #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ |
| #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ |
| #define I2C_CR2_NACK_Pos (15U) |
| #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ |
| #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ |
| #define I2C_CR2_NBYTES_Pos (16U) |
| #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ |
| #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ |
| #define I2C_CR2_RELOAD_Pos (24U) |
| #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ |
| #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ |
| #define I2C_CR2_AUTOEND_Pos (25U) |
| #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ |
| #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ |
| #define I2C_CR2_PECBYTE_Pos (26U) |
| #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ |
| #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ |
| |
| /******************* Bit definition for I2C_OAR1 register ******************/ |
| #define I2C_OAR1_OA1_Pos (0U) |
| #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ |
| #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ |
| #define I2C_OAR1_OA1MODE_Pos (10U) |
| #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ |
| #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ |
| #define I2C_OAR1_OA1EN_Pos (15U) |
| #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ |
| #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ |
| |
| /******************* Bit definition for I2C_OAR2 register ******************/ |
| #define I2C_OAR2_OA2_Pos (1U) |
| #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ |
| #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ |
| #define I2C_OAR2_OA2MSK_Pos (8U) |
| #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ |
| #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ |
| #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ |
| #define I2C_OAR2_OA2MASK01_Pos (8U) |
| #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ |
| #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ |
| #define I2C_OAR2_OA2MASK02_Pos (9U) |
| #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ |
| #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ |
| #define I2C_OAR2_OA2MASK03_Pos (8U) |
| #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ |
| #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ |
| #define I2C_OAR2_OA2MASK04_Pos (10U) |
| #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ |
| #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ |
| #define I2C_OAR2_OA2MASK05_Pos (8U) |
| #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ |
| #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ |
| #define I2C_OAR2_OA2MASK06_Pos (9U) |
| #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ |
| #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ |
| #define I2C_OAR2_OA2MASK07_Pos (8U) |
| #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ |
| #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ |
| #define I2C_OAR2_OA2EN_Pos (15U) |
| #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ |
| #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ |
| |
| /******************* Bit definition for I2C_TIMINGR register *******************/ |
| #define I2C_TIMINGR_SCLL_Pos (0U) |
| #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ |
| #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ |
| #define I2C_TIMINGR_SCLH_Pos (8U) |
| #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ |
| #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ |
| #define I2C_TIMINGR_SDADEL_Pos (16U) |
| #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ |
| #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ |
| #define I2C_TIMINGR_SCLDEL_Pos (20U) |
| #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ |
| #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ |
| #define I2C_TIMINGR_PRESC_Pos (28U) |
| #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ |
| #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ |
| |
| /******************* Bit definition for I2C_TIMEOUTR register *******************/ |
| #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) |
| #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ |
| #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ |
| #define I2C_TIMEOUTR_TIDLE_Pos (12U) |
| #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ |
| #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ |
| #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) |
| #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ |
| #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ |
| #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) |
| #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ |
| #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ |
| #define I2C_TIMEOUTR_TEXTEN_Pos (31U) |
| #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ |
| #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ |
| |
| /****************** Bit definition for I2C_ISR register *********************/ |
| #define I2C_ISR_TXE_Pos (0U) |
| #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ |
| #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ |
|
