| ;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** |
| ;* File Name : startup_stm32l021xx.s |
| ;* Author : MCD Application Team |
| ;* Description : STM32l021xx Devices vector table for MDK-ARM toolchain. |
| ;* This module performs: |
| ;* - Set the initial SP |
| ;* - Set the initial PC == Reset_Handler |
| ;* - Set the vector table entries with the exceptions ISR address |
| ;* - Branches to __main in the C library (which eventually |
| ;* calls main()). |
| ;* After Reset the Cortex-M0+ processor is in Thread mode, |
| ;* priority is Privileged, and the Stack is set to Main. |
| ;******************************************************************************* |
| ;* |
| ;* Redistribution and use in source and binary forms, with or without modification, |
| ;* are permitted provided that the following conditions are met: |
| ;* 1. Redistributions of source code must retain the above copyright notice, |
| ;* this list of conditions and the following disclaimer. |
| ;* 2. Redistributions in binary form must reproduce the above copyright notice, |
| ;* this list of conditions and the following disclaimer in the documentation |
| ;* and/or other materials provided with the distribution. |
| ;* 3. Neither the name of STMicroelectronics nor the names of its contributors |
| ;* may be used to endorse or promote products derived from this software |
| ;* without specific prior written permission. |
| ;* |
| ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| ;* |
| ;******************************************************************************* |
| ; |
| ; Amount of memory (in bytes) allocated for Stack |
| ; Tailor this value to your application needs |
| ; <h> Stack Configuration |
| ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> |
| ; </h> |
| |
| Stack_Size EQU 0x400 |
| |
| AREA STACK, NOINIT, READWRITE, ALIGN=3 |
| Stack_Mem SPACE Stack_Size |
| __initial_sp |
| |
| |
| ; <h> Heap Configuration |
| ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> |
| ; </h> |
| |
| Heap_Size EQU 0x200 |
| |
| AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
| __heap_base |
| Heap_Mem SPACE Heap_Size |
| __heap_limit |
| |
| PRESERVE8 |
| THUMB |
| |
| |
| ; Vector Table Mapped to Address 0 at Reset |
| AREA RESET, DATA, READONLY |
| EXPORT __Vectors |
| EXPORT __Vectors_End |
| EXPORT __Vectors_Size |
| |
| __Vectors DCD __initial_sp ; Top of Stack |
| DCD Reset_Handler ; Reset Handler |
| DCD NMI_Handler ; NMI Handler |
| DCD HardFault_Handler ; Hard Fault Handler |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD SVC_Handler ; SVCall Handler |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD PendSV_Handler ; PendSV Handler |
| DCD SysTick_Handler ; SysTick Handler |
| |
| ; External Interrupts |
| DCD WWDG_IRQHandler ; Window Watchdog |
| DCD PVD_IRQHandler ; PVD through EXTI Line detect |
| DCD RTC_IRQHandler ; RTC through EXTI Line |
| DCD FLASH_IRQHandler ; FLASH |
| DCD RCC_IRQHandler ; RCC |
| DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 |
| DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 |
| DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 |
| DCD 0 ; Reserved |
| DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 |
| DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 |
| DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 |
| DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 |
| DCD LPTIM1_IRQHandler ; LPTIM1 |
| DCD 0 ; Reserved |
| DCD TIM2_IRQHandler ; TIM2 |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD TIM21_IRQHandler ; TIM21 |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD I2C1_IRQHandler ; I2C1 |
| DCD 0 ; Reserved |
| DCD SPI1_IRQHandler ; SPI1 |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD USART2_IRQHandler ; USART2 |
| DCD AES_LPUART1_IRQHandler ; LPUART1 |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| |
| __Vectors_End |
| |
| __Vectors_Size EQU __Vectors_End - __Vectors |
| |
| AREA |.text|, CODE, READONLY |
| |
| ; Reset handler routine |
| Reset_Handler PROC |
| EXPORT Reset_Handler [WEAK] |
| IMPORT __main |
| IMPORT SystemInit |
| |
| LDR R0, =__initial_sp ; set stack pointer |
| MSR MSP, R0 |
| |
| ;;Check if boot space corresponds to system memory |
| |
| LDR R0,=0x00000004 |
| LDR R1, [R0] |
| LSRS R1, R1, #24 |
| LDR R2,=0x1F |
| CMP R1, R2 |
| |
| BNE ApplicationStart |
| |
| ;; SYSCFG clock enable |
| |
| LDR R0,=0x40021034 |
| LDR R1,=0x00000001 |
| STR R1, [R0] |
| |
| ;; Set CFGR1 register with flash memory remap at address 0 |
| |
| LDR R0,=0x40010000 |
| LDR R1,=0x00000000 |
| STR R1, [R0] |
| |
| ApplicationStart |
| LDR R0, =SystemInit |
| BLX R0 |
| LDR R0, =__main |
| BX R0 |
| ENDP |
| |
| ; Dummy Exception Handlers (infinite loops which can be modified) |
| |
| NMI_Handler PROC |
| EXPORT NMI_Handler [WEAK] |
| B . |
| ENDP |
| HardFault_Handler\ |
| PROC |
| EXPORT HardFault_Handler [WEAK] |
| B . |
| ENDP |
| SVC_Handler PROC |
| EXPORT SVC_Handler [WEAK] |
| B . |
| ENDP |
| PendSV_Handler PROC |
| EXPORT PendSV_Handler [WEAK] |
| B . |
| ENDP |
| SysTick_Handler PROC |
| EXPORT SysTick_Handler [WEAK] |
| B . |
| ENDP |
| |
| Default_Handler PROC |
| |
| EXPORT WWDG_IRQHandler [WEAK] |
| EXPORT PVD_IRQHandler [WEAK] |
| EXPORT RTC_IRQHandler [WEAK] |
| EXPORT FLASH_IRQHandler [WEAK] |
| EXPORT RCC_IRQHandler [WEAK] |
| EXPORT EXTI0_1_IRQHandler [WEAK] |
| EXPORT EXTI2_3_IRQHandler [WEAK] |
| EXPORT EXTI4_15_IRQHandler [WEAK] |
| EXPORT DMA1_Channel1_IRQHandler [WEAK] |
| EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
| EXPORT DMA1_Channel4_5_IRQHandler [WEAK] |
| EXPORT ADC1_COMP_IRQHandler [WEAK] |
| EXPORT LPTIM1_IRQHandler [WEAK] |
| EXPORT TIM2_IRQHandler [WEAK] |
| EXPORT TIM21_IRQHandler [WEAK] |
| EXPORT I2C1_IRQHandler [WEAK] |
| EXPORT SPI1_IRQHandler [WEAK] |
| EXPORT USART2_IRQHandler [WEAK] |
| EXPORT AES_LPUART1_IRQHandler [WEAK] |
| |
| WWDG_IRQHandler |
| PVD_IRQHandler |
| RTC_IRQHandler |
| FLASH_IRQHandler |
| RCC_IRQHandler |
| EXTI0_1_IRQHandler |
| EXTI2_3_IRQHandler |
| EXTI4_15_IRQHandler |
| DMA1_Channel1_IRQHandler |
| DMA1_Channel2_3_IRQHandler |
| DMA1_Channel4_5_IRQHandler |
| ADC1_COMP_IRQHandler |
| LPTIM1_IRQHandler |
| TIM2_IRQHandler |
| TIM21_IRQHandler |
| I2C1_IRQHandler |
| SPI1_IRQHandler |
| USART2_IRQHandler |
| AES_LPUART1_IRQHandler |
| |
| B . |
| |
| ENDP |
| |
| ALIGN |
| |
| ;******************************************************************************* |
| ; User Stack and Heap initialization |
| ;******************************************************************************* |
| IF :DEF:__MICROLIB |
| |
| EXPORT __initial_sp |
| EXPORT __heap_base |
| EXPORT __heap_limit |
| |
| ELSE |
| |
| IMPORT __use_two_region_memory |
| EXPORT __user_initial_stackheap |
| |
| __user_initial_stackheap |
| |
| LDR R0, = Heap_Mem |
| LDR R1, =(Stack_Mem + Stack_Size) |
| LDR R2, = (Heap_Mem + Heap_Size) |
| LDR R3, = Stack_Mem |
| BX LR |
| |
| ALIGN |
| |
| ENDIF |
| |
| END |
| |
| ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** |
