Release v2.3.1
diff --git a/Include/stm32l100xb.h b/Include/stm32l100xb.h index 04beda8..13f0d6b 100644 --- a/Include/stm32l100xb.h +++ b/Include/stm32l100xb.h
@@ -722,6 +722,8 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF80078 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +/* No Internal temperature sensor embedded with STM32L100 devices */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -7399,443 +7401,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -7964,10 +7529,10 @@ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l100xba.h b/Include/stm32l100xba.h index 800e51d..0bc4056 100644 --- a/Include/stm32l100xba.h +++ b/Include/stm32l100xba.h
@@ -722,6 +722,8 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF80078 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +/* No Internal temperature sensor embedded with STM32L100 devices */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -7547,443 +7549,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -8112,10 +7677,10 @@ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l100xc.h b/Include/stm32l100xc.h index f4acb2e..e3f0193 100644 --- a/Include/stm32l100xc.h +++ b/Include/stm32l100xc.h
@@ -323,7 +323,6 @@ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** @@ -765,6 +764,8 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +/* No Internal temperature sensor embedded with STM32L100 devices */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -3461,24 +3462,6 @@ #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -/****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 (0x00000001U) -#define GPIO_BRR_BR_1 (0x00000002U) -#define GPIO_BRR_BR_2 (0x00000004U) -#define GPIO_BRR_BR_3 (0x00000008U) -#define GPIO_BRR_BR_4 (0x00000010U) -#define GPIO_BRR_BR_5 (0x00000020U) -#define GPIO_BRR_BR_6 (0x00000040U) -#define GPIO_BRR_BR_7 (0x00000080U) -#define GPIO_BRR_BR_8 (0x00000100U) -#define GPIO_BRR_BR_9 (0x00000200U) -#define GPIO_BRR_BR_10 (0x00000400U) -#define GPIO_BRR_BR_11 (0x00000800U) -#define GPIO_BRR_BR_12 (0x00001000U) -#define GPIO_BRR_BR_13 (0x00002000U) -#define GPIO_BRR_BR_14 (0x00004000U) -#define GPIO_BRR_BR_15 (0x00008000U) - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface (I2C) */ @@ -8119,443 +8102,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -8693,10 +8239,10 @@ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l151xb.h b/Include/stm32l151xb.h index 41a3dc4..7c93776 100644 --- a/Include/stm32l151xb.h +++ b/Include/stm32l151xb.h
@@ -722,6 +722,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF80078 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF8007A /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF8007E /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -7350,443 +7353,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -7916,10 +7482,10 @@ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l151xba.h b/Include/stm32l151xba.h index b339f01..dbb04af 100644 --- a/Include/stm32l151xba.h +++ b/Include/stm32l151xba.h
@@ -722,6 +722,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF80078 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF8007A /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF8007E /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -7426,443 +7429,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -7992,10 +7558,10 @@ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l151xc.h b/Include/stm32l151xc.h index 5d985c4..9b61674 100644 --- a/Include/stm32l151xc.h +++ b/Include/stm32l151xc.h
@@ -339,7 +339,6 @@ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** @@ -801,6 +800,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -3608,24 +3610,6 @@ #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -/****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 (0x00000001U) -#define GPIO_BRR_BR_1 (0x00000002U) -#define GPIO_BRR_BR_2 (0x00000004U) -#define GPIO_BRR_BR_3 (0x00000008U) -#define GPIO_BRR_BR_4 (0x00000010U) -#define GPIO_BRR_BR_5 (0x00000020U) -#define GPIO_BRR_BR_6 (0x00000040U) -#define GPIO_BRR_BR_7 (0x00000080U) -#define GPIO_BRR_BR_8 (0x00000100U) -#define GPIO_BRR_BR_9 (0x00000200U) -#define GPIO_BRR_BR_10 (0x00000400U) -#define GPIO_BRR_BR_11 (0x00000800U) -#define GPIO_BRR_BR_12 (0x00001000U) -#define GPIO_BRR_BR_13 (0x00002000U) -#define GPIO_BRR_BR_14 (0x00004000U) -#define GPIO_BRR_BR_15 (0x00008000U) - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface (I2C) */ @@ -8286,443 +8270,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -8884,10 +8431,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l151xca.h b/Include/stm32l151xca.h index e8a28cf..8279679 100644 --- a/Include/stm32l151xca.h +++ b/Include/stm32l151xca.h
@@ -339,7 +339,6 @@ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** @@ -805,6 +804,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -3645,24 +3647,6 @@ #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -/****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 (0x00000001U) -#define GPIO_BRR_BR_1 (0x00000002U) -#define GPIO_BRR_BR_2 (0x00000004U) -#define GPIO_BRR_BR_3 (0x00000008U) -#define GPIO_BRR_BR_4 (0x00000010U) -#define GPIO_BRR_BR_5 (0x00000020U) -#define GPIO_BRR_BR_6 (0x00000040U) -#define GPIO_BRR_BR_7 (0x00000080U) -#define GPIO_BRR_BR_8 (0x00000100U) -#define GPIO_BRR_BR_9 (0x00000200U) -#define GPIO_BRR_BR_10 (0x00000400U) -#define GPIO_BRR_BR_11 (0x00000800U) -#define GPIO_BRR_BR_12 (0x00001000U) -#define GPIO_BRR_BR_13 (0x00002000U) -#define GPIO_BRR_BR_14 (0x00004000U) -#define GPIO_BRR_BR_15 (0x00008000U) - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface (I2C) */ @@ -8371,443 +8355,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -8971,10 +8518,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l151xd.h b/Include/stm32l151xd.h index 2b272a1..1074112 100644 --- a/Include/stm32l151xd.h +++ b/Include/stm32l151xd.h
@@ -877,6 +877,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -9045,443 +9048,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9649,10 +9215,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l151xdx.h b/Include/stm32l151xdx.h index ad2fbeb..f02fec7 100644 --- a/Include/stm32l151xdx.h +++ b/Include/stm32l151xdx.h
@@ -820,6 +820,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -8416,443 +8419,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9016,10 +8582,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l151xe.h b/Include/stm32l151xe.h index 338eb3f..58ece57 100644 --- a/Include/stm32l151xe.h +++ b/Include/stm32l151xe.h
@@ -820,6 +820,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -8416,443 +8419,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9016,10 +8582,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l152xb.h b/Include/stm32l152xb.h index e1de88f..d6be6bd 100644 --- a/Include/stm32l152xb.h +++ b/Include/stm32l152xb.h
@@ -739,6 +739,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF80078 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF8007A /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF8007E /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -7500,443 +7503,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -8066,10 +7632,10 @@ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l152xba.h b/Include/stm32l152xba.h index 63dfb84..e71cc6a 100644 --- a/Include/stm32l152xba.h +++ b/Include/stm32l152xba.h
@@ -724,6 +724,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF80078 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF8007A /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF8007E /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -7561,443 +7564,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -8127,10 +7693,10 @@ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l152xc.h b/Include/stm32l152xc.h index afbdb1c..85b034a 100644 --- a/Include/stm32l152xc.h +++ b/Include/stm32l152xc.h
@@ -340,7 +340,6 @@ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** @@ -818,6 +817,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -3625,24 +3627,6 @@ #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -/****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 (0x00000001U) -#define GPIO_BRR_BR_1 (0x00000002U) -#define GPIO_BRR_BR_2 (0x00000004U) -#define GPIO_BRR_BR_3 (0x00000008U) -#define GPIO_BRR_BR_4 (0x00000010U) -#define GPIO_BRR_BR_5 (0x00000020U) -#define GPIO_BRR_BR_6 (0x00000040U) -#define GPIO_BRR_BR_7 (0x00000080U) -#define GPIO_BRR_BR_8 (0x00000100U) -#define GPIO_BRR_BR_9 (0x00000200U) -#define GPIO_BRR_BR_10 (0x00000400U) -#define GPIO_BRR_BR_11 (0x00000800U) -#define GPIO_BRR_BR_12 (0x00001000U) -#define GPIO_BRR_BR_13 (0x00002000U) -#define GPIO_BRR_BR_14 (0x00004000U) -#define GPIO_BRR_BR_15 (0x00008000U) - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface (I2C) */ @@ -8436,443 +8420,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9034,10 +8581,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l152xca.h b/Include/stm32l152xca.h index e273912..4b1c460 100644 --- a/Include/stm32l152xca.h +++ b/Include/stm32l152xca.h
@@ -340,7 +340,6 @@ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** @@ -822,6 +821,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -3662,24 +3664,6 @@ #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -/****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 (0x00000001U) -#define GPIO_BRR_BR_1 (0x00000002U) -#define GPIO_BRR_BR_2 (0x00000004U) -#define GPIO_BRR_BR_3 (0x00000008U) -#define GPIO_BRR_BR_4 (0x00000010U) -#define GPIO_BRR_BR_5 (0x00000020U) -#define GPIO_BRR_BR_6 (0x00000040U) -#define GPIO_BRR_BR_7 (0x00000080U) -#define GPIO_BRR_BR_8 (0x00000100U) -#define GPIO_BRR_BR_9 (0x00000200U) -#define GPIO_BRR_BR_10 (0x00000400U) -#define GPIO_BRR_BR_11 (0x00000800U) -#define GPIO_BRR_BR_12 (0x00001000U) -#define GPIO_BRR_BR_13 (0x00002000U) -#define GPIO_BRR_BR_14 (0x00004000U) -#define GPIO_BRR_BR_15 (0x00008000U) - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface (I2C) */ @@ -8521,443 +8505,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9121,10 +8668,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l152xd.h b/Include/stm32l152xd.h index cba914f..4ab18c4 100644 --- a/Include/stm32l152xd.h +++ b/Include/stm32l152xd.h
@@ -894,6 +894,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -9195,443 +9198,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9799,10 +9365,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l152xdx.h b/Include/stm32l152xdx.h index b40c935..56ad742 100644 --- a/Include/stm32l152xdx.h +++ b/Include/stm32l152xdx.h
@@ -837,6 +837,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -8566,443 +8569,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9166,10 +8732,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l152xe.h b/Include/stm32l152xe.h index 7432d11..89f2e37 100644 --- a/Include/stm32l152xe.h +++ b/Include/stm32l152xe.h
@@ -837,6 +837,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -8566,443 +8569,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9166,10 +8732,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l162xc.h b/Include/stm32l162xc.h index ad9e650..524562b 100644 --- a/Include/stm32l162xc.h +++ b/Include/stm32l162xc.h
@@ -361,7 +361,6 @@ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** @@ -841,6 +840,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -3755,24 +3757,6 @@ #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -/****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 (0x00000001U) -#define GPIO_BRR_BR_1 (0x00000002U) -#define GPIO_BRR_BR_2 (0x00000004U) -#define GPIO_BRR_BR_3 (0x00000008U) -#define GPIO_BRR_BR_4 (0x00000010U) -#define GPIO_BRR_BR_5 (0x00000020U) -#define GPIO_BRR_BR_6 (0x00000040U) -#define GPIO_BRR_BR_7 (0x00000080U) -#define GPIO_BRR_BR_8 (0x00000100U) -#define GPIO_BRR_BR_9 (0x00000200U) -#define GPIO_BRR_BR_10 (0x00000400U) -#define GPIO_BRR_BR_11 (0x00000800U) -#define GPIO_BRR_BR_12 (0x00001000U) -#define GPIO_BRR_BR_13 (0x00002000U) -#define GPIO_BRR_BR_14 (0x00004000U) -#define GPIO_BRR_BR_15 (0x00008000U) - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface (I2C) */ @@ -8575,443 +8559,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9176,10 +8723,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l162xca.h b/Include/stm32l162xca.h index ae5c41f..9126134 100644 --- a/Include/stm32l162xca.h +++ b/Include/stm32l162xca.h
@@ -361,7 +361,6 @@ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** @@ -845,6 +844,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -3792,24 +3794,6 @@ #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk -/****************** Bit definition for GPIO_BRR register *********************/ -#define GPIO_BRR_BR_0 (0x00000001U) -#define GPIO_BRR_BR_1 (0x00000002U) -#define GPIO_BRR_BR_2 (0x00000004U) -#define GPIO_BRR_BR_3 (0x00000008U) -#define GPIO_BRR_BR_4 (0x00000010U) -#define GPIO_BRR_BR_5 (0x00000020U) -#define GPIO_BRR_BR_6 (0x00000040U) -#define GPIO_BRR_BR_7 (0x00000080U) -#define GPIO_BRR_BR_8 (0x00000100U) -#define GPIO_BRR_BR_9 (0x00000200U) -#define GPIO_BRR_BR_10 (0x00000400U) -#define GPIO_BRR_BR_11 (0x00000800U) -#define GPIO_BRR_BR_12 (0x00001000U) -#define GPIO_BRR_BR_13 (0x00002000U) -#define GPIO_BRR_BR_14 (0x00004000U) -#define GPIO_BRR_BR_15 (0x00008000U) - /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface (I2C) */ @@ -8660,443 +8644,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9263,10 +8810,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l162xd.h b/Include/stm32l162xd.h index 37bb05f..51c2fed 100644 --- a/Include/stm32l162xd.h +++ b/Include/stm32l162xd.h
@@ -917,6 +917,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -9334,443 +9337,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9941,10 +9507,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l162xdx.h b/Include/stm32l162xdx.h index 9f5f9a9..0ec12e8 100644 --- a/Include/stm32l162xdx.h +++ b/Include/stm32l162xdx.h
@@ -860,6 +860,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -8705,443 +8708,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9308,10 +8874,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l162xe.h b/Include/stm32l162xe.h index ec69dc5..95f56e1 100644 --- a/Include/stm32l162xe.h +++ b/Include/stm32l162xe.h
@@ -860,6 +860,9 @@ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) @@ -8705,443 +8708,6 @@ #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ -/******************************************************************************/ -/* */ -/* SystemTick (SysTick) */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller (NVIC) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFUL << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800UL << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000UL << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000UL << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFUL << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000UL << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFUL << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000UL << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFUL << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000UL << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFUL << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000UL << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ -#define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFUL << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFUL << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFUL << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFUL << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ -#define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFUL << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFUL << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ -/** - * @} - */ - /** * @} */ @@ -9308,10 +8874,10 @@ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM6) || \ + ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM9)) -#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) - #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \
diff --git a/Include/stm32l1xx.h b/Include/stm32l1xx.h index 762015c..4db5261 100644 --- a/Include/stm32l1xx.h +++ b/Include/stm32l1xx.h
@@ -100,11 +100,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number + * @brief CMSIS Device version number V2.3.1 */ -#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32L1xx_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\ |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
diff --git a/License.md b/License.md index 64783f9..e0d829b 100644 --- a/License.md +++ b/License.md
@@ -81,4 +81,3 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. -
diff --git a/README.md b/README.md index 9be9739..9d7c7e1 100644 --- a/README.md +++ b/README.md
@@ -19,17 +19,22 @@ This **cmsis_device_l1** MCU component repo is one element of the STM32CubeL1 MCU embedded software package, providing the **cmsis device** part. +## Release note + +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_l1/blob/master/Release_Notes.html). + ## Compatibility information In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package: CMSIS Device L1 | CMSIS Core | Was delivered in the full MCU package --------------- | ---------- | ------------------------------------- -Tag v2.3.0 | Tag v5.4.0_cm3 | Tag v1.9.0 +Tag v2.3.0 | Tag v5.4.0_cm3 | Tag v1.9.0 (and following, if any, till next new tag) +Tag v2.3.1 | Tag v5.4.0_cm3 | Tag v1.10.0 (and following, if any, till next new tag) The full **STM32CubeL1** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL1). ## Troubleshooting If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_l1/issues/new). -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). +For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file
diff --git a/Release_Notes.html b/Release_Notes.html index a9966a3..f095a8f 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
@@ -51,12 +51,39 @@ <div class="col-sm-12 col-lg-8"> <h1 id="update-history">Update History</h1> <div class="collapse"> -<input type="checkbox" id="collapse-section11" checked aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V2.3.0 / 05-April-2019</label> +<input type="checkbox" id="collapse-section12" checked aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V2.3.1 / 24-June-2020</label> <div> <h2 id="main-changes">Main Changes</h2> <h3 id="maintenance-release">Maintenance release</h3> <h2 id="contents">Contents</h2> <ul> +<li>All header files +<ul> +<li>Remove NVIC CMSIS bits definitions to avoid duplication with CMSIS Core V5.x</li> +<li>Remove GPIOx BRR register from GPIO structure and bit definitions when not supported</li> +<li>Add ADC VREFINT/TEMPSENSOR addresses definitions in line with products datasheets: +<ul> +<li>VREFINT_CAL_ADDR_CMSIS</li> +<li>TEMPSENSOR_CAL1_ADDR_CMSIS</li> +<li>TEMPSENSOR_CAL2_ADDR_CMSIS</li> +</ul></li> +<li>Remove unused IS_TIM_SYNCHRO_INSTANCE() assert macro</li> +<li>Update IS_TIM_MASTER_INSTANCE with all supported instances.</li> +</ul></li> +<li>system_stm32l1xx.c file +<ul> +<li>Update SystemInit() API to don’t reset RCC registers to its reset values</li> +</ul></li> +</ul> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V2.3.0 / 05-April-2019</label> +<div> +<h2 id="main-changes-1">Main Changes</h2> +<h3 id="maintenance-release-1">Maintenance release</h3> +<h2 id="contents-1">Contents</h2> +<ul> <li>stm32l0xx.h <ul> <li>Align ErrorStatus typedef to common error handling</li> @@ -82,9 +109,9 @@ <div class="collapse"> <input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V2.2.3 / 12-January-2018</label> <div> -<h2 id="main-changes-1">Main Changes</h2> +<h2 id="main-changes-2">Main Changes</h2> <h3 id="patch-release">Patch release</h3> -<h2 id="contents-1">Contents</h2> +<h2 id="contents-2">Contents</h2> <ul> <li>Corrected devices supporting RI_HYSCR3, RI_HYSCR4, RI_ASMRx, RI_CMRx, RI_CICRx registers in CMSIS files.</li> </ul> @@ -93,9 +120,9 @@ <div class="collapse"> <input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V2.2.2 / 25-August-2017</label> <div> -<h2 id="main-changes-2">Main Changes</h2> -<h3 id="maintenance-release-1">Maintenance release</h3> -<h2 id="contents-2">Contents</h2> +<h2 id="main-changes-3">Main Changes</h2> +<h3 id="maintenance-release-2">Maintenance release</h3> +<h2 id="contents-3">Contents</h2> <ul> <li>Removed DATE and VERSION fields from header files.</li> </ul> @@ -104,9 +131,9 @@ <div class="collapse"> <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V2.2.1 / 21-April-2017</label> <div> -<h2 id="main-changes-3">Main Changes</h2> -<h3 id="maintenance-release-2">Maintenance release</h3> -<h2 id="contents-3">Contents</h2> +<h2 id="main-changes-4">Main Changes</h2> +<h3 id="maintenance-release-3">Maintenance release</h3> +<h2 id="contents-4">Contents</h2> <ul> <li>Update CMSIS Devices compliancy with MISRA C 2004 rules: <ul> @@ -122,9 +149,9 @@ <div class="collapse"> <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V2.2.0 / 01-July-2016</label> <div> -<h2 id="main-changes-4">Main Changes</h2> -<h3 id="maintenance-release-3">Maintenance release</h3> -<h2 id="contents-4">Contents</h2> +<h2 id="main-changes-5">Main Changes</h2> +<h3 id="maintenance-release-4">Maintenance release</h3> +<h2 id="contents-5">Contents</h2> <ul> <li>Add macros _Pos and _Msk for each constants. <ul> @@ -152,9 +179,9 @@ <div class="collapse"> <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V2.1.3 / 04-March-2016</label> <div> -<h2 id="main-changes-5">Main Changes</h2> -<h3 id="maintenance-release-4">Maintenance release</h3> -<h2 id="contents-5">Contents</h2> +<h2 id="main-changes-6">Main Changes</h2> +<h3 id="maintenance-release-5">Maintenance release</h3> +<h2 id="contents-6">Contents</h2> <ul> <li>Add HardFault_IRQn.</li> <li>Add BKP5R to BKP19R for RTC_TypeDef for stm32l151xba.</li> @@ -191,9 +218,9 @@ <div class="collapse"> <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V2.1.2 / 09-October-2015</label> <div> -<h2 id="main-changes-6">Main Changes</h2> -<h3 id="maintenance-release-5">Maintenance release</h3> -<h2 id="contents-6">Contents</h2> +<h2 id="main-changes-7">Main Changes</h2> +<h3 id="maintenance-release-6">Maintenance release</h3> +<h2 id="contents-7">Contents</h2> <ul> <li>Removing the __IO attribute for PLLMulTable and AHBPrescTable. This was leading to issue during C++ initialisation.</li> <li>IDR field of CRC_TypeDef changed from uint32_t to uint8_t to comply with register structure.</li> @@ -206,9 +233,9 @@ <div class="collapse"> <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V2.1.1 / 31-March-2015</label> <div> -<h2 id="main-changes-7">Main Changes</h2> -<h3 id="maintenance-release-6">Maintenance release</h3> -<h2 id="contents-7">Contents</h2> +<h2 id="main-changes-8">Main Changes</h2> +<h3 id="maintenance-release-7">Maintenance release</h3> +<h2 id="contents-8">Contents</h2> <ul> <li>Ensure compliancy w/ C++</li> <li>Minor update on Timer assert.</li> @@ -219,9 +246,9 @@ <div class="collapse"> <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V2.1.0 / 06-February-2015</label> <div> -<h2 id="main-changes-8">Main Changes</h2> -<h3 id="maintenance-release-7">Maintenance release</h3> -<h2 id="contents-8">Contents</h2> +<h2 id="main-changes-9">Main Changes</h2> +<h3 id="maintenance-release-8">Maintenance release</h3> +<h2 id="contents-9">Contents</h2> <ul> <li>Add CMSIS files for new STM32L1 e<strong>X</strong>tended Devices : <strong>STM32L151xDX, STM32L152xDX and STM32L162xDX</strong></li> </ul> @@ -230,9 +257,9 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V2.0.0 / 05-September-2014</label> <div> -<h2 id="main-changes-9">Main Changes</h2> -<h3 id="maintenance-release-8">Maintenance release</h3> -<h2 id="contents-9">Contents</h2> +<h2 id="main-changes-10">Main Changes</h2> +<h3 id="maintenance-release-9">Maintenance release</h3> +<h2 id="contents-10">Contents</h2> <ul> <li>Update based on STM32Cube specification</li> </ul>
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font-family: Arial; color: blue;"><a href="../../../../../Release_Notes.html">Back to Release page</a></span></td> +</tr> +<tr style=""> +<td style="padding: 1.5pt;"> +<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release +Notes for<o:p></o:p> STM32L1xx CMSIS<br> +</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1> +<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright +© 2017 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p> +<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt;"><img style="border: 0px solid ; width: 86px; height: 65px;" alt="" id="_x0000_i1025" src="../../../../../_htmresc/logo.bmp"></span></p> +</td> +</tr> +</tbody> +</table> +<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p> +<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900"> +<tbody> +<tr style=""> +<td style="padding: 0cm;" valign="top"> +<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update history</span></h2><span style="font-family: "Times New Roman";"><span style="font-weight: bold;"></span></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 0cm; font-size: 13.5pt; font-family: "Times New Roman"; font-weight: bold; color: rgb(0, 0, 0); font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.3.0 / 26-October-2018</span></h3><b style="color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; font-size: medium; font-family: "Times New Roman"; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes</span></u></b><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></p><ul style="margin-bottom: 0cm; color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; list-style-type: square;"><li><span style="text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; font-family: Verdana; font-style: normal; font-weight: normal; font-size: 13px; line-height: normal; font-stretch: normal; white-space: normal; color: rgb(0, 0, 0); word-spacing: 0px; display: inline ! important;">Updated header of startup files for GCC toolchain after removal of Atollic TrueSTUDIO toolchain support.</span></li><li><span style="text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; font-family: Verdana; font-style: normal; font-weight: normal; font-size: 13px; line-height: normal; font-stretch: normal; white-space: normal; color: rgb(0, 0, 0); word-spacing: 0px; display: inline ! important;">Corrected definitions for USB_COUNT3_TX_0 and USB_COUNT3_TX_1 registers.</span></li><li><span style="text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; font-family: Verdana; font-style: normal; font-weight: normal; font-size: 13px; line-height: normal; font-stretch: normal; white-space: normal; color: rgb(0, 0, 0); word-spacing: 0px; display: inline ! important;">Updated macros definition for TIM instances.<br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 0cm; font-size: 13.5pt; font-family: "Times New Roman"; font-weight: bold; color: rgb(0, 0, 0); font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.3 / 12-January-2018</span></h3><b style="color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; font-size: medium; font-family: "Times New Roman"; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes</span></u></b><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></p><ul style="margin-bottom: 0cm; color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; list-style-type: square;"><li><span style="text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; font-family: Verdana; font-style: normal; font-weight: normal; font-size: 13px; line-height: normal; font-stretch: normal; white-space: normal; float: none; color: rgb(0, 0, 0); word-spacing: 0px; display: inline ! important;">Corrected devices supporting RI_HYSCR3, RI_HYSCR4, RI_ASMRx, RI_CMRx, RI_CICRx registers in CMSIS files.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 0cm; font-size: 13.5pt; font-family: "Times New Roman"; font-weight: bold; color: rgb(0, 0, 0); font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.2 / 25-August-2017</span></h3><b style="color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; font-size: medium; font-family: "Times New Roman"; color: rgb(0, 0, 0); font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px;"><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes</span></u></b><b><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></p><ul style="margin-bottom: 0cm; color: rgb(0, 0, 0); font-family: "Times New Roman"; font-size: medium; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; list-style-type: square;"><li><span style="text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; font-family: Verdana; font-style: normal; font-weight: normal; font-size: 13px; line-height: normal; font-stretch: normal; white-space: normal; float: none; color: rgb(0, 0, 0); word-spacing: 0px; display: inline ! important;">Removed DATE and VERSION fields from header files</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.1 +/ 21-April-2017</span></h3> +<b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +</p> +<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">General updates:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated CMSIS Device compliancy with MISRA C 2004 rules:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.6 </span><span style="font-size: 10pt; font-family: Verdana;">('U' suffix applied to all constants of 'unsigned' type)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">U</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">pdated system_stm32l1xx.h/.c files.<br></span></li></ul></ul><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Aligned Bit definitions for SCB_CFSR register to be compliant with CMSIS Core V4.x and V5.x.</span></li><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Renamed RTC_CR_BCK bits in RTC_CR register to RTC_CR_BKP, to be aligned with others series.</span></li><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Renamed GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit definitions (from GPIO_AFRL/AFRH registers) to GPIO_AFRL_AFSELx.<br><br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.0 +/ 01-July-2016 <o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +</p> +<ul style="list-style-type: square;"> +<li>Add macros _Pos and _Msk for each constants.</li> +<ul> +<li>For instance:</li> +<ul> +<li style="font-family: Courier New;">#define +ADC_LTR_LT + ((uint32_t)0x00000FFFU)</li> +</ul> +<li>Is now provided as:</li> +<ul> +<li style="font-family: Courier New;">#define +ADC_LTR_LT_Pos (0U) </li> +<li style="font-family: Courier New;">#define +ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos)</li> +<li><span style="font-family: Courier New;">#define +ADC_LTR_LT ADC_LTR_LT_Msk</span></li> +</ul> +</ul> +</ul> +<ul style="list-style-type: square;"> +<li>IS_I2S_ALL_INSTANCE is now SPI2 and SPI3 +instead of SPI1 and SPI2.</li> +<li>Update the TIM_ARR_ARR and TIM_CNT_CNT as they +support the 32 bit counter feature.</li> +<li>Add macro IS_TIM_ETR_INSTANCE.</li> +<li>Add RI_ASCR2_GR6_x with x = 1,2,3,4 if +applicable.</li> +<li>Add macro IS_SMBUS_ALL_INSTANCE.</li> +<li>Set default value for SystemCoreClock to +2097000 instead of 32000000.</li> +<li>Correct the presence of TIM9 for some devices +inside various TIMER macros.</li> +</ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.3 +/ 04-March-2016 <o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +</p> +<ul style="list-style-type: square;"> +<li>Add HardFault_IRQn.</li> +<li>Add BKP5R to BKP19R for RTC_TypeDef for +stm32l151xba.</li> +<li>Align bits naming on all stm32 families (ex: +WWDG_CFR_WDGTB0 -> WWDG_CFR_WDGTB_0).</li> +<li>Rename RCC_CFGR_MCO_DIVx to RCC_CFGR_MCOPRE_DIVx</li> +<li>Align Bits naming on all stm32 families (ex: +EXTI_IMR_MR0 --> EXTI_IMR_IM0)</li> +<li>Update .icf file to correct empty linker ROM +Start/End menu, under IAR, for stm32l151xdx, stm32l152xdx and +stm32l162xdx.</li> +<li>Rename RCC_CFGR_MCO_x to RCC_CFGR_MCOSEL_x to +be aligned with Reference Manual.</li> +<li>Update CMSIS drivers to apply MISRA C 2004 rule +10.6. (Use U postfix)</li> +<li>Add defines FLASHSIZE_BASE and UID_BASE</li> +<li>ADC common instance standardization (new define +ADC1_COMMON)</li> +<li>Remove bit GPIO_BRR_BR_x from Cat1 to Cat2 +devices</li> +<li>Literals "ADC_SMPR1_SMP27, ADC_SMPR1_SMP28, +ADC_SMPR1_SMP29" are available on Cat4, Cat5 only.</li> +<li>Add DMA_CNDTR_NDT, DMA_CPAR_PA and +DMA_CMAR_MA definitions present on other stm32 families.</li> +<li>Add defines to trig feature inside source code +based on CMSIS content:</li> +<ul> +<li>RTC_TAMPER1_SUPPORT</li> +<li>RTC_TAMPER2_SUPPORT</li> +<li>RTC_TAMPER3_SUPPORT</li> +<li>RTC_BACKUP_SUPPORT</li> +<li>RTC_WAKEUP_SUPPORT</li> +<li>RTC_SMOOTHCALIB_SUPPORT</li> +<li>RTC_SUBSECOND_SUPPORT. </li> +</ul> +<ul> +<li>PWR_PVD_SUPPORT</li> +</ul> +<li>Set CMSIS variables PLLMulTable, AHBPrescTable +and APBPrescTable as external in system_stm32l1xx.h.</li> +<li>Bit 23 of all EXTI registers (IMR, EMR, ...) is +not supported on Cat 1 & 2.</li> +<li>Correct a wrong values for RI_ASCR1_CH_27 to +RI_ASCR1_CH_30</li> +<li>Add defines for LCD capacitance</li> +<li>Suppress SPI1 from I2S_ALL_INSTANCE</li> +</ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.2 +/ 09-October-2015 <o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +</p> +<ul style="list-style-type: square;"> +<li>Removing the __IO attribute for PLLMulTable and +AHBPrescTable. This was leading to issue during C++ initialisation.</li> +<li>IDR field of CRC_TypeDef changed from uint32_t +to uint8_t to comply with register structure.</li> +<li><span style="font-size: 10pt; font-family: Verdana;">Added TIM10 +and TIM11 to IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE).</span></li> +<li><span style="font-size: 10pt; font-family: Verdana;">Renaming +USB_CNTR_LP_MODE to USB_CNTR_LPMODE for naming consistancy with other +bits.</span></li> +<li><span style="font-size: 10pt; font-family: Verdana;">Renaming +USB_ISTR_PMAOVRM to USB_ISTR_PMAOVR to use the name of the bit in this +register.<br> +</span></li> +</ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.1 +/ 31-March-2015 <o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +</p> +<ul style="list-style-type: square;"> +<li><span style="font-size: 10pt; font-family: Verdana;">Ensure +compliancy w/ C++</span></li> +<li><span style="font-size: 10pt; font-family: Verdana;">Minor update +on Timer assert.</span></li> +<li><span style="font-size: 10pt; font-family: Verdana;">Adding +IS_AES_ALL_INSTANCE macro for product with AES.</span></li> +</ul> +<span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.0 +/ 16-January-2015 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> +<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add +CMSIS files for new STM32L1 e<span style="font-weight: bold;">X</span>tended +Devices : <span style="font-weight: bold;">STM32L151xDX</span>, +<span style="font-weight: bold;">STM32L152xDX</span> +& <span style="font-weight: bold;">STM32L162xDX</span></span></li></ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 +/ 05-September-2014 <o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<ul style="list-style-type: square;"> +<li><span style="font-size: 10pt; font-family: Verdana;">Update +based on STM32Cube specification<br> +</span></li> +<li style="font-weight: bold;"><span style="font-size: 10pt; font-family: Verdana;">This version +has to be used only with </span><span style="font-size: 10pt; font-family: Verdana;">STM32CubeF4</span><span style="font-size: 10pt; font-family: Verdana;"> based +development</span></li> +</ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.1 +/ 06-March-2014<o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> +<ul style="margin-top: 0cm;" type="square"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span><span style="font-size: 10pt; font-family: Verdana;">: update RAM +functions attribute definition for GNU compiler</span></li> +</ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0 +/ 31-January-2014<o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> +<ul style="margin-top: 0cm;" type="square"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support +for <span style="font-weight: bold; font-style: italic;">STM32L1xx +XL-density</span> devices </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">"Ultra Low Power XL-density +devices: STM32L151x<span style="font-weight: bold;">E</span>xx, +STM32L152x<span style="font-weight: bold;">E</span>xx +and STM32L162x<span style="font-weight: bold;">E</span>xx"</span></span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new +startup file <span style="font-style: italic;">startup_stm32l1xx_xl.s</span> +for all toolchains</span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span></li> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new macro +<span style="font-style: italic;">STM32L1XX_XL</span> +for XL-density devices<span style="font-style: italic;"></span></span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">IRQn</span> enumeration +for <span style="font-style: italic;">STM32L1XX_XL</span></span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">GPIO BRR +register is declared only for STM32L1XX_HD and STM32L1XX_XL devices</span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All devices </span><span style="font-size: 10pt; font-family: Verdana;">definition </span><span style="font-size: 10pt; font-family: Verdana;">(i.e. +STM32L1XX_xx) are commented out, user need to define the right +STM32L1xx device in the toolchain compiler preprocessor</span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Extend <span style="font-style: italic;">HSE_STARTUP_TIMEOUT</span> +and <span style="font-style: italic;">HSI_STARTUP_TIMEOUT</span> +values to 0x5000</span></li> +</ul> +</ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1 +/ 19-June-2013<o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> +<ul style="margin-top: 0cm;" type="square"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span></li> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">RI_TypeDef</span> +structure by adding registers <span style="font-style: italic;">RI_ASMRx</span>, +<span style="font-style: italic;">RI_CMRx</span> +and <span style="font-style: italic;">RI_CICRx</span> +(x=1..5)</span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add bits +definition for </span><span style="font-size: 10pt; font-family: Verdana;">registers <span style="font-style: italic;">RI_ASMRx</span>, <span style="font-style: italic;">RI_CMRx</span> and <span style="font-style: italic;">RI_CICRx</span> (x=1..5)</span></li> +</ul> +</ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 +/ 22-February-2013<o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> +<ul style="margin-top: 0cm;" type="square"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span></li> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">List of +supported devices: add reference to <span style="font-weight: bold; font-style: italic;">STM32L100xx +Ultra Low Power Value Line devices</span></span></li> +</ul> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add <span style="font-style: italic;">SPRMOD</span> bit +definition in <span style="font-style: italic;">FLASH_OBR</span> +register</span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add <span style="font-style: italic;">RDERR</span> bit +definition in <span style="font-style: italic;">FLASH_SR</span> +register</span></li> +</ul> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">FLASH_OBR_nRST_BFB2</span> +to <span style="font-style: italic;">FLASH_OBR_BFB2</span></span></li> +</ul> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Delete <span style="font-style: italic;">FLASH_OBR_USER</span> +define (useless)<br> +</span></li> +</ul> +</ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 +/ 05-March-2012<o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> +<ul style="margin-top: 0cm;" type="square"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source +files: license disclaimer text update and add link to the +License file on ST Internet.</span></li> +</ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 191px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 +/ 24-January-2012<o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> +<ul style="margin-top: 0cm;" type="square"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Alpha version +for <span style="font-weight: bold; font-style: italic;">STM32L1xx +High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density +Plus</span> devices.</span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support +for </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32L1xx +High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density +Plus</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices:</span></li> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new +product define: "#define STM32L1XX_MDP"</span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new +product define: "#define STM32L1XX_HD"</span></li> +</ul> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the +library version to V1.1.0<br> +</span></li> +</ul> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new IRQ +to support STM32L1XX_HD and </span><span style="font-size: 10pt; font-family: Verdana;">STM32L1XX_MDP +</span><span style="font-size: 10pt; font-family: Verdana;">vector table</span></li> +</ul> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new and +update some Typedef to support new peripherals (AES, SDIO, OPAMP, FSMC, +I2S)</span></li> +</ul> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new +peripherals address mapping</span></li> +</ul> +<ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update bits +definition</span></li> +</ul> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new +startup file "<span style="font-weight: bold; font-style: italic;">startup_stm32l1xx_mdp.s</span>" +for all toolchains</span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new +startup file "<span style="font-weight: bold; font-style: italic;">startup_stm32l1xx_hd.s</span>" +for all toolchains</span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the +RTC "<span style="font-weight: bold; font-style: italic;">CAL</span>" +register name to "<span style="font-weight: bold; font-style: italic;">CALR</span>"</span></li> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update +registers bits definitions.</span><span style="color: black;"><o:p> +</o:p></span><br> +</li> +</ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 +/ 31-December-2010<o:p></o:p></span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes<o:p></o:p></span></u></b></p> +<ul style="margin-top: 0cm;" type="square"> +<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Created</span></li> +</ul> +<span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><br> +<span style="font-size: 10pt; font-family: Verdana;"></span> +<ul style="margin-top: 0cm;" type="square"> +</ul> +<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";"> +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met:</span><br> + </font> + <ol><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions +in binary form must reproduce the above copyright notice, this list of +conditions and the following disclaimer in </span><span style="font-family: "Verdana","sans-serif";">the documentation and/or other materials provided with the distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither +the name of STMicroelectronics nor the names of its contributors may be +used to endorse or promote products derived from this software without +specific prior written permission.</span></font><span style="font-family: "Verdana","sans-serif";"></span><br></li></ol><font size="-1"> + <span style="font-family: "Verdana","sans-serif";"></span><br> + <span style="font-family: "Verdana","sans-serif";">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font> + + </div> +<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;"> +<hr align="center" size="2" width="100%"></span></div> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For +complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers +visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="color: black;"><o:p></o:p></span></p> +</td> +</tr> +</tbody> +</table> +<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p> +</td> +</tr> +</tbody> +</table> +</div> +<p class="MsoNormal"><o:p> </o:p></p> +</div> +</body></html> \ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32l100xb.s b/Source/Templates/arm/startup_stm32l100xb.s index 519be62..2e8e3bd 100644 --- a/Source/Templates/arm/startup_stm32l100xb.s +++ b/Source/Templates/arm/startup_stm32l100xb.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l100xba.s b/Source/Templates/arm/startup_stm32l100xba.s index a280a07..534cc98 100644 --- a/Source/Templates/arm/startup_stm32l100xba.s +++ b/Source/Templates/arm/startup_stm32l100xba.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l100xc.s b/Source/Templates/arm/startup_stm32l100xc.s index 94aa8a8..202148b 100644 --- a/Source/Templates/arm/startup_stm32l100xc.s +++ b/Source/Templates/arm/startup_stm32l100xc.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l151xb.s b/Source/Templates/arm/startup_stm32l151xb.s index 8617d77..38dec85 100644 --- a/Source/Templates/arm/startup_stm32l151xb.s +++ b/Source/Templates/arm/startup_stm32l151xb.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l151xba.s b/Source/Templates/arm/startup_stm32l151xba.s index 6766b7b..4d33c5c 100644 --- a/Source/Templates/arm/startup_stm32l151xba.s +++ b/Source/Templates/arm/startup_stm32l151xba.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l151xc.s b/Source/Templates/arm/startup_stm32l151xc.s index c61e4ca..b8baae4 100644 --- a/Source/Templates/arm/startup_stm32l151xc.s +++ b/Source/Templates/arm/startup_stm32l151xc.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l151xca.s b/Source/Templates/arm/startup_stm32l151xca.s index 2a8a79f..b65fef4 100644 --- a/Source/Templates/arm/startup_stm32l151xca.s +++ b/Source/Templates/arm/startup_stm32l151xca.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l151xd.s b/Source/Templates/arm/startup_stm32l151xd.s index fd8ec00..e5fdc6f 100644 --- a/Source/Templates/arm/startup_stm32l151xd.s +++ b/Source/Templates/arm/startup_stm32l151xd.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l151xdx.s b/Source/Templates/arm/startup_stm32l151xdx.s index 0f846f0..f463bef 100644 --- a/Source/Templates/arm/startup_stm32l151xdx.s +++ b/Source/Templates/arm/startup_stm32l151xdx.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l151xe.s b/Source/Templates/arm/startup_stm32l151xe.s index 9e4f21a..382be8c 100644 --- a/Source/Templates/arm/startup_stm32l151xe.s +++ b/Source/Templates/arm/startup_stm32l151xe.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l152xb.s b/Source/Templates/arm/startup_stm32l152xb.s index bd00243..46d1f41 100644 --- a/Source/Templates/arm/startup_stm32l152xb.s +++ b/Source/Templates/arm/startup_stm32l152xb.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l152xba.s b/Source/Templates/arm/startup_stm32l152xba.s index 3c7baf1..09b9286 100644 --- a/Source/Templates/arm/startup_stm32l152xba.s +++ b/Source/Templates/arm/startup_stm32l152xba.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l152xc.s b/Source/Templates/arm/startup_stm32l152xc.s index 7c319a3..22570aa 100644 --- a/Source/Templates/arm/startup_stm32l152xc.s +++ b/Source/Templates/arm/startup_stm32l152xc.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l152xca.s b/Source/Templates/arm/startup_stm32l152xca.s index 3537f37..f6fa497 100644 --- a/Source/Templates/arm/startup_stm32l152xca.s +++ b/Source/Templates/arm/startup_stm32l152xca.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l152xd.s b/Source/Templates/arm/startup_stm32l152xd.s index 4c92935..57e537a 100644 --- a/Source/Templates/arm/startup_stm32l152xd.s +++ b/Source/Templates/arm/startup_stm32l152xd.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l152xdx.s b/Source/Templates/arm/startup_stm32l152xdx.s index df62ec6..5927660 100644 --- a/Source/Templates/arm/startup_stm32l152xdx.s +++ b/Source/Templates/arm/startup_stm32l152xdx.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l152xe.s b/Source/Templates/arm/startup_stm32l152xe.s index dbc7631..8748e8b 100644 --- a/Source/Templates/arm/startup_stm32l152xe.s +++ b/Source/Templates/arm/startup_stm32l152xe.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l162xc.s b/Source/Templates/arm/startup_stm32l162xc.s index a19e7e2..dd5b5d2 100644 --- a/Source/Templates/arm/startup_stm32l162xc.s +++ b/Source/Templates/arm/startup_stm32l162xc.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l162xca.s b/Source/Templates/arm/startup_stm32l162xca.s index ed07310..1001812 100644 --- a/Source/Templates/arm/startup_stm32l162xca.s +++ b/Source/Templates/arm/startup_stm32l162xca.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l162xd.s b/Source/Templates/arm/startup_stm32l162xd.s index 4b5e2ca..cf5c277 100644 --- a/Source/Templates/arm/startup_stm32l162xd.s +++ b/Source/Templates/arm/startup_stm32l162xd.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l162xdx.s b/Source/Templates/arm/startup_stm32l162xdx.s index 3d49d3e..4d5e128 100644 --- a/Source/Templates/arm/startup_stm32l162xdx.s +++ b/Source/Templates/arm/startup_stm32l162xdx.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/arm/startup_stm32l162xe.s b/Source/Templates/arm/startup_stm32l162xe.s index 7ef19b8..7f17445 100644 --- a/Source/Templates/arm/startup_stm32l162xe.s +++ b/Source/Templates/arm/startup_stm32l162xe.s
@@ -17,12 +17,13 @@ ;* Copyright (c) 2017 STMicroelectronics. All rights reserved. ;* ;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the +;* the "License"; You may not use this file except in compliance with the ;* License. You may obtain a copy of the License at: ;* opensource.org/licenses/BSD-3-Clause -; +;* ;******************************************************************************* - +;* <<< Use Configuration Wizard in Context Menu >>> +; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; <h> Stack Configuration
diff --git a/Source/Templates/system_stm32l1xx.c b/Source/Templates/system_stm32l1xx.c index 7d42a2b..c3d397d 100644 --- a/Source/Templates/system_stm32l1xx.c +++ b/Source/Templates/system_stm32l1xx.c
@@ -139,24 +139,6 @@ */ void SystemInit (void) { - /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; - - /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t)0x88FFC00C; - - /*!< Reset HSION, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xEEFEFFFE; - - /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; - - /*!< Disable all interrupts */ - RCC->CIR = 0x00000000; - #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */
diff --git a/md2html.sh b/md2html.sh new file mode 100644 index 0000000..b996e7a --- /dev/null +++ b/md2html.sh
@@ -0,0 +1,11 @@ +#!/bin/bash + +# How to use Pandoc +# To convert your existing HTML release notes into Markdown (useful to build your history), type the following command in your bash window: + # pandoc --from html --to markdown Release_Notes.html > Release_Notes.md +# To convert a .md file into an HTML one, type the following command in your bash window: + # pandoc -s -r markdown -t html5 -c "_htmresc/mini-st.css" Release_Notes.md > Release_Notes.html + +pandoc -s -r markdown -t html5 -c "_htmresc/mini-st.css" Release_Notes.md > Release_Notes.html + +read -n1 -r -p "Press any key to continue..." key