Google Git
Sign in
pigweed / third_party / github / STMicroelectronics / cmsis_device_l1 / dafdef897e29b4f5934f1e2b9de9957410435476 / . / Include / stm32l152xd.h
blob: 487cc536bb2d61866a88c362c6d3504e0788bd20 [file] [log] [blame]
/**
******************************************************************************
* @file stm32l152xd.h
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L1xx devices.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l152xd
* @{
*/
#ifndef __STM32L152xD_H
#define __STM32L152xD_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */
#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32L1xx Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
/*!< Interrupt Number Definition */
typedef enum
{
/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** STM32L specific Interrupt Numbers ***********************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
DAC_IRQn = 21, /*!< DAC Interrupt */
COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
LCD_IRQn = 24, /*!< LCD Interrupt */
TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
SDIO_IRQn = 45, /*!< SDIO global Interrupt */
TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
UART4_IRQn = 48, /*!< UART4 global Interrupt */
UART5_IRQn = 49, /*!< UART5 global Interrupt */
DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
} IRQn_Type;
/**
* @}
*/
#include "core_cm3.h"
#include "system_stm32l1xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
__IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
__IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
__IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
__IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
__IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
} ADC_Common_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
} COMP_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
} COMP_Common_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
} CRC_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
}DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
__IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
__IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
__IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
__IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
__IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
__IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
__IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
__IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */
uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
__IO uint32_t WRPR3; /*!< Write protection register 3, Address offset: 0x84 */
} FLASH_TypeDef;
/**
* @brief Option Bytes Registers
*/
typedef struct
{
__IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
__IO uint32_t USER; /*!< user register, Address offset: 0x04 */
__IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
__IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
__IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
__IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
__IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */
__IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */
} OB_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
__IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
__IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
} OPAMP_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
__IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */
} OPAMP_Common_TypeDef;
/**
* @brief Flexible Static Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
} FSMC_Bank1_TypeDef;
/**
* @brief Flexible Static Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FSMC_Bank1E_TypeDef;
/**
* @brief General Purpose IO
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
} GPIO_TypeDef;
/**
* @brief SysTem Configuration
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
} SYSCFG_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
__IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
__IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
__IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
__IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
__IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
} IWDG_TypeDef;
/**
* @brief LCD
*/
typedef struct
{
__IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
__IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
__IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
__IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
__IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
} LCD_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
__IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
__IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
__IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
__IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
__IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
__IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
} RCC_TypeDef;
/**
* @brief Routing Interface
*/
typedef struct
{
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
__IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
__IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
__IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
__IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
__IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
__IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
__IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
__IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
__IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
__IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
} RI_TypeDef;
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
__IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
__IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
uint32_t RESERVED7; /*!< Reserved, 0x4C */
__IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
__IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
__IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
__IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
__IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
__IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
__IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
__IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
__IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
__IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
__IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
__IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
__IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
__IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
__IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
__IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
__IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
__IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
__IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
__IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
__IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
__IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
__IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
__IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
__IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
} RTC_TypeDef;
/**
* @brief SD host Interface
*/
typedef struct
{
__IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
__IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
__I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
__I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
__I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
__I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
__I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
__I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
__I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
__I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
__IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
} SDIO_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
uint32_t RESERVED12; /*!< Reserved, 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
uint32_t RESERVED17; /*!< Reserved, 0x44 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
__IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
} USART_TypeDef;
/**
* @brief Universal Serial Bus Full Speed Device
*/
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
__IO uint16_t RESERVED1; /*!< Reserved */
__IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
__IO uint16_t RESERVED2; /*!< Reserved */
__IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
__IO uint16_t RESERVED3; /*!< Reserved */
__IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
__IO uint16_t RESERVED4; /*!< Reserved */
__IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
__IO uint16_t RESERVED5; /*!< Reserved */
__IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
__IO uint16_t RESERVED6; /*!< Reserved */
__IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
__IO uint16_t RESERVED7[17]; /*!< Reserved */
__IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
__IO uint16_t RESERVED8; /*!< Reserved */
__IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
__IO uint16_t RESERVED9; /*!< Reserved */
__IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
__IO uint16_t RESERVEDA; /*!< Reserved */
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
__IO uint16_t RESERVEDC; /*!< Reserved */
} USB_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief Universal Serial Bus Full Speed Device
*/
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
#define FLASH_EEPROM_BASE (FLASH_BASE + 0x80000UL) /*!< FLASH EEPROM base address in the alias region */
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
#define FSMC_BASE (0x60000000UL) /*!< FSMC base address */
#define FSMC_R_BASE (0xA0000000UL) /*!< FSMC registers base address */
#define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
#define FLASH_END (0x0805FFFFUL) /*!< Program end FLASH address for Cat4 */
#define FLASH_BANK2_BASE (0x08030000UL) /*!< FLASH BANK2 base address in the alias region */
#define FLASH_BANK1_END (0x0802FFFFUL) /*!< Program end FLASH BANK1 address */
#define FLASH_BANK2_END (0x0805FFFFUL) /*!< Program end FLASH BANK2 address */
#define FLASH_EEPROM_END (0x08082FFFUL) /*!< FLASH EEPROM end address (12KB) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL)
#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)
#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)
#define LCD_BASE (APB1PERIPH_BASE + 0x00002400UL)
#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)
#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)
#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)
#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
/* USB device FS */
#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
/* USB device FS SRAM */
#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)
#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00UL)
#define RI_BASE (APB1PERIPH_BASE + 0x00007C04UL)
#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CUL)
/*!< APB2 peripherals */
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL)
#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800UL)
#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00UL)
#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000UL)
#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)
#define ADC_BASE (APB2PERIPH_BASE + 0x00002700UL)
#define SDIO_BASE (APB2PERIPH_BASE + 0x00002C00UL)
#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
/*!< AHB peripherals */
#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000UL)
#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400UL)
#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800UL)
#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00UL)
#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000UL)
#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400UL)
#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800UL)
#define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00UL)
#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
#define RCC_BASE (AHBPERIPH_BASE + 0x00003800UL)
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */
#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
#define FLASHSIZE_BASE (0x1FF800CCUL) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
#define UID_BASE (0x1FF800D0UL) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL)
#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL)
#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL)
#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL)
#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL)
#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL)
#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */
#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */
#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */
#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000UL) /*!< FSMC Bank1 registers base address */
#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104UL) /*!< FSMC Bank1E registers base address */
#define DBGMCU_BASE (0xE0042000UL) /*!< Debug MCU registers base address */
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define LCD ((LCD_TypeDef *) LCD_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
/* USB device FS */
#define USB ((USB_TypeDef *) USB_BASE)
/* USB device FS SRAM */
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC1 ((DAC_TypeDef *) DAC_BASE)
/* Legacy define */
#define DAC DAC1
#define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
#define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
#define RI ((RI_TypeDef *) RI_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
#define OPAMP3 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000002U))
#define OPAMP123_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
/* Legacy defines */
#define ADC ADC1_COMMON
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define OB ((OB_TypeDef *) OB_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers Bits Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter (ADC) */
/* */
/******************************************************************************/
#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR_CMSIS 0x1FF800FA /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR_CMSIS 0x1FF800FE /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
#define ADC_SR_EOCS_Pos (1U)
#define ADC_SR_EOCS_Msk (0x1UL << ADC_SR_EOCS_Pos) /*!< 0x00000002 */
#define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
#define ADC_SR_JEOS_Pos (2U)
#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
#define ADC_SR_JSTRT_Pos (3U)
#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
#define ADC_SR_STRT_Pos (4U)
#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */
#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
#define ADC_SR_OVR_Pos (5U)
#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */
#define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */
#define ADC_SR_ADONS_Pos (6U)
#define ADC_SR_ADONS_Msk (0x1UL << ADC_SR_ADONS_Pos) /*!< 0x00000040 */
#define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */
#define ADC_SR_RCNR_Pos (8U)
#define ADC_SR_RCNR_Msk (0x1UL << ADC_SR_RCNR_Pos) /*!< 0x00000100 */
#define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */
#define ADC_SR_JCNR_Pos (9U)
#define ADC_SR_JCNR_Msk (0x1UL << ADC_SR_JCNR_Pos) /*!< 0x00000200 */
#define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */
/* Legacy defines */
#define ADC_SR_EOC (ADC_SR_EOCS)
#define ADC_SR_JEOC (ADC_SR_JEOS)
/******************* Bit definition for ADC_CR1 register ********************/
#define ADC_CR1_AWDCH_Pos (0U)
#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
#define ADC_CR1_EOCSIE_Pos (5U)
#define ADC_CR1_EOCSIE_Msk (0x1UL << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */
#define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
#define ADC_CR1_AWDIE_Pos (6U)
#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
#define ADC_CR1_JEOSIE_Pos (7U)
#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_CR1_SCAN_Pos (8U)
#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
#define ADC_CR1_AWDSGL_Pos (9U)
#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CR1_JAUTO_Pos (10U)
#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
#define ADC_CR1_DISCEN_Pos (11U)
#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CR1_JDISCEN_Pos (12U)
#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CR1_DISCNUM_Pos (13U)
#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
#define ADC_CR1_PDD_Pos (16U)
#define ADC_CR1_PDD_Msk (0x1UL << ADC_CR1_PDD_Pos) /*!< 0x00010000 */
#define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */
#define ADC_CR1_PDI_Pos (17U)
#define ADC_CR1_PDI_Msk (0x1UL << ADC_CR1_PDI_Pos) /*!< 0x00020000 */
#define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */
#define ADC_CR1_JAWDEN_Pos (22U)
#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CR1_AWDEN_Pos (23U)
#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CR1_RES_Pos (24U)
#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */
#define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */
#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */
#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */
#define ADC_CR1_OVRIE_Pos (26U)
#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */
/* Legacy defines */
#define ADC_CR1_EOCIE (ADC_CR1_EOCSIE)
#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
/******************* Bit definition for ADC_CR2 register ********************/
#define ADC_CR2_ADON_Pos (0U)
#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
#define ADC_CR2_CONT_Pos (1U)
#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
#define ADC_CR2_CFG_Pos (2U)
#define ADC_CR2_CFG_Msk (0x1UL << ADC_CR2_CFG_Pos) /*!< 0x00000004 */
#define ADC_CR2_CFG ADC_CR2_CFG_Msk /*!< ADC channels bank selection */
#define ADC_CR2_DELS_Pos (4U)
#define ADC_CR2_DELS_Msk (0x7UL << ADC_CR2_DELS_Pos) /*!< 0x00000070 */
#define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */
#define ADC_CR2_DELS_0 (0x1UL << ADC_CR2_DELS_Pos) /*!< 0x00000010 */
#define ADC_CR2_DELS_1 (0x2UL << ADC_CR2_DELS_Pos) /*!< 0x00000020 */
#define ADC_CR2_DELS_2 (0x4UL << ADC_CR2_DELS_Pos) /*!< 0x00000040 */
#define ADC_CR2_DMA_Pos (8U)
#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
#define ADC_CR2_DDS_Pos (9U)
#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */
#define ADC_CR2_EOCS_Pos (10U)
#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
#define ADC_CR2_JEXTEN_Pos (20U)
#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
#define ADC_CR2_JSWSTART_Pos (22U)
#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
#define ADC_CR2_EXTSEL_Pos (24U)
#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
#define ADC_CR2_EXTEN_Pos (28U)
#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */
#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
#define ADC_CR2_SWSTART_Pos (30U)
#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
/****************** Bit definition for ADC_SMPR1 register *******************/
#define ADC_SMPR1_SMP20_Pos (0U)
#define ADC_SMPR1_SMP20_Msk (0x7UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */
#define ADC_SMPR1_SMP20_0 (0x1UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP20_1 (0x2UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP20_2 (0x4UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP21_Pos (3U)
#define ADC_SMPR1_SMP21_Msk (0x7UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */
#define ADC_SMPR1_SMP21_0 (0x1UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP21_1 (0x2UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP21_2 (0x4UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP22_Pos (6U)
#define ADC_SMPR1_SMP22_Msk (0x7UL << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */
#define ADC_SMPR1_SMP22_0 (0x1UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP22_1 (0x2UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP22_2 (0x4UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP23_Pos (9U)
#define ADC_SMPR1_SMP23_Msk (0x7UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */
#define ADC_SMPR1_SMP23_0 (0x1UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP23_1 (0x2UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP23_2 (0x4UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP24_Pos (12U)
#define ADC_SMPR1_SMP24_Msk (0x7UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */
#define ADC_SMPR1_SMP24_0 (0x1UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP24_1 (0x2UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP24_2 (0x4UL << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP25_Pos (15U)
#define ADC_SMPR1_SMP25_Msk (0x7UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */
#define ADC_SMPR1_SMP25_0 (0x1UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP25_1 (0x2UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP25_2 (0x4UL << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP26_Pos (18U)
#define ADC_SMPR1_SMP26_Msk (0x7UL << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */
#define ADC_SMPR1_SMP26_0 (0x1UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP26_1 (0x2UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP26_2 (0x4UL << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP27_Pos (21U)
#define ADC_SMPR1_SMP27_Msk (0x7UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP27 ADC_SMPR1_SMP27_Msk /*!< ADC channel 27 sampling time selection */
#define ADC_SMPR1_SMP27_0 (0x1UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP27_1 (0x2UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP27_2 (0x4UL << ADC_SMPR1_SMP27_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP28_Pos (24U)
#define ADC_SMPR1_SMP28_Msk (0x7UL << ADC_SMPR1_SMP28_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP28 ADC_SMPR1_SMP28_Msk /*!< ADC channel 28 sampling time selection */
#define ADC_SMPR1_SMP28_0 (0x1UL << ADC_SMPR1_SMP28_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP28_1 (0x2UL << ADC_SMPR1_SMP28_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP28_2 (0x4UL << ADC_SMPR1_SMP28_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP29_Pos (27U)
#define ADC_SMPR1_SMP29_Msk (0x7UL << ADC_SMPR1_SMP29_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP29 ADC_SMPR1_SMP29_Msk /*!< ADC channel 29 sampling time selection */
#define ADC_SMPR1_SMP29_0 (0x1UL << ADC_SMPR1_SMP29_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP29_1 (0x2UL << ADC_SMPR1_SMP29_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP29_2 (0x4UL << ADC_SMPR1_SMP29_Pos) /*!< 0x20000000 */
/****************** Bit definition for ADC_SMPR2 register *******************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
#define ADC_SMPR2_SMP19_Pos (27U)
#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */
#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
/****************** Bit definition for ADC_SMPR3 register *******************/
#define ADC_SMPR3_SMP0_Pos (0U)
#define ADC_SMPR3_SMP0_Msk (0x7UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */
#define ADC_SMPR3_SMP0_0 (0x1UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR3_SMP0_1 (0x2UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR3_SMP0_2 (0x4UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR3_SMP1_Pos (3U)
#define ADC_SMPR3_SMP1_Msk (0x7UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */
#define ADC_SMPR3_SMP1_0 (0x1UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR3_SMP1_1 (0x2UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR3_SMP1_2 (0x4UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR3_SMP2_Pos (6U)
#define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */
#define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR3_SMP3_Pos (9U)
#define ADC_SMPR3_SMP3_Msk (0x7UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */
#define ADC_SMPR3_SMP3_0 (0x1UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR3_SMP3_1 (0x2UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR3_SMP3_2 (0x4UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR3_SMP4_Pos (12U)
#define ADC_SMPR3_SMP4_Msk (0x7UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */
#define ADC_SMPR3_SMP4_0 (0x1UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR3_SMP4_1 (0x2UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR3_SMP4_2 (0x4UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR3_SMP5_Pos (15U)
#define ADC_SMPR3_SMP5_Msk (0x7UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR3_SMP5_0 (0x1UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR3_SMP5_1 (0x2UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR3_SMP5_2 (0x4UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR3_SMP6_Pos (18U)
#define ADC_SMPR3_SMP6_Msk (0x7UL << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */
#define ADC_SMPR3_SMP6_0 (0x1UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR3_SMP6_1 (0x2UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR3_SMP6_2 (0x4UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR3_SMP7_Pos (21U)
#define ADC_SMPR3_SMP7_Msk (0x7UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */
#define ADC_SMPR3_SMP7_0 (0x1UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR3_SMP7_1 (0x2UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR3_SMP7_2 (0x4UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR3_SMP8_Pos (24U)
#define ADC_SMPR3_SMP8_Msk (0x7UL << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */
#define ADC_SMPR3_SMP8_0 (0x1UL << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR3_SMP8_1 (0x2UL << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR3_SMP8_2 (0x4UL << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR3_SMP9_Pos (27U)
#define ADC_SMPR3_SMP9_Msk (0x7UL << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */
#define ADC_SMPR3_SMP9_0 (0x1UL << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR3_SMP9_1 (0x2UL << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR3_SMP9_2 (0x4UL << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */
/****************** Bit definition for ADC_JOFR1 register *******************/
#define ADC_JOFR1_JOFFSET1_Pos (0U)
#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
/****************** Bit definition for ADC_JOFR2 register *******************/
#define ADC_JOFR2_JOFFSET2_Pos (0U)
#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
/****************** Bit definition for ADC_JOFR3 register *******************/
#define ADC_JOFR3_JOFFSET3_Pos (0U)
#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
/****************** Bit definition for ADC_JOFR4 register *******************/
#define ADC_JOFR4_JOFFSET4_Pos (0U)
#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
/******************* Bit definition for ADC_HTR register ********************/
#define ADC_HTR_HT_Pos (0U)
#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
/******************* Bit definition for ADC_LTR register ********************/
#define ADC_LTR_LT_Pos (0U)
#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
/******************* Bit definition for ADC_SQR1 register *******************/
#define ADC_SQR1_L_Pos (20U)
#define ADC_SQR1_L_Msk (0x1FUL << ADC_SQR1_L_Pos) /*!< 0x01F00000 */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0 (0x01UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */
#define ADC_SQR1_L_1 (0x02UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */
#define ADC_SQR1_L_2 (0x04UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */
#define ADC_SQR1_L_3 (0x08UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */
#define ADC_SQR1_L_4 (0x10UL << ADC_SQR1_L_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ28_Pos (15U)
#define ADC_SQR1_SQ28_Msk (0x1FUL << ADC_SQR1_SQ28_Pos) /*!< 0x000F8000 */
#define ADC_SQR1_SQ28 ADC_SQR1_SQ28_Msk /*!< ADC group regular sequencer rank 28 */
#define ADC_SQR1_SQ28_0 (0x01UL << ADC_SQR1_SQ28_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ28_1 (0x02UL << ADC_SQR1_SQ28_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ28_2 (0x04UL << ADC_SQR1_SQ28_Pos) /*!< 0x00020000 */
#define ADC_SQR1_SQ28_3 (0x08UL << ADC_SQR1_SQ28_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ28_4 (0x10UL << ADC_SQR1_SQ28_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ27_Pos (10U)
#define ADC_SQR1_SQ27_Msk (0x1FUL << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */
#define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */
#define ADC_SQR1_SQ27_0 (0x01UL << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ27_1 (0x02UL << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */
#define ADC_SQR1_SQ27_2 (0x04UL << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ27_3 (0x08UL << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ27_4 (0x10UL << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ26_Pos (5U)
#define ADC_SQR1_SQ26_Msk (0x1FUL << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */
#define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */
#define ADC_SQR1_SQ26_0 (0x01UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */
#define ADC_SQR1_SQ26_1 (0x02UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ26_2 (0x04UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ26_3 (0x08UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ26_4 (0x10UL << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ25_Pos (0U)
#define ADC_SQR1_SQ25_Msk (0x1FUL << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */
#define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */
#define ADC_SQR1_SQ25_0 (0x01UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */
#define ADC_SQR1_SQ25_1 (0x02UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */
#define ADC_SQR1_SQ25_2 (0x04UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */
#define ADC_SQR1_SQ25_3 (0x08UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ25_4 (0x10UL << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */
/******************* Bit definition for ADC_SQR2 register *******************/
#define ADC_SQR2_SQ19_Pos (0U)
#define ADC_SQR2_SQ19_Msk (0x1FUL << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */
#define ADC_SQR2_SQ19_0 (0x01UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ19_1 (0x02UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ19_2 (0x04UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ19_3 (0x08UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ19_4 (0x10UL << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ20_Pos (5U)
#define ADC_SQR2_SQ20_Msk (0x1FUL << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */
#define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */
#define ADC_SQR2_SQ20_0 (0x01UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */
#define ADC_SQR2_SQ20_1 (0x02UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ20_2 (0x04UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ20_3 (0x08UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ20_4 (0x10UL << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ21_Pos (10U)
#define ADC_SQR2_SQ21_Msk (0x1FUL << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */
#define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */
#define ADC_SQR2_SQ21_0 (0x01UL << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ21_1 (0x02UL << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */
#define ADC_SQR2_SQ21_2 (0x04UL << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ21_3 (0x08UL << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ21_4 (0x10UL << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ22_Pos (15U)
#define ADC_SQR2_SQ22_Msk (0x1FUL << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */
#define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */
#define ADC_SQR2_SQ22_0 (0x01UL << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ22_1 (0x02UL << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ22_2 (0x04UL << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */
#define ADC_SQR2_SQ22_3 (0x08UL << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ22_4 (0x10UL << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ23_Pos (20U)
#define ADC_SQR2_SQ23_Msk (0x1FUL << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */
#define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */
#define ADC_SQR2_SQ23_0 (0x01UL << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ23_1 (0x02UL << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ23_2 (0x04UL << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ23_3 (0x08UL << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */
#define ADC_SQR2_SQ23_4 (0x10UL << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ24_Pos (25U)
#define ADC_SQR2_SQ24_Msk (0x1FUL << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */
#define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */
#define ADC_SQR2_SQ24_0 (0x01UL << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ24_1 (0x02UL << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ24_2 (0x04UL << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ24_3 (0x08UL << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */
#define ADC_SQR2_SQ24_4 (0x10UL << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */
/******************* Bit definition for ADC_SQR3 register *******************/
#define ADC_SQR3_SQ13_Pos (0U)
#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ14_Pos (5U)
#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */
#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ15_Pos (10U)
#define ADC_SQR3_SQ15_Msk (0x1FUL << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */
#define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR3_SQ15_0 (0x01UL << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ15_1 (0x02UL << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */
#define ADC_SQR3_SQ15_2 (0x04UL << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ15_3 (0x08UL << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ15_4 (0x10UL << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ16_Pos (15U)
#define ADC_SQR3_SQ16_Msk (0x1FUL << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */
#define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR3_SQ16_0 (0x01UL << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ16_1 (0x02UL << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ16_2 (0x04UL << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */
#define ADC_SQR3_SQ16_3 (0x08UL << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ16_4 (0x10UL << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ17_Pos (20U)
#define ADC_SQR3_SQ17_Msk (0x1FUL << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */
#define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */
#define ADC_SQR3_SQ17_0 (0x01UL << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ17_1 (0x02UL << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ17_2 (0x04UL << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ17_3 (0x08UL << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */
#define ADC_SQR3_SQ17_4 (0x10UL << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ18_Pos (25U)
#define ADC_SQR3_SQ18_Msk (0x1FUL << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */
#define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */
#define ADC_SQR3_SQ18_0 (0x01UL << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ18_1 (0x02UL << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ18_2 (0x04UL << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ18_3 (0x08UL << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */
#define ADC_SQR3_SQ18_4 (0x10UL << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */
/******************* Bit definition for ADC_SQR4 register *******************/
#define ADC_SQR4_SQ7_Pos (0U)
#define ADC_SQR4_SQ7_Msk (0x1FUL << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR4_SQ7_0 (0x01UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ7_1 (0x02UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ7_2 (0x04UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ7_3 (0x08UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ7_4 (0x10UL << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ8_Pos (5U)
#define ADC_SQR4_SQ8_Msk (0x1FUL << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */
#define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR4_SQ8_0 (0x01UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */
#define ADC_SQR4_SQ8_1 (0x02UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ8_2 (0x04UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ8_3 (0x08UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ8_4 (0x10UL << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ9_Pos (10U)
#define ADC_SQR4_SQ9_Msk (0x1FUL << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */
#define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR4_SQ9_0 (0x01UL << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */
#define ADC_SQR4_SQ9_1 (0x02UL << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */
#define ADC_SQR4_SQ9_2 (0x04UL << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */
#define ADC_SQR4_SQ9_3 (0x08UL << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */
#define ADC_SQR4_SQ9_4 (0x10UL << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */
#define ADC_SQR4_SQ10_Pos (15U)
#define ADC_SQR4_SQ10_Msk (0x1FUL << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */
#define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR4_SQ10_0 (0x01UL << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */
#define ADC_SQR4_SQ10_1 (0x02UL << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */
#define ADC_SQR4_SQ10_2 (0x04UL << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */
#define ADC_SQR4_SQ10_3 (0x08UL << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */
#define ADC_SQR4_SQ10_4 (0x10UL << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */
#define ADC_SQR4_SQ11_Pos (20U)
#define ADC_SQR4_SQ11_Msk (0x1FUL << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */
#define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR4_SQ11_0 (0x01UL << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */
#define ADC_SQR4_SQ11_1 (0x02UL << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */
#define ADC_SQR4_SQ11_2 (0x04UL << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */
#define ADC_SQR4_SQ11_3 (0x08UL << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */
#define ADC_SQR4_SQ11_4 (0x10UL << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */
#define ADC_SQR4_SQ12_Pos (25U)
#define ADC_SQR4_SQ12_Msk (0x1FUL << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */
#define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR4_SQ12_0 (0x01UL << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */
#define ADC_SQR4_SQ12_1 (0x02UL << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */
#define ADC_SQR4_SQ12_2 (0x04UL << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */
#define ADC_SQR4_SQ12_3 (0x08UL << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */
#define ADC_SQR4_SQ12_4 (0x10UL << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */
/******************* Bit definition for ADC_SQR5 register *******************/
#define ADC_SQR5_SQ1_Pos (0U)
#define ADC_SQR5_SQ1_Msk (0x1FUL << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */
#define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR5_SQ1_0 (0x01UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */
#define ADC_SQR5_SQ1_1 (0x02UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */
#define ADC_SQR5_SQ1_2 (0x04UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */
#define ADC_SQR5_SQ1_3 (0x08UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */
#define ADC_SQR5_SQ1_4 (0x10UL << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */
#define ADC_SQR5_SQ2_Pos (5U)
#define ADC_SQR5_SQ2_Msk (0x1FUL << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
#define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR5_SQ2_0 (0x01UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
#define ADC_SQR5_SQ2_1 (0x02UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
#define ADC_SQR5_SQ2_2 (0x04UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
#define ADC_SQR5_SQ2_3 (0x08UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
#define ADC_SQR5_SQ2_4 (0x10UL << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
#define ADC_SQR5_SQ3_Pos (10U)
#define ADC_SQR5_SQ3_Msk (0x1FUL << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */
#define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR5_SQ3_0 (0x01UL << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */
#define ADC_SQR5_SQ3_1 (0x02UL << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */
#define ADC_SQR5_SQ3_2 (0x04UL << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */
#define ADC_SQR5_SQ3_3 (0x08UL << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */
#define ADC_SQR5_SQ3_4 (0x10UL << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */
#define ADC_SQR5_SQ4_Pos (15U)
#define ADC_SQR5_SQ4_Msk (0x1FUL << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */
#define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR5_SQ4_0 (0x01UL << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */
#define ADC_SQR5_SQ4_1 (0x02UL << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */
#define ADC_SQR5_SQ4_2 (0x04UL << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */
#define ADC_SQR5_SQ4_3 (0x08UL << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */
#define ADC_SQR5_SQ4_4 (0x10UL << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */
#define ADC_SQR5_SQ5_Pos (20U)
#define ADC_SQR5_SQ5_Msk (0x1FUL << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */
#define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR5_SQ5_0 (0x01UL << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */
#define ADC_SQR5_SQ5_1 (0x02UL << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */
#define ADC_SQR5_SQ5_2 (0x04UL << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */
#define ADC_SQR5_SQ5_3 (0x08UL << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */
#define ADC_SQR5_SQ5_4 (0x10UL << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */
#define ADC_SQR5_SQ6_Pos (25U)
#define ADC_SQR5_SQ6_Msk (0x1FUL << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */
#define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR5_SQ6_0 (0x01UL << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */
#define ADC_SQR5_SQ6_1 (0x02UL << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */
#define ADC_SQR5_SQ6_2 (0x04UL << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */
#define ADC_SQR5_SQ6_3 (0x08UL << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */
#define ADC_SQR5_SQ6_4 (0x10UL << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */
/******************* Bit definition for ADC_JSQR register *******************/
#define ADC_JSQR_JSQ1_Pos (0U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JSQ2_Pos (5U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ3_Pos (10U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
#define ADC_JSQR_JSQ4_Pos (15U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
#define ADC_JSQR_JL_Pos (20U)
#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
/******************* Bit definition for ADC_JDR1 register *******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
/******************* Bit definition for ADC_JDR2 register *******************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
/******************* Bit definition for ADC_JDR3 register *******************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
/******************* Bit definition for ADC_JDR4 register *******************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_DATA_Pos (0U)
#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
/****************** Bit definition for ADC_SMPR0 register *******************/
#define ADC_SMPR0_SMP30_Pos (0U)
#define ADC_SMPR0_SMP30_Msk (0x7UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000007 */
#define ADC_SMPR0_SMP30 ADC_SMPR0_SMP30_Msk /*!< ADC channel 30 sampling time selection */
#define ADC_SMPR0_SMP30_0 (0x1UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000001 */
#define ADC_SMPR0_SMP30_1 (0x2UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000002 */
#define ADC_SMPR0_SMP30_2 (0x4UL << ADC_SMPR0_SMP30_Pos) /*!< 0x00000004 */
#define ADC_SMPR0_SMP31_Pos (3U)
#define ADC_SMPR0_SMP31_Msk (0x7UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000038 */
#define ADC_SMPR0_SMP31 ADC_SMPR0_SMP31_Msk /*!< ADC channel 31 sampling time selection */
#define ADC_SMPR0_SMP31_0 (0x1UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000008 */
#define ADC_SMPR0_SMP31_1 (0x2UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000010 */
#define ADC_SMPR0_SMP31_2 (0x4UL << ADC_SMPR0_SMP31_Pos) /*!< 0x00000020 */
/******************* Bit definition for ADC_CSR register ********************/
#define ADC_CSR_AWD1_Pos (0U)
#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_EOCS1_Pos (1U)
#define ADC_CSR_EOCS1_Msk (0x1UL << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */
#define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
#define ADC_CSR_JEOS1_Pos (2U)
#define ADC_CSR_JEOS1_Msk (0x1UL << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */
#define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_JSTRT1_Pos (3U)
#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */
#define ADC_CSR_STRT1_Pos (4U)
#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */
#define ADC_CSR_OVR1_Pos (5U)
#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_ADONS1_Pos (6U)
#define ADC_CSR_ADONS1_Msk (0x1UL << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */
#define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */
/* Legacy defines */
#define ADC_CSR_EOC1 (ADC_CSR_EOCS1)
#define ADC_CSR_JEOC1 (ADC_CSR_JEOS1)
/******************* Bit definition for ADC_CCR register ********************/
#define ADC_CCR_ADCPRE_Pos (16U)
#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */
#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
#define ADC_CCR_TSVREFE_Pos (23U)
#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
/****************** Bit definition for COMP_CSR register ********************/
#define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */
#define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */
#define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */
#define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */
#define COMP_CSR_CMP1EN_Pos (4U)
#define COMP_CSR_CMP1EN_Msk (0x1UL << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */
#define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */
#define COMP_CSR_CMP1OUT_Pos (7U)
#define COMP_CSR_CMP1OUT_Msk (0x1UL << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */
#define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */
#define COMP_CSR_SPEED_Pos (12U)
#define COMP_CSR_SPEED_Msk (0x1UL << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */
#define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */
#define COMP_CSR_CMP2OUT_Pos (13U)
#define COMP_CSR_CMP2OUT_Msk (0x1UL << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */
#define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */
#define COMP_CSR_WNDWE_Pos (17U)
#define COMP_CSR_WNDWE_Msk (0x1UL << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */
#define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
#define COMP_CSR_INSEL_Pos (18U)
#define COMP_CSR_INSEL_Msk (0x7UL << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
#define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */
#define COMP_CSR_INSEL_0 (0x1UL << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
#define COMP_CSR_INSEL_1 (0x2UL << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
#define COMP_CSR_INSEL_2 (0x4UL << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
#define COMP_CSR_OUTSEL_Pos (21U)
#define COMP_CSR_OUTSEL_Msk (0x7UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */
#define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */
#define COMP_CSR_OUTSEL_0 (0x1UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */
#define COMP_CSR_OUTSEL_1 (0x2UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */
#define COMP_CSR_OUTSEL_2 (0x4UL << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */
/* Bits present in COMP register but not related to comparator */
/* (or partially related to comparator, in addition to other peripherals) */
#define COMP_CSR_SW1_Pos (5U)
#define COMP_CSR_SW1_Msk (0x1UL << COMP_CSR_SW1_Pos) /*!< 0x00000020 */
#define COMP_CSR_SW1 COMP_CSR_SW1_Msk /*!< SW1 analog switch enable */
#define COMP_CSR_VREFOUTEN_Pos (16U)
#define COMP_CSR_VREFOUTEN_Msk (0x1UL << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */
#define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */
#define COMP_CSR_FCH3_Pos (26U)
#define COMP_CSR_FCH3_Msk (0x1UL << COMP_CSR_FCH3_Pos) /*!< 0x04000000 */
#define COMP_CSR_FCH3 COMP_CSR_FCH3_Msk /*!< Bit 26 */
#define COMP_CSR_FCH8_Pos (27U)
#define COMP_CSR_FCH8_Msk (0x1UL << COMP_CSR_FCH8_Pos) /*!< 0x08000000 */
#define COMP_CSR_FCH8 COMP_CSR_FCH8_Msk /*!< Bit 27 */
#define COMP_CSR_RCH13_Pos (28U)
#define COMP_CSR_RCH13_Msk (0x1UL << COMP_CSR_RCH13_Pos) /*!< 0x10000000 */
#define COMP_CSR_RCH13 COMP_CSR_RCH13_Msk /*!< Bit 28 */
#define COMP_CSR_CAIE_Pos (29U)
#define COMP_CSR_CAIE_Msk (0x1UL << COMP_CSR_CAIE_Pos) /*!< 0x20000000 */
#define COMP_CSR_CAIE COMP_CSR_CAIE_Msk /*!< Bit 29 */
#define COMP_CSR_CAIF_Pos (30U)
#define COMP_CSR_CAIF_Msk (0x1UL << COMP_CSR_CAIF_Pos) /*!< 0x40000000 */
#define COMP_CSR_CAIF COMP_CSR_CAIF_Msk /*!< Bit 30 */
#define COMP_CSR_TSUSP_Pos (31U)
#define COMP_CSR_TSUSP_Msk (0x1UL << COMP_CSR_TSUSP_Pos) /*!< 0x80000000 */
#define COMP_CSR_TSUSP COMP_CSR_TSUSP_Msk /*!< Bit 31 */
/******************************************************************************/
/* */
/* Operational Amplifier (OPAMP) */
/* */
/******************************************************************************/
/******************* Bit definition for OPAMP_CSR register ******************/
#define OPAMP_CSR_OPA1PD_Pos (0U)
#define OPAMP_CSR_OPA1PD_Msk (0x1UL << OPAMP_CSR_OPA1PD_Pos) /*!< 0x00000001 */
#define OPAMP_CSR_OPA1PD OPAMP_CSR_OPA1PD_Msk /*!< OPAMP1 disable */
#define OPAMP_CSR_S3SEL1_Pos (1U)
#define OPAMP_CSR_S3SEL1_Msk (0x1UL << OPAMP_CSR_S3SEL1_Pos) /*!< 0x00000002 */
#define OPAMP_CSR_S3SEL1 OPAMP_CSR_S3SEL1_Msk /*!< Switch 3 for OPAMP1 Enable */
#define OPAMP_CSR_S4SEL1_Pos (2U)
#define OPAMP_CSR_S4SEL1_Msk (0x1UL << OPAMP_CSR_S4SEL1_Pos) /*!< 0x00000004 */
#define OPAMP_CSR_S4SEL1 OPAMP_CSR_S4SEL1_Msk /*!< Switch 4 for OPAMP1 Enable */
#define OPAMP_CSR_S5SEL1_Pos (3U)
#define OPAMP_CSR_S5SEL1_Msk (0x1UL << OPAMP_CSR_S5SEL1_Pos) /*!< 0x00000008 */
#define OPAMP_CSR_S5SEL1 OPAMP_CSR_S5SEL1_Msk /*!< Switch 5 for OPAMP1 Enable */
#define OPAMP_CSR_S6SEL1_Pos (4U)
#define OPAMP_CSR_S6SEL1_Msk (0x1UL << OPAMP_CSR_S6SEL1_Pos) /*!< 0x00000010 */
#define OPAMP_CSR_S6SEL1 OPAMP_CSR_S6SEL1_Msk /*!< Switch 6 for OPAMP1 Enable */
#define OPAMP_CSR_OPA1CAL_L_Pos (5U)
#define OPAMP_CSR_OPA1CAL_L_Msk (0x1UL << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
#define OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_L_Msk /*!< OPAMP1 Offset calibration for P differential pair */
#define OPAMP_CSR_OPA1CAL_H_Pos (6U)
#define OPAMP_CSR_OPA1CAL_H_Msk (0x1UL << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
#define OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1CAL_H_Msk /*!< OPAMP1 Offset calibration for N differential pair */
#define OPAMP_CSR_OPA1LPM_Pos (7U)
#define OPAMP_CSR_OPA1LPM_Msk (0x1UL << OPAMP_CSR_OPA1LPM_Pos) /*!< 0x00000080 */
#define OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA1LPM_Msk /*!< OPAMP1 Low power enable */
#define OPAMP_CSR_OPA2PD_Pos (8U)
#define OPAMP_CSR_OPA2PD_Msk (0x1UL << OPAMP_CSR_OPA2PD_Pos) /*!< 0x00000100 */
#define OPAMP_CSR_OPA2PD OPAMP_CSR_OPA2PD_Msk /*!< OPAMP2 disable */
#define OPAMP_CSR_S3SEL2_Pos (9U)
#define OPAMP_CSR_S3SEL2_Msk (0x1UL << OPAMP_CSR_S3SEL2_Pos) /*!< 0x00000200 */
#define OPAMP_CSR_S3SEL2 OPAMP_CSR_S3SEL2_Msk /*!< Switch 3 for OPAMP2 Enable */
#define OPAMP_CSR_S4SEL2_Pos (10U)
#define OPAMP_CSR_S4SEL2_Msk (0x1UL << OPAMP_CSR_S4SEL2_Pos) /*!< 0x00000400 */
#define OPAMP_CSR_S4SEL2 OPAMP_CSR_S4SEL2_Msk /*!< Switch 4 for OPAMP2 Enable */
#define OPAMP_CSR_S5SEL2_Pos (11U)
#define OPAMP_CSR_S5SEL2_Msk (0x1UL << OPAMP_CSR_S5SEL2_Pos) /*!< 0x00000800 */
#define OPAMP_CSR_S5SEL2 OPAMP_CSR_S5SEL2_Msk /*!< Switch 5 for OPAMP2 Enable */
#define OPAMP_CSR_S6SEL2_Pos (12U)
#define OPAMP_CSR_S6SEL2_Msk (0x1UL << OPAMP_CSR_S6SEL2_Pos) /*!< 0x00001000 */
#define OPAMP_CSR_S6SEL2 OPAMP_CSR_S6SEL2_Msk /*!< Switch 6 for OPAMP2 Enable */
#define OPAMP_CSR_OPA2CAL_L_Pos (13U)
#define OPAMP_CSR_OPA2CAL_L_Msk (0x1UL << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
#define OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_L_Msk /*!< OPAMP2 Offset calibration for P differential pair */
#define OPAMP_CSR_OPA2CAL_H_Pos (14U)
#define OPAMP_CSR_OPA2CAL_H_Msk (0x1UL << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
#define OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2CAL_H_Msk /*!< OPAMP2 Offset calibration for N differential pair */
#define OPAMP_CSR_OPA2LPM_Pos (15U)
#define OPAMP_CSR_OPA2LPM_Msk (0x1UL << OPAMP_CSR_OPA2LPM_Pos) /*!< 0x00008000 */
#define OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA2LPM_Msk /*!< OPAMP2 Low power enable */
#define OPAMP_CSR_OPA3PD_Pos (16U)
#define OPAMP_CSR_OPA3PD_Msk (0x1UL << OPAMP_CSR_OPA3PD_Pos) /*!< 0x00010000 */
#define OPAMP_CSR_OPA3PD OPAMP_CSR_OPA3PD_Msk /*!< OPAMP3 disable */
#define OPAMP_CSR_S3SEL3_Pos (17U)
#define OPAMP_CSR_S3SEL3_Msk (0x1UL << OPAMP_CSR_S3SEL3_Pos) /*!< 0x00020000 */
#define OPAMP_CSR_S3SEL3 OPAMP_CSR_S3SEL3_Msk /*!< Switch 3 for OPAMP3 Enable */
#define OPAMP_CSR_S4SEL3_Pos (18U)
#define OPAMP_CSR_S4SEL3_Msk (0x1UL << OPAMP_CSR_S4SEL3_Pos) /*!< 0x00040000 */
#define OPAMP_CSR_S4SEL3 OPAMP_CSR_S4SEL3_Msk /*!< Switch 4 for OPAMP3 Enable */
#define OPAMP_CSR_S5SEL3_Pos (19U)
#define OPAMP_CSR_S5SEL3_Msk (0x1UL << OPAMP_CSR_S5SEL3_Pos) /*!< 0x00080000 */
#define OPAMP_CSR_S5SEL3 OPAMP_CSR_S5SEL3_Msk /*!< Switch 5 for OPAMP3 Enable */
#define OPAMP_CSR_S6SEL3_Pos (20U)
#define OPAMP_CSR_S6SEL3_Msk (0x1UL << OPAMP_CSR_S6SEL3_Pos) /*!< 0x00100000 */
#define OPAMP_CSR_S6SEL3 OPAMP_CSR_S6SEL3_Msk /*!< Switch 6 for OPAMP3 Enable */
#define OPAMP_CSR_OPA3CAL_L_Pos (21U)
#define OPAMP_CSR_OPA3CAL_L_Msk (0x1UL << OPAMP_CSR_OPA3CAL_L_Pos) /*!< 0x00200000 */
#define OPAMP_CSR_OPA3CAL_L OPAMP_CSR_OPA3CAL_L_Msk /*!< OPAMP3 Offset calibration for P differential pair */
#define OPAMP_CSR_OPA3CAL_H_Pos (22U)
#define OPAMP_CSR_OPA3CAL_H_Msk (0x1UL << OPAMP_CSR_OPA3CAL_H_Pos) /*!< 0x00400000 */
#define OPAMP_CSR_OPA3CAL_H OPAMP_CSR_OPA3CAL_H_Msk /*!< OPAMP3 Offset calibration for N differential pair */
#define OPAMP_CSR_OPA3LPM_Pos (23U)
#define OPAMP_CSR_OPA3LPM_Msk (0x1UL << OPAMP_CSR_OPA3LPM_Pos) /*!< 0x00800000 */
#define OPAMP_CSR_OPA3LPM OPAMP_CSR_OPA3LPM_Msk /*!< OPAMP3 Low power enable */
#define OPAMP_CSR_ANAWSEL1_Pos (24U)
#define OPAMP_CSR_ANAWSEL1_Msk (0x1UL << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
#define OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL1_Msk /*!< Switch ANA Enable for OPAMP1 */
#define OPAMP_CSR_ANAWSEL2_Pos (25U)
#define OPAMP_CSR_ANAWSEL2_Msk (0x1UL << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
#define OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL2_Msk /*!< Switch ANA Enable for OPAMP2 */
#define OPAMP_CSR_ANAWSEL3_Pos (26U)
#define OPAMP_CSR_ANAWSEL3_Msk (0x1UL << OPAMP_CSR_ANAWSEL3_Pos) /*!< 0x04000000 */
#define OPAMP_CSR_ANAWSEL3 OPAMP_CSR_ANAWSEL3_Msk /*!< Switch ANA Enable for OPAMP3 */
#define OPAMP_CSR_S7SEL2_Pos (27U)
#define OPAMP_CSR_S7SEL2_Msk (0x1UL << OPAMP_CSR_S7SEL2_Pos) /*!< 0x08000000 */
#define OPAMP_CSR_S7SEL2 OPAMP_CSR_S7SEL2_Msk /*!< Switch 7 for OPAMP2 Enable */
#define OPAMP_CSR_AOP_RANGE_Pos (28U)
#define OPAMP_CSR_AOP_RANGE_Msk (0x1UL << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
#define OPAMP_CSR_AOP_RANGE OPAMP_CSR_AOP_RANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
#define OPAMP_CSR_OPA1CALOUT_Pos (29U)
#define OPAMP_CSR_OPA1CALOUT_Msk (0x1UL << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
#define OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA1CALOUT_Msk /*!< OPAMP1 calibration output */
#define OPAMP_CSR_OPA2CALOUT_Pos (30U)
#define OPAMP_CSR_OPA2CALOUT_Msk (0x1UL << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
#define OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA2CALOUT_Msk /*!< OPAMP2 calibration output */
#define OPAMP_CSR_OPA3CALOUT_Pos (31U)
#define OPAMP_CSR_OPA3CALOUT_Msk (0x1UL << OPAMP_CSR_OPA3CALOUT_Pos) /*!< 0x80000000 */
#define OPAMP_CSR_OPA3CALOUT OPAMP_CSR_OPA3CALOUT_Msk /*!< OPAMP3 calibration output */
/******************* Bit definition for OPAMP_OTR register ******************/
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos (20U)
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x01F00000 */
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos (25U)
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x3E000000 */
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */
#define OPAMP_OTR_OT_USER_Pos (31U)
#define OPAMP_OTR_OT_USER_Msk (0x1UL << OPAMP_OTR_OT_USER_Pos) /*!< 0x80000000 */
#define OPAMP_OTR_OT_USER OPAMP_OTR_OT_USER_Msk /*!< Switch to OPAMP offset user trimmed values */
/******************* Bit definition for OPAMP_LPOTR register ****************/
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos (20U)
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x01F00000 */
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP3 */
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos (25U)
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FUL << OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x3E000000 */
#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO3_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP3 */
/******************************************************************************/
/* */
/* CRC calculation unit (CRC) */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
/******************************************************************************/
/* */
/* Digital to Analog Converter (DAC) */
/* */
/******************************************************************************/
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
#define DAC_CR_BOFF1_Pos (1U)
#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
#define DAC_CR_TEN1_Pos (2U)
#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos (3U)
#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos (6U)
#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos (8U)
#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos (12U)
#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos (13U)
#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA Interrupt enable */
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
#define DAC_CR_BOFF2_Pos (17U)
#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
#define DAC_CR_TEN2_Pos (18U)
#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos (19U)
#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos (22U)
#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos (24U)
#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos (28U)
#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos (29U)
#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR_Pos (0U)
#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR_Pos (4U)
#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR_Pos (0U)
#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR_Pos (0U)
#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR_Pos (4U)
#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR_Pos (0U)
#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR_Pos (0U)
#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos (16U)
#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR_Pos (4U)
#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos (20U)
#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR_Pos (0U)
#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR_Pos (8U)
#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR_Pos (0U)
#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR_Pos (0U)
#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DMAUDR1_Pos (13U)
#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_DMAUDR2_Pos (29U)
#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
/******************************************************************************/
/* */
/* Debug MCU (DBGMCU) */
/* */
/******************************************************************************/
/**************** Bit definition for DBGMCU_IDCODE register *****************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
/****************** Bit definition for DBGMCU_CR register *******************/
#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
#define DBGMCU_CR_DBG_STOP_Pos (1U)
#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
#define DBGMCU_CR_TRACE_MODE_Pos (6U)
#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
/****************** Bit definition for DBGMCU_APB1_FZ register **************/
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
/****************** Bit definition for DBGMCU_APB2_FZ register **************/
#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U)
#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U)
#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U)
#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
/******************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
#define DMA_ISR_GIF1_Pos (0U)
#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1_Pos (1U)
#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1_Pos (2U)
#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1_Pos (3U)
#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2_Pos (4U)
#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2_Pos (5U)
#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2_Pos (6U)
#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2_Pos (7U)
#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3_Pos (8U)
#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3_Pos (9U)
#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3_Pos (10U)
#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3_Pos (11U)
#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4_Pos (12U)
#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4_Pos (13U)
#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4_Pos (14U)
#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4_Pos (15U)
#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5_Pos (16U)
#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos (20U)
#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6_Pos (21U)
#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6_Pos (22U)
#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6_Pos (23U)
#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
#define DMA_ISR_GIF7_Pos (24U)
#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
#define DMA_ISR_TCIF7_Pos (25U)
#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
#define DMA_ISR_HTIF7_Pos (26U)
#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
#define DMA_ISR_TEIF7_Pos (27U)
#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
#define DMA_IFCR_CGIF1_Pos (0U)
#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
#define DMA_IFCR_CTCIF1_Pos (1U)
#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1_Pos (2U)
#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1_Pos (3U)
#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2_Pos (4U)
#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2_Pos (5U)
#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2_Pos (6U)
#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2_Pos (7U)
#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3_Pos (8U)
#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3_Pos (9U)
#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3_Pos (10U)
#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4_Pos (12U)
#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4_Pos (13U)
#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4_Pos (14U)
#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4_Pos (15U)
#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos (16U)
#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos (20U)
#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6_Pos (21U)
#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6_Pos (22U)
#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6_Pos (23U)
#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
#define DMA_IFCR_CGIF7_Pos (24U)
#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
#define DMA_IFCR_CTCIF7_Pos (25U)
#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
#define DMA_IFCR_CHTIF7_Pos (26U)
#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
#define DMA_IFCR_CTEIF7_Pos (27U)
#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
/******************* Bit definition for DMA_CCR register *******************/
#define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable*/
#define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (2U)
#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE_Pos (3U)
#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR_Pos (4U)
#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
#define DMA_CCR_CIRC_Pos (5U)
#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
#define DMA_CCR_PINC_Pos (6U)
#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
#define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
#define DMA_CCR_MSIZE_Pos (10U)
#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
#define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
#define DMA_CCR_MEM2MEM_Pos (14U)
#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
/****************** Bit definition generic for DMA_CNDTR register *******************/
#define DMA_CNDTR_NDT_Pos (0U)
#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR1 register ******************/
#define DMA_CNDTR1_NDT_Pos (0U)
#define DMA_CNDTR1_NDT_Msk (0xFFFFUL << DMA_CNDTR1_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR2 register ******************/
#define DMA_CNDTR2_NDT_Pos (0U)
#define DMA_CNDTR2_NDT_Msk (0xFFFFUL << DMA_CNDTR2_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR3 register ******************/
#define DMA_CNDTR3_NDT_Pos (0U)
#define DMA_CNDTR3_NDT_Msk (0xFFFFUL << DMA_CNDTR3_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR4 register ******************/
#define DMA_CNDTR4_NDT_Pos (0U)
#define DMA_CNDTR4_NDT_Msk (0xFFFFUL << DMA_CNDTR4_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR5 register ******************/
#define DMA_CNDTR5_NDT_Pos (0U)
#define DMA_CNDTR5_NDT_Msk (0xFFFFUL << DMA_CNDTR5_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR6 register ******************/
#define DMA_CNDTR6_NDT_Pos (0U)
#define DMA_CNDTR6_NDT_Msk (0xFFFFUL << DMA_CNDTR6_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CNDTR7 register ******************/
#define DMA_CNDTR7_NDT_Pos (0U)
#define DMA_CNDTR7_NDT_Msk (0xFFFFUL << DMA_CNDTR7_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition generic for DMA_CPAR register ********************/
#define DMA_CPAR_PA_Pos (0U)
#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR1 register *******************/
#define DMA_CPAR1_PA_Pos (0U)
#define DMA_CPAR1_PA_Msk (0xFFFFFFFFUL << DMA_CPAR1_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR2 register *******************/
#define DMA_CPAR2_PA_Pos (0U)
#define DMA_CPAR2_PA_Msk (0xFFFFFFFFUL << DMA_CPAR2_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR3 register *******************/
#define DMA_CPAR3_PA_Pos (0U)
#define DMA_CPAR3_PA_Msk (0xFFFFFFFFUL << DMA_CPAR3_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR4 register *******************/
#define DMA_CPAR4_PA_Pos (0U)
#define DMA_CPAR4_PA_Msk (0xFFFFFFFFUL << DMA_CPAR4_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR5 register *******************/
#define DMA_CPAR5_PA_Pos (0U)
#define DMA_CPAR5_PA_Msk (0xFFFFFFFFUL << DMA_CPAR5_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR6 register *******************/
#define DMA_CPAR6_PA_Pos (0U)
#define DMA_CPAR6_PA_Msk (0xFFFFFFFFUL << DMA_CPAR6_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CPAR7 register *******************/
#define DMA_CPAR7_PA_Pos (0U)
#define DMA_CPAR7_PA_Msk (0xFFFFFFFFUL << DMA_CPAR7_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /*!< Peripheral Address */
/****************** Bit definition generic for DMA_CMAR register ********************/
#define DMA_CMAR_MA_Pos (0U)
#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
/****************** Bit definition for DMA_CMAR1 register *******************/
#define DMA_CMAR1_MA_Pos (0U)
#define DMA_CMAR1_MA_Msk (0xFFFFFFFFUL << DMA_CMAR1_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /*!< Memory Address */
/****************** Bit definition for DMA_CMAR2 register *******************/
#define DMA_CMAR2_MA_Pos (0U)
#define DMA_CMAR2_MA_Msk (0xFFFFFFFFUL << DMA_CMAR2_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /*!< Memory Address */
/****************** Bit definition for DMA_CMAR3 register *******************/
#define DMA_CMAR3_MA_Pos (0U)
#define DMA_CMAR3_MA_Msk (0xFFFFFFFFUL << DMA_CMAR3_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /*!< Memory Address */
/****************** Bit definition for DMA_CMAR4 register *******************/
#define DMA_CMAR4_MA_Pos (0U)
#define DMA_CMAR4_MA_Msk (0xFFFFFFFFUL << DMA_CMAR4_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /*!< Memory Address */
/****************** Bit definition for DMA_CMAR5 register *******************/
#define DMA_CMAR5_MA_Pos (0U)
#define DMA_CMAR5_MA_Msk (0xFFFFFFFFUL << DMA_CMAR5_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /*!< Memory Address */
/****************** Bit definition for DMA_CMAR6 register *******************/
#define DMA_CMAR6_MA_Pos (0U)
#define DMA_CMAR6_MA_Msk (0xFFFFFFFFUL << DMA_CMAR6_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /*!< Memory Address */
/****************** Bit definition for DMA_CMAR7 register *******************/
#define DMA_CMAR7_MA_Pos (0U)
#define DMA_CMAR7_MA_Msk (0xFFFFFFFFUL << DMA_CMAR7_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /*!< Memory Address */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0_Pos (0U)
#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1_Pos (1U)
#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2_Pos (2U)
#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR_MR3_Pos (3U)
#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR_MR4_Pos (4U)
#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR_MR5_Pos (5U)
#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */