| /** |
| ****************************************************************************** |
| * @file stm32l4r9xx.h |
| * @author MCD Application Team |
| * @brief CMSIS STM32L4R9xx Device Peripheral Access Layer Header File. |
| * |
| * This file contains: |
| * - Data structures and the address mapping for all peripherals |
| * - Peripheral's registers declarations and bits definition |
| * - Macros to access peripheral's registers hardware |
| * |
| ****************************************************************************** |
| * @attention |
| * |
| * Copyright (c) 2017 STMicroelectronics. |
| * All rights reserved. |
| * |
| * This software is licensed under terms that can be found in the LICENSE file |
| * in the root directory of this software component. |
| * If no LICENSE file comes with this software, it is provided AS-IS. |
| * |
| ****************************************************************************** |
| */ |
| |
| /** @addtogroup CMSIS_Device |
| * @{ |
| */ |
| |
| /** @addtogroup stm32l4r9xx |
| * @{ |
| */ |
| |
| #ifndef __STM32L4R9xx_H |
| #define __STM32L4R9xx_H |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif /* __cplusplus */ |
| |
| /** @addtogroup Configuration_section_for_CMSIS |
| * @{ |
| */ |
| |
| /** |
| * @brief Configuration of the Cortex-M4 Processor and Core Peripherals |
| */ |
| #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ |
| #define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */ |
| #define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */ |
| #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ |
| #define __FPU_PRESENT 1U /*!< FPU present */ |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_interrupt_number_definition |
| * @{ |
| */ |
| |
| /** |
| * @brief STM32L4XX Interrupt Number Definition, according to the selected device |
| * in @ref Library_configuration_section |
| */ |
| typedef enum |
| { |
| /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ |
| NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ |
| HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ |
| MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
| BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ |
| UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ |
| SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ |
| DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ |
| PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ |
| SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ |
| /****** STM32 specific Interrupt Numbers **********************************************************************/ |
| WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ |
| TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ |
| RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ |
| FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
| RCC_IRQn = 5, /*!< RCC global Interrupt */ |
| EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
| EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
| EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
| EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
| EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
| DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
| DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
| DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
| DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
| DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
| DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
| DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
| ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
| CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ |
| CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ |
| CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ |
| TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ |
| TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */ |
| TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ |
| DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */ |
| TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ |
| TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ |
| TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ |
| TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
| FMC_IRQn = 48, /*!< FMC global Interrupt */ |
| SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ |
| TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
| UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
| TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ |
| TIM7_IRQn = 55, /*!< TIM7 global interrupt */ |
| DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
| DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
| DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
| DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ |
| DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ |
| DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ |
| DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ |
| DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */ |
| COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ |
| LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ |
| LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ |
| OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ |
| DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ |
| DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ |
| LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ |
| OCTOSPI1_IRQn = 71, /*!< OctoSPI1 global interrupt */ |
| I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ |
| I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ |
| SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ |
| SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */ |
| OCTOSPI2_IRQn = 76, /*!< OctoSPI2 global interrupt */ |
| TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ |
| DSI_IRQn = 78, /*!< DSI global Interrupt */ |
| RNG_IRQn = 80, /*!< RNG global interrupt */ |
| FPU_IRQn = 81, /*!< FPU global interrupt */ |
| CRS_IRQn = 82, /*!< CRS global interrupt */ |
| I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */ |
| I2C4_EV_IRQn = 84, /*!< I2C4 Event interrupt */ |
| DCMI_IRQn = 85, /*!< DCMI global interrupt */ |
| DMA2D_IRQn = 90, /*!< DMA2D global interrupt */ |
| LTDC_IRQn = 91, /*!< LTDC global Interrupt */ |
| LTDC_ER_IRQn = 92, /*!< LTDC Error global Interrupt */ |
| GFXMMU_IRQn = 93, /*!< GFXMMU global error interrupt */ |
| DMAMUX1_OVR_IRQn = 94 /*!< DMAMUX1 overrun global interrupt */ |
| } IRQn_Type; |
| |
| /** |
| * @} |
| */ |
| |
| #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
| #include "system_stm32l4xx.h" |
| #include <stdint.h> |
| |
| /** @addtogroup Peripheral_registers_structures |
| * @{ |
| */ |
| |
| /** |
| * @brief Analog to Digital Converter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ |
| __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ |
| __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ |
| __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ |
| __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ |
| __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ |
| __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ |
| uint32_t RESERVED1; /*!< Reserved, 0x1C */ |
| __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ |
| __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ |
| __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x2C */ |
| __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ |
| __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ |
| __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ |
| __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ |
| __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ |
| uint32_t RESERVED3; /*!< Reserved, 0x44 */ |
| uint32_t RESERVED4; /*!< Reserved, 0x48 */ |
| __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ |
| uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ |
| __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ |
| __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ |
| __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ |
| __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ |
| uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ |
| __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ |
| __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ |
| __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ |
| __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ |
| uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ |
| __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ |
| __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ |
| uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ |
| uint32_t RESERVED9; /*!< Reserved, 0x0AC */ |
| __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ |
| __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ |
| |
| } ADC_TypeDef; |
| |
| typedef struct |
| { |
| uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ |
| uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ |
| __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ |
| uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ |
| } ADC_Common_TypeDef; |
| |
| /** |
| * @brief DCMI |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< DCMI control register, Address offset: 0x00 */ |
| __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ |
| __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ |
| __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ |
| __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ |
| __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ |
| __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ |
| __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ |
| __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ |
| __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ |
| __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ |
| } DCMI_TypeDef; |
| |
| /** |
| * @brief Controller Area Network TxMailBox |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ |
| __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ |
| __IO uint32_t TDLR; /*!< CAN mailbox data low register */ |
| __IO uint32_t TDHR; /*!< CAN mailbox data high register */ |
| } CAN_TxMailBox_TypeDef; |
| |
| /** |
| * @brief Controller Area Network FIFOMailBox |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ |
| __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ |
| __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ |
| __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ |
| } CAN_FIFOMailBox_TypeDef; |
| |
| /** |
| * @brief Controller Area Network FilterRegister |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ |
| __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ |
| } CAN_FilterRegister_TypeDef; |
| |
| /** |
| * @brief Controller Area Network |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ |
| __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ |
| __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ |
| __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ |
| __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ |
| __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ |
| __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ |
| __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ |
| uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ |
| CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ |
| CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ |
| uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ |
| __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ |
| __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x208 */ |
| __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ |
| uint32_t RESERVED3; /*!< Reserved, 0x210 */ |
| __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ |
| uint32_t RESERVED4; /*!< Reserved, 0x218 */ |
| __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ |
| uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ |
| CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ |
| } CAN_TypeDef; |
| |
| |
| /** |
| * @brief Comparator |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ |
| } COMP_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ |
| } COMP_Common_TypeDef; |
| |
| /** |
| * @brief CRC calculation unit |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x0C */ |
| __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ |
| __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ |
| } CRC_TypeDef; |
| |
| /** |
| * @brief Clock Recovery System |
| */ |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ |
| __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ |
| __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ |
| __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ |
| } CRS_TypeDef; |
| |
| /** |
| * @brief Digital to Analog Converter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ |
| __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ |
| __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ |
| __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ |
| __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ |
| __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ |
| __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ |
| __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ |
| __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ |
| __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ |
| __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ |
| __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ |
| __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ |
| __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ |
| __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ |
| __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ |
| __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ |
| __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ |
| __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ |
| __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ |
| } DAC_TypeDef; |
| |
| /** |
| * @brief DFSDM module registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ |
| __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ |
| __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ |
| __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ |
| __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ |
| __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ |
| __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ |
| __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ |
| __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ |
| __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ |
| __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ |
| __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ |
| __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ |
| __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ |
| __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ |
| } DFSDM_Filter_TypeDef; |
| |
| /** |
| * @brief DFSDM channel configuration registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ |
| __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ |
| __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and |
| short circuit detector register, Address offset: 0x08 */ |
| __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ |
| __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ |
| __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ |
| } DFSDM_Channel_TypeDef; |
| |
| /** |
| * @brief Debug MCU |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ |
| __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ |
| __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ |
| } DBGMCU_TypeDef; |
| |
| |
| /** |
| * @brief DMA Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CCR; /*!< DMA channel x configuration register */ |
| __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ |
| __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ |
| __IO uint32_t CMAR; /*!< DMA channel x memory address register */ |
| } DMA_Channel_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ |
| __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ |
| } DMA_TypeDef; |
| |
| /** |
| * @brief DMA Multiplexer |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ |
| }DMAMUX_Channel_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ |
| __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ |
| }DMAMUX_ChannelStatus_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ |
| }DMAMUX_RequestGen_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ |
| __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ |
| }DMAMUX_RequestGenStatus_TypeDef; |
| |
| |
| /** |
| * @brief DMA2D Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ |
| __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ |
| __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ |
| __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ |
| __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ |
| __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ |
| __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ |
| __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ |
| __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ |
| __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ |
| __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ |
| __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ |
| __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ |
| __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ |
| __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ |
| __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ |
| __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ |
| __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ |
| __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ |
| __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ |
| uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ |
| __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ |
| __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ |
| } DMA2D_TypeDef; |
| |
| /** |
| * @brief DSI Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ |
| __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ |
| __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ |
| __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ |
| __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ |
| __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ |
| __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ |
| uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ |
| __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ |
| __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ |
| __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ |
| __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ |
| __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ |
| __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ |
| __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ |
| __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ |
| __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ |
| __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ |
| __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ |
| __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ |
| __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ |
| __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ |
| __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ |
| __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ |
| __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ |
| __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ |
| __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ |
| __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ |
| uint32_t RESERVED1; /*!< Reserved, 0x90 */ |
| __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ |
| __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ |
| __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ |
| __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ |
| __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ |
| __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ |
| __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ |
| __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ |
| uint32_t RESERVED2[2]; /*!< Reserved, 0xB4 - 0xBB */ |
| __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ |
| __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ |
| uint32_t RESERVED3[3]; /*!< Reserved, 0xD0 - 0xD7 */ |
| __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ |
| uint32_t RESERVED4[8]; /*!< Reserved, 0xE0 - 0xFF */ |
| __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ |
| uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */ |
| __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ |
| __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ |
| uint32_t RESERVED6; /*!< Reserved, 0x114 */ |
| __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ |
| uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */ |
| __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ |
| __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ |
| __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ |
| __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ |
| __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ |
| __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ |
| __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ |
| __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ |
| __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ |
| __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ |
| __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ |
| uint32_t RESERVED8[167]; /*!< Reserved, 0x164 - 0x3FF */ |
| __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ |
| __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ |
| __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ |
| __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ |
| __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ |
| uint32_t RESERVED9; /*!< Reserved, 0x414 */ |
| __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ |
| uint32_t RESERVED10; /*!< Reserved, 0x42C */ |
| __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ |
| } DSI_TypeDef; |
| |
| /** |
| * @brief External Interrupt/Event Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ |
| __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ |
| __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ |
| __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ |
| __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ |
| __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ |
| uint32_t RESERVED1; /*!< Reserved, 0x18 */ |
| uint32_t RESERVED2; /*!< Reserved, 0x1C */ |
| __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ |
| __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ |
| __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ |
| __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ |
| __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ |
| __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ |
| } EXTI_TypeDef; |
| |
| |
| /** |
| * @brief Firewall |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ |
| __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ |
| __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ |
| __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ |
| __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ |
| __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ |
| uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ |
| uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ |
| __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ |
| } FIREWALL_TypeDef; |
| |
| |
| /** |
| * @brief FLASH Registers |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ |
| __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ |
| __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ |
| __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ |
| __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ |
| __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ |
| __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ |
| __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ |
| __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ |
| __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ |
| __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ |
| __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ |
| __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ |
| uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */ |
| __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ |
| __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ |
| __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ |
| __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ |
| uint32_t RESERVED3[55]; /*!< Reserved3, Address offset: 0x54-0x12C */ |
| __IO uint32_t CFGR; /*!< FLASH configuration register, Address offset: 0x130 */ |
| } FLASH_TypeDef; |
| |
| |
| /** |
| * @brief Flexible Memory Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ |
| } FMC_Bank1_TypeDef; |
| |
| /** |
| * @brief Flexible Memory Controller Bank1E |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ |
| } FMC_Bank1E_TypeDef; |
| |
| /** |
| * @brief Flexible Memory Controller Bank3 |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ |
| __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ |
| __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ |
| __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ |
| uint32_t RESERVED0; /*!< Reserved, 0x90 */ |
| __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ |
| } FMC_Bank3_TypeDef; |
| |
| /** |
| * @brief GFXMMU registers |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ |
| __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ |
| __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ |
| uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */ |
| __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ |
| uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */ |
| __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ |
| __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ |
| __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ |
| __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ |
| uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ |
| __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC |
| For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ |
| } GFXMMU_TypeDef; |
| |
| /** |
| * @brief General Purpose I/O |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ |
| __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ |
| __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ |
| |
| } GPIO_TypeDef; |
| |
| |
| /** |
| * @brief Inter-integrated Circuit Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ |
| __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ |
| __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ |
| __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ |
| __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ |
| __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ |
| __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ |
| __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ |
| __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ |
| } I2C_TypeDef; |
| |
| /** |
| * @brief Independent WATCHDOG |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
| __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
| __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
| __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
| __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ |
| } IWDG_TypeDef; |
| |
| /** |
| * @brief LPTIMER |
| */ |
| typedef struct |
| { |
| __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ |
| __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ |
| __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ |
| __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ |
| __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ |
| __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ |
| __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ |
| __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ |
| __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ |
| } LPTIM_TypeDef; |
| |
| /** |
| * @brief LCD-TFT Display Controller |
| */ |
| |
| typedef struct |
| { |
| uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ |
| __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ |
| __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ |
| __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ |
| __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ |
| __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ |
| uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ |
| __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ |
| uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ |
| __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ |
| uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ |
| __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ |
| __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ |
| __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ |
| __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ |
| __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ |
| __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ |
| } LTDC_TypeDef; |
| |
| /** |
| * @brief LCD-TFT Display layer x Controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ |
| __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ |
| __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ |
| __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ |
| __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ |
| __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ |
| __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ |
| __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ |
| uint32_t RESERVED0[2]; /*!< Reserved */ |
| __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ |
| __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ |
| __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ |
| uint32_t RESERVED1[3]; /*!< Reserved */ |
| __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ |
| |
| } LTDC_Layer_TypeDef; |
| |
| /** |
| * @brief Operational Amplifier (OPAMP) |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ |
| __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ |
| __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ |
| } OPAMP_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ |
| } OPAMP_Common_TypeDef; |
| |
| /** |
| * @brief Power Control |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ |
| __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ |
| __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ |
| __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ |
| __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ |
| __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ |
| uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ |
| __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ |
| __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ |
| __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ |
| __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ |
| __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ |
| __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ |
| __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ |
| __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ |
| __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ |
| __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ |
| __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ |
| __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ |
| __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ |
| __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ |
| __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ |
| __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ |
| __IO uint32_t PUCRI; /*!< Pull_up control register of portI, Address offset: 0x60 */ |
| __IO uint32_t PDCRI; /*!< Pull_Down control register of portI, Address offset: 0x64 */ |
| uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x68-0x7C */ |
| __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ |
| } PWR_TypeDef; |
| |
| |
| /** |
| * @brief OCTO Serial Peripheral Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ |
| uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ |
| __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ |
| __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ |
| __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ |
| uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x014-0x01C */ |
| __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ |
| __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ |
| uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ |
| __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ |
| uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ |
| __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ |
| uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ |
| __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */ |
| uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ |
| __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ |
| uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ |
| __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ |
| uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ |
| __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ |
| uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ |
| __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ |
| uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ |
| __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ |
| uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ |
| __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ |
| uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ |
| __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ |
| uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ |
| __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ |
| uint32_t RESERVED13[19]; /*!< Reserved, Address offset: 0x134-0x17C */ |
| __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ |
| uint32_t RESERVED14; /*!< Reserved, Address offset: 0x184 */ |
| __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ |
| uint32_t RESERVED15; /*!< Reserved, Address offset: 0x18C */ |
| __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ |
| uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x194-0x19C */ |
| __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ |
| uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ |
| __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ |
| } OCTOSPI_TypeDef; |
| |
| /** |
| * @brief OCTO Serial Peripheral Interface IO Manager |
| */ |
| |
| typedef struct |
| { |
| uint32_t RESERVED; /*!< Reserved, Address offset: 0x00 */ |
| __IO uint32_t PCR[2]; /*!< OCTOSPI IO Manager Port[1:2] Configuration register, Address offset: 0x04-0x08 */ |
| } OCTOSPIM_TypeDef; |
| |
| /** |
| * @brief Reset and Clock Control |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
| __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ |
| __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ |
| __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ |
| __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */ |
| __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */ |
| __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ |
| __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ |
| __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ |
| uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ |
| __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ |
| __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ |
| __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ |
| uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ |
| __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ |
| __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ |
| __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ |
| uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ |
| __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ |
| __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ |
| __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ |
| uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ |
| __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ |
| __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ |
| __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ |
| uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ |
| __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ |
| __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ |
| __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ |
| uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ |
| __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ |
| __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ |
| __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ |
| uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ |
| __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ |
| uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ |
| __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ |
| __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ |
| __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ |
| __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ |
| uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA0 */ |
| __IO uint32_t DLYCFGR; /*!< RCC peripheral OCTOSPI delay configuration register, Address offset: 0xA4 */ |
| } RCC_TypeDef; |
| |
| /** |
| * @brief Real-Time Clock |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
| __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
| __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
| __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
| __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
| __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
| uint32_t reserved; /*!< Reserved */ |
| __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
| __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ |
| __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
| __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
| __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
| __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
| __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
| __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
| __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
| __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ |
| __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ |
| __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ |
| __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ |
| __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ |
| __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
| __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
| __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
| __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
| __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ |
| __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ |
| __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ |
| __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ |
| __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ |
| __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ |
| __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ |
| __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ |
| __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ |
| __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ |
| __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ |
| __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ |
| __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ |
| __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ |
| __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ |
| __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ |
| __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ |
| __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ |
| __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ |
| __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ |
| __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ |
| __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ |
| __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ |
| __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ |
| __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ |
| __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ |
| __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ |
| } RTC_TypeDef; |
| |
| /** |
| * @brief Serial Audio Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ |
| uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ |
| __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ |
| __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ |
| } SAI_TypeDef; |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ |
| __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ |
| __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ |
| __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ |
| __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ |
| __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ |
| __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ |
| __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ |
| } SAI_Block_TypeDef; |
| |
| |
| /** |
| * @brief Secure digital input/output Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ |
| __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ |
| __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ |
| __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ |
| __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ |
| __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ |
| __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ |
| __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ |
| __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ |
| __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ |
| __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ |
| __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ |
| __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ |
| __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ |
| __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ |
| __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ |
| __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ |
| uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ |
| __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ |
| __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ |
| __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ |
| __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ |
| uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ |
| __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ |
| } SDMMC_TypeDef; |
| /** |
| * @brief Serial Peripheral Interface |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ |
| __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ |
| __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ |
| __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ |
| } SPI_TypeDef; |
| |
| |
| /** |
| * @brief System configuration controller |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ |
| __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ |
| __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ |
| __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ |
| __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ |
| __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ |
| __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ |
| __IO uint32_t SWPR2; /*!< SYSCFG SRAM2 write protection register 2, Address offset: 0x28 */ |
| } SYSCFG_TypeDef; |
| |
| |
| /** |
| * @brief TIM |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ |
| __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ |
| __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ |
| __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ |
| __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ |
| __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ |
| __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ |
| __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ |
| __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ |
| } TIM_TypeDef; |
| |
| |
| /** |
| * @brief Touch Sensing Controller (TSC) |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ |
| __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ |
| __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ |
| __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ |
| __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ |
| uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ |
| __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ |
| uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ |
| __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ |
| uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ |
| __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ |
| uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ |
| __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ |
| __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ |
| } TSC_TypeDef; |
| |
| /** |
| * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ |
| __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ |
| __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ |
| __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ |
| __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ |
| uint16_t RESERVED2; /*!< Reserved, 0x12 */ |
| __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ |
| __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ |
| uint16_t RESERVED3; /*!< Reserved, 0x1A */ |
| __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ |
| __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ |
| __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ |
| uint16_t RESERVED4; /*!< Reserved, 0x26 */ |
| __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ |
| uint16_t RESERVED5; /*!< Reserved, 0x2A */ |
| __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ |
| } USART_TypeDef; |
| |
| /** |
| * @brief VREFBUF |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ |
| __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ |
| } VREFBUF_TypeDef; |
| |
| /** |
| * @brief Window WATCHDOG |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| } WWDG_TypeDef; |
| |
| /** |
| * @brief RNG |
| */ |
| |
| typedef struct |
| { |
| __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ |
| __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ |
| __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ |
| } RNG_TypeDef; |
| |
| /** |
| * @brief USB_OTG_Core_register |
| */ |
| typedef struct |
| { |
| __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ |
| __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ |
| __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ |
| __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ |
| __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ |
| __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ |
| __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ |
| __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ |
| __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ |
| __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/ |
| __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ |
| __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ |
| uint32_t Reserved30[2]; /*!< Reserved 030h*/ |
| __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/ |
| __IO uint32_t CID; /*!< User ID Register 03Ch*/ |
| __IO uint32_t GSNPSID; /*!< USB_OTG core ID 040h*/ |
| __IO uint32_t GHWCFG1; /*!< User HW config1 044h*/ |
| __IO uint32_t GHWCFG2; /*!< User HW config2 048h*/ |
| __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/ |
| uint32_t Reserved6; /*!< Reserved 050h*/ |
| __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/ |
| __IO uint32_t GPWRDN; /*!< Power Down Register 058h*/ |
| __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch*/ |
| __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 060h*/ |
| uint32_t Reserved43[39]; /*!< Reserved 064h-0FFh*/ |
| __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/ |
| __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ |
| } USB_OTG_GlobalTypeDef; |
| |
| /** |
| * @brief USB_OTG_device_Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t DCFG; /* dev Configuration Register 800h*/ |
| __IO uint32_t DCTL; /* dev Control Register 804h*/ |
| __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ |
| uint32_t Reserved0C; /* Reserved 80Ch*/ |
| __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ |
| __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ |
| __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ |
| __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ |
| uint32_t Reserved20; /* Reserved 820h*/ |
| uint32_t Reserved24; /* Reserved 824h*/ |
| __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ |
| __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ |
| __IO uint32_t DTHRCTL; /* dev thr 830h*/ |
| __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ |
| __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ |
| __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ |
| uint32_t Reserved40; /* Reserved 840h*/ |
| __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ |
| uint32_t Reserved44[15]; /* Reserved 848-880h*/ |
| __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ |
| } USB_OTG_DeviceTypeDef; |
| |
| /** |
| * @brief USB_OTG_IN_Endpoint-Specific_Register |
| */ |
| typedef struct |
| { |
| __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ |
| uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ |
| __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ |
| uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ |
| __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ |
| __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ |
| __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ |
| uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ |
| } USB_OTG_INEndpointTypeDef; |
| |
| /** |
| * @brief USB_OTG_OUT_Endpoint-Specific_Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ |
| uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ |
| __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ |
| uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ |
| __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ |
| __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ |
| uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ |
| } USB_OTG_OUTEndpointTypeDef; |
| |
| /** |
| * @brief USB_OTG_Host_Mode_Register_Structures |
| */ |
| typedef struct |
| { |
| __IO uint32_t HCFG; /* Host Configuration Register 400h*/ |
| __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ |
| __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ |
| uint32_t Reserved40C; /* Reserved 40Ch*/ |
| __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ |
| __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ |
| __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ |
| } USB_OTG_HostTypeDef; |
| |
| /** |
| * @brief USB_OTG_Host_Channel_Specific_Registers |
| */ |
| typedef struct |
| { |
| __IO uint32_t HCCHAR; |
| __IO uint32_t HCSPLT; |
| __IO uint32_t HCINT; |
| __IO uint32_t HCINTMSK; |
| __IO uint32_t HCTSIZ; |
| __IO uint32_t HCDMA; |
| uint32_t Reserved[2]; |
| } USB_OTG_HostChannelTypeDef; |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_memory_map |
| * @{ |
| */ |
| #define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 2 MB) base address */ |
| #define FLASH_END (0x081FFFFFUL) /*!< FLASH END address */ |
| #define FLASH_BANK1_END (0x080FFFFFUL) /*!< FLASH END address of bank1 */ |
| #define FLASH_BANK2_END (0x081FFFFFUL) /*!< FLASH END address of bank2 */ |
| #define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 192 KB) base address */ |
| #define SRAM2_BASE (0x10000000UL) /*!< SRAM2(64 KB) base address */ |
| #define SRAM3_BASE (0x20040000UL) /*!< SRAM3(384 KB) base address */ |
| #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ |
| #define FMC_BASE (0x60000000UL) /*!< FMC base address */ |
| #define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ |
| #define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ |
| |
| #define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ |
| #define OCTOSPI1_R_BASE (0xA0001000UL) /*!< OCTOSPI1 control registers base address */ |
| #define OCTOSPI2_R_BASE (0xA0001400UL) /*!< OCTOSPI2 control registers base address */ |
| #define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ |
| #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ |
| /*!< GFXMMU virtual buffers base address */ |
| #define GFXMMU_VIRTUAL_BUFFER0_BASE (0x30000000UL) |
| #define GFXMMU_VIRTUAL_BUFFER1_BASE (0x30400000UL) |
| #define GFXMMU_VIRTUAL_BUFFER2_BASE (0x30800000UL) |
| #define GFXMMU_VIRTUAL_BUFFER3_BASE (0x30C00000UL) |
| |
| /* Legacy defines */ |
| #define SRAM_BASE SRAM1_BASE |
| #define SRAM_BB_BASE SRAM1_BB_BASE |
| |
| #define SRAM1_SIZE_MAX (0x00030000UL) /*!< maximum SRAM1 size (up to 192 KBytes) */ |
| #define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */ |
| #define SRAM3_SIZE (0x00060000UL) /*!< SRAM3 size (384 KBytes) */ |
| |
| #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) |
| |
| #define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \ |
| (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U)) |
| |
| /*!< Peripheral memory map */ |
| #define APB1PERIPH_BASE PERIPH_BASE |
| #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
| #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
| #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) |
| |
| #define FMC_BANK1 FMC_BASE |
| #define FMC_BANK1_1 FMC_BANK1 |
| #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) |
| #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) |
| #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) |
| #define FMC_BANK3 (FMC_BASE + 0x20000000UL) |
| |
| /*!< APB1 peripherals */ |
| #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) |
| #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) |
| #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) |
| #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) |
| #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) |
| #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) |
| #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) |
| #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) |
| #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) |
| #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) |
| #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) |
| #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) |
| #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) |
| #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) |
| #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) |
| #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) |
| #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) |
| #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) |
| #define CRS_BASE (APB1PERIPH_BASE + 0x6000UL) |
| #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) |
| #define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) |
| #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) |
| #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) |
| #define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) |
| #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) |
| #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) |
| #define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL) |
| #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) |
| #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) |
| #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) |
| |
| |
| /*!< APB2 peripherals */ |
| #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) |
| #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) |
| #define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) |
| #define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) |
| #define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) |
| #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) |
| #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) |
| #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) |
| #define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) |
| #define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) |
| #define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) |
| #define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) |
| #define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) |
| #define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) |
| #define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) |
| #define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) |
| #define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL) |
| #define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) |
| #define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) |
| #define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL) |
| #define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL) |
| #define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL) |
| #define DSI_BASE (APB2PERIPH_BASE + 0x6C00UL) |
| #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL) |
| #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL) |
| #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL) |
| #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL) |
| #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL) |
| #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL) |
| #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL) |
| #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL) |
| #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL) |
| #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL) |
| #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL) |
| #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL) |
| #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL) |
| |
| /*!< AHB1 peripherals */ |
| #define DMA1_BASE (AHB1PERIPH_BASE) |
| #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) |
| #define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) |
| #define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) |
| #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) |
| #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) |
| #define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) |
| #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL) |
| #define GFXMMU_BASE (AHB1PERIPH_BASE + 0xC000UL) |
| |
| |
| #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) |
| #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) |
| #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) |
| #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) |
| #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) |
| #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) |
| #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) |
| |
| |
| #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) |
| #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) |
| #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) |
| #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) |
| #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) |
| #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) |
| #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) |
| |
| #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) |
| #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) |
| #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) |
| #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) |
| #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) |
| #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) |
| #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) |
| #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) |
| #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL) |
| #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL) |
| #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL) |
| #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL) |
| #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL) |
| #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL) |
| |
| #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) |
| #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) |
| #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) |
| #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) |
| |
| #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) |
| #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) |
| |
| /*!< AHB2 peripherals */ |
| #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) |
| #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) |
| #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) |
| #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) |
| #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) |
| #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) |
| #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) |
| #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) |
| #define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000UL) |
| |
| #define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000UL) |
| |
| #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) |
| #define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) |
| |
| #define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000UL) |
| |
| #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) |
| |
| #define OCTOSPIM_BASE (AHB2PERIPH_BASE + 0x08061C00UL) |
| #define SDMMC1_BASE (AHB2PERIPH_BASE + 0x08062400UL) |
| |
| /*!< FMC Banks registers base address */ |
| #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) |
| #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) |
| #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) |
| |
| /* Debug MCU registers base address */ |
| #define DBGMCU_BASE (0xE0042000UL) |
| |
| /*!< USB registers base address */ |
| #define USB_OTG_FS_PERIPH_BASE (0x50000000UL) |
| |
| #define USB_OTG_GLOBAL_BASE (0x00000000UL) |
| #define USB_OTG_DEVICE_BASE (0x00000800UL) |
| #define USB_OTG_IN_ENDPOINT_BASE (0x00000900UL) |
| #define USB_OTG_OUT_ENDPOINT_BASE (0x00000B00UL) |
| #define USB_OTG_EP_REG_SIZE (0x00000020UL) |
| #define USB_OTG_HOST_BASE (0x00000400UL) |
| #define USB_OTG_HOST_PORT_BASE (0x00000440UL) |
| #define USB_OTG_HOST_CHANNEL_BASE (0x00000500UL) |
| #define USB_OTG_HOST_CHANNEL_SIZE (0x00000020UL) |
| #define USB_OTG_PCGCCTL_BASE (0x00000E00UL) |
| #define USB_OTG_FIFO_BASE (0x00001000UL) |
| #define USB_OTG_FIFO_SIZE (0x00001000UL) |
| |
| |
| #define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ |
| #define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ |
| #define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_declaration |
| * @{ |
| */ |
| #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
| #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
| #define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
| #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
| #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
| #define RTC ((RTC_TypeDef *) RTC_BASE) |
| #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
| #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
| #define USART2 ((USART_TypeDef *) USART2_BASE) |
| #define USART3 ((USART_TypeDef *) USART3_BASE) |
| #define UART4 ((USART_TypeDef *) UART4_BASE) |
| #define UART5 ((USART_TypeDef *) UART5_BASE) |
| #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
| #define I2C3 ((I2C_TypeDef *) I2C3_BASE) |
| #define CRS ((CRS_TypeDef *) CRS_BASE) |
| #define CAN ((CAN_TypeDef *) CAN1_BASE) |
| #define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
| #define I2C4 ((I2C_TypeDef *) I2C4_BASE) |
| #define PWR ((PWR_TypeDef *) PWR_BASE) |
| #define DAC ((DAC_TypeDef *) DAC1_BASE) |
| #define DAC1 ((DAC_TypeDef *) DAC1_BASE) |
| #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) |
| #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) |
| #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) |
| #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) |
| #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) |
| #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) |
| #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) |
| |
| #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
| #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) |
| #define COMP1 ((COMP_TypeDef *) COMP1_BASE) |
| #define COMP2 ((COMP_TypeDef *) COMP2_BASE) |
| #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) |
| #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) |
| #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
| #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| #define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
| #define USART1 ((USART_TypeDef *) USART1_BASE) |
| #define TIM15 ((TIM_TypeDef *) TIM15_BASE) |
| #define TIM16 ((TIM_TypeDef *) TIM16_BASE) |
| #define TIM17 ((TIM_TypeDef *) TIM17_BASE) |
| #define SAI1 ((SAI_TypeDef *) SAI1_BASE) |
| #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) |
| #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) |
| #define SAI2 ((SAI_TypeDef *) SAI2_BASE) |
| #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) |
| #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) |
| #define LTDC ((LTDC_TypeDef *)LTDC_BASE) |
| #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) |
| #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) |
| #define DSI ((DSI_TypeDef *)DSI_BASE) |
| #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) |
| #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) |
| #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) |
| #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) |
| #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) |
| #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) |
| #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) |
| #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) |
| #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) |
| #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) |
| #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) |
| #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) |
| /* Aliases to keep compatibility after DFSDM renaming */ |
| #define DFSDM_Channel0 DFSDM1_Channel0 |
| #define DFSDM_Channel1 DFSDM1_Channel1 |
| #define DFSDM_Channel2 DFSDM1_Channel2 |
| #define DFSDM_Channel3 DFSDM1_Channel3 |
| #define DFSDM_Channel4 DFSDM1_Channel4 |
| #define DFSDM_Channel5 DFSDM1_Channel5 |
| #define DFSDM_Channel6 DFSDM1_Channel6 |
| #define DFSDM_Channel7 DFSDM1_Channel7 |
| #define DFSDM_Filter0 DFSDM1_Filter0 |
| #define DFSDM_Filter1 DFSDM1_Filter1 |
| #define DFSDM_Filter2 DFSDM1_Filter2 |
| #define DFSDM_Filter3 DFSDM1_Filter3 |
| #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
| #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) |
| #define RCC ((RCC_TypeDef *) RCC_BASE) |
| #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| #define CRC ((CRC_TypeDef *) CRC_BASE) |
| #define TSC ((TSC_TypeDef *) TSC_BASE) |
| |
| #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
| #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
| #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
| #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
| #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
| #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) |
| #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) |
| #define DCMI ((DCMI_TypeDef *) DCMI_BASE) |
| #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) |
| #define RNG ((RNG_TypeDef *) RNG_BASE) |
| #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) |
| |
| |
| #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
| #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
| #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
| #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
| #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
| #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
| #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
| |
| |
| #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
| #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
| #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
| #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
| #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
| #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) |
| #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) |
| |
| #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) |
| #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) |
| #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) |
| #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) |
| #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) |
| #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) |
| #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) |
| #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) |
| #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) |
| #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) |
| #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) |
| #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) |
| #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) |
| #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) |
| |
| #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) |
| #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) |
| #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) |
| #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) |
| |
| #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) |
| #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) |
| |
| |
| #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) |
| #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) |
| #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) |
| |
| #define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE) |
| #define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE) |
| #define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE) |
| |
| #define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE) |
| |
| #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| |
| #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Exported_constants |
| * @{ |
| */ |
| |
| /** @addtogroup Hardware_Constant_Definition |
| * @{ |
| */ |
| #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup Peripheral_Registers_Bits_Definition |
| * @{ |
| */ |
| |
| /******************************************************************************/ |
| /* Peripheral Registers_Bits_Definition */ |
| /******************************************************************************/ |
| |
| /******************************************************************************/ |
| /* */ |
| /* Analog to Digital Converter */ |
| /* */ |
| /******************************************************************************/ |
| |
| /* |
| * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) |
| */ |
| |
| /******************** Bit definition for ADC_ISR register *******************/ |
| #define ADC_ISR_ADRDY_Pos (0U) |
| #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ |
| #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ |
| #define ADC_ISR_EOSMP_Pos (1U) |
| #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ |
| #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ |
| #define ADC_ISR_EOC_Pos (2U) |
| #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ |
| #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ |
| #define ADC_ISR_EOS_Pos (3U) |
| #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ |
| #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ |
| #define ADC_ISR_OVR_Pos (4U) |
| #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ |
| #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ |
| #define ADC_ISR_JEOC_Pos (5U) |
| #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ |
| #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ |
| #define ADC_ISR_JEOS_Pos (6U) |
| #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ |
| #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ |
| #define ADC_ISR_AWD1_Pos (7U) |
| #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ |
| #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ |
| #define ADC_ISR_AWD2_Pos (8U) |
| #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ |
| #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ |
| #define ADC_ISR_AWD3_Pos (9U) |
| #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ |
| #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ |
| #define ADC_ISR_JQOVF_Pos (10U) |
| #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ |
| #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ |
| |
| /******************** Bit definition for ADC_IER register *******************/ |
| #define ADC_IER_ADRDYIE_Pos (0U) |
| #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ |
| #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ |
| #define ADC_IER_EOSMPIE_Pos (1U) |
| #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ |
| #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ |
| #define ADC_IER_EOCIE_Pos (2U) |
| #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ |
| #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ |
| #define ADC_IER_EOSIE_Pos (3U) |
| #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ |
| #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ |
| #define ADC_IER_OVRIE_Pos (4U) |
| #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ |
| #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ |
| #define ADC_IER_JEOCIE_Pos (5U) |
| #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ |
| #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ |
| #define ADC_IER_JEOSIE_Pos (6U) |
| #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ |
| #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ |
| #define ADC_IER_AWD1IE_Pos (7U) |
| #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ |
| #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ |
| #define ADC_IER_AWD2IE_Pos (8U) |
| #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ |
| #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ |
| #define ADC_IER_AWD3IE_Pos (9U) |
| #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ |
| #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ |
| #define ADC_IER_JQOVFIE_Pos (10U) |
| #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ |
| #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ |
| |
| /* Legacy defines */ |
| #define ADC_IER_ADRDY (ADC_IER_ADRDYIE) |
| #define ADC_IER_EOSMP (ADC_IER_EOSMPIE) |
| #define ADC_IER_EOC (ADC_IER_EOCIE) |
| #define ADC_IER_EOS (ADC_IER_EOSIE) |
| #define ADC_IER_OVR (ADC_IER_OVRIE) |
| #define ADC_IER_JEOC (ADC_IER_JEOCIE) |
| #define ADC_IER_JEOS (ADC_IER_JEOSIE) |
| #define ADC_IER_AWD1 (ADC_IER_AWD1IE) |
| #define ADC_IER_AWD2 (ADC_IER_AWD2IE) |
| #define ADC_IER_AWD3 (ADC_IER_AWD3IE) |
| #define ADC_IER_JQOVF (ADC_IER_JQOVFIE) |
| |
| /******************** Bit definition for ADC_CR register ********************/ |
| #define ADC_CR_ADEN_Pos (0U) |
| #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ |
| #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ |
| #define ADC_CR_ADDIS_Pos (1U) |
| #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ |
| #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ |
| #define ADC_CR_ADSTART_Pos (2U) |
| #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ |
| #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ |
| #define ADC_CR_JADSTART_Pos (3U) |
| #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ |
| #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ |
| #define ADC_CR_ADSTP_Pos (4U) |
| #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ |
| #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ |
| #define ADC_CR_JADSTP_Pos (5U) |
| #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ |
| #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ |
| #define ADC_CR_ADVREGEN_Pos (28U) |
| #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ |
| #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ |
| #define ADC_CR_DEEPPWD_Pos (29U) |
| #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ |
| #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ |
| #define ADC_CR_ADCALDIF_Pos (30U) |
| #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ |
| #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ |
| #define ADC_CR_ADCAL_Pos (31U) |
| #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ |
| #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ |
| |
| /******************** Bit definition for ADC_CFGR register ******************/ |
| #define ADC_CFGR_DMAEN_Pos (0U) |
| #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ |
| #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ |
| #define ADC_CFGR_DMACFG_Pos (1U) |
| #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ |
| #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ |
| |
| #define ADC_CFGR_DFSDMCFG_Pos (2U) |
| #define ADC_CFGR_DFSDMCFG_Msk (0x1UL << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */ |
| #define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */ |
| |
| #define ADC_CFGR_RES_Pos (3U) |
| #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ |
| #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ |
| #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ |
| #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ |
| |
| #define ADC_CFGR_ALIGN_Pos (5U) |
| #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ |
| #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ |
| |
| #define ADC_CFGR_EXTSEL_Pos (6U) |
| #define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ |
| #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ |
| #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ |
| #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ |
| #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ |
| #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ |
| |
| #define ADC_CFGR_EXTEN_Pos (10U) |
| #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ |
| #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ |
| #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ |
| #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_CFGR_OVRMOD_Pos (12U) |
| #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ |
| #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ |
| #define ADC_CFGR_CONT_Pos (13U) |
| #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ |
| #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ |
| #define ADC_CFGR_AUTDLY_Pos (14U) |
| #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ |
| #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ |
| |
| #define ADC_CFGR_DISCEN_Pos (16U) |
| #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ |
| #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ |
| |
| #define ADC_CFGR_DISCNUM_Pos (17U) |
| #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ |
| #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ |
| #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ |
| #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ |
| #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ |
| |
| #define ADC_CFGR_JDISCEN_Pos (20U) |
| #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ |
| #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ |
| #define ADC_CFGR_JQM_Pos (21U) |
| #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ |
| #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ |
| #define ADC_CFGR_AWD1SGL_Pos (22U) |
| #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ |
| #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ |
| #define ADC_CFGR_AWD1EN_Pos (23U) |
| #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ |
| #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ |
| #define ADC_CFGR_JAWD1EN_Pos (24U) |
| #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ |
| #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ |
| #define ADC_CFGR_JAUTO_Pos (25U) |
| #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ |
| #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ |
| |
| #define ADC_CFGR_AWD1CH_Pos (26U) |
| #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ |
| #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ |
| #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ |
| #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ |
| #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ |
| #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ |
| #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ |
| |
| #define ADC_CFGR_JQDIS_Pos (31U) |
| #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ |
| #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ |
| |
| /******************** Bit definition for ADC_CFGR2 register *****************/ |
| #define ADC_CFGR2_ROVSE_Pos (0U) |
| #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ |
| #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ |
| #define ADC_CFGR2_JOVSE_Pos (1U) |
| #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ |
| #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ |
| |
| #define ADC_CFGR2_OVSR_Pos (2U) |
| #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ |
| #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ |
| #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ |
| #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ |
| #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ |
| |
| #define ADC_CFGR2_OVSS_Pos (5U) |
| #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ |
| #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ |
| #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ |
| #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ |
| #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ |
| #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ |
| |
| #define ADC_CFGR2_TROVS_Pos (9U) |
| #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ |
| #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ |
| #define ADC_CFGR2_ROVSM_Pos (10U) |
| #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ |
| #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ |
| |
| /******************** Bit definition for ADC_SMPR1 register *****************/ |
| #define ADC_SMPR1_SMP0_Pos (0U) |
| #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ |
| #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ |
| #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ |
| #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ |
| #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ |
| |
| #define ADC_SMPR1_SMP1_Pos (3U) |
| #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ |
| #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ |
| #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ |
| #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ |
| #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ |
| |
| #define ADC_SMPR1_SMP2_Pos (6U) |
| #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ |
| #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ |
| #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ |
| #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ |
| #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ |
| |
| #define ADC_SMPR1_SMP3_Pos (9U) |
| #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ |
| #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ |
| #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ |
| #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ |
| #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_SMPR1_SMP4_Pos (12U) |
| #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ |
| #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ |
| #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ |
| #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ |
| #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ |
| |
| #define ADC_SMPR1_SMP5_Pos (15U) |
| #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ |
| #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ |
| #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ |
| #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ |
| #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ |
| |
| #define ADC_SMPR1_SMP6_Pos (18U) |
| #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ |
| #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ |
| #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ |
| #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ |
| #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ |
| |
| #define ADC_SMPR1_SMP7_Pos (21U) |
| #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ |
| #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ |
| #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ |
| #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ |
| #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ |
| |
| #define ADC_SMPR1_SMP8_Pos (24U) |
| #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ |
| #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ |
| #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ |
| #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ |
| #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ |
| |
| #define ADC_SMPR1_SMP9_Pos (27U) |
| #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ |
| #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ |
| #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ |
| #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ |
| #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ |
| |
| #define ADC_SMPR1_SMPPLUS_Pos (31U) |
| #define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ |
| #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ |
| |
| /******************** Bit definition for ADC_SMPR2 register *****************/ |
| #define ADC_SMPR2_SMP10_Pos (0U) |
| #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ |
| #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ |
| #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ |
| #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ |
| #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ |
| |
| #define ADC_SMPR2_SMP11_Pos (3U) |
| #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ |
| #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ |
| #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ |
| #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ |
| #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ |
| |
| #define ADC_SMPR2_SMP12_Pos (6U) |
| #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ |
| #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ |
| #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ |
| #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ |
| #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ |
| |
| #define ADC_SMPR2_SMP13_Pos (9U) |
| #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ |
| #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ |
| #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ |
| #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ |
| #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_SMPR2_SMP14_Pos (12U) |
| #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ |
| #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ |
| #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ |
| #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ |
| #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ |
| |
| #define ADC_SMPR2_SMP15_Pos (15U) |
| #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ |
| #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ |
| #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ |
| #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ |
| #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ |
| |
| #define ADC_SMPR2_SMP16_Pos (18U) |
| #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ |
| #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ |
| #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ |
| #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ |
| #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ |
| |
| #define ADC_SMPR2_SMP17_Pos (21U) |
| #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ |
| #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ |
| #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ |
| #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ |
| #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ |
| |
| #define ADC_SMPR2_SMP18_Pos (24U) |
| #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ |
| #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ |
| #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ |
| #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ |
| #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ |
| |
| /******************** Bit definition for ADC_TR1 register *******************/ |
| #define ADC_TR1_LT1_Pos (0U) |
| #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ |
| #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ |
| #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ |
| #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ |
| #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ |
| #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ |
| #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ |
| #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ |
| #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ |
| #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ |
| #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ |
| #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ |
| #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ |
| #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_TR1_HT1_Pos (16U) |
| #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ |
| #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ |
| #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ |
| #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ |
| #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ |
| #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ |
| #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ |
| #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ |
| #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ |
| #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ |
| #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ |
| #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ |
| #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ |
| #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ |
| |
| /******************** Bit definition for ADC_TR2 register *******************/ |
| #define ADC_TR2_LT2_Pos (0U) |
| #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ |
| #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ |
| #define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ |
| #define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ |
| #define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ |
| #define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ |
| #define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ |
| #define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ |
| #define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ |
| #define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ |
| |
| #define ADC_TR2_HT2_Pos (16U) |
| #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ |
| #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ |
| #define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ |
| #define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ |
| #define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ |
| #define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ |
| #define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ |
| #define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ |
| #define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ |
| #define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ |
| |
| /******************** Bit definition for ADC_TR3 register *******************/ |
| #define ADC_TR3_LT3_Pos (0U) |
| #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ |
| #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ |
| #define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ |
| #define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ |
| #define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ |
| #define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ |
| #define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ |
| #define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ |
| #define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ |
| #define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ |
| |
| #define ADC_TR3_HT3_Pos (16U) |
| #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ |
| #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ |
| #define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ |
| #define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ |
| #define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ |
| #define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ |
| #define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ |
| #define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ |
| #define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ |
| #define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ |
| |
| /******************** Bit definition for ADC_SQR1 register ******************/ |
| #define ADC_SQR1_L_Pos (0U) |
| #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ |
| #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ |
| #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ |
| #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ |
| #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ |
| #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ |
| |
| #define ADC_SQR1_SQ1_Pos (6U) |
| #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ |
| #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ |
| #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ |
| #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ |
| #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ |
| #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ |
| #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ |
| |
| #define ADC_SQR1_SQ2_Pos (12U) |
| #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ |
| #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ |
| #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ |
| #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ |
| #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ |
| #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ |
| #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ |
| |
| #define ADC_SQR1_SQ3_Pos (18U) |
| #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ |
| #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ |
| #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ |
| #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ |
| #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ |
| #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ |
| #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ |
| |
| #define ADC_SQR1_SQ4_Pos (24U) |
| #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ |
| #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ |
| #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ |
| #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ |
| #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ |
| #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ |
| #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ |
| |
| /******************** Bit definition for ADC_SQR2 register ******************/ |
| #define ADC_SQR2_SQ5_Pos (0U) |
| #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ |
| #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ |
| #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ |
| #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ |
| #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ |
| #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ |
| #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ |
| |
| #define ADC_SQR2_SQ6_Pos (6U) |
| #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ |
| #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ |
| #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ |
| #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ |
| #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ |
| #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ |
| #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ |
| |
| #define ADC_SQR2_SQ7_Pos (12U) |
| #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ |
| #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ |
| #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ |
| #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ |
| #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ |
| #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ |
| #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ |
| |
| #define ADC_SQR2_SQ8_Pos (18U) |
| #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ |
| #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ |
| #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ |
| #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ |
| #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ |
| #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ |
| #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ |
| |
| #define ADC_SQR2_SQ9_Pos (24U) |
| #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ |
| #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ |
| #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ |
| #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ |
| #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ |
| #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ |
| #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ |
| |
| /******************** Bit definition for ADC_SQR3 register ******************/ |
| #define ADC_SQR3_SQ10_Pos (0U) |
| #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ |
| #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ |
| #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ |
| #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ |
| #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ |
| #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ |
| #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ |
| |
| #define ADC_SQR3_SQ11_Pos (6U) |
| #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ |
| #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ |
| #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ |
| #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ |
| #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ |
| #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ |
| #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ |
| |
| #define ADC_SQR3_SQ12_Pos (12U) |
| #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ |
| #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ |
| #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ |
| #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ |
| #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ |
| #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ |
| #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ |
| |
| #define ADC_SQR3_SQ13_Pos (18U) |
| #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ |
| #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ |
| #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ |
| #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ |
| #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ |
| #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ |
| #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ |
| |
| #define ADC_SQR3_SQ14_Pos (24U) |
| #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ |
| #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ |
| #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ |
| #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ |
| #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ |
| #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ |
| #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ |
| |
| /******************** Bit definition for ADC_SQR4 register ******************/ |
| #define ADC_SQR4_SQ15_Pos (0U) |
| #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ |
| #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ |
| #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ |
| #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ |
| #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ |
| #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ |
| #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ |
| |
| #define ADC_SQR4_SQ16_Pos (6U) |
| #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ |
| #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ |
| #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ |
| #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ |
| #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ |
| #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ |
| #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ |
| |
| /******************** Bit definition for ADC_DR register ********************/ |
| #define ADC_DR_RDATA_Pos (0U) |
| #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ |
| #define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ |
| #define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ |
| #define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ |
| #define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ |
| #define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ |
| #define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ |
| #define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ |
| #define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ |
| #define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ |
| #define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ |
| #define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ |
| #define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ |
| #define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ |
| #define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ |
| #define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ |
| #define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ |
| |
| /******************** Bit definition for ADC_JSQR register ******************/ |
| #define ADC_JSQR_JL_Pos (0U) |
| #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ |
| #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ |
| #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ |
| #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ |
| |
| #define ADC_JSQR_JEXTSEL_Pos (2U) |
| #define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ |
| #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ |
| #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ |
| #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ |
| #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ |
| #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ |
| |
| #define ADC_JSQR_JEXTEN_Pos (6U) |
| #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ |
| #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ |
| #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ |
| #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ |
| |
| #define ADC_JSQR_JSQ1_Pos (8U) |
| #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ |
| #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ |
| #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ |
| #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ |
| #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ |
| #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ |
| #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ |
| |
| #define ADC_JSQR_JSQ2_Pos (14U) |
| #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ |
| #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ |
| #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ |
| #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ |
| #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ |
| #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ |
| #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ |
| |
| #define ADC_JSQR_JSQ3_Pos (20U) |
| #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ |
| #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ |
| #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ |
| #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ |
| #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ |
| #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ |
| #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ |
| |
| #define ADC_JSQR_JSQ4_Pos (26U) |
| #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ |
| #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ |
| #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ |
| #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ |
| #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ |
| #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ |
| #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ |
| |
| /******************** Bit definition for ADC_OFR1 register ******************/ |
| #define ADC_OFR1_OFFSET1_Pos (0U) |
| #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ |
| #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ |
| #define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ |
| #define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ |
| #define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ |
| #define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ |
| #define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ |
| #define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ |
| #define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ |
| #define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ |
| #define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ |
| #define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ |
| #define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ |
| #define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_OFR1_OFFSET1_CH_Pos (26U) |
| #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ |
| #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ |
| #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ |
| #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ |
| #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ |
| #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ |
| #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ |
| |
| #define ADC_OFR1_OFFSET1_EN_Pos (31U) |
| #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ |
| #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ |
| |
| /******************** Bit definition for ADC_OFR2 register ******************/ |
| #define ADC_OFR2_OFFSET2_Pos (0U) |
| #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ |
| #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ |
| #define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ |
| #define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ |
| #define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ |
| #define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ |
| #define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ |
| #define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ |
| #define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ |
| #define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ |
| #define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ |
| #define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ |
| #define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ |
| #define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_OFR2_OFFSET2_CH_Pos (26U) |
| #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ |
| #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ |
| #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ |
| #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ |
| #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ |
| #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ |
| #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ |
| |
| #define ADC_OFR2_OFFSET2_EN_Pos (31U) |
| #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ |
| #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ |
| |
| /******************** Bit definition for ADC_OFR3 register ******************/ |
| #define ADC_OFR3_OFFSET3_Pos (0U) |
| #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ |
| #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ |
| #define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ |
| #define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ |
| #define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ |
| #define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ |
| #define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ |
| #define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ |
| #define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ |
| #define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ |
| #define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ |
| #define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ |
| #define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ |
| #define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_OFR3_OFFSET3_CH_Pos (26U) |
| #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ |
| #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ |
| #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ |
| #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ |
| #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ |
| #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ |
| #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ |
| |
| #define ADC_OFR3_OFFSET3_EN_Pos (31U) |
| #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ |
| #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ |
| |
| /******************** Bit definition for ADC_OFR4 register ******************/ |
| #define ADC_OFR4_OFFSET4_Pos (0U) |
| #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ |
| #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ |
| #define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ |
| #define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ |
| #define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ |
| #define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ |
| #define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ |
| #define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ |
| #define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ |
| #define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ |
| #define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ |
| #define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ |
| #define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ |
| #define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ |
| |
| #define ADC_OFR4_OFFSET4_CH_Pos (26U) |
| #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ |
| #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ |
| #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ |
| #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ |
| #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ |
| #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ |
| #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ |
| |
| #define ADC_OFR4_OFFSET4_EN_Pos (31U) |
| #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ |
| #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ |
| |
| /******************** Bit definition for ADC_JDR1 register ******************/ |
| #define ADC_JDR1_JDATA_Pos (0U) |
| #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ |
| #define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ |
| #define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ |
| #define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ |
| #define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ |
| #define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ |
| #define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ |
| #define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ |
| #define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ |
| #define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ |
| #define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ |
| #define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ |
| #define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ |
| #define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ |
| #define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ |
| #define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ |
| #define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ |
| |
| /******************** Bit definition for ADC_JDR2 register ******************/ |
| #define ADC_JDR2_JDATA_Pos (0U) |
| #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ |
| #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ |
| #define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ |
| #define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ |
| #define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ |
| #define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ |
| #define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ |
| #define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ |
| #define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ |
|