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pigweed / third_party / github / STMicroelectronics / cmsis_device_l4 / refs/heads/master / . / Include / stm32l4r9xx.h
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/**
******************************************************************************
* @file stm32l4r9xx.h
* @author MCD Application Team
* @brief CMSIS STM32L4R9xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32l4r9xx
* @{
*/
#ifndef __STM32L4R9xx_H
#define __STM32L4R9xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32L4XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers **********************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */
TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
TIM7_IRQn = 55, /*!< TIM7 global interrupt */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */
COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
OCTOSPI1_IRQn = 71, /*!< OctoSPI1 global interrupt */
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
OCTOSPI2_IRQn = 76, /*!< OctoSPI2 global interrupt */
TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
DSI_IRQn = 78, /*!< DSI global Interrupt */
RNG_IRQn = 80, /*!< RNG global interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
CRS_IRQn = 82, /*!< CRS global interrupt */
I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */
I2C4_EV_IRQn = 84, /*!< I2C4 Event interrupt */
DCMI_IRQn = 85, /*!< DCMI global interrupt */
DMA2D_IRQn = 90, /*!< DMA2D global interrupt */
LTDC_IRQn = 91, /*!< LTDC global Interrupt */
LTDC_ER_IRQn = 92, /*!< LTDC Error global Interrupt */
GFXMMU_IRQn = 93, /*!< GFXMMU global error interrupt */
DMAMUX1_OVR_IRQn = 94 /*!< DMAMUX1 overrun global interrupt */
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_stm32l4xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, 0x1C */
__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
__IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
__IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
uint32_t RESERVED2; /*!< Reserved, 0x2C */
__IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x44 */
uint32_t RESERVED4; /*!< Reserved, 0x48 */
__IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
__IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
__IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
} ADC_TypeDef;
typedef struct
{
uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
} ADC_Common_TypeDef;
/**
* @brief DCMI
*/
typedef struct
{
__IO uint32_t CR; /*!< DCMI control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
__IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
__IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
__IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
__IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
__IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
__IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
__IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
__IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
__IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
} DCMI_TypeDef;
/**
* @brief Controller Area Network TxMailBox
*/
typedef struct
{
__IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
__IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
__IO uint32_t TDLR; /*!< CAN mailbox data low register */
__IO uint32_t TDHR; /*!< CAN mailbox data high register */
} CAN_TxMailBox_TypeDef;
/**
* @brief Controller Area Network FIFOMailBox
*/
typedef struct
{
__IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
__IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
__IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
__IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
} CAN_FIFOMailBox_TypeDef;
/**
* @brief Controller Area Network FilterRegister
*/
typedef struct
{
__IO uint32_t FR1; /*!< CAN Filter bank register 1 */
__IO uint32_t FR2; /*!< CAN Filter bank register 1 */
} CAN_FilterRegister_TypeDef;
/**
* @brief Controller Area Network
*/
typedef struct
{
__IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
__IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
__IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
__IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
__IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
__IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
__IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
__IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
__IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
__IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
uint32_t RESERVED2; /*!< Reserved, 0x208 */
__IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
uint32_t RESERVED3; /*!< Reserved, 0x210 */
__IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
uint32_t RESERVED4; /*!< Reserved, 0x218 */
__IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
} CAN_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
} COMP_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
} COMP_Common_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
} DAC_TypeDef;
/**
* @brief DFSDM module registers
*/
typedef struct
{
__IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
__IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
__IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
__IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
__IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
__IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
__IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
__IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
__IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
__IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
__IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
__IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
__IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
__IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
__IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
} DFSDM_Filter_TypeDef;
/**
* @brief DFSDM channel configuration registers
*/
typedef struct
{
__IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
__IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
__IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
short circuit detector register, Address offset: 0x08 */
__IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
__IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
__IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
} DFSDM_Channel_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
} DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
* @brief DMA Multiplexer
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
}DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
}DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
}DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
__IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
}DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief DMA2D Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
__IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
__IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
__IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
__IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
__IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
__IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
__IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
__IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
__IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
__IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
__IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
__IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
__IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
__IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
__IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
__IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
} DMA2D_TypeDef;
/**
* @brief DSI Controller
*/
typedef struct
{
__IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
__IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
__IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
__IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
__IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
__IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
__IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
__IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
__IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
__IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
__IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
__IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
__IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
__IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
__IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
__IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
__IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
__IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
__IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
__IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
__IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
__IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
__IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
__IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
__IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
__IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
__IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
uint32_t RESERVED1; /*!< Reserved, 0x90 */
__IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
__IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
__IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
__IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
__IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
__IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
__IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
__IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
uint32_t RESERVED2[2]; /*!< Reserved, 0xB4 - 0xBB */
__IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
__IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
uint32_t RESERVED3[3]; /*!< Reserved, 0xD0 - 0xD7 */
__IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
uint32_t RESERVED4[8]; /*!< Reserved, 0xE0 - 0xFF */
__IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */
__IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
__IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
uint32_t RESERVED6; /*!< Reserved, 0x114 */
__IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */
__IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
__IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
__IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */
__IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
__IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
__IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
__IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
__IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
__IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
__IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
__IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
uint32_t RESERVED8[167]; /*!< Reserved, 0x164 - 0x3FF */
__IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
__IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
__IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
__IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
__IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
uint32_t RESERVED9; /*!< Reserved, 0x414 */
__IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
uint32_t RESERVED10; /*!< Reserved, 0x42C */
__IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
} DSI_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
__IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
__IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
__IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
__IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
} EXTI_TypeDef;
/**
* @brief Firewall
*/
typedef struct
{
__IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
__IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
__IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
__IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
__IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
__IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
__IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
} FIREWALL_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
__IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
__IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
__IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
__IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
__IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
__IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
__IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
__IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
uint32_t RESERVED3[55]; /*!< Reserved3, Address offset: 0x54-0x12C */
__IO uint32_t CFGR; /*!< FLASH configuration register, Address offset: 0x130 */
} FLASH_TypeDef;
/**
* @brief Flexible Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
} FMC_Bank1_TypeDef;
/**
* @brief Flexible Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;
/**
* @brief Flexible Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
__IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
__IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
__IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
uint32_t RESERVED0; /*!< Reserved, 0x90 */
__IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
} FMC_Bank3_TypeDef;
/**
* @brief GFXMMU registers
*/
typedef struct
{
__IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */
__IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */
__IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */
__IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */
uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */
__IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
} GPIO_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief LPTIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief LCD-TFT Display Controller
*/
typedef struct
{
uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
__IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
__IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
__IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
__IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
__IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
__IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
__IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
__IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
__IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
__IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
__IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
__IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
__IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
} LTDC_TypeDef;
/**
* @brief LCD-TFT Display layer x Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
__IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
__IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
__IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
__IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
__IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
__IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
uint32_t RESERVED0[2]; /*!< Reserved */
__IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
__IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
__IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
} OPAMP_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
} OPAMP_Common_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
__IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
__IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
__IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
__IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
__IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
__IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
__IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
__IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
__IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
__IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
__IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
__IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
__IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
__IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
__IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
__IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
__IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
__IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
__IO uint32_t PUCRI; /*!< Pull_up control register of portI, Address offset: 0x60 */
__IO uint32_t PDCRI; /*!< Pull_Down control register of portI, Address offset: 0x64 */
uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x68-0x7C */
__IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
} PWR_TypeDef;
/**
* @brief OCTO Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
__IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
__IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
__IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x014-0x01C */
__IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
__IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
__IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
__IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
__IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */
uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
__IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
__IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
__IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
__IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
__IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
__IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
__IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
__IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
uint32_t RESERVED13[19]; /*!< Reserved, Address offset: 0x134-0x17C */
__IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
uint32_t RESERVED14; /*!< Reserved, Address offset: 0x184 */
__IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
uint32_t RESERVED15; /*!< Reserved, Address offset: 0x18C */
__IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x194-0x19C */
__IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
__IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
} OCTOSPI_TypeDef;
/**
* @brief OCTO Serial Peripheral Interface IO Manager
*/
typedef struct
{
uint32_t RESERVED; /*!< Reserved, Address offset: 0x00 */
__IO uint32_t PCR[2]; /*!< OCTOSPI IO Manager Port[1:2] Configuration register, Address offset: 0x04-0x08 */
} OCTOSPIM_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
__IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
__IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
__IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
__IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
__IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
__IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
__IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
__IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
__IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
__IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
__IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
__IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
__IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
__IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
__IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA0 */
__IO uint32_t DLYCFGR; /*!< RCC peripheral OCTOSPI delay configuration register, Address offset: 0xA4 */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
uint32_t reserved; /*!< Reserved */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
__IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
__IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
__IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
__IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
__IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
__IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
__IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
__IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
__IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
__IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
__IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
__IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
__IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
__IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
__IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
__IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
__IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
__IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
__IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
__IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
__IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
__IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
__IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
__IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
__IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
__IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
__IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
__IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
__IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
} RTC_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief Secure digital input/output Interface
*/
typedef struct
{
__IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
__IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
__I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
__I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
__I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
__I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
__I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
__I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
__I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
__IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
__IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
__IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
__IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
__IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
} SDMMC_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
} SPI_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
__IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
__IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
__IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
__IO uint32_t SWPR2; /*!< SYSCFG SRAM2 write protection register 2, Address offset: 0x28 */
} SYSCFG_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
__IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
__IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
__IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
__IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
__IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
} TIM_TypeDef;
/**
* @brief Touch Sensing Controller (TSC)
*/
typedef struct
{
__IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
__IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
__IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
__IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
__IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
__IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
} TSC_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
uint16_t RESERVED2; /*!< Reserved, 0x12 */
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
__IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
uint16_t RESERVED3; /*!< Reserved, 0x1A */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
uint16_t RESERVED4; /*!< Reserved, 0x26 */
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED5; /*!< Reserved, 0x2A */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
} USART_TypeDef;
/**
* @brief VREFBUF
*/
typedef struct
{
__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
} VREFBUF_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @brief USB_OTG_Core_register
*/
typedef struct
{
__IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
__IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
__IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
__IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
__IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
__IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
__IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
__IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
__IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
__IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
__IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
uint32_t Reserved30[2]; /*!< Reserved 030h*/
__IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/
__IO uint32_t CID; /*!< User ID Register 03Ch*/
__IO uint32_t GSNPSID; /*!< USB_OTG core ID 040h*/
__IO uint32_t GHWCFG1; /*!< User HW config1 044h*/
__IO uint32_t GHWCFG2; /*!< User HW config2 048h*/
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/
uint32_t Reserved6; /*!< Reserved 050h*/
__IO uint32_t GLPMCFG; /*!< LPM Register 054h*/
__IO uint32_t GPWRDN; /*!< Power Down Register 058h*/
__IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch*/
__IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 060h*/
uint32_t Reserved43[39]; /*!< Reserved 064h-0FFh*/
__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/
__IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
} USB_OTG_GlobalTypeDef;
/**
* @brief USB_OTG_device_Registers
*/
typedef struct
{
__IO uint32_t DCFG; /* dev Configuration Register 800h*/
__IO uint32_t DCTL; /* dev Control Register 804h*/
__IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
uint32_t Reserved0C; /* Reserved 80Ch*/
__IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
__IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
__IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
__IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
uint32_t Reserved20; /* Reserved 820h*/
uint32_t Reserved24; /* Reserved 824h*/
__IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
__IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
__IO uint32_t DTHRCTL; /* dev thr 830h*/
__IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
__IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
__IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
uint32_t Reserved40; /* Reserved 840h*/
__IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
uint32_t Reserved44[15]; /* Reserved 848-880h*/
__IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
} USB_OTG_DeviceTypeDef;
/**
* @brief USB_OTG_IN_Endpoint-Specific_Register
*/
typedef struct
{
__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
__IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
__IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
} USB_OTG_INEndpointTypeDef;
/**
* @brief USB_OTG_OUT_Endpoint-Specific_Registers
*/
typedef struct
{
__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
__IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
} USB_OTG_OUTEndpointTypeDef;
/**
* @brief USB_OTG_Host_Mode_Register_Structures
*/
typedef struct
{
__IO uint32_t HCFG; /* Host Configuration Register 400h*/
__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
uint32_t Reserved40C; /* Reserved 40Ch*/
__IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
__IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
__IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
} USB_OTG_HostTypeDef;
/**
* @brief USB_OTG_Host_Channel_Specific_Registers
*/
typedef struct
{
__IO uint32_t HCCHAR;
__IO uint32_t HCSPLT;
__IO uint32_t HCINT;
__IO uint32_t HCINTMSK;
__IO uint32_t HCTSIZ;
__IO uint32_t HCDMA;
uint32_t Reserved[2];
} USB_OTG_HostChannelTypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 2 MB) base address */
#define FLASH_END (0x081FFFFFUL) /*!< FLASH END address */
#define FLASH_BANK1_END (0x080FFFFFUL) /*!< FLASH END address of bank1 */
#define FLASH_BANK2_END (0x081FFFFFUL) /*!< FLASH END address of bank2 */
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 192 KB) base address */
#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(64 KB) base address */
#define SRAM3_BASE (0x20040000UL) /*!< SRAM3(384 KB) base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define FMC_BASE (0x60000000UL) /*!< FMC base address */
#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */
#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */
#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */
#define OCTOSPI1_R_BASE (0xA0001000UL) /*!< OCTOSPI1 control registers base address */
#define OCTOSPI2_R_BASE (0xA0001400UL) /*!< OCTOSPI2 control registers base address */
#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
/*!< GFXMMU virtual buffers base address */
#define GFXMMU_VIRTUAL_BUFFER0_BASE (0x30000000UL)
#define GFXMMU_VIRTUAL_BUFFER1_BASE (0x30400000UL)
#define GFXMMU_VIRTUAL_BUFFER2_BASE (0x30800000UL)
#define GFXMMU_VIRTUAL_BUFFER3_BASE (0x30C00000UL)
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
#define SRAM1_SIZE_MAX (0x00030000UL) /*!< maximum SRAM1 size (up to 192 KBytes) */
#define SRAM2_SIZE (0x00010000UL) /*!< SRAM2 size (64 KBytes) */
#define SRAM3_SIZE (0x00060000UL) /*!< SRAM3 size (384 KBytes) */
#define FLASH_SIZE_DATA_REGISTER (0x1FFF75E0UL)
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x800U << 10U) : \
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
#define FMC_BANK1 FMC_BASE
#define FMC_BANK1_1 FMC_BANK1
#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL)
#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL)
#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL)
#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL)
#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL)
/*!< APB2 peripherals */
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
#define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL)
#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL)
#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL)
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL)
#define DSI_BASE (APB2PERIPH_BASE + 0x6C00UL)
#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL)
#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL)
#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL)
#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL)
#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL)
#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL)
#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL)
#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL)
#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL)
#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL)
#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL)
#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL)
#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL)
/*!< AHB1 peripherals */
#define DMA1_BASE (AHB1PERIPH_BASE)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL)
#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
#define GFXMMU_BASE (AHB1PERIPH_BASE + 0xC000UL)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL)
#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL)
#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL)
#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL)
#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL)
#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL)
#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020UL)
#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024UL)
#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028UL)
#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002CUL)
#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030UL)
#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034UL)
#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL)
#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL)
#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL)
#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL)
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
/*!< AHB2 peripherals */
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL)
#define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000UL)
#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000UL)
#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL)
#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL)
#define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000UL)
#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
#define OCTOSPIM_BASE (AHB2PERIPH_BASE + 0x08061C00UL)
#define SDMMC1_BASE (AHB2PERIPH_BASE + 0x08062400UL)
/*!< FMC Banks registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
/* Debug MCU registers base address */
#define DBGMCU_BASE (0xE0042000UL)
/*!< USB registers base address */
#define USB_OTG_FS_PERIPH_BASE (0x50000000UL)
#define USB_OTG_GLOBAL_BASE (0x00000000UL)
#define USB_OTG_DEVICE_BASE (0x00000800UL)
#define USB_OTG_IN_ENDPOINT_BASE (0x00000900UL)
#define USB_OTG_OUT_ENDPOINT_BASE (0x00000B00UL)
#define USB_OTG_EP_REG_SIZE (0x00000020UL)
#define USB_OTG_HOST_BASE (0x00000400UL)
#define USB_OTG_HOST_PORT_BASE (0x00000440UL)
#define USB_OTG_HOST_CHANNEL_BASE (0x00000500UL)
#define USB_OTG_HOST_CHANNEL_SIZE (0x00000020UL)
#define USB_OTG_PCGCCTL_BASE (0x00000E00UL)
#define USB_OTG_FIFO_BASE (0x00001000UL)
#define USB_OTG_FIFO_SIZE (0x00001000UL)
#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define CAN ((CAN_TypeDef *) CAN1_BASE)
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC1_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define DSI ((DSI_TypeDef *)DSI_BASE)
#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
/* Aliases to keep compatibility after DFSDM renaming */
#define DFSDM_Channel0 DFSDM1_Channel0
#define DFSDM_Channel1 DFSDM1_Channel1
#define DFSDM_Channel2 DFSDM1_Channel2
#define DFSDM_Channel3 DFSDM1_Channel3
#define DFSDM_Channel4 DFSDM1_Channel4
#define DFSDM_Channel5 DFSDM1_Channel5
#define DFSDM_Channel6 DFSDM1_Channel6
#define DFSDM_Channel7 DFSDM1_Channel7
#define DFSDM_Filter0 DFSDM1_Filter0
#define DFSDM_Filter1 DFSDM1_Filter1
#define DFSDM_Filter2 DFSDM1_Filter2
#define DFSDM_Filter3 DFSDM1_Filter3
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define TSC ((TSC_TypeDef *) TSC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
#define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
*/
/******************** Bit definition for ADC_ISR register *******************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
/******************** Bit definition for ADC_IER register *******************/
#define ADC_IER_ADRDYIE_Pos (0U)
#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos (1U)
#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos (2U)
#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos (3U)
#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos (4U)
#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos (5U)
#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos (6U)
#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos (7U)
#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos (8U)
#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos (9U)
#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
#define ADC_IER_JQOVFIE_Pos (10U)
#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
/* Legacy defines */
#define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
#define ADC_IER_EOC (ADC_IER_EOCIE)
#define ADC_IER_EOS (ADC_IER_EOSIE)
#define ADC_IER_OVR (ADC_IER_OVRIE)
#define ADC_IER_JEOC (ADC_IER_JEOCIE)
#define ADC_IER_JEOS (ADC_IER_JEOSIE)
#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
/******************** Bit definition for ADC_CFGR register ******************/
#define ADC_CFGR_DMAEN_Pos (0U)
#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
#define ADC_CFGR_DMACFG_Pos (1U)
#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
#define ADC_CFGR_DFSDMCFG_Pos (2U)
#define ADC_CFGR_DFSDMCFG_Msk (0x1UL << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */
#define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */
#define ADC_CFGR_RES_Pos (3U)
#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos (10U)
#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos (12U)
#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
#define ADC_CFGR_CONT_Pos (13U)
#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR_AUTDLY_Pos (14U)
#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CFGR_DISCNUM_Pos (17U)
#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos (20U)
#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CFGR_JQM_Pos (21U)
#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
#define ADC_CFGR_AWD1SGL_Pos (22U)
#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR_AWD1EN_Pos (23U)
#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR_JAWD1EN_Pos (24U)
#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR_JAUTO_Pos (25U)
#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
#define ADC_CFGR_AWD1CH_Pos (26U)
#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
#define ADC_CFGR_JQDIS_Pos (31U)
#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
/******************** Bit definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
#define ADC_CFGR2_OVSR_Pos (2U)
#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
#define ADC_SMPR1_SMPPLUS_Pos (31U)
#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
/******************** Bit definition for ADC_SMPR2 register *****************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
/******************** Bit definition for ADC_TR1 register *******************/
#define ADC_TR1_LT1_Pos (0U)
#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
#define ADC_TR1_HT1_Pos (16U)
#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
/******************** Bit definition for ADC_TR2 register *******************/
#define ADC_TR2_LT2_Pos (0U)
#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
#define ADC_TR2_HT2_Pos (16U)
#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
/******************** Bit definition for ADC_TR3 register *******************/
#define ADC_TR3_LT3_Pos (0U)
#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
#define ADC_TR3_HT3_Pos (16U)
#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
/******************** Bit definition for ADC_SQR1 register ******************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ******************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ******************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ******************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
/******************** Bit definition for ADC_JSQR register ******************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTEN_Pos (6U)
#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JSQ1_Pos (8U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ2_Pos (14U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ3_Pos (20U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ4_Pos (26U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
/******************** Bit definition for ADC_OFR1 register ******************/
#define ADC_OFR1_OFFSET1_Pos (0U)
#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
#define ADC_OFR1_OFFSET1_CH_Pos (26U)
#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR1_OFFSET1_EN_Pos (31U)
#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
/******************** Bit definition for ADC_OFR2 register ******************/
#define ADC_OFR2_OFFSET2_Pos (0U)
#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
#define ADC_OFR2_OFFSET2_CH_Pos (26U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR2_OFFSET2_EN_Pos (31U)
#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
/******************** Bit definition for ADC_OFR3 register ******************/
#define ADC_OFR3_OFFSET3_Pos (0U)
#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
#define ADC_OFR3_OFFSET3_CH_Pos (26U)
#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR3_OFFSET3_EN_Pos (31U)
#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
/******************** Bit definition for ADC_OFR4 register ******************/
#define ADC_OFR4_OFFSET4_Pos (0U)
#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
#define ADC_OFR4_OFFSET4_CH_Pos (26U)
#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR4_OFFSET4_EN_Pos (31U)
#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
/******************** Bit definition for ADC_JDR1 register ******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
/******************** Bit definition for ADC_JDR2 register ******************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
/******************** Bit definition for ADC_JDR3 register ******************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
/******************** Bit definition for ADC_JDR4 register ******************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
/******************** Bit definition for ADC_AWD2CR register ****************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_AWD3CR register ****************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_CALFACT register ***************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CCR register *******************/
#define ADC_CCR_CKMODE_Pos (16U)
#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos (18U)
#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
#define ADC_CCR_TSEN_Pos (23U)
#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
#define ADC_CCR_VBATEN_Pos (24U)
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/******************************************************************************/
/* */
/* Controller Area Network */
/* */
/******************************************************************************/
/*!<CAN control and status registers */
/******************* Bit definition for CAN_MCR register ********************/
#define CAN_MCR_INRQ_Pos (0U)
#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
#define CAN_MCR_SLEEP_Pos (1U)
#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
#define CAN_MCR_TXFP_Pos (2U)
#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
#define CAN_MCR_RFLM_Pos (3U)
#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
#define CAN_MCR_NART_Pos (4U)
#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */
#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
#define CAN_MCR_AWUM_Pos (5U)
#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
#define CAN_MCR_ABOM_Pos (6U)
#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
#define CAN_MCR_TTCM_Pos (7U)
#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
#define CAN_MCR_RESET_Pos (15U)
#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
/******************* Bit definition for CAN_MSR register ********************/
#define CAN_MSR_INAK_Pos (0U)
#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
#define CAN_MSR_SLAK_Pos (1U)
#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
#define CAN_MSR_ERRI_Pos (2U)
#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
#define CAN_MSR_WKUI_Pos (3U)
#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
#define CAN_MSR_SLAKI_Pos (4U)
#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
#define CAN_MSR_TXM_Pos (8U)
#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
#define CAN_MSR_RXM_Pos (9U)
#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
#define CAN_MSR_SAMP_Pos (10U)
#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
#define CAN_MSR_RX_Pos (11U)
#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */
#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
/******************* Bit definition for CAN_TSR register ********************/
#define CAN_TSR_RQCP0_Pos (0U)
#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
#define CAN_TSR_TXOK0_Pos (1U)
#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
#define CAN_TSR_ALST0_Pos (2U)
#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
#define CAN_TSR_TERR0_Pos (3U)
#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
#define CAN_TSR_ABRQ0_Pos (7U)
#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
#define CAN_TSR_RQCP1_Pos (8U)
#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
#define CAN_TSR_TXOK1_Pos (9U)
#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
#define CAN_TSR_ALST1_Pos (10U)
#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
#define CAN_TSR_TERR1_Pos (11U)
#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
#define CAN_TSR_ABRQ1_Pos (15U)
#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
#define CAN_TSR_RQCP2_Pos (16U)
#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
#define CAN_TSR_TXOK2_Pos (17U)
#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
#define CAN_TSR_ALST2_Pos (18U)
#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
#define CAN_TSR_TERR2_Pos (19U)
#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
#define CAN_TSR_ABRQ2_Pos (23U)
#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
#define CAN_TSR_CODE_Pos (24U)
#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
#define CAN_TSR_TME_Pos (26U)
#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
#define CAN_TSR_TME0_Pos (26U)
#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
#define CAN_TSR_TME1_Pos (27U)
#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
#define CAN_TSR_TME2_Pos (28U)
#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
#define CAN_TSR_LOW_Pos (29U)
#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
#define CAN_TSR_LOW0_Pos (29U)
#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
#define CAN_TSR_LOW1_Pos (30U)
#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
#define CAN_TSR_LOW2_Pos (31U)
#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
/******************* Bit definition for CAN_RF0R register *******************/
#define CAN_RF0R_FMP0_Pos (0U)
#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
#define CAN_RF0R_FULL0_Pos (3U)
#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
#define CAN_RF0R_FOVR0_Pos (4U)
#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
#define CAN_RF0R_RFOM0_Pos (5U)
#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
/******************* Bit definition for CAN_RF1R register *******************/
#define CAN_RF1R_FMP1_Pos (0U)
#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
#define CAN_RF1R_FULL1_Pos (3U)
#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
#define CAN_RF1R_FOVR1_Pos (4U)
#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
#define CAN_RF1R_RFOM1_Pos (5U)
#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
/******************** Bit definition for CAN_IER register *******************/
#define CAN_IER_TMEIE_Pos (0U)
#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
#define CAN_IER_FMPIE0_Pos (1U)
#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
#define CAN_IER_FFIE0_Pos (2U)
#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
#define CAN_IER_FOVIE0_Pos (3U)
#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
#define CAN_IER_FMPIE1_Pos (4U)
#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
#define CAN_IER_FFIE1_Pos (5U)
#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
#define CAN_IER_FOVIE1_Pos (6U)
#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
#define CAN_IER_EWGIE_Pos (8U)
#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
#define CAN_IER_EPVIE_Pos (9U)
#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
#define CAN_IER_BOFIE_Pos (10U)
#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
#define CAN_IER_LECIE_Pos (11U)
#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
#define CAN_IER_ERRIE_Pos (15U)
#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
#define CAN_IER_WKUIE_Pos (16U)
#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
#define CAN_IER_SLKIE_Pos (17U)
#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
/******************** Bit definition for CAN_ESR register *******************/
#define CAN_ESR_EWGF_Pos (0U)
#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
#define CAN_ESR_EPVF_Pos (1U)
#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
#define CAN_ESR_BOFF_Pos (2U)
#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
#define CAN_ESR_LEC_Pos (4U)
#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
#define CAN_ESR_TEC_Pos (16U)
#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
#define CAN_ESR_REC_Pos (24U)
#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
/******************* Bit definition for CAN_BTR register ********************/
#define CAN_BTR_BRP_Pos (0U)
#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
#define CAN_BTR_TS1_Pos (16U)
#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
#define CAN_BTR_TS2_Pos (20U)
#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
#define CAN_BTR_SJW_Pos (24U)
#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
#define CAN_BTR_LBKM_Pos (30U)
#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
#define CAN_BTR_SILM_Pos (31U)
#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
/*!<Mailbox registers */
/****************** Bit definition for CAN_TI0R register ********************/
#define CAN_TI0R_TXRQ_Pos (0U)
#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
#define CAN_TI0R_RTR_Pos (1U)
#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
#define CAN_TI0R_IDE_Pos (2U)
#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
#define CAN_TI0R_EXID_Pos (3U)
#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
#define CAN_TI0R_STID_Pos (21U)
#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
/****************** Bit definition for CAN_TDT0R register *******************/
#define CAN_TDT0R_DLC_Pos (0U)
#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
#define CAN_TDT0R_TGT_Pos (8U)
#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
#define CAN_TDT0R_TIME_Pos (16U)
#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
/****************** Bit definition for CAN_TDL0R register *******************/
#define CAN_TDL0R_DATA0_Pos (0U)
#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
#define CAN_TDL0R_DATA1_Pos (8U)
#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
#define CAN_TDL0R_DATA2_Pos (16U)
#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
#define CAN_TDL0R_DATA3_Pos (24U)
#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
/****************** Bit definition for CAN_TDH0R register *******************/
#define CAN_TDH0R_DATA4_Pos (0U)
#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
#define CAN_TDH0R_DATA5_Pos (8U)
#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
#define CAN_TDH0R_DATA6_Pos (16U)
#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
#define CAN_TDH0R_DATA7_Pos (24U)
#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
/******************* Bit definition for CAN_TI1R register *******************/
#define CAN_TI1R_TXRQ_Pos (0U)
#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
#define CAN_TI1R_RTR_Pos (1U)
#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
#define CAN_TI1R_IDE_Pos (2U)
#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
#define CAN_TI1R_EXID_Pos (3U)
#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
#define CAN_TI1R_STID_Pos (21U)
#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_TDT1R register ******************/
#define CAN_TDT1R_DLC_Pos (0U)
#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
#define CAN_TDT1R_TGT_Pos (8U)
#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
#define CAN_TDT1R_TIME_Pos (16U)
#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
/******************* Bit definition for CAN_TDL1R register ******************/
#define CAN_TDL1R_DATA0_Pos (0U)
#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
#define CAN_TDL1R_DATA1_Pos (8U)
#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
#define CAN_TDL1R_DATA2_Pos (16U)
#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
#define CAN_TDL1R_DATA3_Pos (24U)
#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
/******************* Bit definition for CAN_TDH1R register ******************/
#define CAN_TDH1R_DATA4_Pos (0U)
#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
#define CAN_TDH1R_DATA5_Pos (8U)
#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
#define CAN_TDH1R_DATA6_Pos (16U)
#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
#define CAN_TDH1R_DATA7_Pos (24U)
#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
/******************* Bit definition for CAN_TI2R register *******************/
#define CAN_TI2R_TXRQ_Pos (0U)
#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
#define CAN_TI2R_RTR_Pos (1U)
#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
#define CAN_TI2R_IDE_Pos (2U)
#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
#define CAN_TI2R_EXID_Pos (3U)
#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
#define CAN_TI2R_STID_Pos (21U)
#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_TDT2R register ******************/
#define CAN_TDT2R_DLC_Pos (0U)
#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
#define CAN_TDT2R_TGT_Pos (8U)
#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
#define CAN_TDT2R_TIME_Pos (16U)
#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
/******************* Bit definition for CAN_TDL2R register ******************/
#define CAN_TDL2R_DATA0_Pos (0U)
#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
#define CAN_TDL2R_DATA1_Pos (8U)
#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
#define CAN_TDL2R_DATA2_Pos (16U)
#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
#define CAN_TDL2R_DATA3_Pos (24U)
#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
/******************* Bit definition for CAN_TDH2R register ******************/
#define CAN_TDH2R_DATA4_Pos (0U)
#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
#define CAN_TDH2R_DATA5_Pos (8U)
#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
#define CAN_TDH2R_DATA6_Pos (16U)
#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
#define CAN_TDH2R_DATA7_Pos (24U)
#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
/******************* Bit definition for CAN_RI0R register *******************/
#define CAN_RI0R_RTR_Pos (1U)
#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
#define CAN_RI0R_IDE_Pos (2U)
#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
#define CAN_RI0R_EXID_Pos (3U)
#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
#define CAN_RI0R_STID_Pos (21U)
#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_RDT0R register ******************/
#define CAN_RDT0R_DLC_Pos (0U)
#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
#define CAN_RDT0R_FMI_Pos (8U)
#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
#define CAN_RDT0R_TIME_Pos (16U)
#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
/******************* Bit definition for CAN_RDL0R register ******************/
#define CAN_RDL0R_DATA0_Pos (0U)
#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
#define CAN_RDL0R_DATA1_Pos (8U)
#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
#define CAN_RDL0R_DATA2_Pos (16U)
#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
#define CAN_RDL0R_DATA3_Pos (24U)
#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
/******************* Bit definition for CAN_RDH0R register ******************/
#define CAN_RDH0R_DATA4_Pos (0U)
#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
#define CAN_RDH0R_DATA5_Pos (8U)
#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
#define CAN_RDH0R_DATA6_Pos (16U)
#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
#define CAN_RDH0R_DATA7_Pos (24U)
#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
/******************* Bit definition for CAN_RI1R register *******************/
#define CAN_RI1R_RTR_Pos (1U)
#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
#define CAN_RI1R_IDE_Pos (2U)
#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
#define CAN_RI1R_EXID_Pos (3U)
#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
#define CAN_RI1R_STID_Pos (21U)
#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_RDT1R register ******************/
#define CAN_RDT1R_DLC_Pos (0U)
#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
#define CAN_RDT1R_FMI_Pos (8U)
#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
#define CAN_RDT1R_TIME_Pos (16U)
#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
/******************* Bit definition for CAN_RDL1R register ******************/
#define CAN_RDL1R_DATA0_Pos (0U)
#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
#define CAN_RDL1R_DATA1_Pos (8U)
#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
#define CAN_RDL1R_DATA2_Pos (16U)
#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
#define CAN_RDL1R_DATA3_Pos (24U)
#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
/******************* Bit definition for CAN_RDH1R register ******************/
#define CAN_RDH1R_DATA4_Pos (0U)
#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
#define CAN_RDH1R_DATA5_Pos (8U)
#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
#define CAN_RDH1R_DATA6_Pos (16U)
#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
#define CAN_RDH1R_DATA7_Pos (24U)
#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
/*!<CAN filter registers */
/******************* Bit definition for CAN_FMR register ********************/
#define CAN_FMR_FINIT_Pos (0U)
#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
/******************* Bit definition for CAN_FM1R register *******************/
#define CAN_FM1R_FBM_Pos (0U)
#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
#define CAN_FM1R_FBM0_Pos (0U)
#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1_Pos (1U)
#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2_Pos (2U)
#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
#define CAN_FM1R_FBM3_Pos (3U)
#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
#define CAN_FM1R_FBM4_Pos (4U)
#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
#define CAN_FM1R_FBM5_Pos (5U)
#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
#define CAN_FM1R_FBM6_Pos (6U)
#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
#define CAN_FM1R_FBM7_Pos (7U)
#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
#define CAN_FM1R_FBM8_Pos (8U)
#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
#define CAN_FM1R_FBM9_Pos (9U)
#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
#define CAN_FM1R_FBM10_Pos (10U)
#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
#define CAN_FM1R_FBM11_Pos (11U)
#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12_Pos (12U)
#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13_Pos (13U)
#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
/******************* Bit definition for CAN_FS1R register *******************/
#define CAN_FS1R_FSC_Pos (0U)
#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0_Pos (0U)
#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1_Pos (1U)
#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2_Pos (2U)
#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
#define CAN_FS1R_FSC3_Pos (3U)
#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
#define CAN_FS1R_FSC4_Pos (4U)
#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
#define CAN_FS1R_FSC5_Pos (5U)
#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
#define CAN_FS1R_FSC6_Pos (6U)
#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
#define CAN_FS1R_FSC7_Pos (7U)
#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
#define CAN_FS1R_FSC8_Pos (8U)
#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
#define CAN_FS1R_FSC9_Pos (9U)
#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
#define CAN_FS1R_FSC10_Pos (10U)
#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
#define CAN_FS1R_FSC11_Pos (11U)
#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12_Pos (12U)
#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13_Pos (13U)
#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
/****************** Bit definition for CAN_FFA1R register *******************/
#define CAN_FFA1R_FFA_Pos (0U)
#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
#define CAN_FFA1R_FFA0_Pos (0U)
#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
#define CAN_FFA1R_FFA1_Pos (1U)
#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
#define CAN_FFA1R_FFA2_Pos (2U)
#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
#define CAN_FFA1R_FFA3_Pos (3U)
#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
#define CAN_FFA1R_FFA4_Pos (4U)
#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
#define CAN_FFA1R_FFA5_Pos (5U)
#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
#define CAN_FFA1R_FFA6_Pos (6U)
#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
#define CAN_FFA1R_FFA7_Pos (7U)
#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
#define CAN_FFA1R_FFA8_Pos (8U)
#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
#define CAN_FFA1R_FFA9_Pos (9U)
#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
#define CAN_FFA1R_FFA10_Pos (10U)
#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
#define CAN_FFA1R_FFA11_Pos (11U)
#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
#define CAN_FFA1R_FFA12_Pos (12U)
#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
#define CAN_FFA1R_FFA13_Pos (13U)
#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
/******************* Bit definition for CAN_FA1R register *******************/
#define CAN_FA1R_FACT_Pos (0U)
#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
#define CAN_FA1R_FACT0_Pos (0U)
#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
#define CAN_FA1R_FACT1_Pos (1U)
#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
#define CAN_FA1R_FACT2_Pos (2U)
#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
#define CAN_FA1R_FACT3_Pos (3U)
#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
#define CAN_FA1R_FACT4_Pos (4U)
#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
#define CAN_FA1R_FACT5_Pos (5U)
#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
#define CAN_FA1R_FACT6_Pos (6U)
#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
#define CAN_FA1R_FACT7_Pos (7U)
#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
#define CAN_FA1R_FACT8_Pos (8U)
#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
#define CAN_FA1R_FACT9_Pos (9U)
#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
#define CAN_FA1R_FACT10_Pos (10U)
#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
#define CAN_FA1R_FACT11_Pos (11U)
#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
#define CAN_FA1R_FACT12_Pos (12U)
#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
#define CAN_FA1R_FACT13_Pos (13U)
#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0_Pos (0U)
#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F0R1_FB1_Pos (1U)
#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F0R1_FB2_Pos (2U)
#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F0R1_FB3_Pos (3U)
#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F0R1_FB4_Pos (4U)
#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F0R1_FB5_Pos (5U)
#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F0R1_FB6_Pos (6U)
#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F0R1_FB7_Pos (7U)
#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F0R1_FB8_Pos (8U)
#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F0R1_FB9_Pos (9U)
#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F0R1_FB10_Pos (10U)
#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F0R1_FB11_Pos (11U)
#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F0R1_FB12_Pos (12U)
#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F0R1_FB13_Pos (13U)
#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F0R1_FB14_Pos (14U)
#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F0R1_FB15_Pos (15U)
#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F0R1_FB16_Pos (16U)
#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F0R1_FB17_Pos (17U)
#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F0R1_FB18_Pos (18U)
#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F0R1_FB19_Pos (19U)
#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F0R1_FB20_Pos (20U)
#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F0R1_FB21_Pos (21U)
#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F0R1_FB22_Pos (22U)
#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F0R1_FB23_Pos (23U)
#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F0R1_FB24_Pos (24U)
#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F0R1_FB25_Pos (25U)
#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F0R1_FB26_Pos (26U)
#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F0R1_FB27_Pos (27U)
#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F0R1_FB28_Pos (28U)
#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F0R1_FB29_Pos (29U)
#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F0R1_FB30_Pos (30U)
#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F0R1_FB31_Pos (31U)
#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F1R1 register *******************/
#define CAN_F1R1_FB0_Pos (0U)
#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F1R1_FB1_Pos (1U)
#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F1R1_FB2_Pos (2U)
#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F1R1_FB3_Pos (3U)
#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F1R1_FB4_Pos (4U)
#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F1R1_FB5_Pos (5U)
#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F1R1_FB6_Pos (6U)
#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F1R1_FB7_Pos (7U)
#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F1R1_FB8_Pos (8U)
#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F1R1_FB9_Pos (9U)
#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F1R1_FB10_Pos (10U)
#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F1R1_FB11_Pos (11U)
#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F1R1_FB12_Pos (12U)
#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F1R1_FB13_Pos (13U)
#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F1R1_FB14_Pos (14U)
#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F1R1_FB15_Pos (15U)
#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F1R1_FB16_Pos (16U)
#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F1R1_FB17_Pos (17U)
#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F1R1_FB18_Pos (18U)
#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F1R1_FB19_Pos (19U)
#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F1R1_FB20_Pos (20U)
#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F1R1_FB21_Pos (21U)
#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F1R1_FB22_Pos (22U)
#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F1R1_FB23_Pos (23U)
#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F1R1_FB24_Pos (24U)
#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F1R1_FB25_Pos (25U)
#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F1R1_FB26_Pos (26U)
#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F1R1_FB27_Pos (27U)
#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F1R1_FB28_Pos (28U)
#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F1R1_FB29_Pos (29U)
#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F1R1_FB30_Pos (30U)
#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F1R1_FB31_Pos (31U)
#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F2R1 register *******************/
#define CAN_F2R1_FB0_Pos (0U)
#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F2R1_FB1_Pos (1U)
#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F2R1_FB2_Pos (2U)
#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F2R1_FB3_Pos (3U)
#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F2R1_FB4_Pos (4U)
#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F2R1_FB5_Pos (5U)
#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F2R1_FB6_Pos (6U)
#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F2R1_FB7_Pos (7U)
#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F2R1_FB8_Pos (8U)
#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F2R1_FB9_Pos (9U)
#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F2R1_FB10_Pos (10U)
#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F2R1_FB11_Pos (11U)
#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F2R1_FB12_Pos (12U)
#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F2R1_FB13_Pos (13U)
#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F2R1_FB14_Pos (14U)
#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F2R1_FB15_Pos (15U)
#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F2R1_FB16_Pos (16U)
#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F2R1_FB17_Pos (17U)
#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F2R1_FB18_Pos (18U)
#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F2R1_FB19_Pos (19U)
#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F2R1_FB20_Pos (20U)
#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F2R1_FB21_Pos (21U)
#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F2R1_FB22_Pos (22U)
#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F2R1_FB23_Pos (23U)
#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F2R1_FB24_Pos (24U)
#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F2R1_FB25_Pos (25U)
#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F2R1_FB26_Pos (26U)
#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F2R1_FB27_Pos (27U)
#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F2R1_FB28_Pos (28U)
#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F2R1_FB29_Pos (29U)
#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F2R1_FB30_Pos (30U)
#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F2R1_FB31_Pos (31U)
#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F3R1 register *******************/
#define CAN_F3R1_FB0_Pos (0U)
#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F3R1_FB1_Pos (1U)
#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F3R1_FB2_Pos (2U)
#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F3R1_FB3_Pos (3U)
#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F3R1_FB4_Pos (4U)
#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F3R1_FB5_Pos (5U)
#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F3R1_FB6_Pos (6U)
#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F3R1_FB7_Pos (7U)
#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F3R1_FB8_Pos (8U)
#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F3R1_FB9_Pos (9U)
#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F3R1_FB10_Pos (10U)
#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F3R1_FB11_Pos (11U)
#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F3R1_FB12_Pos (12U)
#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F3R1_FB13_Pos (13U)
#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F3R1_FB14_Pos (14U)
#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F3R1_FB15_Pos (15U)
#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F3R1_FB16_Pos (16U)
#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F3R1_FB17_Pos (17U)
#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F3R1_FB18_Pos (18U)
#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F3R1_FB19_Pos (19U)
#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F3R1_FB20_Pos (20U)
#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F3R1_FB21_Pos (21U)
#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F3R1_FB22_Pos (22U)
#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F3R1_FB23_Pos (23U)
#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F3R1_FB24_Pos (24U)
#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F3R1_FB25_Pos (25U)
#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F3R1_FB26_Pos (26U)
#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F3R1_FB27_Pos (27U)
#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F3R1_FB28_Pos (28U)
#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F3R1_FB29_Pos (29U)
#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F3R1_FB30_Pos (30U)
#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F3R1_FB31_Pos (31U)
#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F4R1 register *******************/
#define CAN_F4R1_FB0_Pos (0U)
#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F4R1_FB1_Pos (1U)
#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F4R1_FB2_Pos (2U)
#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F4R1_FB3_Pos (3U)
#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F4R1_FB4_Pos (4U)
#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F4R1_FB5_Pos (5U)
#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F4R1_FB6_Pos (6U)
#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F4R1_FB7_Pos (7U)
#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F4R1_FB8_Pos (8U)
#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F4R1_FB9_Pos (9U)
#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F4R1_FB10_Pos (10U)
#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F4R1_FB11_Pos (11U)
#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F4R1_FB12_Pos (12U)
#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F4R1_FB13_Pos (13U)
#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F4R1_FB14_Pos (14U)
#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F4R1_FB15_Pos (15U)
#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F4R1_FB16_Pos (16U)
#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F4R1_FB17_Pos (17U)
#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F4R1_FB18_Pos (18U)
#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F4R1_FB19_Pos (19U)
#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F4R1_FB20_Pos (20U)
#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F4R1_FB21_Pos (21U)
#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F4R1_FB22_Pos (22U)
#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F4R1_FB23_Pos (23U)
#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F4R1_FB24_Pos (24U)
#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F4R1_FB25_Pos (25U)
#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F4R1_FB26_Pos (26U)
#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F4R1_FB27_Pos (27U)
#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F4R1_FB28_Pos (28U)
#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F4R1_FB29_Pos (29U)
#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F4R1_FB30_Pos (30U)
#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F4R1_FB31_Pos (31U)
#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F5R1 register *******************/
#define CAN_F5R1_FB0_Pos (0U)
#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F5R1_FB1_Pos (1U)
#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F5R1_FB2_Pos (2U)
#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F5R1_FB3_Pos (3U)
#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F5R1_FB4_Pos (4U)
#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F5R1_FB5_Pos (5U)
#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F5R1_FB6_Pos (6U)
#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F5R1_FB7_Pos (7U)
#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F5R1_FB8_Pos (8U)
#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F5R1_FB9_Pos (9U)
#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F5R1_FB10_Pos (10U)
#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F5R1_FB11_Pos (11U)
#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F5R1_FB12_Pos (12U)
#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F5R1_FB13_Pos (13U)
#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F5R1_FB14_Pos (14U)
#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F5R1_FB15_Pos (15U)
#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F5R1_FB16_Pos (16U)
#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F5R1_FB17_Pos (17U)
#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F5R1_FB18_Pos (18U)
#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F5R1_FB19_Pos (19U)
#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F5R1_FB20_Pos (20U)
#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F5R1_FB21_Pos (21U)
#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F5R1_FB22_Pos (22U)
#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F5R1_FB23_Pos (23U)
#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F5R1_FB24_Pos (24U)
#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F5R1_FB25_Pos (25U)
#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F5R1_FB26_Pos (26U)
#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F5R1_FB27_Pos (27U)
#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F5R1_FB28_Pos (28U)
#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F5R1_FB29_Pos (29U)
#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F5R1_FB30_Pos (30U)
#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F5R1_FB31_Pos (31U)
#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F6R1 register *******************/
#define CAN_F6R1_FB0_Pos (0U)
#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F6R1_FB1_Pos (1U)
#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F6R1_FB2_Pos (2U)
#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F6R1_FB3_Pos (3U)
#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F6R1_FB4_Pos (4U)
#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F6R1_FB5_Pos (5U)
#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F6R1_FB6_Pos (6U)
#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F6R1_FB7_Pos (7U)
#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F6R1_FB8_Pos (8U)
#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F6R1_FB9_Pos (9U)
#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F6R1_FB10_Pos (10U)
#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F6R1_FB11_Pos (11U)
#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F6R1_FB12_Pos (12U)
#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F6R1_FB13_Pos (13U)
#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F6R1_FB14_Pos (14U)
#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F6R1_FB15_Pos (15U)
#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F6R1_FB16_Pos (16U)
#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F6R1_FB17_Pos (17U)
#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F6R1_FB18_Pos (18U)
#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F6R1_FB19_Pos (19U)
#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F6R1_FB20_Pos (20U)
#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F6R1_FB21_Pos (21U)
#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F6R1_FB22_Pos (22U)
#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F6R1_FB23_Pos (23U)
#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F6R1_FB24_Pos (24U)
#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F6R1_FB25_Pos (25U)
#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F6R1_FB26_Pos (26U)
#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F6R1_FB27_Pos (27U)
#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F6R1_FB28_Pos (28U)
#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F6R1_FB29_Pos (29U)
#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F6R1_FB30_Pos (30U)
#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F6R1_FB31_Pos (31U)
#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F7R1 register *******************/
#define CAN_F7R1_FB0_Pos (0U)
#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F7R1_FB1_Pos (1U)
#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F7R1_FB2_Pos (2U)
#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F7R1_FB3_Pos (3U)
#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F7R1_FB4_Pos (4U)
#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F7R1_FB5_Pos (5U)
#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F7R1_FB6_Pos (6U)
#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F7R1_FB7_Pos (7U)
#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F7R1_FB8_Pos (8U)
#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F7R1_FB9_Pos (9U)
#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F7R1_FB10_Pos (10U)
#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F7R1_FB11_Pos (11U)
#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F7R1_FB12_Pos (12U)
#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F7R1_FB13_Pos (13U)
#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F7R1_FB14_Pos (14U)
#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F7R1_FB15_Pos (15U)
#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F7R1_FB16_Pos (16U)
#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F7R1_FB17_Pos (17U)
#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F7R1_FB18_Pos (18U)
#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F7R1_FB19_Pos (19U)
#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F7R1_FB20_Pos (20U)
#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F7R1_FB21_Pos (21U)
#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F7R1_FB22_Pos (22U)
#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F7R1_FB23_Pos (23U)
#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F7R1_FB24_Pos (24U)
#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F7R1_FB25_Pos (25U)
#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F7R1_FB26_Pos (26U)
#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F7R1_FB27_Pos (27U)
#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F7R1_FB28_Pos (28U)
#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F7R1_FB29_Pos (29U)
#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F7R1_FB30_Pos (30U)
#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F7R1_FB31_Pos (31U)
#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F8R1 register *******************/
#define CAN_F8R1_FB0_Pos (0U)
#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F8R1_FB1_Pos (1U)
#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F8R1_FB2_Pos (2U)
#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F8R1_FB3_Pos (3U)
#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F8R1_FB4_Pos (4U)
#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F8R1_FB5_Pos (5U)
#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F8R1_FB6_Pos (6U)
#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F8R1_FB7_Pos (7U)
#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F8R1_FB8_Pos (8U)
#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F8R1_FB9_Pos (9U)
#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F8R1_FB10_Pos (10U)
#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F8R1_FB11_Pos (11U)
#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F8R1_FB12_Pos (12U)
#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F8R1_FB13_Pos (13U)
#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F8R1_FB14_Pos (14U)
#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F8R1_FB15_Pos (15U)
#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F8R1_FB16_Pos (16U)
#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F8R1_FB17_Pos (17U)
#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F8R1_FB18_Pos (18U)
#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F8R1_FB19_Pos (19U)
#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F8R1_FB20_Pos (20U)
#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F8R1_FB21_Pos (21U)
#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F8R1_FB22_Pos (22U)
#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F8R1_FB23_Pos (23U)
#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F8R1_FB24_Pos (24U)
#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F8R1_FB25_Pos (25U)
#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F8R1_FB26_Pos (26U)
#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F8R1_FB27_Pos (27U)
#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F8R1_FB28_Pos (28U)
#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F8R1_FB29_Pos (29U)
#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F8R1_FB30_Pos (30U)
#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F8R1_FB31_Pos (31U)
#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F9R1 register *******************/
#define CAN_F9R1_FB0_Pos (0U)
#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F9R1_FB1_Pos (1U)
#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F9R1_FB2_Pos (2U)
#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F9R1_FB3_Pos (3U)
#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F9R1_FB4_Pos (4U)
#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F9R1_FB5_Pos (5U)
#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F9R1_FB6_Pos (6U)
#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F9R1_FB7_Pos (7U)
#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F9R1_FB8_Pos (8U)
#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F9R1_FB9_Pos (9U)
#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F9R1_FB10_Pos (10U)
#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F9R1_FB11_Pos (11U)
#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F9R1_FB12_Pos (12U)
#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F9R1_FB13_Pos (13U)
#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F9R1_FB14_Pos (14U)
#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F9R1_FB15_Pos (15U)
#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F9R1_FB16_Pos (16U)
#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F9R1_FB17_Pos (17U)
#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F9R1_FB18_Pos (18U)
#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F9R1_FB19_Pos (19U)
#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F9R1_FB20_Pos (20U)
#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F9R1_FB21_Pos (21U)
#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F9R1_FB22_Pos (22U)
#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F9R1_FB23_Pos (23U)
#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F9R1_FB24_Pos (24U)
#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F9R1_FB25_Pos (25U)
#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F9R1_FB26_Pos (26U)
#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F9R1_FB27_Pos (27U)
#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F9R1_FB28_Pos (28U)
#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F9R1_FB29_Pos (29U)
#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F9R1_FB30_Pos (30U)
#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F9R1_FB31_Pos (31U)
#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F10R1 register ******************/
#define CAN_F10R1_FB0_Pos (0U)
#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F10R1_FB1_Pos (1U)
#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F10R1_FB2_Pos (2U)
#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F10R1_FB3_Pos (3U)
#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F10R1_FB4_Pos (4U)
#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F10R1_FB5_Pos (5U)
#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F10R1_FB6_Pos (6U)
#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F10R1_FB7_Pos (7U)
#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F10R1_FB8_Pos (8U)
#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F10R1_FB9_Pos (9U)
#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F10R1_FB10_Pos (10U)
#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F10R1_FB11_Pos (11U)
#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F10R1_FB12_Pos (12U)
#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F10R1_FB13_Pos (13U)
#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F10R1_FB14_Pos (14U)
#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F10R1_FB15_Pos (15U)
#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F10R1_FB16_Pos (16U)
#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F10R1_FB17_Pos (17U)
#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F10R1_FB18_Pos (18U)
#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F10R1_FB19_Pos (19U)
#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F10R1_FB20_Pos (20U)
#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F10R1_FB21_Pos (21U)
#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F10R1_FB22_Pos (22U)
#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F10R1_FB23_Pos (23U)
#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F10R1_FB24_Pos (24U)
#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F10R1_FB25_Pos (25U)
#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F10R1_FB26_Pos (26U)
#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F10R1_FB27_Pos (27U)
#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F10R1_FB28_Pos (28U)
#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F10R1_FB29_Pos (29U)
#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F10R1_FB30_Pos (30U)
#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F10R1_FB31_Pos (31U)
#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F11R1 register ******************/
#define CAN_F11R1_FB0_Pos (0U)
#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F11R1_FB1_Pos (1U)
#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F11R1_FB2_Pos (2U)
#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F11R1_FB3_Pos (3U)
#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F11R1_FB4_Pos (4U)
#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F11R1_FB5_Pos (5U)
#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F11R1_FB6_Pos (6U)
#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F11R1_FB7_Pos (7U)
#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F11R1_FB8_Pos (8U)
#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F11R1_FB9_Pos (9U)
#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F11R1_FB10_Pos (10U)
#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F11R1_FB11_Pos (11U)
#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F11R1_FB12_Pos (12U)
#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F11R1_FB13_Pos (13U)
#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F11R1_FB14_Pos (14U)
#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F11R1_FB15_Pos (15U)
#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F11R1_FB16_Pos (16U)
#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F11R1_FB17_Pos (17U)
#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F11R1_FB18_Pos (18U)
#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F11R1_FB19_Pos (19U)
#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F11R1_FB20_Pos (20U)
#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F11R1_FB21_Pos (21U)
#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F11R1_FB22_Pos (22U)
#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F11R1_FB23_Pos (23U)
#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F11R1_FB24_Pos (24U)
#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F11R1_FB25_Pos (25U)
#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F11R1_FB26_Pos (26U)
#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F11R1_FB27_Pos (27U)
#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F11R1_FB28_Pos (28U)
#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F11R1_FB29_Pos (29U)
#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F11R1_FB30_Pos (30U)
#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F11R1_FB31_Pos (31U)
#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F12R1 register ******************/
#define CAN_F12R1_FB0_Pos (0U)
#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F12R1_FB1_Pos (1U)
#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F12R1_FB2_Pos (2U)
#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F12R1_FB3_Pos (3U)
#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F12R1_FB4_Pos (4U)
#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F12R1_FB5_Pos (5U)
#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F12R1_FB6_Pos (6U)
#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F12R1_FB7_Pos (7U)
#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F12R1_FB8_Pos (8U)
#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F12R1_FB9_Pos (9U)
#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F12R1_FB10_Pos (10U)
#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F12R1_FB11_Pos (11U)
#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F12R1_FB12_Pos (12U)
#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F12R1_FB13_Pos (13U)
#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F12R1_FB14_Pos (14U)
#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F12R1_FB15_Pos (15U)
#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F12R1_FB16_Pos (16U)
#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F12R1_FB17_Pos (17U)
#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F12R1_FB18_Pos (18U)
#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F12R1_FB19_Pos (19U)
#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F12R1_FB20_Pos (20U)
#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F12R1_FB21_Pos (21U)
#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F12R1_FB22_Pos (22U)
#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F12R1_FB23_Pos (23U)
#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F12R1_FB24_Pos (24U)
#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F12R1_FB25_Pos (25U)
#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F12R1_FB26_Pos (26U)
#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F12R1_FB27_Pos (27U)
#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F12R1_FB28_Pos (28U)
#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F12R1_FB29_Pos (29U)
#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F12R1_FB30_Pos (30U)
#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F12R1_FB31_Pos (31U)
#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F13R1 register ******************/
#define CAN_F13R1_FB0_Pos (0U)
#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
#define CAN_F13R1_FB1_Pos (1U)
#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
#define CAN_F13R1_FB2_Pos (2U)
#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
#define CAN_F13R1_FB3_Pos (3U)
#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
#define CAN_F13R1_FB4_Pos (4U)
#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
#define CAN_F13R1_FB5_Pos (5U)
#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
#define CAN_F13R1_FB6_Pos (6U)
#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
#define CAN_F13R1_FB7_Pos (7U)
#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
#define CAN_F13R1_FB8_Pos (8U)
#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
#define CAN_F13R1_FB9_Pos (9U)
#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
#define CAN_F13R1_FB10_Pos (10U)
#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
#define CAN_F13R1_FB11_Pos (11U)
#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
#define CAN_F13R1_FB12_Pos (12U)
#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
#define CAN_F13R1_FB13_Pos (13U)
#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
#define CAN_F13R1_FB14_Pos (14U)
#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
#define CAN_F13R1_FB15_Pos (15U)
#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
#define CAN_F13R1_FB16_Pos (16U)
#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
#define CAN_F13R1_FB17_Pos (17U)
#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
#define CAN_F13R1_FB18_Pos (18U)
#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
#define CAN_F13R1_FB19_Pos (19U)
#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
#define CAN_F13R1_FB20_Pos (20U)
#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
#define CAN_F13R1_FB21_Pos (21U)
#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
#define CAN_F13R1_FB22_Pos (22U)
#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
#define CAN_F13R1_FB23_Pos (23U)
#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
#define CAN_F13R1_FB24_Pos (24U)
#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
#define CAN_F13R1_FB25_Pos (25U)
#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
#define CAN_F13R1_FB26_Pos (26U)
#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
#define CAN_F13R1_FB27_Pos (27U)
#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
#define CAN_F13R1_FB28_Pos (28U)
#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
#define CAN_F13R1_FB29_Pos (29U)
#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
#define CAN_F13R1_FB30_Pos (30U)
#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
#define CAN_F13R1_FB31_Pos (31U)
#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F0R2 register *******************/
#define CAN_F0R2_FB0_Pos (0U)
#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F0R2_FB1_Pos (1U)
#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F0R2_FB2_Pos (2U)
#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F0R2_FB3_Pos (3U)
#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F0R2_FB4_Pos (4U)
#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F0R2_FB5_Pos (5U)
#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F0R2_FB6_Pos (6U)
#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F0R2_FB7_Pos (7U)
#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F0R2_FB8_Pos (8U)
#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F0R2_FB9_Pos (9U)
#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F0R2_FB10_Pos (10U)
#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F0R2_FB11_Pos (11U)
#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F0R2_FB12_Pos (12U)
#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F0R2_FB13_Pos (13U)
#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F0R2_FB14_Pos (14U)
#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F0R2_FB15_Pos (15U)
#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F0R2_FB16_Pos (16U)
#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F0R2_FB17_Pos (17U)
#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F0R2_FB18_Pos (18U)
#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F0R2_FB19_Pos (19U)
#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F0R2_FB20_Pos (20U)
#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F0R2_FB21_Pos (21U)
#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F0R2_FB22_Pos (22U)
#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F0R2_FB23_Pos (23U)
#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F0R2_FB24_Pos (24U)
#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F0R2_FB25_Pos (25U)
#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F0R2_FB26_Pos (26U)
#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F0R2_FB27_Pos (27U)
#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F0R2_FB28_Pos (28U)
#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F0R2_FB29_Pos (29U)
#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F0R2_FB30_Pos (30U)
#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F0R2_FB31_Pos (31U)
#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F1R2 register *******************/
#define CAN_F1R2_FB0_Pos (0U)
#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F1R2_FB1_Pos (1U)
#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F1R2_FB2_Pos (2U)
#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F1R2_FB3_Pos (3U)
#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F1R2_FB4_Pos (4U)
#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F1R2_FB5_Pos (5U)
#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F1R2_FB6_Pos (6U)
#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F1R2_FB7_Pos (7U)
#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F1R2_FB8_Pos (8U)
#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F1R2_FB9_Pos (9U)
#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F1R2_FB10_Pos (10U)
#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F1R2_FB11_Pos (11U)
#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F1R2_FB12_Pos (12U)
#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F1R2_FB13_Pos (13U)
#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F1R2_FB14_Pos (14U)
#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F1R2_FB15_Pos (15U)
#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F1R2_FB16_Pos (16U)
#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F1R2_FB17_Pos (17U)
#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F1R2_FB18_Pos (18U)
#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F1R2_FB19_Pos (19U)
#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F1R2_FB20_Pos (20U)
#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F1R2_FB21_Pos (21U)
#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F1R2_FB22_Pos (22U)
#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F1R2_FB23_Pos (23U)
#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F1R2_FB24_Pos (24U)
#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F1R2_FB25_Pos (25U)
#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F1R2_FB26_Pos (26U)
#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F1R2_FB27_Pos (27U)
#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F1R2_FB28_Pos (28U)
#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F1R2_FB29_Pos (29U)
#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F1R2_FB30_Pos (30U)
#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F1R2_FB31_Pos (31U)
#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F2R2 register *******************/
#define CAN_F2R2_FB0_Pos (0U)
#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F2R2_FB1_Pos (1U)
#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F2R2_FB2_Pos (2U)
#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F2R2_FB3_Pos (3U)
#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F2R2_FB4_Pos (4U)
#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F2R2_FB5_Pos (5U)
#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F2R2_FB6_Pos (6U)
#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F2R2_FB7_Pos (7U)
#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F2R2_FB8_Pos (8U)
#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F2R2_FB9_Pos (9U)
#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F2R2_FB10_Pos (10U)
#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F2R2_FB11_Pos (11U)
#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F2R2_FB12_Pos (12U)
#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F2R2_FB13_Pos (13U)
#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F2R2_FB14_Pos (14U)
#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F2R2_FB15_Pos (15U)
#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F2R2_FB16_Pos (16U)
#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F2R2_FB17_Pos (17U)
#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F2R2_FB18_Pos (18U)
#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F2R2_FB19_Pos (19U)
#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F2R2_FB20_Pos (20U)
#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F2R2_FB21_Pos (21U)
#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F2R2_FB22_Pos (22U)
#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F2R2_FB23_Pos (23U)
#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F2R2_FB24_Pos (24U)
#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F2R2_FB25_Pos (25U)
#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F2R2_FB26_Pos (26U)
#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F2R2_FB27_Pos (27U)
#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F2R2_FB28_Pos (28U)
#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F2R2_FB29_Pos (29U)
#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F2R2_FB30_Pos (30U)
#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F2R2_FB31_Pos (31U)
#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F3R2 register *******************/
#define CAN_F3R2_FB0_Pos (0U)
#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F3R2_FB1_Pos (1U)
#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F3R2_FB2_Pos (2U)
#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F3R2_FB3_Pos (3U)
#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F3R2_FB4_Pos (4U)
#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F3R2_FB5_Pos (5U)
#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F3R2_FB6_Pos (6U)
#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F3R2_FB7_Pos (7U)
#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F3R2_FB8_Pos (8U)
#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F3R2_FB9_Pos (9U)
#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F3R2_FB10_Pos (10U)
#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F3R2_FB11_Pos (11U)
#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F3R2_FB12_Pos (12U)
#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F3R2_FB13_Pos (13U)
#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F3R2_FB14_Pos (14U)
#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F3R2_FB15_Pos (15U)
#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F3R2_FB16_Pos (16U)
#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F3R2_FB17_Pos (17U)
#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F3R2_FB18_Pos (18U)
#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F3R2_FB19_Pos (19U)
#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F3R2_FB20_Pos (20U)
#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F3R2_FB21_Pos (21U)
#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F3R2_FB22_Pos (22U)
#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F3R2_FB23_Pos (23U)
#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F3R2_FB24_Pos (24U)
#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F3R2_FB25_Pos (25U)
#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F3R2_FB26_Pos (26U)
#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F3R2_FB27_Pos (27U)
#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F3R2_FB28_Pos (28U)
#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F3R2_FB29_Pos (29U)
#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F3R2_FB30_Pos (30U)
#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F3R2_FB31_Pos (31U)
#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F4R2 register *******************/
#define CAN_F4R2_FB0_Pos (0U)
#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F4R2_FB1_Pos (1U)
#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F4R2_FB2_Pos (2U)
#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F4R2_FB3_Pos (3U)
#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F4R2_FB4_Pos (4U)
#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F4R2_FB5_Pos (5U)
#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F4R2_FB6_Pos (6U)
#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F4R2_FB7_Pos (7U)
#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F4R2_FB8_Pos (8U)
#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F4R2_FB9_Pos (9U)
#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F4R2_FB10_Pos (10U)
#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F4R2_FB11_Pos (11U)
#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F4R2_FB12_Pos (12U)
#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F4R2_FB13_Pos (13U)
#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F4R2_FB14_Pos (14U)
#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F4R2_FB15_Pos (15U)
#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F4R2_FB16_Pos (16U)
#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F4R2_FB17_Pos (17U)
#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F4R2_FB18_Pos (18U)
#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F4R2_FB19_Pos (19U)
#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F4R2_FB20_Pos (20U)
#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F4R2_FB21_Pos (21U)
#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F4R2_FB22_Pos (22U)
#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F4R2_FB23_Pos (23U)
#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F4R2_FB24_Pos (24U)
#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F4R2_FB25_Pos (25U)
#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F4R2_FB26_Pos (26U)
#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F4R2_FB27_Pos (27U)
#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F4R2_FB28_Pos (28U)
#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F4R2_FB29_Pos (29U)
#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F4R2_FB30_Pos (30U)
#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F4R2_FB31_Pos (31U)
#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F5R2 register *******************/
#define CAN_F5R2_FB0_Pos (0U)
#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F5R2_FB1_Pos (1U)
#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F5R2_FB2_Pos (2U)
#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F5R2_FB3_Pos (3U)
#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F5R2_FB4_Pos (4U)
#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F5R2_FB5_Pos (5U)
#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F5R2_FB6_Pos (6U)
#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F5R2_FB7_Pos (7U)
#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F5R2_FB8_Pos (8U)
#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F5R2_FB9_Pos (9U)
#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F5R2_FB10_Pos (10U)
#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F5R2_FB11_Pos (11U)
#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F5R2_FB12_Pos (12U)
#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F5R2_FB13_Pos (13U)
#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F5R2_FB14_Pos (14U)
#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F5R2_FB15_Pos (15U)
#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F5R2_FB16_Pos (16U)
#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F5R2_FB17_Pos (17U)
#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F5R2_FB18_Pos (18U)
#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F5R2_FB19_Pos (19U)
#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F5R2_FB20_Pos (20U)
#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F5R2_FB21_Pos (21U)
#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F5R2_FB22_Pos (22U)
#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F5R2_FB23_Pos (23U)
#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F5R2_FB24_Pos (24U)
#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F5R2_FB25_Pos (25U)
#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F5R2_FB26_Pos (26U)
#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F5R2_FB27_Pos (27U)
#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F5R2_FB28_Pos (28U)
#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F5R2_FB29_Pos (29U)
#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F5R2_FB30_Pos (30U)
#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F5R2_FB31_Pos (31U)
#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F6R2 register *******************/
#define CAN_F6R2_FB0_Pos (0U)
#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F6R2_FB1_Pos (1U)
#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F6R2_FB2_Pos (2U)
#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F6R2_FB3_Pos (3U)
#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F6R2_FB4_Pos (4U)
#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F6R2_FB5_Pos (5U)
#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F6R2_FB6_Pos (6U)
#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F6R2_FB7_Pos (7U)
#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F6R2_FB8_Pos (8U)
#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F6R2_FB9_Pos (9U)
#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F6R2_FB10_Pos (10U)
#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F6R2_FB11_Pos (11U)
#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F6R2_FB12_Pos (12U)
#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F6R2_FB13_Pos (13U)
#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F6R2_FB14_Pos (14U)
#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F6R2_FB15_Pos (15U)
#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F6R2_FB16_Pos (16U)
#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F6R2_FB17_Pos (17U)
#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F6R2_FB18_Pos (18U)
#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F6R2_FB19_Pos (19U)
#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F6R2_FB20_Pos (20U)
#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F6R2_FB21_Pos (21U)
#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F6R2_FB22_Pos (22U)
#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F6R2_FB23_Pos (23U)
#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F6R2_FB24_Pos (24U)
#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F6R2_FB25_Pos (25U)
#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F6R2_FB26_Pos (26U)
#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F6R2_FB27_Pos (27U)
#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F6R2_FB28_Pos (28U)
#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F6R2_FB29_Pos (29U)
#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F6R2_FB30_Pos (30U)
#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F6R2_FB31_Pos (31U)
#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F7R2 register *******************/
#define CAN_F7R2_FB0_Pos (0U)
#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F7R2_FB1_Pos (1U)
#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F7R2_FB2_Pos (2U)
#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F7R2_FB3_Pos (3U)
#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F7R2_FB4_Pos (4U)
#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F7R2_FB5_Pos (5U)
#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F7R2_FB6_Pos (6U)
#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F7R2_FB7_Pos (7U)
#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F7R2_FB8_Pos (8U)
#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F7R2_FB9_Pos (9U)
#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F7R2_FB10_Pos (10U)
#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F7R2_FB11_Pos (11U)
#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F7R2_FB12_Pos (12U)
#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F7R2_FB13_Pos (13U)
#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F7R2_FB14_Pos (14U)
#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F7R2_FB15_Pos (15U)
#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F7R2_FB16_Pos (16U)
#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F7R2_FB17_Pos (17U)
#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F7R2_FB18_Pos (18U)
#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F7R2_FB19_Pos (19U)
#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F7R2_FB20_Pos (20U)
#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F7R2_FB21_Pos (21U)
#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F7R2_FB22_Pos (22U)
#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F7R2_FB23_Pos (23U)
#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F7R2_FB24_Pos (24U)
#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F7R2_FB25_Pos (25U)
#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F7R2_FB26_Pos (26U)
#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F7R2_FB27_Pos (27U)
#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F7R2_FB28_Pos (28U)
#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F7R2_FB29_Pos (29U)
#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F7R2_FB30_Pos (30U)
#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F7R2_FB31_Pos (31U)
#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F8R2 register *******************/
#define CAN_F8R2_FB0_Pos (0U)
#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F8R2_FB1_Pos (1U)
#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F8R2_FB2_Pos (2U)
#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F8R2_FB3_Pos (3U)
#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F8R2_FB4_Pos (4U)
#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F8R2_FB5_Pos (5U)
#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F8R2_FB6_Pos (6U)
#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F8R2_FB7_Pos (7U)
#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F8R2_FB8_Pos (8U)
#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F8R2_FB9_Pos (9U)
#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F8R2_FB10_Pos (10U)
#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F8R2_FB11_Pos (11U)
#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F8R2_FB12_Pos (12U)
#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F8R2_FB13_Pos (13U)
#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F8R2_FB14_Pos (14U)
#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F8R2_FB15_Pos (15U)
#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F8R2_FB16_Pos (16U)
#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F8R2_FB17_Pos (17U)
#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F8R2_FB18_Pos (18U)
#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F8R2_FB19_Pos (19U)
#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F8R2_FB20_Pos (20U)
#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F8R2_FB21_Pos (21U)
#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F8R2_FB22_Pos (22U)
#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F8R2_FB23_Pos (23U)
#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F8R2_FB24_Pos (24U)
#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F8R2_FB25_Pos (25U)
#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F8R2_FB26_Pos (26U)
#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F8R2_FB27_Pos (27U)
#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F8R2_FB28_Pos (28U)
#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F8R2_FB29_Pos (29U)
#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F8R2_FB30_Pos (30U)
#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F8R2_FB31_Pos (31U)
#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F9R2 register *******************/
#define CAN_F9R2_FB0_Pos (0U)
#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F9R2_FB1_Pos (1U)
#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F9R2_FB2_Pos (2U)
#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F9R2_FB3_Pos (3U)
#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F9R2_FB4_Pos (4U)
#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F9R2_FB5_Pos (5U)
#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F9R2_FB6_Pos (6U)
#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F9R2_FB7_Pos (7U)
#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F9R2_FB8_Pos (8U)
#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F9R2_FB9_Pos (9U)
#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F9R2_FB10_Pos (10U)
#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F9R2_FB11_Pos (11U)
#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F9R2_FB12_Pos (12U)
#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F9R2_FB13_Pos (13U)
#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F9R2_FB14_Pos (14U)
#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F9R2_FB15_Pos (15U)
#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F9R2_FB16_Pos (16U)
#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F9R2_FB17_Pos (17U)
#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F9R2_FB18_Pos (18U)
#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F9R2_FB19_Pos (19U)
#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F9R2_FB20_Pos (20U)
#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F9R2_FB21_Pos (21U)
#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F9R2_FB22_Pos (22U)
#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F9R2_FB23_Pos (23U)
#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F9R2_FB24_Pos (24U)
#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F9R2_FB25_Pos (25U)
#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F9R2_FB26_Pos (26U)
#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F9R2_FB27_Pos (27U)
#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F9R2_FB28_Pos (28U)
#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F9R2_FB29_Pos (29U)
#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F9R2_FB30_Pos (30U)
#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F9R2_FB31_Pos (31U)
#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F10R2 register ******************/
#define CAN_F10R2_FB0_Pos (0U)
#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F10R2_FB1_Pos (1U)
#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F10R2_FB2_Pos (2U)
#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F10R2_FB3_Pos (3U)
#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F10R2_FB4_Pos (4U)
#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F10R2_FB5_Pos (5U)
#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F10R2_FB6_Pos (6U)
#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F10R2_FB7_Pos (7U)
#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F10R2_FB8_Pos (8U)
#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F10R2_FB9_Pos (9U)
#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F10R2_FB10_Pos (10U)
#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F10R2_FB11_Pos (11U)
#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F10R2_FB12_Pos (12U)
#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F10R2_FB13_Pos (13U)
#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F10R2_FB14_Pos (14U)
#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F10R2_FB15_Pos (15U)
#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F10R2_FB16_Pos (16U)
#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F10R2_FB17_Pos (17U)
#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F10R2_FB18_Pos (18U)
#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F10R2_FB19_Pos (19U)
#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F10R2_FB20_Pos (20U)
#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F10R2_FB21_Pos (21U)
#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F10R2_FB22_Pos (22U)
#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F10R2_FB23_Pos (23U)
#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F10R2_FB24_Pos (24U)
#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F10R2_FB25_Pos (25U)
#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F10R2_FB26_Pos (26U)
#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F10R2_FB27_Pos (27U)
#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F10R2_FB28_Pos (28U)
#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F10R2_FB29_Pos (29U)
#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F10R2_FB30_Pos (30U)
#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F10R2_FB31_Pos (31U)
#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F11R2 register ******************/
#define CAN_F11R2_FB0_Pos (0U)
#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F11R2_FB1_Pos (1U)
#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F11R2_FB2_Pos (2U)
#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F11R2_FB3_Pos (3U)
#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F11R2_FB4_Pos (4U)
#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F11R2_FB5_Pos (5U)
#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F11R2_FB6_Pos (6U)
#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F11R2_FB7_Pos (7U)
#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F11R2_FB8_Pos (8U)
#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F11R2_FB9_Pos (9U)
#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F11R2_FB10_Pos (10U)
#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F11R2_FB11_Pos (11U)
#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F11R2_FB12_Pos (12U)
#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F11R2_FB13_Pos (13U)
#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F11R2_FB14_Pos (14U)
#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F11R2_FB15_Pos (15U)
#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F11R2_FB16_Pos (16U)
#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F11R2_FB17_Pos (17U)
#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F11R2_FB18_Pos (18U)
#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F11R2_FB19_Pos (19U)
#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F11R2_FB20_Pos (20U)
#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F11R2_FB21_Pos (21U)
#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F11R2_FB22_Pos (22U)
#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F11R2_FB23_Pos (23U)
#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F11R2_FB24_Pos (24U)
#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F11R2_FB25_Pos (25U)
#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F11R2_FB26_Pos (26U)
#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F11R2_FB27_Pos (27U)
#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F11R2_FB28_Pos (28U)
#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F11R2_FB29_Pos (29U)
#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F11R2_FB30_Pos (30U)
#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F11R2_FB31_Pos (31U)
#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F12R2 register ******************/
#define CAN_F12R2_FB0_Pos (0U)
#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F12R2_FB1_Pos (1U)
#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F12R2_FB2_Pos (2U)
#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F12R2_FB3_Pos (3U)
#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F12R2_FB4_Pos (4U)
#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F12R2_FB5_Pos (5U)
#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F12R2_FB6_Pos (6U)
#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F12R2_FB7_Pos (7U)
#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F12R2_FB8_Pos (8U)
#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F12R2_FB9_Pos (9U)
#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F12R2_FB10_Pos (10U)
#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F12R2_FB11_Pos (11U)
#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F12R2_FB12_Pos (12U)
#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F12R2_FB13_Pos (13U)
#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F12R2_FB14_Pos (14U)
#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F12R2_FB15_Pos (15U)
#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F12R2_FB16_Pos (16U)
#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F12R2_FB17_Pos (17U)
#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F12R2_FB18_Pos (18U)
#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F12R2_FB19_Pos (19U)
#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F12R2_FB20_Pos (20U)
#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F12R2_FB21_Pos (21U)
#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F12R2_FB22_Pos (22U)
#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F12R2_FB23_Pos (23U)
#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F12R2_FB24_Pos (24U)
#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F12R2_FB25_Pos (25U)
#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F12R2_FB26_Pos (26U)
#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F12R2_FB27_Pos (27U)
#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F12R2_FB28_Pos (28U)
#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F12R2_FB29_Pos (29U)
#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F12R2_FB30_Pos (30U)
#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F12R2_FB31_Pos (31U)
#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
/******************* Bit definition for CAN_F13R2 register ******************/
#define CAN_F13R2_FB0_Pos (0U)
#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
#define CAN_F13R2_FB1_Pos (1U)
#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
#define CAN_F13R2_FB2_Pos (2U)
#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
#define CAN_F13R2_FB3_Pos (3U)
#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
#define CAN_F13R2_FB4_Pos (4U)
#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
#define CAN_F13R2_FB5_Pos (5U)
#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
#define CAN_F13R2_FB6_Pos (6U)
#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
#define CAN_F13R2_FB7_Pos (7U)
#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
#define CAN_F13R2_FB8_Pos (8U)
#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
#define CAN_F13R2_FB9_Pos (9U)
#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
#define CAN_F13R2_FB10_Pos (10U)
#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
#define CAN_F13R2_FB11_Pos (11U)
#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
#define CAN_F13R2_FB12_Pos (12U)
#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
#define CAN_F13R2_FB13_Pos (13U)
#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
#define CAN_F13R2_FB14_Pos (14U)
#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
#define CAN_F13R2_FB15_Pos (15U)
#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
#define CAN_F13R2_FB16_Pos (16U)
#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
#define CAN_F13R2_FB17_Pos (17U)
#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
#define CAN_F13R2_FB18_Pos (18U)
#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
#define CAN_F13R2_FB19_Pos (19U)
#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
#define CAN_F13R2_FB20_Pos (20U)
#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
#define CAN_F13R2_FB21_Pos (21U)
#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
#define CAN_F13R2_FB22_Pos (22U)
#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
#define CAN_F13R2_FB23_Pos (23U)
#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
#define CAN_F13R2_FB24_Pos (24U)
#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
#define CAN_F13R2_FB25_Pos (25U)
#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
#define CAN_F13R2_FB26_Pos (26U)
#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
#define CAN_F13R2_FB27_Pos (27U)
#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
#define CAN_F13R2_FB28_Pos (28U)
#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
#define CAN_F13R2_FB29_Pos (29U)
#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
#define CAN_F13R2_FB30_Pos (30U)
#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
#define CAN_F13R2_FB31_Pos (31U)
#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* CRS Clock Recovery System */
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
#define CRS_CR_SYNCOKIE_Pos (0U)
#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos (1U)
#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos (2U)
#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos (3U)
#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos (5U)
#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos (6U)
#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos (7U)
#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos (8U)
#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */
#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */
#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */
#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos (16U)
#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos (24U)
#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos (28U)
#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos (31U)
#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
#define CRS_ISR_SYNCOKF_Pos (0U)
#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos (1U)
#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos (2U)
#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos (3U)
#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos (8U)
#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos (9U)
#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos (10U)
#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos (15U)
#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos (16U)
#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
#define CRS_ICR_SYNCOKC_Pos (0U)
#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos (1U)
#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos (2U)
#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos (3U)
#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
#define DAC_CR_TEN1_Pos (1U)
#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos (2U)
#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos (6U)
#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos (8U)
#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos (12U)
#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos (13U)
#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
#define DAC_CR_HFSEL_Pos (15U)
#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
#define DAC_CR_TEN2_Pos (17U)
#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos (18U)
#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos (22U)
#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos (24U)
#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos (28U)
#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos (29U)
#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR_Pos (0U)
#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR_Pos (4U)
#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR_Pos (0U)
#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR_Pos (0U)
#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR_Pos (4U)
#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR_Pos (0U)
#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR_Pos (0U)
#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos (16U)
#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR_Pos (4U)
#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos (20U)
#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR_Pos (0U)
#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR_Pos (8U)
#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR_Pos (0U)
#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR_Pos (0U)
#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DMAUDR1_Pos (13U)
#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos (14U)
#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
#define DAC_SR_BWST1_Pos (15U)
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
#define DAC_SR_DMAUDR2_Pos (29U)
#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
#define DAC_SR_CAL_FLAG2_Pos (30U)
#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
#define DAC_SR_BWST2_Pos (31U)
#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
/******************* Bit definition for DAC_CCR register ********************/
#define DAC_CCR_OTRIM1_Pos (0U)
#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM2_Pos (16U)
#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
/******************* Bit definition for DAC_MCR register *******************/
#define DAC_MCR_MODE1_Pos (0U)
#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
#define DAC_MCR_MODE2_Pos (16U)
#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
/****************** Bit definition for DAC_SHSR1 register ******************/
#define DAC_SHSR1_TSAMPLE1_Pos (0U)
#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
/****************** Bit definition for DAC_SHSR2 register ******************/
#define DAC_SHSR2_TSAMPLE2_Pos (0U)
#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
/****************** Bit definition for DAC_SHHR register ******************/
#define DAC_SHHR_THOLD1_Pos (0U)
#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
#define DAC_SHHR_THOLD2_Pos (16U)
#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
/****************** Bit definition for DAC_SHRR register ******************/
#define DAC_SHRR_TREFRESH1_Pos (0U)
#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
#define DAC_SHRR_TREFRESH2_Pos (16U)
#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
/******************************************************************************/
/* */
/* DCMI */
/* */
/******************************************************************************/
/******************** Bits definition for DCMI_CR register ******************/
#define DCMI_CR_CAPTURE_Pos (0U)
#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk /*!< DCMI Capture enable */
#define DCMI_CR_CM_Pos (1U)
#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
#define DCMI_CR_CM DCMI_CR_CM_Msk /*!< DCMI Capture mode */
#define DCMI_CR_CROP_Pos (2U)
#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
#define DCMI_CR_CROP DCMI_CR_CROP_Msk /*!< DCMI Crop feature */
#define DCMI_CR_JPEG_Pos (3U)
#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk /*!< DCMI JPEG format */
#define DCMI_CR_ESS_Pos (4U)
#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
#define DCMI_CR_ESS DCMI_CR_ESS_Msk /*!< DCMI Embedded synchronization select */
#define DCMI_CR_PCKPOL_Pos (5U)
#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk /*!< DCMI Pixel clock polarity */
#define DCMI_CR_HSPOL_Pos (6U)
#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk /*!< DCMI Horizontal synchronization polarity */
#define DCMI_CR_VSPOL_Pos (7U)
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk /*!< DCMI Vertical synchronization polarity */
#define DCMI_CR_FCRC_Pos (8U)
#define DCMI_CR_FCRC_Msk (0x3UL << DCMI_CR_FCRC_Pos) /*!< 0x00000300 */
#define DCMI_CR_FCRC DCMI_CR_FCRC_Msk /*!< DCMI Frame capture rate control FCRC[1:0] */
#define DCMI_CR_FCRC_0 (0x1UL << DCMI_CR_FCRC_Pos) /*!< 0x00000100 */
#define DCMI_CR_FCRC_1 (0x2UL << DCMI_CR_FCRC_Pos) /*!< 0x00000200 */
#define DCMI_CR_EDM_Pos (10U)
#define DCMI_CR_EDM_Msk (0x3UL << DCMI_CR_EDM_Pos) /*!< 0x00000C00 */
#define DCMI_CR_EDM DCMI_CR_EDM_Msk /*!< DCMI Extended data mode EDM[1:0] */
#define DCMI_CR_EDM_0 (0x1UL << DCMI_CR_EDM_Pos) /*!< 0x00000400 */
#define DCMI_CR_EDM_1 (0x2UL << DCMI_CR_EDM_Pos) /*!< 0x00000800 */
#define DCMI_CR_ENABLE_Pos (14U)
#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk /*!< DCMI DCMI enable */
#define DCMI_CR_BSM_Pos (16U)
#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
#define DCMI_CR_BSM DCMI_CR_BSM_Msk /*!< DCMI Byte Select mode BSM[1:0] */
#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
#define DCMI_CR_OEBS_Pos (18U)
#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk /*!< DCMI Odd/Even Byte Select (Byte Select Start) */
#define DCMI_CR_LSM_Pos (19U)
#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
#define DCMI_CR_LSM DCMI_CR_LSM_Msk /*!< DCMI Line Select mode */
#define DCMI_CR_OELS_Pos (20U)
#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
#define DCMI_CR_OELS DCMI_CR_OELS_Msk /*!< DCMI Odd/Even Line Select (Line Select Start) */
/******************** Bits definition for DCMI_SR register ******************/
#define DCMI_SR_HSYNC_Pos (0U)
#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
#define DCMI_SR_VSYNC_Pos (1U)
#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
#define DCMI_SR_FNE_Pos (2U)
#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
#define DCMI_SR_FNE DCMI_SR_FNE_Msk /*!< DCMI FIFO not empty */
/******************** Bits definition for DCMI_RISR register ****************/
#define DCMI_RIS_FRAME_RIS_Pos (0U)
#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk /*!< DCMI Capture complete raw interrupt status */
#define DCMI_RIS_OVR_RIS_Pos (1U)
#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk /*!< DCMI Overrun raw interrupt status */
#define DCMI_RIS_ERR_RIS_Pos (2U)
#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk /*!< DCMI Synchronization error raw interrupt status */
#define DCMI_RIS_VSYNC_RIS_Pos (3U)
#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk /*!< DCMI VSYNC raw interrupt status */
#define DCMI_RIS_LINE_RIS_Pos (4U)
#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk /*!< DCMI Line raw interrupt status */
/******************** Bits definition for DCMI_IER register *****************/
#define DCMI_IER_FRAME_IE_Pos (0U)
#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk /*!< DCMI Capture complete interrupt enable */
#define DCMI_IER_OVR_IE_Pos (1U)
#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk /*!< DCMI Overrun interrupt enable */
#define DCMI_IER_ERR_IE_Pos (2U)
#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk /*!< DCMI Synchronization error interrupt enable */
#define DCMI_IER_VSYNC_IE_Pos (3U)
#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk /*!< DCMI VSYNC interrupt enable */
#define DCMI_IER_LINE_IE_Pos (4U)
#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk /*!< DCMI Line interrupt enable */
#define DCMI_IER_INT_IE_Pos (0U)
#define DCMI_IER_INT_IE_Msk (0x1FUL << DCMI_IER_INT_IE_Pos) /*!< 0x0000001F */
#define DCMI_IER_INT_IE DCMI_IER_INT_IE_Msk
/******************** Bits definition for DCMI_MIS register *****************/
#define DCMI_MIS_FRAME_MIS_Pos (0U)
#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk /*!< DCMI Capture complete masked interrupt status */
#define DCMI_MIS_OVR_MIS_Pos (1U)
#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk /*!< DCMI Overrun masked interrupt status */
#define DCMI_MIS_ERR_MIS_Pos (2U)
#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk /*!< DCMI Synchronization error masked interrupt status */
#define DCMI_MIS_VSYNC_MIS_Pos (3U)
#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk /*!< DCMI VSYNC masked interrupt status */
#define DCMI_MIS_LINE_MIS_Pos (4U)
#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk /*!< DCMI Line masked interrupt status */
/******************** Bits definition for DCMI_ICR register *****************/
#define DCMI_ICR_FRAME_ISC_Pos (0U)
#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk /*!< DCMI Capture complete interrupt status clear */
#define DCMI_ICR_OVR_ISC_Pos (1U)
#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk /*!< DCMI Overrun interrupt status clear */
#define DCMI_ICR_ERR_ISC_Pos (2U)
#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk /*!< DCMI Synchronization error interrupt status clear */
#define DCMI_ICR_VSYNC_ISC_Pos (3U)
#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk /*!< DCMI Vertical synch interrupt status clear */
#define DCMI_ICR_LINE_ISC_Pos (4U)
#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk /*!< DCMI line interrupt status clear */
/******************** Bits definition for DCMI_ESCR register ****************/
#define DCMI_ESCR_FSC_Pos (0U)
#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk /*!< DCMI Frame start delimiter code FSC[7:0] */
#define DCMI_ESCR_FSC_0 (0x01UL << DCMI_ESCR_FSC_Pos) /*!< 0x00000001 */
#define DCMI_ESCR_FSC_1 (0x02UL << DCMI_ESCR_FSC_Pos) /*!< 0x00000002 */
#define DCMI_ESCR_FSC_2 (0x04UL << DCMI_ESCR_FSC_Pos) /*!< 0x00000004 */
#define DCMI_ESCR_FSC_3 (0x08UL << DCMI_ESCR_FSC_Pos) /*!< 0x00000008 */
#define DCMI_ESCR_FSC_4 (0x10UL << DCMI_ESCR_FSC_Pos) /*!< 0x00000010 */
#define DCMI_ESCR_FSC_5 (0x20UL << DCMI_ESCR_FSC_Pos) /*!< 0x00000020 */
#define DCMI_ESCR_FSC_6 (0x40UL << DCMI_ESCR_FSC_Pos) /*!< 0x00000040 */
#define DCMI_ESCR_FSC_7 (0x80UL << DCMI_ESCR_FSC_Pos) /*!< 0x00000080 */
#define DCMI_ESCR_LSC_Pos (8U)
#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk /*!< DCMI Line start delimiter code LSC[7:0] */
#define DCMI_ESCR_LSC_0 (0x01UL << DCMI_ESCR_LSC_Pos) /*!< 0x00000100 */
#define DCMI_ESCR_LSC_1 (0x02UL << DCMI_ESCR_LSC_Pos) /*!< 0x00000200 */
#define DCMI_ESCR_LSC_2 (0x04UL << DCMI_ESCR_LSC_Pos) /*!< 0x00000400 */
#define DCMI_ESCR_LSC_3 (0x08UL << DCMI_ESCR_LSC_Pos) /*!< 0x00000800 */
#define DCMI_ESCR_LSC_4 (0x10UL << DCMI_ESCR_LSC_Pos) /*!< 0x00001000 */
#define DCMI_ESCR_LSC_5 (0x20UL << DCMI_ESCR_LSC_Pos) /*!< 0x00002000 */
#define DCMI_ESCR_LSC_6 (0x40UL << DCMI_ESCR_LSC_Pos) /*!< 0x00004000 */
#define DCMI_ESCR_LSC_7 (0x80UL << DCMI_ESCR_LSC_Pos) /*!< 0x00008000 */
#define DCMI_ESCR_LEC_Pos (16U)
#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk /*!< DCMI Line end delimiter code LEC[7:0] */
#define DCMI_ESCR_LEC_0 (0x01UL << DCMI_ESCR_LEC_Pos) /*!< 0x00010000 */
#define DCMI_ESCR_LEC_1 (0x02UL << DCMI_ESCR_LEC_Pos) /*!< 0x00020000 */
#define DCMI_ESCR_LEC_2 (0x04UL << DCMI_ESCR_LEC_Pos) /*!< 0x00040000 */
#define DCMI_ESCR_LEC_3 (0x08UL << DCMI_ESCR_LEC_Pos) /*!< 0x00080000 */
#define DCMI_ESCR_LEC_4 (0x10UL << DCMI_ESCR_LEC_Pos) /*!< 0x00100000 */
#define DCMI_ESCR_LEC_5 (0x20UL << DCMI_ESCR_LEC_Pos) /*!< 0x00200000 */
#define DCMI_ESCR_LEC_6 (0x40UL << DCMI_ESCR_LEC_Pos) /*!< 0x00400000 */
#define DCMI_ESCR_LEC_7 (0x80UL << DCMI_ESCR_LEC_Pos) /*!< 0x00800000 */
#define DCMI_ESCR_FEC_Pos (24U)
#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk /*!< DCMI Frame end delimiter code FEC[7:0] */
#define DCMI_ESCR_FEC_0 (0x01UL << DCMI_ESCR_FEC_Pos) /*!< 0x01000000 */
#define DCMI_ESCR_FEC_1 (0x02UL << DCMI_ESCR_FEC_Pos) /*!< 0x02000000 */
#define DCMI_ESCR_FEC_2 (0x04UL << DCMI_ESCR_FEC_Pos) /*!< 0x04000000 */
#define DCMI_ESCR_FEC_3 (0x08UL << DCMI_ESCR_FEC_Pos) /*!< 0x08000000 */
#define DCMI_ESCR_FEC_4 (0x10UL << DCMI_ESCR_FEC_Pos) /*!< 0x10000000 */
#define DCMI_ESCR_FEC_5 (0x20UL << DCMI_ESCR_FEC_Pos) /*!< 0x20000000 */
#define DCMI_ESCR_FEC_6 (0x40UL << DCMI_ESCR_FEC_Pos) /*!< 0x40000000 */
#define DCMI_ESCR_FEC_7 (0x80UL << DCMI_ESCR_FEC_Pos) /*!< 0x80000000 */
/******************** Bits definition for DCMI_ESUR register ****************/
#define DCMI_ESUR_FSU_Pos (0U)
#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk /*!< DCMI Frame start delimiter unmask FSU[7:0] */
#define DCMI_ESUR_FSU_0 (0x01UL << DCMI_ESUR_FSU_Pos) /*!< 0x00000001 */
#define DCMI_ESUR_FSU_1 (0x02UL << DCMI_ESUR_FSU_Pos) /*!< 0x00000002 */
#define DCMI_ESUR_FSU_2 (0x04UL << DCMI_ESUR_FSU_Pos) /*!< 0x00000004 */
#define DCMI_ESUR_FSU_3 (0x08UL << DCMI_ESUR_FSU_Pos) /*!< 0x00000008 */
#define DCMI_ESUR_FSU_4 (0x10UL << DCMI_ESUR_FSU_Pos) /*!< 0x00000010 */
#define DCMI_ESUR_FSU_5 (0x20UL << DCMI_ESUR_FSU_Pos) /*!< 0x00000020 */
#define DCMI_ESUR_FSU_6 (0x40UL << DCMI_ESUR_FSU_Pos) /*!< 0x00000040 */
#define DCMI_ESUR_FSU_7 (0x80UL << DCMI_ESUR_FSU_Pos) /*!< 0x00000080 */
#define DCMI_ESUR_LSU_Pos (8U)
#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk /*!< DCMI Line start delimiter unmask LSU[7:0] */
#define DCMI_ESUR_LSU_0 (0x01UL << DCMI_ESUR_LSU_Pos) /*!< 0x00000100 */
#define DCMI_ESUR_LSU_1 (0x02UL << DCMI_ESUR_LSU_Pos) /*!< 0x00000200 */
#define DCMI_ESUR_LSU_2 (0x04UL << DCMI_ESUR_LSU_Pos) /*!< 0x00000400 */
#define DCMI_ESUR_LSU_3 (0x08UL << DCMI_ESUR_LSU_Pos) /*!< 0x00000800 */
#define DCMI_ESUR_LSU_4 (0x10UL << DCMI_ESUR_LSU_Pos) /*!< 0x00001000 */
#define DCMI_ESUR_LSU_5 (0x20UL << DCMI_ESUR_LSU_Pos) /*!< 0x00002000 */
#define DCMI_ESUR_LSU_6 (0x40UL << DCMI_ESUR_LSU_Pos) /*!< 0x00004000 */
#define DCMI_ESUR_LSU_7 (0x80UL << DCMI_ESUR_LSU_Pos) /*!< 0x00008000 */
#define DCMI_ESUR_LEU_Pos (16U)
#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk /*!< DCMI Line end delimiter unmask LEU[7:0] */
#define DCMI_ESUR_LEU_0 (0x01UL << DCMI_ESUR_LEU_Pos) /*!< 0x00010000 */
#define DCMI_ESUR_LEU_1 (0x02UL << DCMI_ESUR_LEU_Pos) /*!< 0x00020000 */
#define DCMI_ESUR_LEU_2 (0x04UL << DCMI_ESUR_LEU_Pos) /*!< 0x00040000 */
#define DCMI_ESUR_LEU_3 (0x08UL << DCMI_ESUR_LEU_Pos) /*!< 0x00080000 */
#define DCMI_ESUR_LEU_4 (0x10UL << DCMI_ESUR_LEU_Pos) /*!< 0x00100000 */
#define DCMI_ESUR_LEU_5 (0x20UL << DCMI_ESUR_LEU_Pos) /*!< 0x00200000 */
#define DCMI_ESUR_LEU_6 (0x40UL << DCMI_ESUR_LEU_Pos) /*!< 0x00400000 */
#define DCMI_ESUR_LEU_7 (0x80UL << DCMI_ESUR_LEU_Pos) /*!< 0x00800000 */
#define DCMI_ESUR_FEU_Pos (24U)
#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk /*!< DCMI Frame end delimiter unmask FEU[7:0] */
#define DCMI_ESUR_FEU_0 (0x01UL << DCMI_ESUR_FEU_Pos) /*!< 0x01000000 */
#define DCMI_ESUR_FEU_1 (0x02UL << DCMI_ESUR_FEU_Pos) /*!< 0x02000000 */
#define DCMI_ESUR_FEU_2 (0x04UL << DCMI_ESUR_FEU_Pos) /*!< 0x04000000 */
#define DCMI_ESUR_FEU_3 (0x08UL << DCMI_ESUR_FEU_Pos) /*!< 0x08000000 */
#define DCMI_ESUR_FEU_4 (0x10UL << DCMI_ESUR_FEU_Pos) /*!< 0x10000000 */
#define DCMI_ESUR_FEU_5 (0x20UL << DCMI_ESUR_FEU_Pos) /*!< 0x20000000 */
#define DCMI_ESUR_FEU_6 (0x40UL << DCMI_ESUR_FEU_Pos) /*!< 0x40000000 */
#define DCMI_ESUR_FEU_7 (0x80UL << DCMI_ESUR_FEU_Pos) /*!< 0x80000000 */
/******************** Bits definition for DCMI_CWSTRT register **************/
#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk /*!< DCMI Horizontal offset count HOFFCNT[13:0] */
#define DCMI_CWSTRT_HOFFCNT_0 (0x0001UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000001 */
#define DCMI_CWSTRT_HOFFCNT_1 (0x0002UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000002 */
#define DCMI_CWSTRT_HOFFCNT_2 (0x0004UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000004 */
#define DCMI_CWSTRT_HOFFCNT_3 (0x0008UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000008 */
#define DCMI_CWSTRT_HOFFCNT_4 (0x0010UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000010 */
#define DCMI_CWSTRT_HOFFCNT_5 (0x0020UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000020 */
#define DCMI_CWSTRT_HOFFCNT_6 (0x0040UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000040 */
#define DCMI_CWSTRT_HOFFCNT_7 (0x0080UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000080 */
#define DCMI_CWSTRT_HOFFCNT_8 (0x0100UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000100 */
#define DCMI_CWSTRT_HOFFCNT_9 (0x0200UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000200 */
#define DCMI_CWSTRT_HOFFCNT_10 (0x0400UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000400 */
#define DCMI_CWSTRT_HOFFCNT_11 (0x0800UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000800 */
#define DCMI_CWSTRT_HOFFCNT_12 (0x1000UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00001000 */
#define DCMI_CWSTRT_HOFFCNT_13 (0x2000UL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00002000 */
#define DCMI_CWSTRT_VST_Pos (16U)
#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk /*!< DCMI Vertical start line count VST[12:0] */
#define DCMI_CWSTRT_VST_0 (0x0001UL << DCMI_CWSTRT_VST_Pos) /*!< 0x00010000 */
#define DCMI_CWSTRT_VST_1 (0x0002UL << DCMI_CWSTRT_VST_Pos) /*!< 0x00020000 */
#define DCMI_CWSTRT_VST_2 (0x0004UL << DCMI_CWSTRT_VST_Pos) /*!< 0x00040000 */
#define DCMI_CWSTRT_VST_3 (0x0008UL << DCMI_CWSTRT_VST_Pos) /*!< 0x00080000 */
#define DCMI_CWSTRT_VST_4 (0x0010UL << DCMI_CWSTRT_VST_Pos) /*!< 0x00100000 */
#define DCMI_CWSTRT_VST_5 (0x0020UL << DCMI_CWSTRT_VST_Pos) /*!< 0x00200000 */
#define DCMI_CWSTRT_VST_6 (0x0040UL << DCMI_CWSTRT_VST_Pos) /*!< 0x00400000 */
#define DCMI_CWSTRT_VST_7 (0x0080UL << DCMI_CWSTRT_VST_Pos) /*!< 0x00800000 */
#define DCMI_CWSTRT_VST_8 (0x0100UL << DCMI_CWSTRT_VST_Pos) /*!< 0x01000000 */
#define DCMI_CWSTRT_VST_9 (0x0200UL << DCMI_CWSTRT_VST_Pos) /*!< 0x02000000 */
#define DCMI_CWSTRT_VST_10 (0x0400UL << DCMI_CWSTRT_VST_Pos) /*!< 0x04000000 */
#define DCMI_CWSTRT_VST_11 (0x0800UL << DCMI_CWSTRT_VST_Pos) /*!< 0x08000000 */
#define DCMI_CWSTRT_VST_12 (0x1000UL << DCMI_CWSTRT_VST_Pos) /*!< 0x10000000 */
/******************** Bits definition for DCMI_CWSIZE register **************/
#define DCMI_CWSIZE_CAPCNT_Pos (0U)
#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk /*!< DCMI Capture count CAPCNT[13:0] */
#define DCMI_CWSIZE_CAPCNT_0 (0x0001UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000001 */
#define DCMI_CWSIZE_CAPCNT_1 (0x0002UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000002 */
#define DCMI_CWSIZE_CAPCNT_2 (0x0004UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000004 */
#define DCMI_CWSIZE_CAPCNT_3 (0x0008UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000008 */
#define DCMI_CWSIZE_CAPCNT_4 (0x0010UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000010 */
#define DCMI_CWSIZE_CAPCNT_5 (0x0020UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000020 */
#define DCMI_CWSIZE_CAPCNT_6 (0x0040UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000040 */
#define DCMI_CWSIZE_CAPCNT_7 (0x0080UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000080 */
#define DCMI_CWSIZE_CAPCNT_8 (0x0100UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000100 */
#define DCMI_CWSIZE_CAPCNT_9 (0x0200UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000200 */
#define DCMI_CWSIZE_CAPCNT_10 (0x0400UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000400 */
#define DCMI_CWSIZE_CAPCNT_11 (0x0800UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000800 */
#define DCMI_CWSIZE_CAPCNT_12 (0x1000UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00001000 */
#define DCMI_CWSIZE_CAPCNT_13 (0x2000UL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00002000 */
#define DCMI_CWSIZE_VLINE_Pos (16U)
#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk /*!< DCMI Vertical line count VLINE[13:0] */
#define DCMI_CWSIZE_VLINE_0 (0x0001UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00010000 */
#define DCMI_CWSIZE_VLINE_1 (0x0002UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00020000 */
#define DCMI_CWSIZE_VLINE_2 (0x0004UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00040000 */
#define DCMI_CWSIZE_VLINE_3 (0x0008UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00080000 */
#define DCMI_CWSIZE_VLINE_4 (0x0010UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00100000 */
#define DCMI_CWSIZE_VLINE_5 (0x0020UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00200000 */
#define DCMI_CWSIZE_VLINE_6 (0x0040UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00400000 */
#define DCMI_CWSIZE_VLINE_7 (0x0080UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00800000 */
#define DCMI_CWSIZE_VLINE_8 (0x0100UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x01000000 */
#define DCMI_CWSIZE_VLINE_9 (0x0200UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x02000000 */
#define DCMI_CWSIZE_VLINE_10 (0x0400UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x04000000 */
#define DCMI_CWSIZE_VLINE_11 (0x0800UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x08000000 */
#define DCMI_CWSIZE_VLINE_12 (0x1000UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x10000000 */
#define DCMI_CWSIZE_VLINE_13 (0x2000UL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x20000000 */
/******************** Bits definition for DCMI_DR register **************/
#define DCMI_DR_BYTE0_Pos (0U)
#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk /*!< DCMI Data byte 0 Byte0[7:0] */
#define DCMI_DR_BYTE0_0 (0x01UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
#define DCMI_DR_BYTE0_1 (0x02UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
#define DCMI_DR_BYTE0_2 (0x04UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
#define DCMI_DR_BYTE0_3 (0x08UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
#define DCMI_DR_BYTE0_4 (0x10UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
#define DCMI_DR_BYTE0_5 (0x20UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
#define DCMI_DR_BYTE0_6 (0x40UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
#define DCMI_DR_BYTE0_7 (0x80UL << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
#define DCMI_DR_BYTE1_Pos (8U)
#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk /*!< DCMI Data byte 1 Byte1[7:0] */
#define DCMI_DR_BYTE1_0 (0x01UL << DCMI_DR_BYTE1_Pos) /*!< 0x00000100 */
#define DCMI_DR_BYTE1_1 (0x02UL << DCMI_DR_BYTE1_Pos) /*!< 0x00000200 */
#define DCMI_DR_BYTE1_2 (0x04UL << DCMI_DR_BYTE1_Pos) /*!< 0x00000400 */
#define DCMI_DR_BYTE1_3 (0x08UL << DCMI_DR_BYTE1_Pos) /*!< 0x00000800 */
#define DCMI_DR_BYTE1_4 (0x10UL << DCMI_DR_BYTE1_Pos) /*!< 0x00001000 */
#define DCMI_DR_BYTE1_5 (0x20UL << DCMI_DR_BYTE1_Pos) /*!< 0x00002000 */
#define DCMI_DR_BYTE1_6 (0x40UL << DCMI_DR_BYTE1_Pos) /*!< 0x00004000 */
#define DCMI_DR_BYTE1_7 (0x80UL << DCMI_DR_BYTE1_Pos) /*!< 0x00008000 */
#define DCMI_DR_BYTE2_Pos (16U)
#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk /*!< DCMI Data byte 2 Byte2[7:0] */
#define DCMI_DR_BYTE2_0 (0x01UL << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
#define DCMI_DR_BYTE2_1 (0x02UL << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
#define DCMI_DR_BYTE2_2 (0x04UL << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
#define DCMI_DR_BYTE2_3 (0x08UL << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
#define DCMI_DR_BYTE2_4 (0x10UL << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
#define DCMI_DR_BYTE2_5 (0x20UL << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
#define DCMI_DR_BYTE2_6 (0x40UL << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
#define DCMI_DR_BYTE2_7 (0x80UL << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
#define DCMI_DR_BYTE3_Pos (24U)
#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk /*!< DCMI Data byte 3 Byte3[7:0] */
#define DCMI_DR_BYTE3_0 (0x01UL << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
#define DCMI_DR_BYTE3_1 (0x02UL << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
#define DCMI_DR_BYTE3_2 (0x04UL << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
#define DCMI_DR_BYTE3_3 (0x08UL << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
#define DCMI_DR_BYTE3_4 (0x10UL << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
#define DCMI_DR_BYTE3_5 (0x20UL << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
#define DCMI_DR_BYTE3_6 (0x40UL << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
#define DCMI_DR_BYTE3_7 (0x80UL << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
/******************************************************************************/
/* */
/* Digital Filter for Sigma Delta Modulators */
/* */
/******************************************************************************/
/**************** DFSDM channel configuration registers ********************/
/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
#define DFSDM_CHCFGR1_CHEN_Pos (7U)
#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
#define DFSDM_CHCFGR1_SITP_Pos (0U)
#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
/**************** Bit definition for DFSDM_CHWDATR register *******************/
#define DFSDM_CHWDATR_WDATA_Pos (0U)
#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
/**************** Bit definition for DFSDM_CHDATINR register *****************/
#define DFSDM_CHDATINR_INDAT0_Pos (0U)
#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
#define DFSDM_CHDATINR_INDAT1_Pos (16U)
#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
/**************** Bit definition for DFSDM_CHDLYR register *******************/
#define DFSDM_CHDLYR_PLSSKP_Pos (0U)
#define DFSDM_CHDLYR_PLSSKP_Msk (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos) /*!< 0x0000003F */
#define DFSDM_CHDLYR_PLSSKP DFSDM_CHDLYR_PLSSKP_Msk /*!< PLSSKP[5:0] Number of input serial samples that will be skipped */
/************************ DFSDM module registers ****************************/
/***************** Bit definition for DFSDM_FLTCR1 register *******************/
#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
#define DFSDM_FLTCR1_FAST_Pos (29U)
#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
#define DFSDM_FLTCR1_RCH_Pos (24U)
#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
#define DFSDM_FLTCR1_RSYNC_Pos (19U)
#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
#define DFSDM_FLTCR1_RCONT_Pos (18U)
#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
#define DFSDM_FLTCR1_JSCAN_Pos (4U)
#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
#define DFSDM_FLTCR1_JSYNC_Pos (3U)
#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
#define DFSDM_FLTCR1_DFEN_Pos (0U)
#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
/***************** Bit definition for DFSDM_FLTCR2 register *******************/
#define DFSDM_FLTCR2_AWDCH_Pos (16U)
#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
#define DFSDM_FLTCR2_EXCH_Pos (8U)
#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
#define DFSDM_FLTCR2_CKABIE_Pos (6U)
#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
#define DFSDM_FLTCR2_SCDIE_Pos (5U)
#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
#define DFSDM_FLTCR2_AWDIE_Pos (4U)
#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
#define DFSDM_FLTCR2_REOCIE_Pos (1U)
#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
/***************** Bit definition for DFSDM_FLTISR register *******************/
#define DFSDM_FLTISR_SCDF_Pos (24U)
#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
#define DFSDM_FLTISR_CKABF_Pos (16U)
#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
#define DFSDM_FLTISR_RCIP_Pos (14U)
#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
#define DFSDM_FLTISR_JCIP_Pos (13U)
#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
#define DFSDM_FLTISR_AWDF_Pos (4U)
#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
#define DFSDM_FLTISR_ROVRF_Pos (3U)
#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
#define DFSDM_FLTISR_JOVRF_Pos (2U)
#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
#define DFSDM_FLTISR_REOCF_Pos (1U)
#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
#define DFSDM_FLTISR_JEOCF_Pos (0U)
#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
/***************** Bit definition for DFSDM_FLTICR register *******************/
#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCDF[7:0] Clear the short circuit detector flag */
#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
/***************** Bit definition for DFSDM_FLTFCR register *******************/
#define DFSDM_FLTFCR_FORD_Pos (29U)
#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
#define DFSDM_FLTFCR_FOSR_Pos (16U)
#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
#define DFSDM_FLTFCR_IOSR_Pos (0U)
#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
/*************** Bit definition for DFSDM_FLTAWSR register *******************/
#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
/******************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
#define DMA_ISR_GIF1_Pos (0U)
#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1_Pos (1U)
#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1_Pos (2U)
#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1_Pos (3U)
#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2_Pos (4U)
#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2_Pos (5U)
#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2_Pos (6U)
#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2_Pos (7U)
#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3_Pos (8U)
#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3_Pos (9U)
#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3_Pos (10U)
#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3_Pos (11U)
#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4_Pos (12U)
#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4_Pos (13U)
#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4_Pos (14U)
#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4_Pos (15U)
#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5_Pos (16U)
#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos (20U)
#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6_Pos (21U)
#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6_Pos (22U)
#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6_Pos (23U)
#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
#define DMA_ISR_GIF7_Pos (24U)
#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
#define DMA_ISR_TCIF7_Pos (25U)
#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
#define DMA_ISR_HTIF7_Pos (26U)
#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
#define DMA_ISR_TEIF7_Pos (27U)
#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
#define DMA_IFCR_CGIF1_Pos (0U)
#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
#define DMA_IFCR_CTCIF1_Pos (1U)
#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1_Pos (2U)
#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1_Pos (3U)
#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2_Pos (4U)
#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2_Pos (5U)
#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2_Pos (6U)
#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2_Pos (7U)
#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3_Pos (8U)
#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3_Pos (9U)
#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3_Pos (10U)
#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4_Pos (12U)
#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4_Pos (13U)
#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4_Pos (14U)
#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4_Pos (15U)
#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos (16U)
#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos (20U)
#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6_Pos (21U)
#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6_Pos (22U)
#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6_Pos (23U)
#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
#define DMA_IFCR_CGIF7_Pos (24U)
#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
#define DMA_IFCR_CTCIF7_Pos (25U)
#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
#define DMA_IFCR_CHTIF7_Pos (26U)
#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
#define DMA_IFCR_CTEIF7_Pos (27U)
#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
#define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
#define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (2U)
#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE_Pos (3U)
#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR_Pos (4U)
#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
#define DMA_CCR_CIRC_Pos (5U)
#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
#define DMA_CCR_PINC_Pos (6U)
#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
#define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
#define DMA_CCR_MSIZE_Pos (10U)
#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
#define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
#define DMA_CCR_MEM2MEM_Pos (14U)
#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
#define DMA_CNDTR_NDT_Pos (0U)
#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
#define DMA_CPAR_PA_Pos (0U)
#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
#define DMA_CMAR_MA_Pos (0U)
#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
/******************************************************************************/
/* */
/* DMAMUX Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
#define DMAMUX_CxCR_SOIE_Pos (8U)
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
#define DMAMUX_CxCR_EGE_Pos (9U)
#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
#define DMAMUX_CxCR_SE_Pos (16U)
#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
#define DMAMUX_CxCR_SPOL_Pos (17U)
#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
#define DMAMUX_CxCR_NBREQ_Pos (19U)
#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
/******************** Bits definition for DMAMUX_CSR register ****************/
#define DMAMUX_CSR_SOF0_Pos (0U)
#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
#define DMAMUX_CSR_SOF1_Pos (1U)
#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
#define DMAMUX_CSR_SOF2_Pos (2U)
#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
#define DMAMUX_CSR_SOF3_Pos (3U)
#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
#define DMAMUX_CSR_SOF4_Pos (4U)
#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
#define DMAMUX_CSR_SOF5_Pos (5U)
#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
#define DMAMUX_CSR_SOF6_Pos (6U)
#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
#define DMAMUX_CSR_SOF7_Pos (7U)
#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
#define DMAMUX_CSR_SOF8_Pos (8U)
#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
#define DMAMUX_CSR_SOF9_Pos (9U)
#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
#define DMAMUX_CSR_SOF10_Pos (10U)
#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
#define DMAMUX_CSR_SOF11_Pos (11U)
#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
#define DMAMUX_CSR_SOF12_Pos (12U)
#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
#define DMAMUX_CSR_SOF13_Pos (13U)
#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
/******************** Bits definition for DMAMUX_CFR register ****************/
#define DMAMUX_CFR_CSOF0_Pos (0U)
#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
#define DMAMUX_CFR_CSOF1_Pos (1U)
#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
#define DMAMUX_CFR_CSOF2_Pos (2U)
#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
#define DMAMUX_CFR_CSOF3_Pos (3U)
#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
#define DMAMUX_CFR_CSOF4_Pos (4U)
#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
#define DMAMUX_CFR_CSOF5_Pos (5U)
#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
#define DMAMUX_CFR_CSOF6_Pos (6U)
#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
#define DMAMUX_CFR_CSOF7_Pos (7U)
#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
#define DMAMUX_CFR_CSOF8_Pos (8U)
#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
#define DMAMUX_CFR_CSOF9_Pos (9U)
#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
#define DMAMUX_CFR_CSOF10_Pos (10U)
#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
#define DMAMUX_CFR_CSOF11_Pos (11U)
#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
#define DMAMUX_CFR_CSOF12_Pos (12U)
#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
#define DMAMUX_CFR_CSOF13_Pos (13U)
#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
/******************** Bits definition for DMAMUX_RGxCR register ************/
#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
#define DMAMUX_RGxCR_OIE_Pos (8U)
#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
#define DMAMUX_RGxCR_GE_Pos (16U)
#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
#define DMAMUX_RGxCR_GPOL_Pos (17U)
#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
/******************** Bits definition for DMAMUX_RGSR register **************/
#define DMAMUX_RGSR_OF0_Pos (0U)
#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
#define DMAMUX_RGSR_OF1_Pos (1U)
#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
#define DMAMUX_RGSR_OF2_Pos (2U)
#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
#define DMAMUX_RGSR_OF3_Pos (3U)
#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
/******************** Bits definition for DMAMUX_RGCFR register ************/
#define DMAMUX_RGCFR_COF0_Pos (0U)
#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
#define DMAMUX_RGCFR_COF1_Pos (1U)
#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
#define DMAMUX_RGCFR_COF2_Pos (2U)
#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
#define DMAMUX_RGCFR_COF3_Pos (3U)
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
/******************************************************************************/
/* */
/* AHB Master DMA2D Controller (DMA2D) */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
*/
#define DMA2D_LINE_OFFSET_MODE_SUPPORT
#define DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT
#define DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT
/******************** Bit definition for DMA2D_CR register ******************/
#define DMA2D_CR_START_Pos (0U)
#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
#define DMA2D_CR_SUSP_Pos (1U)
#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
#define DMA2D_CR_ABORT_Pos (2U)
#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
#define DMA2D_CR_LOM_Pos (6U)
#define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
#define DMA2D_CR_TEIE_Pos (8U)
#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
#define DMA2D_CR_TCIE_Pos (9U)
#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
#define DMA2D_CR_TWIE_Pos (10U)
#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
#define DMA2D_CR_CAEIE_Pos (11U)
#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
#define DMA2D_CR_CTCIE_Pos (12U)
#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
#define DMA2D_CR_CEIE_Pos (13U)
#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
#define DMA2D_CR_MODE_Pos (16U)
#define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
#define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
/******************** Bit definition for DMA2D_ISR register *****************/
#define DMA2D_ISR_TEIF_Pos (0U)
#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
#define DMA2D_ISR_TCIF_Pos (1U)
#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
#define DMA2D_ISR_TWIF_Pos (2U)
#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_ISR_CAEIF_Pos (3U)
#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
#define DMA2D_ISR_CTCIF_Pos (4U)
#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
#define DMA2D_ISR_CEIF_Pos (5U)
#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
/******************** Bit definition for DMA2D_IFCR register ****************/
#define DMA2D_IFCR_CTEIF_Pos (0U)
#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
#define DMA2D_IFCR_CTCIF_Pos (1U)
#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
#define DMA2D_IFCR_CTWIF_Pos (2U)
#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
#define DMA2D_IFCR_CAECIF_Pos (3U)
#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
#define DMA2D_IFCR_CCTCIF_Pos (4U)
#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
#define DMA2D_IFCR_CCEIF_Pos (5U)
#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
/******************** Bit definition for DMA2D_FGMAR register ***************/
#define DMA2D_FGMAR_MA_Pos (0U)
#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
/******************** Bit definition for DMA2D_FGOR register ****************/
#define DMA2D_FGOR_LO_Pos (0U)
#define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
/******************** Bit definition for DMA2D_BGMAR register ***************/
#define DMA2D_BGMAR_MA_Pos (0U)
#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
/******************** Bit definition for DMA2D_BGOR register ****************/
#define DMA2D_BGOR_LO_Pos (0U)
#define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
/******************** Bit definition for DMA2D_FGPFCCR register *************/
#define DMA2D_FGPFCCR_CM_Pos (0U)
#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
#define DMA2D_FGPFCCR_CCM_Pos (4U)
#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
#define DMA2D_FGPFCCR_START_Pos (5U)
#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
#define DMA2D_FGPFCCR_CS_Pos (8U)
#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
#define DMA2D_FGPFCCR_AM_Pos (16U)
#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
#define DMA2D_FGPFCCR_AI_Pos (20U)
#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Alpha Inverted */
#define DMA2D_FGPFCCR_RBS_Pos (21U)
#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Red Blue Swap */
#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
/******************** Bit definition for DMA2D_FGCOLR register **************/
#define DMA2D_FGCOLR_BLUE_Pos (0U)
#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
#define DMA2D_FGCOLR_GREEN_Pos (8U)
#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
#define DMA2D_FGCOLR_RED_Pos (16U)
#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
/******************** Bit definition for DMA2D_BGPFCCR register *************/
#define DMA2D_BGPFCCR_CM_Pos (0U)
#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
#define DMA2D_BGPFCCR_CCM_Pos (4U)
#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
#define DMA2D_BGPFCCR_START_Pos (5U)
#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
#define DMA2D_BGPFCCR_CS_Pos (8U)
#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
#define DMA2D_BGPFCCR_AM_Pos (16U)
#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
#define DMA2D_BGPFCCR_AI_Pos (20U)
#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< Alpha Inverted */
#define DMA2D_BGPFCCR_RBS_Pos (21U)
#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Red Blue Swap */
#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< Alpha value */
/******************** Bit definition for DMA2D_BGCOLR register **************/
#define DMA2D_BGCOLR_BLUE_Pos (0U)
#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
#define DMA2D_BGCOLR_GREEN_Pos (8U)
#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
#define DMA2D_BGCOLR_RED_Pos (16U)
#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
/******************** Bit definition for DMA2D_FGCMAR register **************/
#define DMA2D_FGCMAR_MA_Pos (0U)
#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
/******************** Bit definition for DMA2D_BGCMAR register **************/
#define DMA2D_BGCMAR_MA_Pos (0U)
#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
/******************** Bit definition for DMA2D_OPFCCR register **************/
#define DMA2D_OPFCCR_CM_Pos (0U)
#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
#define DMA2D_OPFCCR_SB_Pos (8U)
#define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
#define DMA2D_OPFCCR_AI_Pos (20U)
#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Alpha Inverted */
#define DMA2D_OPFCCR_RBS_Pos (21U)
#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Red Blue Swap */
/******************** Bit definition for DMA2D_OCOLR register ***************/
/*!<Mode_ARGB8888/RGB888 */
#define DMA2D_OCOLR_BLUE_1 (0x000000FFUL) /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_1 (0x0000FF00UL) /*!< Green Value */
#define DMA2D_OCOLR_RED_1 (0x00FF0000UL) /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_1 (0xFF000000UL) /*!< Alpha Channel Value */
/*!<Mode_RGB565 */
#define DMA2D_OCOLR_BLUE_2 (0x0000001FUL) /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_2 (0x000007E0UL) /*!< Green Value */
#define DMA2D_OCOLR_RED_2 (0x0000F800UL) /*!< Red Value */
/*!<Mode_ARGB1555 */
#define DMA2D_OCOLR_BLUE_3 (0x0000001FUL) /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_3 (0x000003E0UL) /*!< Green Value */
#define DMA2D_OCOLR_RED_3 (0x00007C00UL) /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_3 (0x00008000UL) /*!< Alpha Channel Value */
/*!<Mode_ARGB4444 */
#define DMA2D_OCOLR_BLUE_4 (0x0000000FUL) /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_4 (0x000000F0UL) /*!< Green Value */
#define DMA2D_OCOLR_RED_4 (0x00000F00UL) /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_4 (0x0000F000UL) /*!< Alpha Channel Value */
/******************** Bit definition for DMA2D_OMAR register ****************/
#define DMA2D_OMAR_MA_Pos (0U)
#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
/******************** Bit definition for DMA2D_OOR register *****************/
#define DMA2D_OOR_LO_Pos (0U)
#define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
/******************** Bit definition for DMA2D_NLR register *****************/
#define DMA2D_NLR_NL_Pos (0U)
#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
#define DMA2D_NLR_PL_Pos (16U)
#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
/******************** Bit definition for DMA2D_LWR register *****************/
#define DMA2D_LWR_LW_Pos (0U)
#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
/******************** Bit definition for DMA2D_AMTCR register ***************/
#define DMA2D_AMTCR_EN_Pos (0U)
#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
#define DMA2D_AMTCR_DT_Pos (8U)
#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/
/******************************************************************************/
/* */
/* Display Serial Interface (DSI) */
/* */
/******************************************************************************/
/******************* Bit definition for DSI_VR register *****************/
#define DSI_VR_Pos (1U)
#define DSI_VR_Msk (0x18999815UL << DSI_VR_Pos) /*!< 0x3133302A */
#define DSI_VR DSI_VR_Msk /*!< DSI Host Version */
/******************* Bit definition for DSI_CR register *****************/
#define DSI_CR_EN_Pos (0U)
#define DSI_CR_EN_Msk (0x1UL << DSI_CR_EN_Pos) /*!< 0x00000001 */
#define DSI_CR_EN DSI_CR_EN_Msk /*!< DSI Host power up and reset */
/******************* Bit definition for DSI_CCR register ****************/
#define DSI_CCR_TXECKDIV_Pos (0U)
#define DSI_CCR_TXECKDIV_Msk (0xFFUL << DSI_CCR_TXECKDIV_Pos) /*!< 0x000000FF */
#define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk /*!< TX Escape Clock Division */
#define DSI_CCR_TXECKDIV0_Pos (0U)
#define DSI_CCR_TXECKDIV0_Msk (0x1UL << DSI_CCR_TXECKDIV0_Pos) /*!< 0x00000001 */
#define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
#define DSI_CCR_TXECKDIV1_Pos (1U)
#define DSI_CCR_TXECKDIV1_Msk (0x1UL << DSI_CCR_TXECKDIV1_Pos) /*!< 0x00000002 */
#define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
#define DSI_CCR_TXECKDIV2_Pos (2U)
#define DSI_CCR_TXECKDIV2_Msk (0x1UL << DSI_CCR_TXECKDIV2_Pos) /*!< 0x00000004 */
#define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
#define DSI_CCR_TXECKDIV3_Pos (3U)
#define DSI_CCR_TXECKDIV3_Msk (0x1UL << DSI_CCR_TXECKDIV3_Pos) /*!< 0x00000008 */
#define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
#define DSI_CCR_TXECKDIV4_Pos (4U)
#define DSI_CCR_TXECKDIV4_Msk (0x1UL << DSI_CCR_TXECKDIV4_Pos) /*!< 0x00000010 */
#define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
#define DSI_CCR_TXECKDIV5_Pos (5U)
#define DSI_CCR_TXECKDIV5_Msk (0x1UL << DSI_CCR_TXECKDIV5_Pos) /*!< 0x00000020 */
#define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
#define DSI_CCR_TXECKDIV6_Pos (6U)
#define DSI_CCR_TXECKDIV6_Msk (0x1UL << DSI_CCR_TXECKDIV6_Pos) /*!< 0x00000040 */
#define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
#define DSI_CCR_TXECKDIV7_Pos (7U)
#define DSI_CCR_TXECKDIV7_Msk (0x1UL << DSI_CCR_TXECKDIV7_Pos) /*!< 0x00000080 */
#define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
#define DSI_CCR_TOCKDIV_Pos (8U)
#define DSI_CCR_TOCKDIV_Msk (0xFFUL << DSI_CCR_TOCKDIV_Pos) /*!< 0x0000FF00 */
#define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk /*!< Timeout Clock Division */
#define DSI_CCR_TOCKDIV0_Pos (8U)
#define DSI_CCR_TOCKDIV0_Msk (0x1UL << DSI_CCR_TOCKDIV0_Pos) /*!< 0x00000100 */
#define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
#define DSI_CCR_TOCKDIV1_Pos (9U)
#define DSI_CCR_TOCKDIV1_Msk (0x1UL << DSI_CCR_TOCKDIV1_Pos) /*!< 0x00000200 */
#define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
#define DSI_CCR_TOCKDIV2_Pos (10U)
#define DSI_CCR_TOCKDIV2_Msk (0x1UL << DSI_CCR_TOCKDIV2_Pos) /*!< 0x00000400 */
#define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
#define DSI_CCR_TOCKDIV3_Pos (11U)
#define DSI_CCR_TOCKDIV3_Msk (0x1UL << DSI_CCR_TOCKDIV3_Pos) /*!< 0x00000800 */
#define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
#define DSI_CCR_TOCKDIV4_Pos (12U)
#define DSI_CCR_TOCKDIV4_Msk (0x1UL << DSI_CCR_TOCKDIV4_Pos) /*!< 0x00001000 */
#define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
#define DSI_CCR_TOCKDIV5_Pos (13U)
#define DSI_CCR_TOCKDIV5_Msk (0x1UL << DSI_CCR_TOCKDIV5_Pos) /*!< 0x00002000 */
#define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
#define DSI_CCR_TOCKDIV6_Pos (14U)
#define DSI_CCR_TOCKDIV6_Msk (0x1UL << DSI_CCR_TOCKDIV6_Pos) /*!< 0x00004000 */
#define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
#define DSI_CCR_TOCKDIV7_Pos (15U)
#define DSI_CCR_TOCKDIV7_Msk (0x1UL << DSI_CCR_TOCKDIV7_Pos) /*!< 0x00008000 */
#define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
/******************* Bit definition for DSI_LVCIDR register *************/
#define DSI_LVCIDR_VCID_Pos (0U)
#define DSI_LVCIDR_VCID_Msk (0x3UL << DSI_LVCIDR_VCID_Pos) /*!< 0x00000003 */
#define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk /*!< Virtual Channel ID */
#define DSI_LVCIDR_VCID0_Pos (0U)
#define DSI_LVCIDR_VCID0_Msk (0x1UL << DSI_LVCIDR_VCID0_Pos) /*!< 0x00000001 */
#define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
#define DSI_LVCIDR_VCID1_Pos (1U)
#define DSI_LVCIDR_VCID1_Msk (0x1UL << DSI_LVCIDR_VCID1_Pos) /*!< 0x00000002 */
#define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
/******************* Bit definition for DSI_LCOLCR register *************/
#define DSI_LCOLCR_COLC_Pos (0U)
#define DSI_LCOLCR_COLC_Msk (0xFUL << DSI_LCOLCR_COLC_Pos) /*!< 0x0000000F */
#define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk /*!< Color Coding */
#define DSI_LCOLCR_COLC0_Pos (0U)
#define DSI_LCOLCR_COLC0_Msk (0x1UL << DSI_LCOLCR_COLC0_Pos) /*!< 0x00000001 */
#define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
#define DSI_LCOLCR_COLC1_Pos (5U)
#define DSI_LCOLCR_COLC1_Msk (0x1UL << DSI_LCOLCR_COLC1_Pos) /*!< 0x00000020 */
#define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
#define DSI_LCOLCR_COLC2_Pos (6U)
#define DSI_LCOLCR_COLC2_Msk (0x1UL << DSI_LCOLCR_COLC2_Pos) /*!< 0x00000040 */
#define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
#define DSI_LCOLCR_COLC3_Pos (7U)
#define DSI_LCOLCR_COLC3_Msk (0x1UL << DSI_LCOLCR_COLC3_Pos) /*!< 0x00000080 */
#define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
#define DSI_LCOLCR_LPE_Pos (8U)
#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosely Packet Enable */
/******************* Bit definition for DSI_LPCR register ***************/
#define DSI_LPCR_DEP_Pos (0U)
#define DSI_LPCR_DEP_Msk (0x1UL << DSI_LPCR_DEP_Pos) /*!< 0x00000001 */
#define DSI_LPCR_DEP DSI_LPCR_DEP_Msk /*!< Data Enable Polarity */
#define DSI_LPCR_VSP_Pos (1U)
#define DSI_LPCR_VSP_Msk (0x1UL << DSI_LPCR_VSP_Pos) /*!< 0x00000002 */
#define DSI_LPCR_VSP DSI_LPCR_VSP_Msk /*!< VSYNC Polarity */
#define DSI_LPCR_HSP_Pos (2U)
#define DSI_LPCR_HSP_Msk (0x1UL << DSI_LPCR_HSP_Pos) /*!< 0x00000004 */
#define DSI_LPCR_HSP DSI_LPCR_HSP_Msk /*!< HSYNC Polarity */
/******************* Bit definition for DSI_LPMCR register **************/
#define DSI_LPMCR_VLPSIZE_Pos (0U)
#define DSI_LPMCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCR_VLPSIZE_Pos) /*!< 0x000000FF */
#define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
#define DSI_LPMCR_VLPSIZE0_Pos (0U)
#define DSI_LPMCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCR_VLPSIZE0_Pos) /*!< 0x00000001 */
#define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
#define DSI_LPMCR_VLPSIZE1_Pos (1U)
#define DSI_LPMCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCR_VLPSIZE1_Pos) /*!< 0x00000002 */
#define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
#define DSI_LPMCR_VLPSIZE2_Pos (2U)
#define DSI_LPMCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCR_VLPSIZE2_Pos) /*!< 0x00000004 */
#define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
#define DSI_LPMCR_VLPSIZE3_Pos (3U)
#define DSI_LPMCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCR_VLPSIZE3_Pos) /*!< 0x00000008 */
#define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
#define DSI_LPMCR_VLPSIZE4_Pos (4U)
#define DSI_LPMCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCR_VLPSIZE4_Pos) /*!< 0x00000010 */
#define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
#define DSI_LPMCR_VLPSIZE5_Pos (5U)
#define DSI_LPMCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCR_VLPSIZE5_Pos) /*!< 0x00000020 */
#define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
#define DSI_LPMCR_VLPSIZE6_Pos (6U)
#define DSI_LPMCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCR_VLPSIZE6_Pos) /*!< 0x00000040 */
#define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
#define DSI_LPMCR_VLPSIZE7_Pos (7U)
#define DSI_LPMCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCR_VLPSIZE7_Pos) /*!< 0x00000080 */
#define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
#define DSI_LPMCR_LPSIZE_Pos (16U)
#define DSI_LPMCR_LPSIZE_Msk (0xFFUL << DSI_LPMCR_LPSIZE_Pos) /*!< 0x00FF0000 */
#define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk /*!< Largest Packet Size */
#define DSI_LPMCR_LPSIZE0_Pos (16U)
#define DSI_LPMCR_LPSIZE0_Msk (0x1UL << DSI_LPMCR_LPSIZE0_Pos) /*!< 0x00010000 */
#define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
#define DSI_LPMCR_LPSIZE1_Pos (17U)
#define DSI_LPMCR_LPSIZE1_Msk (0x1UL << DSI_LPMCR_LPSIZE1_Pos) /*!< 0x00020000 */
#define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
#define DSI_LPMCR_LPSIZE2_Pos (18U)
#define DSI_LPMCR_LPSIZE2_Msk (0x1UL << DSI_LPMCR_LPSIZE2_Pos) /*!< 0x00040000 */
#define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
#define DSI_LPMCR_LPSIZE3_Pos (19U)
#define DSI_LPMCR_LPSIZE3_Msk (0x1UL << DSI_LPMCR_LPSIZE3_Pos) /*!< 0x00080000 */
#define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
#define DSI_LPMCR_LPSIZE4_Pos (20U)
#define DSI_LPMCR_LPSIZE4_Msk (0x1UL << DSI_LPMCR_LPSIZE4_Pos) /*!< 0x00100000 */
#define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
#define DSI_LPMCR_LPSIZE5_Pos (21U)
#define DSI_LPMCR_LPSIZE5_Msk (0x1UL << DSI_LPMCR_LPSIZE5_Pos) /*!< 0x00200000 */
#define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
#define DSI_LPMCR_LPSIZE6_Pos (22U)
#define DSI_LPMCR_LPSIZE6_Msk (0x1UL << DSI_LPMCR_LPSIZE6_Pos) /*!< 0x00400000 */
#define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
#define DSI_LPMCR_LPSIZE7_Pos (23U)
#define DSI_LPMCR_LPSIZE7_Msk (0x1UL << DSI_LPMCR_LPSIZE7_Pos) /*!< 0x00800000 */
#define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
/******************* Bit definition for DSI_PCR register ****************/
#define DSI_PCR_ETTXE_Pos (0U)
#define DSI_PCR_ETTXE_Msk (0x1UL << DSI_PCR_ETTXE_Pos) /*!< 0x00000001 */
#define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk /*!< EoTp Transmission Enable */
#define DSI_PCR_ETRXE_Pos (1U)
#define DSI_PCR_ETRXE_Msk (0x1UL << DSI_PCR_ETRXE_Pos) /*!< 0x00000002 */
#define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk /*!< EoTp Reception Enable */
#define DSI_PCR_BTAE_Pos (2U)
#define DSI_PCR_BTAE_Msk (0x1UL << DSI_PCR_BTAE_Pos) /*!< 0x00000004 */
#define DSI_PCR_BTAE DSI_PCR_BTAE_Msk /*!< Bus Turn Around Enable */
#define DSI_PCR_ECCRXE_Pos (3U)
#define DSI_PCR_ECCRXE_Msk (0x1UL << DSI_PCR_ECCRXE_Pos) /*!< 0x00000008 */
#define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk /*!< ECC Reception Enable */
#define DSI_PCR_CRCRXE_Pos (4U)
#define DSI_PCR_CRCRXE_Msk (0x1UL << DSI_PCR_CRCRXE_Pos) /*!< 0x00000010 */
#define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk /*!< CRC Reception Enable */
/******************* Bit definition for DSI_GVCIDR register *************/
#define DSI_GVCIDR_VCID_Pos (0U)
#define DSI_GVCIDR_VCID_Msk (0x3UL << DSI_GVCIDR_VCID_Pos) /*!< 0x00000003 */
#define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk /*!< Virtual Channel ID */
#define DSI_GVCIDR_VCID0_Pos (0U)
#define DSI_GVCIDR_VCID0_Msk (0x1UL << DSI_GVCIDR_VCID0_Pos) /*!< 0x00000001 */
#define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
#define DSI_GVCIDR_VCID1_Pos (1U)
#define DSI_GVCIDR_VCID1_Msk (0x1UL << DSI_GVCIDR_VCID1_Pos) /*!< 0x00000002 */
#define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
/******************* Bit definition for DSI_MCR register ****************/
#define DSI_MCR_CMDM_Pos (0U)
#define DSI_MCR_CMDM_Msk (0x1UL << DSI_MCR_CMDM_Pos) /*!< 0x00000001 */
#define DSI_MCR_CMDM DSI_MCR_CMDM_Msk /*!< Command Mode */
/******************* Bit definition for DSI_VMCR register ***************/
#define DSI_VMCR_VMT_Pos (0U)
#define DSI_VMCR_VMT_Msk (0x3UL << DSI_VMCR_VMT_Pos) /*!< 0x00000003 */
#define DSI_VMCR_VMT DSI_VMCR_VMT_Msk /*!< Video Mode Type */
#define DSI_VMCR_VMT0_Pos (0U)
#define DSI_VMCR_VMT0_Msk (0x1UL << DSI_VMCR_VMT0_Pos) /*!< 0x00000001 */
#define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
#define DSI_VMCR_VMT1_Pos (1U)
#define DSI_VMCR_VMT1_Msk (0x1UL << DSI_VMCR_VMT1_Pos) /*!< 0x00000002 */
#define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
#define DSI_VMCR_LPVSAE_Pos (8U)
#define DSI_VMCR_LPVSAE_Msk (0x1UL << DSI_VMCR_LPVSAE_Pos) /*!< 0x00000100 */
#define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Vertical Sync Active Enable */
#define DSI_VMCR_LPVBPE_Pos (9U)
#define DSI_VMCR_LPVBPE_Msk (0x1UL << DSI_VMCR_LPVBPE_Pos) /*!< 0x00000200 */
#define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enable */
#define DSI_VMCR_LPVFPE_Pos (10U)
#define DSI_VMCR_LPVFPE_Msk (0x1UL << DSI_VMCR_LPVFPE_Pos) /*!< 0x00000400 */
#define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
#define DSI_VMCR_LPVAE_Pos (11U)
#define DSI_VMCR_LPVAE_Msk (0x1UL << DSI_VMCR_LPVAE_Pos) /*!< 0x00000800 */
#define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Vertical Active Enable */
#define DSI_VMCR_LPHBPE_Pos (12U)
#define DSI_VMCR_LPHBPE_Msk (0x1UL << DSI_VMCR_LPHBPE_Pos) /*!< 0x00001000 */
#define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enable */
#define DSI_VMCR_LPHFPE_Pos (13U)
#define DSI_VMCR_LPHFPE_Msk (0x1UL << DSI_VMCR_LPHFPE_Pos) /*!< 0x00002000 */
#define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enable */
#define DSI_VMCR_FBTAAE_Pos (14U)
#define DSI_VMCR_FBTAAE_Msk (0x1UL << DSI_VMCR_FBTAAE_Pos) /*!< 0x00004000 */
#define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-Around Acknowledge Enable */
#define DSI_VMCR_LPCE_Pos (15U)
#define DSI_VMCR_LPCE_Msk (0x1UL << DSI_VMCR_LPCE_Pos) /*!< 0x00008000 */
#define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Command Enable */
#define DSI_VMCR_PGE_Pos (16U)
#define DSI_VMCR_PGE_Msk (0x1UL << DSI_VMCR_PGE_Pos) /*!< 0x00010000 */
#define DSI_VMCR_PGE DSI_VMCR_PGE_Msk /*!< Pattern Generator Enable */
#define DSI_VMCR_PGM_Pos (20U)
#define DSI_VMCR_PGM_Msk (0x1UL << DSI_VMCR_PGM_Pos) /*!< 0x00100000 */
#define DSI_VMCR_PGM DSI_VMCR_PGM_Msk /*!< Pattern Generator Mode */
#define DSI_VMCR_PGO_Pos (24U)
#define DSI_VMCR_PGO_Msk (0x1UL << DSI_VMCR_PGO_Pos) /*!< 0x01000000 */
#define DSI_VMCR_PGO DSI_VMCR_PGO_Msk /*!< Pattern Generator Orientation */
/******************* Bit definition for DSI_VPCR register ***************/
#define DSI_VPCR_VPSIZE_Pos (0U)
#define DSI_VPCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCR_VPSIZE_Pos) /*!< 0x00003FFF */
#define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk /*!< Video Packet Size */
#define DSI_VPCR_VPSIZE0_Pos (0U)
#define DSI_VPCR_VPSIZE0_Msk (0x1UL << DSI_VPCR_VPSIZE0_Pos) /*!< 0x00000001 */
#define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
#define DSI_VPCR_VPSIZE1_Pos (1U)
#define DSI_VPCR_VPSIZE1_Msk (0x1UL << DSI_VPCR_VPSIZE1_Pos) /*!< 0x00000002 */
#define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
#define DSI_VPCR_VPSIZE2_Pos (2U)
#define DSI_VPCR_VPSIZE2_Msk (0x1UL << DSI_VPCR_VPSIZE2_Pos) /*!< 0x00000004 */
#define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
#define DSI_VPCR_VPSIZE3_Pos (3U)
#define DSI_VPCR_VPSIZE3_Msk (0x1UL << DSI_VPCR_VPSIZE3_Pos) /*!< 0x00000008 */
#define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
#define DSI_VPCR_VPSIZE4_Pos (4U)
#define DSI_VPCR_VPSIZE4_Msk (0x1UL << DSI_VPCR_VPSIZE4_Pos) /*!< 0x00000010 */
#define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
#define DSI_VPCR_VPSIZE5_Pos (5U)
#define DSI_VPCR_VPSIZE5_Msk (0x1UL << DSI_VPCR_VPSIZE5_Pos) /*!< 0x00000020 */
#define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
#define DSI_VPCR_VPSIZE6_Pos (6U)
#define DSI_VPCR_VPSIZE6_Msk (0x1UL << DSI_VPCR_VPSIZE6_Pos) /*!< 0x00000040 */
#define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
#define DSI_VPCR_VPSIZE7_Pos (7U)
#define DSI_VPCR_VPSIZE7_Msk (0x1UL << DSI_VPCR_VPSIZE7_Pos) /*!< 0x00000080 */
#define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
#define DSI_VPCR_VPSIZE8_Pos (8U)
#define DSI_VPCR_VPSIZE8_Msk (0x1UL << DSI_VPCR_VPSIZE8_Pos) /*!< 0x00000100 */
#define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
#define DSI_VPCR_VPSIZE9_Pos (9U)
#define DSI_VPCR_VPSIZE9_Msk (0x1UL << DSI_VPCR_VPSIZE9_Pos) /*!< 0x00000200 */
#define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
#define DSI_VPCR_VPSIZE10_Pos (10U)
#define DSI_VPCR_VPSIZE10_Msk (0x1UL << DSI_VPCR_VPSIZE10_Pos) /*!< 0x00000400 */
#define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
#define DSI_VPCR_VPSIZE11_Pos (11U)
#define DSI_VPCR_VPSIZE11_Msk (0x1UL << DSI_VPCR_VPSIZE11_Pos) /*!< 0x00000800 */
#define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
#define DSI_VPCR_VPSIZE12_Pos (12U)
#define DSI_VPCR_VPSIZE12_Msk (0x1UL << DSI_VPCR_VPSIZE12_Pos) /*!< 0x00001000 */
#define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
#define DSI_VPCR_VPSIZE13_Pos (13U)
#define DSI_VPCR_VPSIZE13_Msk (0x1UL << DSI_VPCR_VPSIZE13_Pos) /*!< 0x00002000 */
#define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
/******************* Bit definition for DSI_VCCR register ***************/
#define DSI_VCCR_NUMC_Pos (0U)
#define DSI_VCCR_NUMC_Msk (0x1FFFUL << DSI_VCCR_NUMC_Pos) /*!< 0x00001FFF */
#define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk /*!< Number of Chunks */
#define DSI_VCCR_NUMC0_Pos (0U)
#define DSI_VCCR_NUMC0_Msk (0x1UL << DSI_VCCR_NUMC0_Pos) /*!< 0x00000001 */
#define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
#define DSI_VCCR_NUMC1_Pos (1U)
#define DSI_VCCR_NUMC1_Msk (0x1UL << DSI_VCCR_NUMC1_Pos) /*!< 0x00000002 */
#define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
#define DSI_VCCR_NUMC2_Pos (2U)
#define DSI_VCCR_NUMC2_Msk (0x1UL << DSI_VCCR_NUMC2_Pos) /*!< 0x00000004 */
#define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
#define DSI_VCCR_NUMC3_Pos (3U)
#define DSI_VCCR_NUMC3_Msk (0x1UL << DSI_VCCR_NUMC3_Pos) /*!< 0x00000008 */
#define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
#define DSI_VCCR_NUMC4_Pos (4U)
#define DSI_VCCR_NUMC4_Msk (0x1UL << DSI_VCCR_NUMC4_Pos) /*!< 0x00000010 */
#define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
#define DSI_VCCR_NUMC5_Pos (5U)
#define DSI_VCCR_NUMC5_Msk (0x1UL << DSI_VCCR_NUMC5_Pos) /*!< 0x00000020 */
#define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
#define DSI_VCCR_NUMC6_Pos (6U)
#define DSI_VCCR_NUMC6_Msk (0x1UL << DSI_VCCR_NUMC6_Pos) /*!< 0x00000040 */
#define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
#define DSI_VCCR_NUMC7_Pos (7U)
#define DSI_VCCR_NUMC7_Msk (0x1UL << DSI_VCCR_NUMC7_Pos) /*!< 0x00000080 */
#define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
#define DSI_VCCR_NUMC8_Pos (8U)
#define DSI_VCCR_NUMC8_Msk (0x1UL << DSI_VCCR_NUMC8_Pos) /*!< 0x00000100 */
#define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
#define DSI_VCCR_NUMC9_Pos (9U)
#define DSI_VCCR_NUMC9_Msk (0x1UL << DSI_VCCR_NUMC9_Pos) /*!< 0x00000200 */
#define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
#define DSI_VCCR_NUMC10_Pos (10U)
#define DSI_VCCR_NUMC10_Msk (0x1UL << DSI_VCCR_NUMC10_Pos) /*!< 0x00000400 */
#define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
#define DSI_VCCR_NUMC11_Pos (11U)
#define DSI_VCCR_NUMC11_Msk (0x1UL << DSI_VCCR_NUMC11_Pos) /*!< 0x00000800 */
#define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
#define DSI_VCCR_NUMC12_Pos (12U)
#define DSI_VCCR_NUMC12_Msk (0x1UL << DSI_VCCR_NUMC12_Pos) /*!< 0x00001000 */
#define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
/******************* Bit definition for DSI_VNPCR register **************/
#define DSI_VNPCR_NPSIZE_Pos (0U)
#define DSI_VNPCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos) /*!< 0x00001FFF */
#define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk /*!< Null Packet Size */
#define DSI_VNPCR_NPSIZE0_Pos (0U)
#define DSI_VNPCR_NPSIZE0_Msk (0x1UL << DSI_VNPCR_NPSIZE0_Pos) /*!< 0x00000001 */
#define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
#define DSI_VNPCR_NPSIZE1_Pos (1U)
#define DSI_VNPCR_NPSIZE1_Msk (0x1UL << DSI_VNPCR_NPSIZE1_Pos) /*!< 0x00000002 */
#define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
#define DSI_VNPCR_NPSIZE2_Pos (2U)
#define DSI_VNPCR_NPSIZE2_Msk (0x1UL << DSI_VNPCR_NPSIZE2_Pos) /*!< 0x00000004 */
#define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
#define DSI_VNPCR_NPSIZE3_Pos (3U)
#define DSI_VNPCR_NPSIZE3_Msk (0x1UL << DSI_VNPCR_NPSIZE3_Pos) /*!< 0x00000008 */
#define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
#define DSI_VNPCR_NPSIZE4_Pos (4U)
#define DSI_VNPCR_NPSIZE4_Msk (0x1UL << DSI_VNPCR_NPSIZE4_Pos) /*!< 0x00000010 */
#define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
#define DSI_VNPCR_NPSIZE5_Pos (5U)
#define DSI_VNPCR_NPSIZE5_Msk (0x1UL << DSI_VNPCR_NPSIZE5_Pos) /*!< 0x00000020 */
#define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
#define DSI_VNPCR_NPSIZE6_Pos (6U)
#define DSI_VNPCR_NPSIZE6_Msk (0x1UL << DSI_VNPCR_NPSIZE6_Pos) /*!< 0x00000040 */
#define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
#define DSI_VNPCR_NPSIZE7_Pos (7U)
#define DSI_VNPCR_NPSIZE7_Msk (0x1UL << DSI_VNPCR_NPSIZE7_Pos) /*!< 0x00000080 */
#define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
#define DSI_VNPCR_NPSIZE8_Pos (8U)
#define DSI_VNPCR_NPSIZE8_Msk (0x1UL << DSI_VNPCR_NPSIZE8_Pos) /*!< 0x00000100 */
#define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
#define DSI_VNPCR_NPSIZE9_Pos (9U)
#define DSI_VNPCR_NPSIZE9_Msk (0x1UL << DSI_VNPCR_NPSIZE9_Pos) /*!< 0x00000200 */
#define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
#define DSI_VNPCR_NPSIZE10_Pos (10U)
#define DSI_VNPCR_NPSIZE10_Msk (0x1UL << DSI_VNPCR_NPSIZE10_Pos) /*!< 0x00000400 */
#define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
#define DSI_VNPCR_NPSIZE11_Pos (11U)
#define DSI_VNPCR_NPSIZE11_Msk (0x1UL << DSI_VNPCR_NPSIZE11_Pos) /*!< 0x00000800 */
#define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
#define DSI_VNPCR_NPSIZE12_Pos (12U)
#define DSI_VNPCR_NPSIZE12_Msk (0x1UL << DSI_VNPCR_NPSIZE12_Pos) /*!< 0x00001000 */
#define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
/******************* Bit definition for DSI_VHSACR register *************/
#define DSI_VHSACR_HSA_Pos (0U)
#define DSI_VHSACR_HSA_Msk (0xFFFUL << DSI_VHSACR_HSA_Pos) /*!< 0x00000FFF */
#define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk /*!< Horizontal Synchronism Active duration */
#define DSI_VHSACR_HSA0_Pos (0U)
#define DSI_VHSACR_HSA0_Msk (0x1UL << DSI_VHSACR_HSA0_Pos) /*!< 0x00000001 */
#define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
#define DSI_VHSACR_HSA1_Pos (1U)
#define DSI_VHSACR_HSA1_Msk (0x1UL << DSI_VHSACR_HSA1_Pos) /*!< 0x00000002 */
#define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
#define DSI_VHSACR_HSA2_Pos (2U)
#define DSI_VHSACR_HSA2_Msk (0x1UL << DSI_VHSACR_HSA2_Pos) /*!< 0x00000004 */
#define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
#define DSI_VHSACR_HSA3_Pos (3U)
#define DSI_VHSACR_HSA3_Msk (0x1UL << DSI_VHSACR_HSA3_Pos) /*!< 0x00000008 */
#define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
#define DSI_VHSACR_HSA4_Pos (4U)
#define DSI_VHSACR_HSA4_Msk (0x1UL << DSI_VHSACR_HSA4_Pos) /*!< 0x00000010 */
#define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
#define DSI_VHSACR_HSA5_Pos (5U)
#define DSI_VHSACR_HSA5_Msk (0x1UL << DSI_VHSACR_HSA5_Pos) /*!< 0x00000020 */
#define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
#define DSI_VHSACR_HSA6_Pos (6U)
#define DSI_VHSACR_HSA6_Msk (0x1UL << DSI_VHSACR_HSA6_Pos) /*!< 0x00000040 */
#define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
#define DSI_VHSACR_HSA7_Pos (7U)
#define DSI_VHSACR_HSA7_Msk (0x1UL << DSI_VHSACR_HSA7_Pos) /*!< 0x00000080 */
#define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
#define DSI_VHSACR_HSA8_Pos (8U)
#define DSI_VHSACR_HSA8_Msk (0x1UL << DSI_VHSACR_HSA8_Pos) /*!< 0x00000100 */
#define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
#define DSI_VHSACR_HSA9_Pos (9U)
#define DSI_VHSACR_HSA9_Msk (0x1UL << DSI_VHSACR_HSA9_Pos) /*!< 0x00000200 */
#define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
#define DSI_VHSACR_HSA10_Pos (10U)
#define DSI_VHSACR_HSA10_Msk (0x1UL << DSI_VHSACR_HSA10_Pos) /*!< 0x00000400 */
#define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
#define DSI_VHSACR_HSA11_Pos (11U)
#define DSI_VHSACR_HSA11_Msk (0x1UL << DSI_VHSACR_HSA11_Pos) /*!< 0x00000800 */
#define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
/******************* Bit definition for DSI_VHBPCR register *************/
#define DSI_VHBPCR_HBP_Pos (0U)
#define DSI_VHBPCR_HBP_Msk (0xFFFUL << DSI_VHBPCR_HBP_Pos) /*!< 0x00000FFF */
#define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */
#define DSI_VHBPCR_HBP0_Pos (0U)
#define DSI_VHBPCR_HBP0_Msk (0x1UL << DSI_VHBPCR_HBP0_Pos) /*!< 0x00000001 */
#define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
#define DSI_VHBPCR_HBP1_Pos (1U)
#define DSI_VHBPCR_HBP1_Msk (0x1UL << DSI_VHBPCR_HBP1_Pos) /*!< 0x00000002 */
#define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
#define DSI_VHBPCR_HBP2_Pos (2U)
#define DSI_VHBPCR_HBP2_Msk (0x1UL << DSI_VHBPCR_HBP2_Pos) /*!< 0x00000004 */
#define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
#define DSI_VHBPCR_HBP3_Pos (3U)
#define DSI_VHBPCR_HBP3_Msk (0x1UL << DSI_VHBPCR_HBP3_Pos) /*!< 0x00000008 */
#define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
#define DSI_VHBPCR_HBP4_Pos (4U)
#define DSI_VHBPCR_HBP4_Msk (0x1UL << DSI_VHBPCR_HBP4_Pos) /*!< 0x00000010 */
#define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
#define DSI_VHBPCR_HBP5_Pos (5U)
#define DSI_VHBPCR_HBP5_Msk (0x1UL << DSI_VHBPCR_HBP5_Pos) /*!< 0x00000020 */
#define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
#define DSI_VHBPCR_HBP6_Pos (6U)
#define DSI_VHBPCR_HBP6_Msk (0x1UL << DSI_VHBPCR_HBP6_Pos) /*!< 0x00000040 */
#define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
#define DSI_VHBPCR_HBP7_Pos (7U)
#define DSI_VHBPCR_HBP7_Msk (0x1UL << DSI_VHBPCR_HBP7_Pos) /*!< 0x00000080 */
#define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
#define DSI_VHBPCR_HBP8_Pos (8U)
#define DSI_VHBPCR_HBP8_Msk (0x1UL << DSI_VHBPCR_HBP8_Pos) /*!< 0x00000100 */
#define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
#define DSI_VHBPCR_HBP9_Pos (9U)
#define DSI_VHBPCR_HBP9_Msk (0x1UL << DSI_VHBPCR_HBP9_Pos) /*!< 0x00000200 */
#define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
#define DSI_VHBPCR_HBP10_Pos (10U)
#define DSI_VHBPCR_HBP10_Msk (0x1UL << DSI_VHBPCR_HBP10_Pos) /*!< 0x00000400 */
#define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
#define DSI_VHBPCR_HBP11_Pos (11U)
#define DSI_VHBPCR_HBP11_Msk (0x1UL << DSI_VHBPCR_HBP11_Pos) /*!< 0x00000800 */
#define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
/******************* Bit definition for DSI_VLCR register ***************/
#define DSI_VLCR_HLINE_Pos (0U)
#define DSI_VLCR_HLINE_Msk (0x7FFFUL << DSI_VLCR_HLINE_Pos) /*!< 0x00007FFF */
#define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk /*!< Horizontal Line duration */
#define DSI_VLCR_HLINE0_Pos (0U)
#define DSI_VLCR_HLINE0_Msk (0x1UL << DSI_VLCR_HLINE0_Pos) /*!< 0x00000001 */
#define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
#define DSI_VLCR_HLINE1_Pos (1U)
#define DSI_VLCR_HLINE1_Msk (0x1UL << DSI_VLCR_HLINE1_Pos) /*!< 0x00000002 */
#define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
#define DSI_VLCR_HLINE2_Pos (2U)
#define DSI_VLCR_HLINE2_Msk (0x1UL << DSI_VLCR_HLINE2_Pos) /*!< 0x00000004 */
#define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
#define DSI_VLCR_HLINE3_Pos (3U)
#define DSI_VLCR_HLINE3_Msk (0x1UL << DSI_VLCR_HLINE3_Pos) /*!< 0x00000008 */
#define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
#define DSI_VLCR_HLINE4_Pos (4U)
#define DSI_VLCR_HLINE4_Msk (0x1UL << DSI_VLCR_HLINE4_Pos) /*!< 0x00000010 */
#define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
#define DSI_VLCR_HLINE5_Pos (5U)
#define DSI_VLCR_HLINE5_Msk (0x1UL << DSI_VLCR_HLINE5_Pos) /*!< 0x00000020 */
#define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
#define DSI_VLCR_HLINE6_Pos (6U)
#define DSI_VLCR_HLINE6_Msk (0x1UL << DSI_VLCR_HLINE6_Pos) /*!< 0x00000040 */
#define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
#define DSI_VLCR_HLINE7_Pos (7U)
#define DSI_VLCR_HLINE7_Msk (0x1UL << DSI_VLCR_HLINE7_Pos) /*!< 0x00000080 */
#define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
#define DSI_VLCR_HLINE8_Pos (8U)
#define DSI_VLCR_HLINE8_Msk (0x1UL << DSI_VLCR_HLINE8_Pos) /*!< 0x00000100 */
#define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
#define DSI_VLCR_HLINE9_Pos (9U)
#define DSI_VLCR_HLINE9_Msk (0x1UL << DSI_VLCR_HLINE9_Pos) /*!< 0x00000200 */
#define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
#define DSI_VLCR_HLINE10_Pos (10U)
#define DSI_VLCR_HLINE10_Msk (0x1UL << DSI_VLCR_HLINE10_Pos) /*!< 0x00000400 */
#define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
#define DSI_VLCR_HLINE11_Pos (11U)
#define DSI_VLCR_HLINE11_Msk (0x1UL << DSI_VLCR_HLINE11_Pos) /*!< 0x00000800 */
#define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
#define DSI_VLCR_HLINE12_Pos (12U)
#define DSI_VLCR_HLINE12_Msk (0x1UL << DSI_VLCR_HLINE12_Pos) /*!< 0x00001000 */
#define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
#define DSI_VLCR_HLINE13_Pos (13U)
#define DSI_VLCR_HLINE13_Msk (0x1UL << DSI_VLCR_HLINE13_Pos) /*!< 0x00002000 */
#define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
#define DSI_VLCR_HLINE14_Pos (14U)
#define DSI_VLCR_HLINE14_Msk (0x1UL << DSI_VLCR_HLINE14_Pos) /*!< 0x00004000 */
#define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
/******************* Bit definition for DSI_VVSACR register *************/
#define DSI_VVSACR_VSA_Pos (0U)
#define DSI_VVSACR_VSA_Msk (0x3FFUL << DSI_VVSACR_VSA_Pos) /*!< 0x000003FF */
#define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk /*!< Vertical Synchronism Active duration */
#define DSI_VVSACR_VSA0_Pos (0U)
#define DSI_VVSACR_VSA0_Msk (0x1UL << DSI_VVSACR_VSA0_Pos) /*!< 0x00000001 */
#define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
#define DSI_VVSACR_VSA1_Pos (1U)
#define DSI_VVSACR_VSA1_Msk (0x1UL << DSI_VVSACR_VSA1_Pos) /*!< 0x00000002 */
#define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
#define DSI_VVSACR_VSA2_Pos (2U)
#define DSI_VVSACR_VSA2_Msk (0x1UL << DSI_VVSACR_VSA2_Pos) /*!< 0x00000004 */
#define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
#define DSI_VVSACR_VSA3_Pos (3U)
#define DSI_VVSACR_VSA3_Msk (0x1UL << DSI_VVSACR_VSA3_Pos) /*!< 0x00000008 */
#define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
#define DSI_VVSACR_VSA4_Pos (4U)
#define DSI_VVSACR_VSA4_Msk (0x1UL << DSI_VVSACR_VSA4_Pos) /*!< 0x00000010 */
#define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
#define DSI_VVSACR_VSA5_Pos (5U)
#define DSI_VVSACR_VSA5_Msk (0x1UL << DSI_VVSACR_VSA5_Pos) /*!< 0x00000020 */
#define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
#define DSI_VVSACR_VSA6_Pos (6U)
#define DSI_VVSACR_VSA6_Msk (0x1UL << DSI_VVSACR_VSA6_Pos) /*!< 0x00000040 */
#define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
#define DSI_VVSACR_VSA7_Pos (7U)
#define DSI_VVSACR_VSA7_Msk (0x1UL << DSI_VVSACR_VSA7_Pos) /*!< 0x00000080 */
#define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
#define DSI_VVSACR_VSA8_Pos (8U)
#define DSI_VVSACR_VSA8_Msk (0x1UL << DSI_VVSACR_VSA8_Pos) /*!< 0x00000100 */
#define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
#define DSI_VVSACR_VSA9_Pos (9U)
#define DSI_VVSACR_VSA9_Msk (0x1UL << DSI_VVSACR_VSA9_Pos) /*!< 0x00000200 */
#define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
/******************* Bit definition for DSI_VVBPCR register *************/
#define DSI_VVBPCR_VBP_Pos (0U)
#define DSI_VVBPCR_VBP_Msk (0x3FFUL << DSI_VVBPCR_VBP_Pos) /*!< 0x000003FF */
#define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-Porch duration */
#define DSI_VVBPCR_VBP0_Pos (0U)
#define DSI_VVBPCR_VBP0_Msk (0x1UL << DSI_VVBPCR_VBP0_Pos) /*!< 0x00000001 */
#define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
#define DSI_VVBPCR_VBP1_Pos (1U)
#define DSI_VVBPCR_VBP1_Msk (0x1UL << DSI_VVBPCR_VBP1_Pos) /*!< 0x00000002 */
#define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
#define DSI_VVBPCR_VBP2_Pos (2U)
#define DSI_VVBPCR_VBP2_Msk (0x1UL << DSI_VVBPCR_VBP2_Pos) /*!< 0x00000004 */
#define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
#define DSI_VVBPCR_VBP3_Pos (3U)
#define DSI_VVBPCR_VBP3_Msk (0x1UL << DSI_VVBPCR_VBP3_Pos) /*!< 0x00000008 */
#define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
#define DSI_VVBPCR_VBP4_Pos (4U)
#define DSI_VVBPCR_VBP4_Msk (0x1UL << DSI_VVBPCR_VBP4_Pos) /*!< 0x00000010 */
#define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
#define DSI_VVBPCR_VBP5_Pos (5U)
#define DSI_VVBPCR_VBP5_Msk (0x1UL << DSI_VVBPCR_VBP5_Pos) /*!< 0x00000020 */
#define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
#define DSI_VVBPCR_VBP6_Pos (6U)
#define DSI_VVBPCR_VBP6_Msk (0x1UL << DSI_VVBPCR_VBP6_Pos) /*!< 0x00000040 */
#define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
#define DSI_VVBPCR_VBP7_Pos (7U)
#define DSI_VVBPCR_VBP7_Msk (0x1UL << DSI_VVBPCR_VBP7_Pos) /*!< 0x00000080 */
#define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
#define DSI_VVBPCR_VBP8_Pos (8U)
#define DSI_VVBPCR_VBP8_Msk (0x1UL << DSI_VVBPCR_VBP8_Pos) /*!< 0x00000100 */
#define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
#define DSI_VVBPCR_VBP9_Pos (9U)
#define DSI_VVBPCR_VBP9_Msk (0x1UL << DSI_VVBPCR_VBP9_Pos) /*!< 0x00000200 */
#define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
/******************* Bit definition for DSI_VVFPCR register *************/
#define DSI_VVFPCR_VFP_Pos (0U)
#define DSI_VVFPCR_VFP_Msk (0x3FFUL << DSI_VVFPCR_VFP_Pos) /*!< 0x000003FF */
#define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-Porch duration */
#define DSI_VVFPCR_VFP0_Pos (0U)
#define DSI_VVFPCR_VFP0_Msk (0x1UL << DSI_VVFPCR_VFP0_Pos) /*!< 0x00000001 */
#define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
#define DSI_VVFPCR_VFP1_Pos (1U)
#define DSI_VVFPCR_VFP1_Msk (0x1UL << DSI_VVFPCR_VFP1_Pos) /*!< 0x00000002 */
#define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
#define DSI_VVFPCR_VFP2_Pos (2U)
#define DSI_VVFPCR_VFP2_Msk (0x1UL << DSI_VVFPCR_VFP2_Pos) /*!< 0x00000004 */
#define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
#define DSI_VVFPCR_VFP3_Pos (3U)
#define DSI_VVFPCR_VFP3_Msk (0x1UL << DSI_VVFPCR_VFP3_Pos) /*!< 0x00000008 */
#define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
#define DSI_VVFPCR_VFP4_Pos (4U)
#define DSI_VVFPCR_VFP4_Msk (0x1UL << DSI_VVFPCR_VFP4_Pos) /*!< 0x00000010 */
#define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
#define DSI_VVFPCR_VFP5_Pos (5U)
#define DSI_VVFPCR_VFP5_Msk (0x1UL << DSI_VVFPCR_VFP5_Pos) /*!< 0x00000020 */
#define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
#define DSI_VVFPCR_VFP6_Pos (6U)
#define DSI_VVFPCR_VFP6_Msk (0x1UL << DSI_VVFPCR_VFP6_Pos) /*!< 0x00000040 */
#define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
#define DSI_VVFPCR_VFP7_Pos (7U)
#define DSI_VVFPCR_VFP7_Msk (0x1UL << DSI_VVFPCR_VFP7_Pos) /*!< 0x00000080 */
#define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
#define DSI_VVFPCR_VFP8_Pos (8U)
#define DSI_VVFPCR_VFP8_Msk (0x1UL << DSI_VVFPCR_VFP8_Pos) /*!< 0x00000100 */
#define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
#define DSI_VVFPCR_VFP9_Pos (9U)
#define DSI_VVFPCR_VFP9_Msk (0x1UL << DSI_VVFPCR_VFP9_Pos) /*!< 0x00000200 */
#define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
/******************* Bit definition for DSI_VVACR register **************/
#define DSI_VVACR_VA_Pos (0U)
#define DSI_VVACR_VA_Msk (0x3FFFUL << DSI_VVACR_VA_Pos) /*!< 0x00003FFF */
#define DSI_VVACR_VA DSI_VVACR_VA_Msk /*!< Vertical Active duration */
#define DSI_VVACR_VA0_Pos (0U)
#define DSI_VVACR_VA0_Msk (0x1UL << DSI_VVACR_VA0_Pos) /*!< 0x00000001 */
#define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
#define DSI_VVACR_VA1_Pos (1U)
#define DSI_VVACR_VA1_Msk (0x1UL << DSI_VVACR_VA1_Pos) /*!< 0x00000002 */
#define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
#define DSI_VVACR_VA2_Pos (2U)
#define DSI_VVACR_VA2_Msk (0x1UL << DSI_VVACR_VA2_Pos) /*!< 0x00000004 */
#define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
#define DSI_VVACR_VA3_Pos (3U)
#define DSI_VVACR_VA3_Msk (0x1UL << DSI_VVACR_VA3_Pos) /*!< 0x00000008 */
#define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
#define DSI_VVACR_VA4_Pos (4U)
#define DSI_VVACR_VA4_Msk (0x1UL << DSI_VVACR_VA4_Pos) /*!< 0x00000010 */
#define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
#define DSI_VVACR_VA5_Pos (5U)
#define DSI_VVACR_VA5_Msk (0x1UL << DSI_VVACR_VA5_Pos) /*!< 0x00000020 */
#define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
#define DSI_VVACR_VA6_Pos (6U)
#define DSI_VVACR_VA6_Msk (0x1UL << DSI_VVACR_VA6_Pos) /*!< 0x00000040 */
#define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
#define DSI_VVACR_VA7_Pos (7U)
#define DSI_VVACR_VA7_Msk (0x1UL << DSI_VVACR_VA7_Pos) /*!< 0x00000080 */
#define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
#define DSI_VVACR_VA8_Pos (8U)
#define DSI_VVACR_VA8_Msk (0x1UL << DSI_VVACR_VA8_Pos) /*!< 0x00000100 */
#define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
#define DSI_VVACR_VA9_Pos (9U)
#define DSI_VVACR_VA9_Msk (0x1UL << DSI_VVACR_VA9_Pos) /*!< 0x00000200 */
#define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
#define DSI_VVACR_VA10_Pos (10U)
#define DSI_VVACR_VA10_Msk (0x1UL << DSI_VVACR_VA10_Pos) /*!< 0x00000400 */
#define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
#define DSI_VVACR_VA11_Pos (11U)
#define DSI_VVACR_VA11_Msk (0x1UL << DSI_VVACR_VA11_Pos) /*!< 0x00000800 */
#define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
#define DSI_VVACR_VA12_Pos (12U)
#define DSI_VVACR_VA12_Msk (0x1UL << DSI_VVACR_VA12_Pos) /*!< 0x00001000 */
#define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
#define DSI_VVACR_VA13_Pos (13U)
#define DSI_VVACR_VA13_Msk (0x1UL << DSI_VVACR_VA13_Pos) /*!< 0x00002000 */
#define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
/******************* Bit definition for DSI_LCCR register ***************/
#define DSI_LCCR_CMDSIZE_Pos (0U)
#define DSI_LCCR_CMDSIZE_Msk (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos) /*!< 0x0000FFFF */
#define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk /*!< Command Size */
#define DSI_LCCR_CMDSIZE0_Pos (0U)
#define DSI_LCCR_CMDSIZE0_Msk (0x1UL << DSI_LCCR_CMDSIZE0_Pos) /*!< 0x00000001 */
#define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
#define DSI_LCCR_CMDSIZE1_Pos (1U)
#define DSI_LCCR_CMDSIZE1_Msk (0x1UL << DSI_LCCR_CMDSIZE1_Pos) /*!< 0x00000002 */
#define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
#define DSI_LCCR_CMDSIZE2_Pos (2U)
#define DSI_LCCR_CMDSIZE2_Msk (0x1UL << DSI_LCCR_CMDSIZE2_Pos) /*!< 0x00000004 */
#define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
#define DSI_LCCR_CMDSIZE3_Pos (3U)
#define DSI_LCCR_CMDSIZE3_Msk (0x1UL << DSI_LCCR_CMDSIZE3_Pos) /*!< 0x00000008 */
#define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
#define DSI_LCCR_CMDSIZE4_Pos (4U)
#define DSI_LCCR_CMDSIZE4_Msk (0x1UL << DSI_LCCR_CMDSIZE4_Pos) /*!< 0x00000010 */
#define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
#define DSI_LCCR_CMDSIZE5_Pos (5U)
#define DSI_LCCR_CMDSIZE5_Msk (0x1UL << DSI_LCCR_CMDSIZE5_Pos) /*!< 0x00000020 */
#define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
#define DSI_LCCR_CMDSIZE6_Pos (6U)
#define DSI_LCCR_CMDSIZE6_Msk (0x1UL << DSI_LCCR_CMDSIZE6_Pos) /*!< 0x00000040 */
#define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
#define DSI_LCCR_CMDSIZE7_Pos (7U)
#define DSI_LCCR_CMDSIZE7_Msk (0x1UL << DSI_LCCR_CMDSIZE7_Pos) /*!< 0x00000080 */
#define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
#define DSI_LCCR_CMDSIZE8_Pos (8U)
#define DSI_LCCR_CMDSIZE8_Msk (0x1UL << DSI_LCCR_CMDSIZE8_Pos) /*!< 0x00000100 */
#define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
#define DSI_LCCR_CMDSIZE9_Pos (9U)
#define DSI_LCCR_CMDSIZE9_Msk (0x1UL << DSI_LCCR_CMDSIZE9_Pos) /*!< 0x00000200 */
#define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
#define DSI_LCCR_CMDSIZE10_Pos (10U)
#define DSI_LCCR_CMDSIZE10_Msk (0x1UL << DSI_LCCR_CMDSIZE10_Pos) /*!< 0x00000400 */
#define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
#define DSI_LCCR_CMDSIZE11_Pos (11U)
#define DSI_LCCR_CMDSIZE11_Msk (0x1UL << DSI_LCCR_CMDSIZE11_Pos) /*!< 0x00000800 */
#define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
#define DSI_LCCR_CMDSIZE12_Pos (12U)
#define DSI_LCCR_CMDSIZE12_Msk (0x1UL << DSI_LCCR_CMDSIZE12_Pos) /*!< 0x00001000 */
#define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
#define DSI_LCCR_CMDSIZE13_Pos (13U)
#define DSI_LCCR_CMDSIZE13_Msk (0x1UL << DSI_LCCR_CMDSIZE13_Pos) /*!< 0x00002000 */
#define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
#define DSI_LCCR_CMDSIZE14_Pos (14U)
#define DSI_LCCR_CMDSIZE14_Msk (0x1UL << DSI_LCCR_CMDSIZE14_Pos) /*!< 0x00004000 */
#define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
#define DSI_LCCR_CMDSIZE15_Pos (15U)
#define DSI_LCCR_CMDSIZE15_Msk (0x1UL << DSI_LCCR_CMDSIZE15_Pos) /*!< 0x00008000 */
#define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
/******************* Bit definition for DSI_CMCR register ***************/
#define DSI_CMCR_TEARE_Pos (0U)
#define DSI_CMCR_TEARE_Msk (0x1UL << DSI_CMCR_TEARE_Pos) /*!< 0x00000001 */
#define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk /*!< Tearing Effect Acknowledge Request Enable */
#define DSI_CMCR_ARE_Pos (1U)
#define DSI_CMCR_ARE_Msk (0x1UL << DSI_CMCR_ARE_Pos) /*!< 0x00000002 */
#define DSI_CMCR_ARE DSI_CMCR_ARE_Msk /*!< Acknowledge Request Enable */
#define DSI_CMCR_GSW0TX_Pos (8U)
#define DSI_CMCR_GSW0TX_Msk (0x1UL << DSI_CMCR_GSW0TX_Pos) /*!< 0x00000100 */
#define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk /*!< Generic Short Write Zero parameters Transmission */
#define DSI_CMCR_GSW1TX_Pos (9U)
#define DSI_CMCR_GSW1TX_Msk (0x1UL << DSI_CMCR_GSW1TX_Pos) /*!< 0x00000200 */
#define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk /*!< Generic Short Write One parameters Transmission */
#define DSI_CMCR_GSW2TX_Pos (10U)
#define DSI_CMCR_GSW2TX_Msk (0x1UL << DSI_CMCR_GSW2TX_Pos) /*!< 0x00000400 */
#define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk /*!< Generic Short Write Two parameters Transmission */
#define DSI_CMCR_GSR0TX_Pos (11U)
#define DSI_CMCR_GSR0TX_Msk (0x1UL << DSI_CMCR_GSR0TX_Pos) /*!< 0x00000800 */
#define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk /*!< Generic Short Read Zero parameters Transmission */
#define DSI_CMCR_GSR1TX_Pos (12U)
#define DSI_CMCR_GSR1TX_Msk (0x1UL << DSI_CMCR_GSR1TX_Pos) /*!< 0x00001000 */
#define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk /*!< Generic Short Read One parameters Transmission */
#define DSI_CMCR_GSR2TX_Pos (13U)
#define DSI_CMCR_GSR2TX_Msk (0x1UL << DSI_CMCR_GSR2TX_Pos) /*!< 0x00002000 */
#define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk /*!< Generic Short Read Two parameters Transmission */
#define DSI_CMCR_GLWTX_Pos (14U)
#define DSI_CMCR_GLWTX_Msk (0x1UL << DSI_CMCR_GLWTX_Pos) /*!< 0x00004000 */
#define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk /*!< Generic Long Write Transmission */
#define DSI_CMCR_DSW0TX_Pos (16U)
#define DSI_CMCR_DSW0TX_Msk (0x1UL << DSI_CMCR_DSW0TX_Pos) /*!< 0x00010000 */
#define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk /*!< DCS Short Write Zero parameter Transmission */
#define DSI_CMCR_DSW1TX_Pos (17U)
#define DSI_CMCR_DSW1TX_Msk (0x1UL << DSI_CMCR_DSW1TX_Pos) /*!< 0x00020000 */
#define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk /*!< DCS Short Read One parameter Transmission */
#define DSI_CMCR_DSR0TX_Pos (18U)
#define DSI_CMCR_DSR0TX_Msk (0x1UL << DSI_CMCR_DSR0TX_Pos) /*!< 0x00040000 */
#define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk /*!< DCS Short Read Zero parameter Transmission */
#define DSI_CMCR_DLWTX_Pos (19U)
#define DSI_CMCR_DLWTX_Msk (0x1UL << DSI_CMCR_DLWTX_Pos) /*!< 0x00080000 */
#define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk /*!< DCS Long Write Transmission */
#define DSI_CMCR_MRDPS_Pos (24U)
#define DSI_CMCR_MRDPS_Msk (0x1UL << DSI_CMCR_MRDPS_Pos) /*!< 0x01000000 */
#define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk /*!< Maximum Read Packet Size */
/******************* Bit definition for DSI_GHCR register ***************/
#define DSI_GHCR_DT_Pos (0U)
#define DSI_GHCR_DT_Msk (0x3FUL << DSI_GHCR_DT_Pos) /*!< 0x0000003F */
#define DSI_GHCR_DT DSI_GHCR_DT_Msk /*!< Type */
#define DSI_GHCR_DT0_Pos (0U)
#define DSI_GHCR_DT0_Msk (0x1UL << DSI_GHCR_DT0_Pos) /*!< 0x00000001 */
#define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
#define DSI_GHCR_DT1_Pos (1U)
#define DSI_GHCR_DT1_Msk (0x1UL << DSI_GHCR_DT1_Pos) /*!< 0x00000002 */
#define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
#define DSI_GHCR_DT2_Pos (2U)
#define DSI_GHCR_DT2_Msk (0x1UL << DSI_GHCR_DT2_Pos) /*!< 0x00000004 */
#define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
#define DSI_GHCR_DT3_Pos (3U)
#define DSI_GHCR_DT3_Msk (0x1UL << DSI_GHCR_DT3_Pos) /*!< 0x00000008 */
#define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
#define DSI_GHCR_DT4_Pos (4U)
#define DSI_GHCR_DT4_Msk (0x1UL << DSI_GHCR_DT4_Pos) /*!< 0x00000010 */
#define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
#define DSI_GHCR_DT5_Pos (5U)
#define DSI_GHCR_DT5_Msk (0x1UL << DSI_GHCR_DT5_Pos) /*!< 0x00000020 */
#define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
#define DSI_GHCR_VCID_Pos (6U)
#define DSI_GHCR_VCID_Msk (0x3UL << DSI_GHCR_VCID_Pos) /*!< 0x000000C0 */
#define DSI_GHCR_VCID DSI_GHCR_VCID_Msk /*!< Channel */
#define DSI_GHCR_VCID0_Pos (6U)
#define DSI_GHCR_VCID0_Msk (0x1UL << DSI_GHCR_VCID0_Pos) /*!< 0x00000040 */
#define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
#define DSI_GHCR_VCID1_Pos (7U)
#define DSI_GHCR_VCID1_Msk (0x1UL << DSI_GHCR_VCID1_Pos) /*!< 0x00000080 */
#define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
#define DSI_GHCR_WCLSB_Pos (8U)
#define DSI_GHCR_WCLSB_Msk (0xFFUL << DSI_GHCR_WCLSB_Pos) /*!< 0x0000FF00 */
#define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk /*!< WordCount LSB */
#define DSI_GHCR_WCLSB0_Pos (8U)
#define DSI_GHCR_WCLSB0_Msk (0x1UL << DSI_GHCR_WCLSB0_Pos) /*!< 0x00000100 */
#define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
#define DSI_GHCR_WCLSB1_Pos (9U)
#define DSI_GHCR_WCLSB1_Msk (0x1UL << DSI_GHCR_WCLSB1_Pos) /*!< 0x00000200 */
#define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
#define DSI_GHCR_WCLSB2_Pos (10U)
#define DSI_GHCR_WCLSB2_Msk (0x1UL << DSI_GHCR_WCLSB2_Pos) /*!< 0x00000400 */
#define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
#define DSI_GHCR_WCLSB3_Pos (11U)
#define DSI_GHCR_WCLSB3_Msk (0x1UL << DSI_GHCR_WCLSB3_Pos) /*!< 0x00000800 */
#define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
#define DSI_GHCR_WCLSB4_Pos (12U)
#define DSI_GHCR_WCLSB4_Msk (0x1UL << DSI_GHCR_WCLSB4_Pos) /*!< 0x00001000 */
#define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
#define DSI_GHCR_WCLSB5_Pos (13U)
#define DSI_GHCR_WCLSB5_Msk (0x1UL << DSI_GHCR_WCLSB5_Pos) /*!< 0x00002000 */
#define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
#define DSI_GHCR_WCLSB6_Pos (14U)
#define DSI_GHCR_WCLSB6_Msk (0x1UL << DSI_GHCR_WCLSB6_Pos) /*!< 0x00004000 */
#define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
#define DSI_GHCR_WCLSB7_Pos (15U)
#define DSI_GHCR_WCLSB7_Msk (0x1UL << DSI_GHCR_WCLSB7_Pos) /*!< 0x00008000 */
#define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
#define DSI_GHCR_WCMSB_Pos (16U)
#define DSI_GHCR_WCMSB_Msk (0xFFUL << DSI_GHCR_WCMSB_Pos) /*!< 0x00FF0000 */
#define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk /*!< WordCount MSB */
#define DSI_GHCR_WCMSB0_Pos (16U)
#define DSI_GHCR_WCMSB0_Msk (0x1UL << DSI_GHCR_WCMSB0_Pos) /*!< 0x00010000 */
#define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
#define DSI_GHCR_WCMSB1_Pos (17U)
#define DSI_GHCR_WCMSB1_Msk (0x1UL << DSI_GHCR_WCMSB1_Pos) /*!< 0x00020000 */
#define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
#define DSI_GHCR_WCMSB2_Pos (18U)
#define DSI_GHCR_WCMSB2_Msk (0x1UL << DSI_GHCR_WCMSB2_Pos) /*!< 0x00040000 */
#define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
#define DSI_GHCR_WCMSB3_Pos (19U)
#define DSI_GHCR_WCMSB3_Msk (0x1UL << DSI_GHCR_WCMSB3_Pos) /*!< 0x00080000 */
#define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
#define DSI_GHCR_WCMSB4_Pos (20U)
#define DSI_GHCR_WCMSB4_Msk (0x1UL << DSI_GHCR_WCMSB4_Pos) /*!< 0x00100000 */
#define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
#define DSI_GHCR_WCMSB5_Pos (21U)
#define DSI_GHCR_WCMSB5_Msk (0x1UL << DSI_GHCR_WCMSB5_Pos) /*!< 0x00200000 */
#define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
#define DSI_GHCR_WCMSB6_Pos (22U)
#define DSI_GHCR_WCMSB6_Msk (0x1UL << DSI_GHCR_WCMSB6_Pos) /*!< 0x00400000 */
#define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
#define DSI_GHCR_WCMSB7_Pos (23U)
#define DSI_GHCR_WCMSB7_Msk (0x1UL << DSI_GHCR_WCMSB7_Pos) /*!< 0x00800000 */
#define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
/******************* Bit definition for DSI_GPDR register ***************/
#define DSI_GPDR_DATA1_Pos (0U)
#define DSI_GPDR_DATA1_Msk (0xFFUL << DSI_GPDR_DATA1_Pos) /*!< 0x000000FF */
#define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk /*!< Payload Byte 1 */
#define DSI_GPDR_DATA1_0 (0x01UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000001 */
#define DSI_GPDR_DATA1_1 (0x02UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000002 */
#define DSI_GPDR_DATA1_2 (0x04UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000004 */
#define DSI_GPDR_DATA1_3 (0x08UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000008 */
#define DSI_GPDR_DATA1_4 (0x10UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000010 */
#define DSI_GPDR_DATA1_5 (0x20UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000020 */
#define DSI_GPDR_DATA1_6 (0x40UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000040 */
#define DSI_GPDR_DATA1_7 (0x80UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000080 */
#define DSI_GPDR_DATA2_Pos (8U)
#define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
#define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk /*!< Payload Byte 2 */
#define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
#define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
#define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
#define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
#define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
#define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
#define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
#define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
#define DSI_GPDR_DATA3_Pos (16U)
#define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
#define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk /*!< Payload Byte 3 */
#define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
#define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
#define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
#define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
#define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
#define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
#define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
#define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
#define DSI_GPDR_DATA4_Pos (24U)
#define DSI_GPDR_DATA4_Msk (0xFFUL << DSI_GPDR_DATA4_Pos) /*!< 0xFF000000 */
#define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk /*!< Payload Byte 4 */
#define DSI_GPDR_DATA4_0 (0x01UL << DSI_GPDR_DATA4_Pos) /*!< 0x01000000 */
#define DSI_GPDR_DATA4_1 (0x02UL << DSI_GPDR_DATA4_Pos) /*!< 0x02000000 */
#define DSI_GPDR_DATA4_2 (0x04UL << DSI_GPDR_DATA4_Pos) /*!< 0x04000000 */
#define DSI_GPDR_DATA4_3 (0x08UL << DSI_GPDR_DATA4_Pos) /*!< 0x08000000 */
#define DSI_GPDR_DATA4_4 (0x10UL << DSI_GPDR_DATA4_Pos) /*!< 0x10000000 */
#define DSI_GPDR_DATA4_5 (0x20UL << DSI_GPDR_DATA4_Pos) /*!< 0x20000000 */
#define DSI_GPDR_DATA4_6 (0x40UL << DSI_GPDR_DATA4_Pos) /*!< 0x40000000 */
#define DSI_GPDR_DATA4_7 (0x80UL << DSI_GPDR_DATA4_Pos) /*!< 0x80000000 */
/******************* Bit definition for DSI_GPSR register ***************/
#define DSI_GPSR_CMDFE_Pos (0U)
#define DSI_GPSR_CMDFE_Msk (0x1UL << DSI_GPSR_CMDFE_Pos) /*!< 0x00000001 */
#define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk /*!< Command FIFO Empty */
#define DSI_GPSR_CMDFF_Pos (1U)
#define DSI_GPSR_CMDFF_Msk (0x1UL << DSI_GPSR_CMDFF_Pos) /*!< 0x00000002 */
#define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk /*!< Command FIFO Full */
#define DSI_GPSR_PWRFE_Pos (2U)
#define DSI_GPSR_PWRFE_Msk (0x1UL << DSI_GPSR_PWRFE_Pos) /*!< 0x00000004 */
#define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk /*!< Payload Write FIFO Empty */
#define DSI_GPSR_PWRFF_Pos (3U)
#define DSI_GPSR_PWRFF_Msk (0x1UL << DSI_GPSR_PWRFF_Pos) /*!< 0x00000008 */
#define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk /*!< Payload Write FIFO Full */
#define DSI_GPSR_PRDFE_Pos (4U)
#define DSI_GPSR_PRDFE_Msk (0x1UL << DSI_GPSR_PRDFE_Pos) /*!< 0x00000010 */
#define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk /*!< Payload Read FIFO Empty */
#define DSI_GPSR_PRDFF_Pos (5U)
#define DSI_GPSR_PRDFF_Msk (0x1UL << DSI_GPSR_PRDFF_Pos) /*!< 0x00000020 */
#define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk /*!< Payload Read FIFO Full */
#define DSI_GPSR_RCB_Pos (6U)
#define DSI_GPSR_RCB_Msk (0x1UL << DSI_GPSR_RCB_Pos) /*!< 0x00000040 */
#define DSI_GPSR_RCB DSI_GPSR_RCB_Msk /*!< Read Command Busy */
/******************* Bit definition for DSI_TCCR0 register **************/
#define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
#define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos) /*!< 0x0000FFFF */
#define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Reception Timeout Counter */
#define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
#define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos) /*!< 0x00000001 */
#define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
#define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
#define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos) /*!< 0x00000002 */
#define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
#define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
#define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos) /*!< 0x00000004 */
#define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
#define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
#define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos) /*!< 0x00000008 */
#define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
#define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
#define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos) /*!< 0x00000010 */
#define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
#define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
#define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos) /*!< 0x00000020 */
#define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
#define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
#define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos) /*!< 0x00000040 */
#define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
#define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
#define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos) /*!< 0x00000080 */
#define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
#define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
#define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos) /*!< 0x00000100 */
#define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
#define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
#define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos) /*!< 0x00000200 */
#define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
#define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
#define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos) /*!< 0x00000400 */
#define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
#define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
#define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos) /*!< 0x00000800 */
#define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
#define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
#define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos) /*!< 0x00001000 */
#define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
#define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
#define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos) /*!< 0x00002000 */
#define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
#define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
#define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos) /*!< 0x00004000 */
#define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
#define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
#define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos) /*!< 0x00008000 */
#define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
#define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
#define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos) /*!< 0xFFFF0000 */
#define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Transmission Timeout Counter */
#define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
#define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos) /*!< 0x00010000 */
#define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
#define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
#define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos) /*!< 0x00020000 */
#define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
#define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
#define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos) /*!< 0x00040000 */
#define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
#define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
#define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos) /*!< 0x00080000 */
#define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
#define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
#define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos) /*!< 0x00100000 */
#define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
#define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
#define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos) /*!< 0x00200000 */
#define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
#define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
#define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos) /*!< 0x00400000 */
#define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
#define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
#define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos) /*!< 0x00800000 */
#define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
#define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
#define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos) /*!< 0x01000000 */
#define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
#define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
#define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos) /*!< 0x02000000 */
#define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
#define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
#define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos) /*!< 0x04000000 */
#define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
#define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
#define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos) /*!< 0x08000000 */
#define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
#define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
#define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos) /*!< 0x10000000 */
#define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
#define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
#define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos) /*!< 0x20000000 */
#define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
#define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
#define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos) /*!< 0x40000000 */
#define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
#define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
#define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos) /*!< 0x80000000 */
#define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
/******************* Bit definition for DSI_TCCR1 register **************/
#define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
#define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos) /*!< 0x0000FFFF */
#define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read Timeout Counter */
#define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
#define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos) /*!< 0x00000001 */
#define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
#define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
#define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos) /*!< 0x00000002 */
#define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
#define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
#define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos) /*!< 0x00000004 */
#define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
#define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
#define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos) /*!< 0x00000008 */
#define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
#define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
#define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos) /*!< 0x00000010 */
#define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
#define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
#define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos) /*!< 0x00000020 */
#define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
#define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
#define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos) /*!< 0x00000040 */
#define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
#define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
#define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos) /*!< 0x00000080 */
#define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
#define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
#define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos) /*!< 0x00000100 */
#define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
#define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
#define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos) /*!< 0x00000200 */
#define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
#define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
#define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos) /*!< 0x00000400 */
#define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
#define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
#define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos) /*!< 0x00000800 */
#define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
#define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
#define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos) /*!< 0x00001000 */
#define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
#define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
#define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos) /*!< 0x00002000 */
#define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
#define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
#define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos) /*!< 0x00004000 */
#define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
#define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
#define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos) /*!< 0x00008000 */
#define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
/******************* Bit definition for DSI_TCCR2 register **************/
#define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
#define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos) /*!< 0x0000FFFF */
#define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read Timeout Counter */
#define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
#define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos) /*!< 0x00000001 */
#define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
#define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
#define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos) /*!< 0x00000002 */
#define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
#define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
#define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos) /*!< 0x00000004 */
#define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
#define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
#define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos) /*!< 0x00000008 */
#define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
#define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
#define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos) /*!< 0x00000010 */
#define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
#define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
#define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos) /*!< 0x00000020 */
#define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
#define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
#define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos) /*!< 0x00000040 */
#define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
#define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
#define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos) /*!< 0x00000080 */
#define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
#define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
#define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos) /*!< 0x00000100 */
#define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
#define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
#define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos) /*!< 0x00000200 */
#define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
#define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
#define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos) /*!< 0x00000400 */
#define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
#define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
#define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos) /*!< 0x00000800 */
#define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
#define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
#define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos) /*!< 0x00001000 */
#define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
#define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
#define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos) /*!< 0x00002000 */
#define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
#define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
#define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos) /*!< 0x00004000 */
#define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
#define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
#define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos) /*!< 0x00008000 */
#define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
/******************* Bit definition for DSI_TCCR3 register **************/
#define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
#define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos) /*!< 0x0000FFFF */
#define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Write Timeout Counter */
#define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
#define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos) /*!< 0x00000001 */
#define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
#define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
#define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos) /*!< 0x00000002 */
#define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
#define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
#define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos) /*!< 0x00000004 */
#define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
#define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
#define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos) /*!< 0x00000008 */
#define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
#define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
#define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos) /*!< 0x00000010 */
#define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
#define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
#define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos) /*!< 0x00000020 */
#define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
#define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
#define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos) /*!< 0x00000040 */
#define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
#define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
#define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos) /*!< 0x00000080 */
#define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
#define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
#define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos) /*!< 0x00000100 */
#define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
#define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
#define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos) /*!< 0x00000200 */
#define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
#define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
#define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos) /*!< 0x00000400 */
#define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
#define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
#define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos) /*!< 0x00000800 */
#define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
#define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
#define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos) /*!< 0x00001000 */
#define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
#define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
#define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos) /*!< 0x00002000 */
#define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
#define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
#define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos) /*!< 0x00004000 */
#define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
#define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
#define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos) /*!< 0x00008000 */
#define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
#define DSI_TCCR3_PM_Pos (24U)
#define DSI_TCCR3_PM_Msk (0x1UL << DSI_TCCR3_PM_Pos) /*!< 0x01000000 */
#define DSI_TCCR3_PM DSI_TCCR3_PM_Msk /*!< Presp Mode */
/******************* Bit definition for DSI_TCCR4 register **************/
#define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
#define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos) /*!< 0x0000FFFF */
#define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write Timeout Counter */
#define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
#define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos) /*!< 0x00000001 */
#define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
#define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
#define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos) /*!< 0x00000002 */
#define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
#define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
#define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos) /*!< 0x00000004 */
#define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
#define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
#define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos) /*!< 0x00000008 */
#define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
#define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
#define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos) /*!< 0x00000010 */
#define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
#define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
#define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos) /*!< 0x00000020 */
#define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
#define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
#define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos) /*!< 0x00000040 */
#define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
#define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
#define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos) /*!< 0x00000080 */
#define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
#define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
#define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos) /*!< 0x00000100 */
#define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
#define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
#define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos) /*!< 0x00000200 */
#define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
#define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
#define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos) /*!< 0x00000400 */
#define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
#define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
#define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos) /*!< 0x00000800 */
#define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
#define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
#define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos) /*!< 0x00001000 */
#define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
#define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
#define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos) /*!< 0x00002000 */
#define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
#define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
#define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos) /*!< 0x00004000 */
#define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
#define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
#define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos) /*!< 0x00008000 */
#define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
/******************* Bit definition for DSI_TCCR5 register **************/
#define DSI_TCCR5_BTA_TOCNT_Pos (0U)
#define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos) /*!< 0x0000FFFF */
#define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around Timeout Counter */
#define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
#define DSI_TCCR5_BTA_TOCNT0_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos) /*!< 0x00000001 */
#define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
#define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
#define DSI_TCCR5_BTA_TOCNT1_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos) /*!< 0x00000002 */
#define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
#define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
#define DSI_TCCR5_BTA_TOCNT2_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos) /*!< 0x00000004 */
#define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
#define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
#define DSI_TCCR5_BTA_TOCNT3_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos) /*!< 0x00000008 */
#define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
#define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
#define DSI_TCCR5_BTA_TOCNT4_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos) /*!< 0x00000010 */
#define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
#define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
#define DSI_TCCR5_BTA_TOCNT5_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos) /*!< 0x00000020 */
#define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
#define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
#define DSI_TCCR5_BTA_TOCNT6_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos) /*!< 0x00000040 */
#define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
#define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
#define DSI_TCCR5_BTA_TOCNT7_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos) /*!< 0x00000080 */
#define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
#define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
#define DSI_TCCR5_BTA_TOCNT8_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos) /*!< 0x00000100 */
#define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
#define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
#define DSI_TCCR5_BTA_TOCNT9_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos) /*!< 0x00000200 */
#define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
#define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
#define DSI_TCCR5_BTA_TOCNT10_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos) /*!< 0x00000400 */
#define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
#define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
#define DSI_TCCR5_BTA_TOCNT11_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos) /*!< 0x00000800 */
#define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
#define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
#define DSI_TCCR5_BTA_TOCNT12_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos) /*!< 0x00001000 */
#define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
#define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
#define DSI_TCCR5_BTA_TOCNT13_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos) /*!< 0x00002000 */
#define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
#define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
#define DSI_TCCR5_BTA_TOCNT14_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos) /*!< 0x00004000 */
#define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
#define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
#define DSI_TCCR5_BTA_TOCNT15_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos) /*!< 0x00008000 */
#define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
/******************* Bit definition for DSI_CLCR register ***************/
#define DSI_CLCR_DPCC_Pos (0U)
#define DSI_CLCR_DPCC_Msk (0x1UL << DSI_CLCR_DPCC_Pos) /*!< 0x00000001 */
#define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Control */
#define DSI_CLCR_ACR_Pos (1U)
#define DSI_CLCR_ACR_Msk (0x1UL << DSI_CLCR_ACR_Pos) /*!< 0x00000002 */
#define DSI_CLCR_ACR DSI_CLCR_ACR_Msk /*!< Automatic Clocklane Control */
/******************* Bit definition for DSI_CLTCR register **************/
#define DSI_CLTCR_LP2HS_TIME_Pos (0U)
#define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos) /*!< 0x000003FF */
#define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */
#define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
#define DSI_CLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos) /*!< 0x00000001 */
#define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
#define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
#define DSI_CLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos) /*!< 0x00000002 */
#define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
#define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
#define DSI_CLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos) /*!< 0x00000004 */
#define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
#define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
#define DSI_CLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos) /*!< 0x00000008 */
#define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
#define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
#define DSI_CLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos) /*!< 0x00000010 */
#define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
#define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
#define DSI_CLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos) /*!< 0x00000020 */
#define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
#define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
#define DSI_CLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos) /*!< 0x00000040 */
#define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
#define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
#define DSI_CLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos) /*!< 0x00000080 */
#define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
#define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
#define DSI_CLTCR_LP2HS_TIME8_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos) /*!< 0x00000100 */
#define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
#define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
#define DSI_CLTCR_LP2HS_TIME9_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos) /*!< 0x00000200 */
#define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
#define DSI_CLTCR_HS2LP_TIME_Pos (16U)
#define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos) /*!< 0x03FF0000 */
#define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */
#define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
#define DSI_CLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos) /*!< 0x00010000 */
#define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
#define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
#define DSI_CLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos) /*!< 0x00020000 */
#define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
#define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
#define DSI_CLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos) /*!< 0x00040000 */
#define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
#define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
#define DSI_CLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos) /*!< 0x00080000 */
#define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
#define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
#define DSI_CLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos) /*!< 0x00100000 */
#define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
#define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
#define DSI_CLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos) /*!< 0x00200000 */
#define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
#define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
#define DSI_CLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos) /*!< 0x00400000 */
#define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
#define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
#define DSI_CLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos) /*!< 0x00800000 */
#define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
#define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
#define DSI_CLTCR_HS2LP_TIME8_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos) /*!< 0x01000000 */
#define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
#define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
#define DSI_CLTCR_HS2LP_TIME9_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos) /*!< 0x02000000 */
#define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
/******************* Bit definition for DSI_DLTCR register **************/
#define DSI_DLTCR_MRD_TIME_Pos (0U)
#define DSI_DLTCR_MRD_TIME_Msk (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos) /*!< 0x00007FFF */
#define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk /*!< Maximum Read Time */
#define DSI_DLTCR_MRD_TIME0_Pos (0U)
#define DSI_DLTCR_MRD_TIME0_Msk (0x1UL << DSI_DLTCR_MRD_TIME0_Pos) /*!< 0x00000001 */
#define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
#define DSI_DLTCR_MRD_TIME1_Pos (1U)
#define DSI_DLTCR_MRD_TIME1_Msk (0x1UL << DSI_DLTCR_MRD_TIME1_Pos) /*!< 0x00000002 */
#define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
#define DSI_DLTCR_MRD_TIME2_Pos (2U)
#define DSI_DLTCR_MRD_TIME2_Msk (0x1UL << DSI_DLTCR_MRD_TIME2_Pos) /*!< 0x00000004 */
#define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
#define DSI_DLTCR_MRD_TIME3_Pos (3U)
#define DSI_DLTCR_MRD_TIME3_Msk (0x1UL << DSI_DLTCR_MRD_TIME3_Pos) /*!< 0x00000008 */
#define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
#define DSI_DLTCR_MRD_TIME4_Pos (4U)
#define DSI_DLTCR_MRD_TIME4_Msk (0x1UL << DSI_DLTCR_MRD_TIME4_Pos) /*!< 0x00000010 */
#define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
#define DSI_DLTCR_MRD_TIME5_Pos (5U)
#define DSI_DLTCR_MRD_TIME5_Msk (0x1UL << DSI_DLTCR_MRD_TIME5_Pos) /*!< 0x00000020 */
#define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
#define DSI_DLTCR_MRD_TIME6_Pos (6U)
#define DSI_DLTCR_MRD_TIME6_Msk (0x1UL << DSI_DLTCR_MRD_TIME6_Pos) /*!< 0x00000040 */
#define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
#define DSI_DLTCR_MRD_TIME7_Pos (7U)
#define DSI_DLTCR_MRD_TIME7_Msk (0x1UL << DSI_DLTCR_MRD_TIME7_Pos) /*!< 0x00000080 */
#define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
#define DSI_DLTCR_MRD_TIME8_Pos (8U)
#define DSI_DLTCR_MRD_TIME8_Msk (0x1UL << DSI_DLTCR_MRD_TIME8_Pos) /*!< 0x00000100 */
#define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
#define DSI_DLTCR_MRD_TIME9_Pos (9U)
#define DSI_DLTCR_MRD_TIME9_Msk (0x1UL << DSI_DLTCR_MRD_TIME9_Pos) /*!< 0x00000200 */
#define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
#define DSI_DLTCR_MRD_TIME10_Pos (10U)
#define DSI_DLTCR_MRD_TIME10_Msk (0x1UL << DSI_DLTCR_MRD_TIME10_Pos) /*!< 0x00000400 */
#define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
#define DSI_DLTCR_MRD_TIME11_Pos (11U)
#define DSI_DLTCR_MRD_TIME11_Msk (0x1UL << DSI_DLTCR_MRD_TIME11_Pos) /*!< 0x00000800 */
#define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
#define DSI_DLTCR_MRD_TIME12_Pos (12U)
#define DSI_DLTCR_MRD_TIME12_Msk (0x1UL << DSI_DLTCR_MRD_TIME12_Pos) /*!< 0x00001000 */
#define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
#define DSI_DLTCR_MRD_TIME13_Pos (13U)
#define DSI_DLTCR_MRD_TIME13_Msk (0x1UL << DSI_DLTCR_MRD_TIME13_Pos) /*!< 0x00002000 */
#define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
#define DSI_DLTCR_MRD_TIME14_Pos (14U)
#define DSI_DLTCR_MRD_TIME14_Msk (0x1UL << DSI_DLTCR_MRD_TIME14_Pos) /*!< 0x00004000 */
#define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
#define DSI_DLTCR_LP2HS_TIME_Pos (16U)
#define DSI_DLTCR_LP2HS_TIME_Msk (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos) /*!< 0x00FF0000 */
#define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */
#define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
#define DSI_DLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos) /*!< 0x00010000 */
#define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
#define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
#define DSI_DLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos) /*!< 0x00020000 */
#define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
#define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
#define DSI_DLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos) /*!< 0x00040000 */
#define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
#define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
#define DSI_DLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos) /*!< 0x00080000 */
#define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
#define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
#define DSI_DLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos) /*!< 0x00100000 */
#define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
#define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
#define DSI_DLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos) /*!< 0x00200000 */
#define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
#define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
#define DSI_DLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos) /*!< 0x00400000 */
#define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
#define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
#define DSI_DLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos) /*!< 0x00800000 */
#define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
#define DSI_DLTCR_HS2LP_TIME_Pos (24U)
#define DSI_DLTCR_HS2LP_TIME_Msk (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos) /*!< 0xFF000000 */
#define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */
#define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
#define DSI_DLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos) /*!< 0x01000000 */
#define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
#define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
#define DSI_DLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos) /*!< 0x02000000 */
#define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
#define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
#define DSI_DLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos) /*!< 0x04000000 */
#define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
#define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
#define DSI_DLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos) /*!< 0x08000000 */
#define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
#define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
#define DSI_DLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos) /*!< 0x10000000 */
#define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
#define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
#define DSI_DLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos) /*!< 0x20000000 */
#define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
#define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
#define DSI_DLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos) /*!< 0x40000000 */
#define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
#define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
#define DSI_DLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos) /*!< 0x80000000 */
#define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
/******************* Bit definition for DSI_PCTLR register **************/
#define DSI_PCTLR_DEN_Pos (1U)
#define DSI_PCTLR_DEN_Msk (0x1UL << DSI_PCTLR_DEN_Pos) /*!< 0x00000002 */
#define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk /*!< Digital Enable */
#define DSI_PCTLR_CKE_Pos (2U)
#define DSI_PCTLR_CKE_Msk (0x1UL << DSI_PCTLR_CKE_Pos) /*!< 0x00000004 */
#define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk /*!< Clock Enable */
/******************* Bit definition for DSI_PCONFR register *************/
#define DSI_PCONFR_NL_Pos (0U)
#define DSI_PCONFR_NL_Msk (0x3UL << DSI_PCONFR_NL_Pos) /*!< 0x00000003 */
#define DSI_PCONFR_NL DSI_PCONFR_NL_Msk /*!< Number of Lanes */
#define DSI_PCONFR_NL0_Pos (0U)
#define DSI_PCONFR_NL0_Msk (0x1UL << DSI_PCONFR_NL0_Pos) /*!< 0x00000001 */
#define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
#define DSI_PCONFR_NL1_Pos (1U)
#define DSI_PCONFR_NL1_Msk (0x1UL << DSI_PCONFR_NL1_Pos) /*!< 0x00000002 */
#define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
#define DSI_PCONFR_SW_TIME_Pos (8U)
#define DSI_PCONFR_SW_TIME_Msk (0xFFUL << DSI_PCONFR_SW_TIME_Pos) /*!< 0x0000FF00 */
#define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk /*!< Stop Wait Time */
#define DSI_PCONFR_SW_TIME0_Pos (8U)
#define DSI_PCONFR_SW_TIME0_Msk (0x1UL << DSI_PCONFR_SW_TIME0_Pos) /*!< 0x00000100 */
#define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
#define DSI_PCONFR_SW_TIME1_Pos (9U)
#define DSI_PCONFR_SW_TIME1_Msk (0x1UL << DSI_PCONFR_SW_TIME1_Pos) /*!< 0x00000200 */
#define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
#define DSI_PCONFR_SW_TIME2_Pos (10U)
#define DSI_PCONFR_SW_TIME2_Msk (0x1UL << DSI_PCONFR_SW_TIME2_Pos) /*!< 0x00000400 */
#define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
#define DSI_PCONFR_SW_TIME3_Pos (11U)
#define DSI_PCONFR_SW_TIME3_Msk (0x1UL << DSI_PCONFR_SW_TIME3_Pos) /*!< 0x00000800 */
#define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
#define DSI_PCONFR_SW_TIME4_Pos (12U)
#define DSI_PCONFR_SW_TIME4_Msk (0x1UL << DSI_PCONFR_SW_TIME4_Pos) /*!< 0x00001000 */
#define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
#define DSI_PCONFR_SW_TIME5_Pos (13U)
#define DSI_PCONFR_SW_TIME5_Msk (0x1UL << DSI_PCONFR_SW_TIME5_Pos) /*!< 0x00002000 */
#define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
#define DSI_PCONFR_SW_TIME6_Pos (14U)
#define DSI_PCONFR_SW_TIME6_Msk (0x1UL << DSI_PCONFR_SW_TIME6_Pos) /*!< 0x00004000 */
#define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
#define DSI_PCONFR_SW_TIME7_Pos (15U)
#define DSI_PCONFR_SW_TIME7_Msk (0x1UL << DSI_PCONFR_SW_TIME7_Pos) /*!< 0x00008000 */
#define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
/******************* Bit definition for DSI_PUCR register ***************/
#define DSI_PUCR_URCL_Pos (0U)
#define DSI_PUCR_URCL_Msk (0x1UL << DSI_PUCR_URCL_Pos) /*!< 0x00000001 */
#define DSI_PUCR_URCL DSI_PUCR_URCL_Msk /*!< ULPS Request on Clock Lane */
#define DSI_PUCR_UECL_Pos (1U)
#define DSI_PUCR_UECL_Msk (0x1UL << DSI_PUCR_UECL_Pos) /*!< 0x00000002 */
#define DSI_PUCR_UECL DSI_PUCR_UECL_Msk /*!< ULPS Exit on Clock Lane */
#define DSI_PUCR_URDL_Pos (2U)
#define DSI_PUCR_URDL_Msk (0x1UL << DSI_PUCR_URDL_Pos) /*!< 0x00000004 */
#define DSI_PUCR_URDL DSI_PUCR_URDL_Msk /*!< ULPS Request on Data Lane */
#define DSI_PUCR_UEDL_Pos (3U)
#define DSI_PUCR_UEDL_Msk (0x1UL << DSI_PUCR_UEDL_Pos) /*!< 0x00000008 */
#define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk /*!< ULPS Exit on Data Lane */
/******************* Bit definition for DSI_PTTCR register **************/
#define DSI_PTTCR_TX_TRIG_Pos (0U)
#define DSI_PTTCR_TX_TRIG_Msk (0xFUL << DSI_PTTCR_TX_TRIG_Pos) /*!< 0x0000000F */
#define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk /*!< Transmission Trigger */
#define DSI_PTTCR_TX_TRIG0_Pos (0U)
#define DSI_PTTCR_TX_TRIG0_Msk (0x1UL << DSI_PTTCR_TX_TRIG0_Pos) /*!< 0x00000001 */
#define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
#define DSI_PTTCR_TX_TRIG1_Pos (1U)
#define DSI_PTTCR_TX_TRIG1_Msk (0x1UL << DSI_PTTCR_TX_TRIG1_Pos) /*!< 0x00000002 */
#define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
#define DSI_PTTCR_TX_TRIG2_Pos (2U)
#define DSI_PTTCR_TX_TRIG2_Msk (0x1UL << DSI_PTTCR_TX_TRIG2_Pos) /*!< 0x00000004 */
#define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
#define DSI_PTTCR_TX_TRIG3_Pos (3U)
#define DSI_PTTCR_TX_TRIG3_Msk (0x1UL << DSI_PTTCR_TX_TRIG3_Pos) /*!< 0x00000008 */
#define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
/******************* Bit definition for DSI_PSR register ****************/
#define DSI_PSR_PD_Pos (1U)
#define DSI_PSR_PD_Msk (0x1UL << DSI_PSR_PD_Pos) /*!< 0x00000002 */
#define DSI_PSR_PD DSI_PSR_PD_Msk /*!< PHY Direction */
#define DSI_PSR_PSSC_Pos (2U)
#define DSI_PSR_PSSC_Msk (0x1UL << DSI_PSR_PSSC_Pos) /*!< 0x00000004 */
#define DSI_PSR_PSSC DSI_PSR_PSSC_Msk /*!< PHY Stop State Clock lane */
#define DSI_PSR_UANC_Pos (3U)
#define DSI_PSR_UANC_Msk (0x1UL << DSI_PSR_UANC_Pos) /*!< 0x00000008 */
#define DSI_PSR_UANC DSI_PSR_UANC_Msk /*!< ULPS Active Not Clock lane */
#define DSI_PSR_PSS0_Pos (4U)
#define DSI_PSR_PSS0_Msk (0x1UL << DSI_PSR_PSS0_Pos) /*!< 0x00000010 */
#define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk /*!< PHY Stop State lane 0 */
#define DSI_PSR_UAN0_Pos (5U)
#define DSI_PSR_UAN0_Msk (0x1UL << DSI_PSR_UAN0_Pos) /*!< 0x00000020 */
#define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk /*!< ULPS Active Not lane 0 */
#define DSI_PSR_RUE0_Pos (6U)
#define DSI_PSR_RUE0_Msk (0x1UL << DSI_PSR_RUE0_Pos) /*!< 0x00000040 */
#define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk /*!< RX ULPS Escape lane 0 */
#define DSI_PSR_PSS1_Pos (7U)
#define DSI_PSR_PSS1_Msk (0x1UL << DSI_PSR_PSS1_Pos) /*!< 0x00000080 */
#define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk /*!< PHY Stop State lane 1 */
#define DSI_PSR_UAN1_Pos (8U)
#define DSI_PSR_UAN1_Msk (0x1UL << DSI_PSR_UAN1_Pos) /*!< 0x00000100 */
#define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk /*!< ULPS Active Not lane 1 */
/******************* Bit definition for DSI_ISR0 register ***************/
#define DSI_ISR0_AE0_Pos (0U)
#define DSI_ISR0_AE0_Msk (0x1UL << DSI_ISR0_AE0_Pos) /*!< 0x00000001 */
#define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk /*!< Acknowledge Error 0 */
#define DSI_ISR0_AE1_Pos (1U)
#define DSI_ISR0_AE1_Msk (0x1UL << DSI_ISR0_AE1_Pos) /*!< 0x00000002 */
#define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk /*!< Acknowledge Error 1 */
#define DSI_ISR0_AE2_Pos (2U)
#define DSI_ISR0_AE2_Msk (0x1UL << DSI_ISR0_AE2_Pos) /*!< 0x00000004 */
#define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk /*!< Acknowledge Error 2 */
#define DSI_ISR0_AE3_Pos (3U)
#define DSI_ISR0_AE3_Msk (0x1UL << DSI_ISR0_AE3_Pos) /*!< 0x00000008 */
#define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk /*!< Acknowledge Error 3 */
#define DSI_ISR0_AE4_Pos (4U)
#define DSI_ISR0_AE4_Msk (0x1UL << DSI_ISR0_AE4_Pos) /*!< 0x00000010 */
#define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk /*!< Acknowledge Error 4 */
#define DSI_ISR0_AE5_Pos (5U)
#define DSI_ISR0_AE5_Msk (0x1UL << DSI_ISR0_AE5_Pos) /*!< 0x00000020 */
#define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk /*!< Acknowledge Error 5 */
#define DSI_ISR0_AE6_Pos (6U)
#define DSI_ISR0_AE6_Msk (0x1UL << DSI_ISR0_AE6_Pos) /*!< 0x00000040 */
#define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk /*!< Acknowledge Error 6 */
#define DSI_ISR0_AE7_Pos (7U)
#define DSI_ISR0_AE7_Msk (0x1UL << DSI_ISR0_AE7_Pos) /*!< 0x00000080 */
#define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk /*!< Acknowledge Error 7 */
#define DSI_ISR0_AE8_Pos (8U)
#define DSI_ISR0_AE8_Msk (0x1UL << DSI_ISR0_AE8_Pos) /*!< 0x00000100 */
#define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk /*!< Acknowledge Error 8 */
#define DSI_ISR0_AE9_Pos (9U)
#define DSI_ISR0_AE9_Msk (0x1UL << DSI_ISR0_AE9_Pos) /*!< 0x00000200 */
#define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk /*!< Acknowledge Error 9 */
#define DSI_ISR0_AE10_Pos (10U)
#define DSI_ISR0_AE10_Msk (0x1UL << DSI_ISR0_AE10_Pos) /*!< 0x00000400 */
#define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk /*!< Acknowledge Error 10 */
#define DSI_ISR0_AE11_Pos (11U)
#define DSI_ISR0_AE11_Msk (0x1UL << DSI_ISR0_AE11_Pos) /*!< 0x00000800 */
#define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk /*!< Acknowledge Error 11 */
#define DSI_ISR0_AE12_Pos (12U)
#define DSI_ISR0_AE12_Msk (0x1UL << DSI_ISR0_AE12_Pos) /*!< 0x00001000 */
#define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk /*!< Acknowledge Error 12 */
#define DSI_ISR0_AE13_Pos (13U)
#define DSI_ISR0_AE13_Msk (0x1UL << DSI_ISR0_AE13_Pos) /*!< 0x00002000 */
#define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk /*!< Acknowledge Error 13 */
#define DSI_ISR0_AE14_Pos (14U)
#define DSI_ISR0_AE14_Msk (0x1UL << DSI_ISR0_AE14_Pos) /*!< 0x00004000 */
#define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk /*!< Acknowledge Error 14 */
#define DSI_ISR0_AE15_Pos (15U)
#define DSI_ISR0_AE15_Msk (0x1UL << DSI_ISR0_AE15_Pos) /*!< 0x00008000 */
#define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk /*!< Acknowledge Error 15 */
#define DSI_ISR0_PE0_Pos (16U)
#define DSI_ISR0_PE0_Msk (0x1UL << DSI_ISR0_PE0_Pos) /*!< 0x00010000 */
#define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk /*!< PHY Error 0 */
#define DSI_ISR0_PE1_Pos (17U)
#define DSI_ISR0_PE1_Msk (0x1UL << DSI_ISR0_PE1_Pos) /*!< 0x00020000 */
#define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk /*!< PHY Error 1 */
#define DSI_ISR0_PE2_Pos (18U)
#define DSI_ISR0_PE2_Msk (0x1UL << DSI_ISR0_PE2_Pos) /*!< 0x00040000 */
#define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk /*!< PHY Error 2 */
#define DSI_ISR0_PE3_Pos (19U)
#define DSI_ISR0_PE3_Msk (0x1UL << DSI_ISR0_PE3_Pos) /*!< 0x00080000 */
#define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk /*!< PHY Error 3 */
#define DSI_ISR0_PE4_Pos (20U)
#define DSI_ISR0_PE4_Msk (0x1UL << DSI_ISR0_PE4_Pos) /*!< 0x00100000 */
#define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk /*!< PHY Error 4 */
/******************* Bit definition for DSI_ISR1 register ***************/
#define DSI_ISR1_TOHSTX_Pos (0U)
#define DSI_ISR1_TOHSTX_Msk (0x1UL << DSI_ISR1_TOHSTX_Pos) /*!< 0x00000001 */
#define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Speed Transmission */
#define DSI_ISR1_TOLPRX_Pos (1U)
#define DSI_ISR1_TOLPRX_Msk (0x1UL << DSI_ISR1_TOLPRX_Pos) /*!< 0x00000002 */
#define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Power Reception */
#define DSI_ISR1_ECCSE_Pos (2U)
#define DSI_ISR1_ECCSE_Msk (0x1UL << DSI_ISR1_ECCSE_Pos) /*!< 0x00000004 */
#define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit Error */
#define DSI_ISR1_ECCME_Pos (3U)
#define DSI_ISR1_ECCME_Msk (0x1UL << DSI_ISR1_ECCME_Pos) /*!< 0x00000008 */
#define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit Error */
#define DSI_ISR1_CRCE_Pos (4U)
#define DSI_ISR1_CRCE_Msk (0x1UL << DSI_ISR1_CRCE_Pos) /*!< 0x00000010 */
#define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk /*!< CRC Error */
#define DSI_ISR1_PSE_Pos (5U)
#define DSI_ISR1_PSE_Msk (0x1UL << DSI_ISR1_PSE_Pos) /*!< 0x00000020 */
#define DSI_ISR1_PSE DSI_ISR1_PSE_Msk /*!< Packet Size Error */
#define DSI_ISR1_EOTPE_Pos (6U)
#define DSI_ISR1_EOTPE_Msk (0x1UL << DSI_ISR1_EOTPE_Pos) /*!< 0x00000040 */
#define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk /*!< EoTp Error */
#define DSI_ISR1_LPWRE_Pos (7U)
#define DSI_ISR1_LPWRE_Msk (0x1UL << DSI_ISR1_LPWRE_Pos) /*!< 0x00000080 */
#define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk /*!< LTDC Payload Write Error */
#define DSI_ISR1_GCWRE_Pos (8U)
#define DSI_ISR1_GCWRE_Msk (0x1UL << DSI_ISR1_GCWRE_Pos) /*!< 0x00000100 */
#define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk /*!< Generic Command Write Error */
#define DSI_ISR1_GPWRE_Pos (9U)
#define DSI_ISR1_GPWRE_Msk (0x1UL << DSI_ISR1_GPWRE_Pos) /*!< 0x00000200 */
#define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk /*!< Generic Payload Write Error */
#define DSI_ISR1_GPTXE_Pos (10U)
#define DSI_ISR1_GPTXE_Msk (0x1UL << DSI_ISR1_GPTXE_Pos) /*!< 0x00000400 */
#define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk /*!< Generic Payload Transmit Error */
#define DSI_ISR1_GPRDE_Pos (11U)
#define DSI_ISR1_GPRDE_Msk (0x1UL << DSI_ISR1_GPRDE_Pos) /*!< 0x00000800 */
#define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk /*!< Generic Payload Read Error */
#define DSI_ISR1_GPRXE_Pos (12U)
#define DSI_ISR1_GPRXE_Msk (0x1UL << DSI_ISR1_GPRXE_Pos) /*!< 0x00001000 */
#define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk /*!< Generic Payload Receive Error */
/******************* Bit definition for DSI_IER0 register ***************/
#define DSI_IER0_AE0IE_Pos (0U)
#define DSI_IER0_AE0IE_Msk (0x1UL << DSI_IER0_AE0IE_Pos) /*!< 0x00000001 */
#define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk /*!< Acknowledge Error 0 Interrupt Enable */
#define DSI_IER0_AE1IE_Pos (1U)
#define DSI_IER0_AE1IE_Msk (0x1UL << DSI_IER0_AE1IE_Pos) /*!< 0x00000002 */
#define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk /*!< Acknowledge Error 1 Interrupt Enable */
#define DSI_IER0_AE2IE_Pos (2U)
#define DSI_IER0_AE2IE_Msk (0x1UL << DSI_IER0_AE2IE_Pos) /*!< 0x00000004 */
#define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk /*!< Acknowledge Error 2 Interrupt Enable */
#define DSI_IER0_AE3IE_Pos (3U)
#define DSI_IER0_AE3IE_Msk (0x1UL << DSI_IER0_AE3IE_Pos) /*!< 0x00000008 */
#define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk /*!< Acknowledge Error 3 Interrupt Enable */
#define DSI_IER0_AE4IE_Pos (4U)
#define DSI_IER0_AE4IE_Msk (0x1UL << DSI_IER0_AE4IE_Pos) /*!< 0x00000010 */
#define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk /*!< Acknowledge Error 4 Interrupt Enable */
#define DSI_IER0_AE5IE_Pos (5U)
#define DSI_IER0_AE5IE_Msk (0x1UL << DSI_IER0_AE5IE_Pos) /*!< 0x00000020 */
#define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk /*!< Acknowledge Error 5 Interrupt Enable */
#define DSI_IER0_AE6IE_Pos (6U)
#define DSI_IER0_AE6IE_Msk (0x1UL << DSI_IER0_AE6IE_Pos) /*!< 0x00000040 */
#define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk /*!< Acknowledge Error 6 Interrupt Enable */
#define DSI_IER0_AE7IE_Pos (7U)
#define DSI_IER0_AE7IE_Msk (0x1UL << DSI_IER0_AE7IE_Pos) /*!< 0x00000080 */
#define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk /*!< Acknowledge Error 7 Interrupt Enable */
#define DSI_IER0_AE8IE_Pos (8U)
#define DSI_IER0_AE8IE_Msk (0x1UL << DSI_IER0_AE8IE_Pos) /*!< 0x00000100 */
#define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk /*!< Acknowledge Error 8 Interrupt Enable */
#define DSI_IER0_AE9IE_Pos (9U)
#define DSI_IER0_AE9IE_Msk (0x1UL << DSI_IER0_AE9IE_Pos) /*!< 0x00000200 */
#define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk /*!< Acknowledge Error 9 Interrupt Enable */
#define DSI_IER0_AE10IE_Pos (10U)
#define DSI_IER0_AE10IE_Msk (0x1UL << DSI_IER0_AE10IE_Pos) /*!< 0x00000400 */
#define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk /*!< Acknowledge Error 10 Interrupt Enable */
#define DSI_IER0_AE11IE_Pos (11U)
#define DSI_IER0_AE11IE_Msk (0x1UL << DSI_IER0_AE11IE_Pos) /*!< 0x00000800 */
#define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk /*!< Acknowledge Error 11 Interrupt Enable */
#define DSI_IER0_AE12IE_Pos (12U)
#define DSI_IER0_AE12IE_Msk (0x1UL << DSI_IER0_AE12IE_Pos) /*!< 0x00001000 */
#define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk /*!< Acknowledge Error 12 Interrupt Enable */
#define DSI_IER0_AE13IE_Pos (13U)
#define DSI_IER0_AE13IE_Msk (0x1UL << DSI_IER0_AE13IE_Pos) /*!< 0x00002000 */
#define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk /*!< Acknowledge Error 13 Interrupt Enable */
#define DSI_IER0_AE14IE_Pos (14U)
#define DSI_IER0_AE14IE_Msk (0x1UL << DSI_IER0_AE14IE_Pos) /*!< 0x00004000 */
#define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk /*!< Acknowledge Error 14 Interrupt Enable */
#define DSI_IER0_AE15IE_Pos (15U)
#define DSI_IER0_AE15IE_Msk (0x1UL << DSI_IER0_AE15IE_Pos) /*!< 0x00008000 */
#define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk /*!< Acknowledge Error 15 Interrupt Enable */
#define DSI_IER0_PE0IE_Pos (16U)
#define DSI_IER0_PE0IE_Msk (0x1UL << DSI_IER0_PE0IE_Pos) /*!< 0x00010000 */
#define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk /*!< PHY Error 0 Interrupt Enable */
#define DSI_IER0_PE1IE_Pos (17U)
#define DSI_IER0_PE1IE_Msk (0x1UL << DSI_IER0_PE1IE_Pos) /*!< 0x00020000 */
#define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk /*!< PHY Error 1 Interrupt Enable */
#define DSI_IER0_PE2IE_Pos (18U)
#define DSI_IER0_PE2IE_Msk (0x1UL << DSI_IER0_PE2IE_Pos) /*!< 0x00040000 */
#define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk /*!< PHY Error 2 Interrupt Enable */
#define DSI_IER0_PE3IE_Pos (19U)
#define DSI_IER0_PE3IE_Msk (0x1UL << DSI_IER0_PE3IE_Pos) /*!< 0x00080000 */
#define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk /*!< PHY Error 3 Interrupt Enable */
#define DSI_IER0_PE4IE_Pos (20U)
#define DSI_IER0_PE4IE_Msk (0x1UL << DSI_IER0_PE4IE_Pos) /*!< 0x00100000 */
#define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk /*!< PHY Error 4 Interrupt Enable */
/******************* Bit definition for DSI_IER1 register ***************/
#define DSI_IER1_TOHSTXIE_Pos (0U)
#define DSI_IER1_TOHSTXIE_Msk (0x1UL << DSI_IER1_TOHSTXIE_Pos) /*!< 0x00000001 */
#define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Speed Transmission Interrupt Enable */
#define DSI_IER1_TOLPRXIE_Pos (1U)
#define DSI_IER1_TOLPRXIE_Msk (0x1UL << DSI_IER1_TOLPRXIE_Pos) /*!< 0x00000002 */
#define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Power Reception Interrupt Enable */
#define DSI_IER1_ECCSEIE_Pos (2U)
#define DSI_IER1_ECCSEIE_Msk (0x1UL << DSI_IER1_ECCSEIE_Pos) /*!< 0x00000004 */
#define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit Error Interrupt Enable */
#define DSI_IER1_ECCMEIE_Pos (3U)
#define DSI_IER1_ECCMEIE_Msk (0x1UL << DSI_IER1_ECCMEIE_Pos) /*!< 0x00000008 */
#define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit Error Interrupt Enable */
#define DSI_IER1_CRCEIE_Pos (4U)
#define DSI_IER1_CRCEIE_Msk (0x1UL << DSI_IER1_CRCEIE_Pos) /*!< 0x00000010 */
#define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk /*!< CRC Error Interrupt Enable */
#define DSI_IER1_PSEIE_Pos (5U)
#define DSI_IER1_PSEIE_Msk (0x1UL << DSI_IER1_PSEIE_Pos) /*!< 0x00000020 */
#define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk /*!< Packet Size Error Interrupt Enable */
#define DSI_IER1_EOTPEIE_Pos (6U)
#define DSI_IER1_EOTPEIE_Msk (0x1UL << DSI_IER1_EOTPEIE_Pos) /*!< 0x00000040 */
#define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk /*!< EoTp Error Interrupt Enable */
#define DSI_IER1_LPWREIE_Pos (7U)
#define DSI_IER1_LPWREIE_Msk (0x1UL << DSI_IER1_LPWREIE_Pos) /*!< 0x00000080 */
#define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk /*!< LTDC Payload Write Error Interrupt Enable */
#define DSI_IER1_GCWREIE_Pos (8U)
#define DSI_IER1_GCWREIE_Msk (0x1UL << DSI_IER1_GCWREIE_Pos) /*!< 0x00000100 */
#define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk /*!< Generic Command Write Error Interrupt Enable */
#define DSI_IER1_GPWREIE_Pos (9U)
#define DSI_IER1_GPWREIE_Msk (0x1UL << DSI_IER1_GPWREIE_Pos) /*!< 0x00000200 */
#define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk /*!< Generic Payload Write Error Interrupt Enable */
#define DSI_IER1_GPTXEIE_Pos (10U)
#define DSI_IER1_GPTXEIE_Msk (0x1UL << DSI_IER1_GPTXEIE_Pos) /*!< 0x00000400 */
#define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk /*!< Generic Payload Transmit Error Interrupt Enable */
#define DSI_IER1_GPRDEIE_Pos (11U)
#define DSI_IER1_GPRDEIE_Msk (0x1UL << DSI_IER1_GPRDEIE_Pos) /*!< 0x00000800 */
#define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk /*!< Generic Payload Read Error Interrupt Enable */
#define DSI_IER1_GPRXEIE_Pos (12U)
#define DSI_IER1_GPRXEIE_Msk (0x1UL << DSI_IER1_GPRXEIE_Pos) /*!< 0x00001000 */
#define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk /*!< Generic Payload Receive Error Interrupt Enable */
/******************* Bit definition for DSI_FIR0 register ***************/
#define DSI_FIR0_FAE0_Pos (0U)
#define DSI_FIR0_FAE0_Msk (0x1UL << DSI_FIR0_FAE0_Pos) /*!< 0x00000001 */
#define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk /*!< Force Acknowledge Error 0 */
#define DSI_FIR0_FAE1_Pos (1U)
#define DSI_FIR0_FAE1_Msk (0x1UL << DSI_FIR0_FAE1_Pos) /*!< 0x00000002 */
#define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk /*!< Force Acknowledge Error 1 */
#define DSI_FIR0_FAE2_Pos (2U)
#define DSI_FIR0_FAE2_Msk (0x1UL << DSI_FIR0_FAE2_Pos) /*!< 0x00000004 */
#define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk /*!< Force Acknowledge Error 2 */
#define DSI_FIR0_FAE3_Pos (3U)
#define DSI_FIR0_FAE3_Msk (0x1UL << DSI_FIR0_FAE3_Pos) /*!< 0x00000008 */
#define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk /*!< Force Acknowledge Error 3 */
#define DSI_FIR0_FAE4_Pos (4U)
#define DSI_FIR0_FAE4_Msk (0x1UL << DSI_FIR0_FAE4_Pos) /*!< 0x00000010 */
#define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk /*!< Force Acknowledge Error 4 */
#define DSI_FIR0_FAE5_Pos (5U)
#define DSI_FIR0_FAE5_Msk (0x1UL << DSI_FIR0_FAE5_Pos) /*!< 0x00000020 */
#define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk /*!< Force Acknowledge Error 5 */
#define DSI_FIR0_FAE6_Pos (6U)
#define DSI_FIR0_FAE6_Msk (0x1UL << DSI_FIR0_FAE6_Pos) /*!< 0x00000040 */
#define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk /*!< Force Acknowledge Error 6 */
#define DSI_FIR0_FAE7_Pos (7U)
#define DSI_FIR0_FAE7_Msk (0x1UL << DSI_FIR0_FAE7_Pos) /*!< 0x00000080 */
#define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk /*!< Force Acknowledge Error 7 */
#define DSI_FIR0_FAE8_Pos (8U)
#define DSI_FIR0_FAE8_Msk (0x1UL << DSI_FIR0_FAE8_Pos) /*!< 0x00000100 */
#define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk /*!< Force Acknowledge Error 8 */
#define DSI_FIR0_FAE9_Pos (9U)
#define DSI_FIR0_FAE9_Msk (0x1UL << DSI_FIR0_FAE9_Pos) /*!< 0x00000200 */
#define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk /*!< Force Acknowledge Error 9 */
#define DSI_FIR0_FAE10_Pos (10U)
#define DSI_FIR0_FAE10_Msk (0x1UL << DSI_FIR0_FAE10_Pos) /*!< 0x00000400 */
#define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk /*!< Force Acknowledge Error 10 */
#define DSI_FIR0_FAE11_Pos (11U)
#define DSI_FIR0_FAE11_Msk (0x1UL << DSI_FIR0_FAE11_Pos) /*!< 0x00000800 */
#define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk /*!< Force Acknowledge Error 11 */
#define DSI_FIR0_FAE12_Pos (12U)
#define DSI_FIR0_FAE12_Msk (0x1UL << DSI_FIR0_FAE12_Pos) /*!< 0x00001000 */
#define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk /*!< Force Acknowledge Error 12 */
#define DSI_FIR0_FAE13_Pos (13U)
#define DSI_FIR0_FAE13_Msk (0x1UL << DSI_FIR0_FAE13_Pos) /*!< 0x00002000 */
#define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk /*!< Force Acknowledge Error 13 */
#define DSI_FIR0_FAE14_Pos (14U)
#define DSI_FIR0_FAE14_Msk (0x1UL << DSI_FIR0_FAE14_Pos) /*!< 0x00004000 */
#define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk /*!< Force Acknowledge Error 14 */
#define DSI_FIR0_FAE15_Pos (15U)
#define DSI_FIR0_FAE15_Msk (0x1UL << DSI_FIR0_FAE15_Pos) /*!< 0x00008000 */
#define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk /*!< Force Acknowledge Error 15 */
#define DSI_FIR0_FPE0_Pos (16U)
#define DSI_FIR0_FPE0_Msk (0x1UL << DSI_FIR0_FPE0_Pos) /*!< 0x00010000 */
#define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk /*!< Force PHY Error 0 */
#define DSI_FIR0_FPE1_Pos (17U)
#define DSI_FIR0_FPE1_Msk (0x1UL << DSI_FIR0_FPE1_Pos) /*!< 0x00020000 */
#define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk /*!< Force PHY Error 1 */
#define DSI_FIR0_FPE2_Pos (18U)
#define DSI_FIR0_FPE2_Msk (0x1UL << DSI_FIR0_FPE2_Pos) /*!< 0x00040000 */
#define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk /*!< Force PHY Error 2 */
#define DSI_FIR0_FPE3_Pos (19U)
#define DSI_FIR0_FPE3_Msk (0x1UL << DSI_FIR0_FPE3_Pos) /*!< 0x00080000 */
#define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk /*!< Force PHY Error 3 */
#define DSI_FIR0_FPE4_Pos (20U)
#define DSI_FIR0_FPE4_Msk (0x1UL << DSI_FIR0_FPE4_Pos) /*!< 0x00100000 */
#define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk /*!< Force PHY Error 4 */
/******************* Bit definition for DSI_FIR1 register ***************/
#define DSI_FIR1_FTOHSTX_Pos (0U)
#define DSI_FIR1_FTOHSTX_Msk (0x1UL << DSI_FIR1_FTOHSTX_Pos) /*!< 0x00000001 */
#define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */
#define DSI_FIR1_FTOLPRX_Pos (1U)
#define DSI_FIR1_FTOLPRX_Msk (0x1UL << DSI_FIR1_FTOLPRX_Pos) /*!< 0x00000002 */
#define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */
#define DSI_FIR1_FECCSE_Pos (2U)
#define DSI_FIR1_FECCSE_Msk (0x1UL << DSI_FIR1_FECCSE_Pos) /*!< 0x00000004 */
#define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */
#define DSI_FIR1_FECCME_Pos (3U)
#define DSI_FIR1_FECCME_Msk (0x1UL << DSI_FIR1_FECCME_Pos) /*!< 0x00000008 */
#define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */
#define DSI_FIR1_FCRCE_Pos (4U)
#define DSI_FIR1_FCRCE_Msk (0x1UL << DSI_FIR1_FCRCE_Pos) /*!< 0x00000010 */
#define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk /*!< Force CRC Error */
#define DSI_FIR1_FPSE_Pos (5U)
#define DSI_FIR1_FPSE_Msk (0x1UL << DSI_FIR1_FPSE_Pos) /*!< 0x00000020 */
#define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk /*!< Force Packet Size Error */
#define DSI_FIR1_FEOTPE_Pos (6U)
#define DSI_FIR1_FEOTPE_Msk (0x1UL << DSI_FIR1_FEOTPE_Pos) /*!< 0x00000040 */
#define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk /*!< Force EoTp Error */
#define DSI_FIR1_FLPWRE_Pos (7U)
#define DSI_FIR1_FLPWRE_Msk (0x1UL << DSI_FIR1_FLPWRE_Pos) /*!< 0x00000080 */
#define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk /*!< Force LTDC Payload Write Error */
#define DSI_FIR1_FGCWRE_Pos (8U)
#define DSI_FIR1_FGCWRE_Msk (0x1UL << DSI_FIR1_FGCWRE_Pos) /*!< 0x00000100 */
#define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk /*!< Force Generic Command Write Error */
#define DSI_FIR1_FGPWRE_Pos (9U)
#define DSI_FIR1_FGPWRE_Msk (0x1UL << DSI_FIR1_FGPWRE_Pos) /*!< 0x00000200 */
#define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk /*!< Force Generic Payload Write Error */
#define DSI_FIR1_FGPTXE_Pos (10U)
#define DSI_FIR1_FGPTXE_Msk (0x1UL << DSI_FIR1_FGPTXE_Pos) /*!< 0x00000400 */
#define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk /*!< Force Generic Payload Transmit Error */
#define DSI_FIR1_FGPRDE_Pos (11U)
#define DSI_FIR1_FGPRDE_Msk (0x1UL << DSI_FIR1_FGPRDE_Pos) /*!< 0x00000800 */
#define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk /*!< Force Generic Payload Read Error */
#define DSI_FIR1_FGPRXE_Pos (12U)
#define DSI_FIR1_FGPRXE_Msk (0x1UL << DSI_FIR1_FGPRXE_Pos) /*!< 0x00001000 */
#define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk /*!< Force Generic Payload Receive Error */
/******************* Bit definition for DSI_VSCR register ***************/
#define DSI_VSCR_EN_Pos (0U)
#define DSI_VSCR_EN_Msk (0x1UL << DSI_VSCR_EN_Pos) /*!< 0x00000001 */
#define DSI_VSCR_EN DSI_VSCR_EN_Msk /*!< Enable */
#define DSI_VSCR_UR_Pos (8U)
#define DSI_VSCR_UR_Msk (0x1UL << DSI_VSCR_UR_Pos) /*!< 0x00000100 */
#define DSI_VSCR_UR DSI_VSCR_UR_Msk /*!< Update Register */
/******************* Bit definition for DSI_LCVCIDR register ************/
#define DSI_LCVCIDR_VCID_Pos (0U)
#define DSI_LCVCIDR_VCID_Msk (0x3UL << DSI_LCVCIDR_VCID_Pos) /*!< 0x00000003 */
#define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk /*!< Virtual Channel ID */
#define DSI_LCVCIDR_VCID0_Pos (0U)
#define DSI_LCVCIDR_VCID0_Msk (0x1UL << DSI_LCVCIDR_VCID0_Pos) /*!< 0x00000001 */
#define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
#define DSI_LCVCIDR_VCID1_Pos (1U)
#define DSI_LCVCIDR_VCID1_Msk (0x1UL << DSI_LCVCIDR_VCID1_Pos) /*!< 0x00000002 */
#define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
/******************* Bit definition for DSI_LCCCR register **************/
#define DSI_LCCCR_COLC_Pos (0U)
#define DSI_LCCCR_COLC_Msk (0xFUL << DSI_LCCCR_COLC_Pos) /*!< 0x0000000F */
#define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk /*!< Color Coding */
#define DSI_LCCCR_COLC0_Pos (0U)
#define DSI_LCCCR_COLC0_Msk (0x1UL << DSI_LCCCR_COLC0_Pos) /*!< 0x00000001 */
#define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
#define DSI_LCCCR_COLC1_Pos (1U)
#define DSI_LCCCR_COLC1_Msk (0x1UL << DSI_LCCCR_COLC1_Pos) /*!< 0x00000002 */
#define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
#define DSI_LCCCR_COLC2_Pos (2U)
#define DSI_LCCCR_COLC2_Msk (0x1UL << DSI_LCCCR_COLC2_Pos) /*!< 0x00000004 */
#define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
#define DSI_LCCCR_COLC3_Pos (3U)
#define DSI_LCCCR_COLC3_Msk (0x1UL << DSI_LCCCR_COLC3_Pos) /*!< 0x00000008 */
#define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
#define DSI_LCCCR_LPE_Pos (8U)
#define DSI_LCCCR_LPE_Msk (0x1UL << DSI_LCCCR_LPE_Pos) /*!< 0x00000100 */
#define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk /*!< Loosely Packed Enable */
/******************* Bit definition for DSI_LPMCCR register *************/
#define DSI_LPMCCR_VLPSIZE_Pos (0U)
#define DSI_LPMCCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos) /*!< 0x000000FF */
#define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
#define DSI_LPMCCR_VLPSIZE0_Pos (0U)
#define DSI_LPMCCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos) /*!< 0x00000001 */
#define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
#define DSI_LPMCCR_VLPSIZE1_Pos (1U)
#define DSI_LPMCCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos) /*!< 0x00000002 */
#define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
#define DSI_LPMCCR_VLPSIZE2_Pos (2U)
#define DSI_LPMCCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos) /*!< 0x00000004 */
#define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
#define DSI_LPMCCR_VLPSIZE3_Pos (3U)
#define DSI_LPMCCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos) /*!< 0x00000008 */
#define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
#define DSI_LPMCCR_VLPSIZE4_Pos (4U)
#define DSI_LPMCCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos) /*!< 0x00000010 */
#define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
#define DSI_LPMCCR_VLPSIZE5_Pos (5U)
#define DSI_LPMCCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos) /*!< 0x00000020 */
#define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
#define DSI_LPMCCR_VLPSIZE6_Pos (6U)
#define DSI_LPMCCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos) /*!< 0x00000040 */
#define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
#define DSI_LPMCCR_VLPSIZE7_Pos (7U)
#define DSI_LPMCCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos) /*!< 0x00000080 */
#define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
#define DSI_LPMCCR_LPSIZE_Pos (16U)
#define DSI_LPMCCR_LPSIZE_Msk (0xFFUL << DSI_LPMCCR_LPSIZE_Pos) /*!< 0x00FF0000 */
#define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk /*!< Largest Packet Size */
#define DSI_LPMCCR_LPSIZE0_Pos (16U)
#define DSI_LPMCCR_LPSIZE0_Msk (0x1UL << DSI_LPMCCR_LPSIZE0_Pos) /*!< 0x00010000 */
#define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
#define DSI_LPMCCR_LPSIZE1_Pos (17U)
#define DSI_LPMCCR_LPSIZE1_Msk (0x1UL << DSI_LPMCCR_LPSIZE1_Pos) /*!< 0x00020000 */
#define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
#define DSI_LPMCCR_LPSIZE2_Pos (18U)
#define DSI_LPMCCR_LPSIZE2_Msk (0x1UL << DSI_LPMCCR_LPSIZE2_Pos) /*!< 0x00040000 */
#define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
#define DSI_LPMCCR_LPSIZE3_Pos (19U)
#define DSI_LPMCCR_LPSIZE3_Msk (0x1UL << DSI_LPMCCR_LPSIZE3_Pos) /*!< 0x00080000 */
#define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
#define DSI_LPMCCR_LPSIZE4_Pos (20U)
#define DSI_LPMCCR_LPSIZE4_Msk (0x1UL << DSI_LPMCCR_LPSIZE4_Pos) /*!< 0x00100000 */
#define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
#define DSI_LPMCCR_LPSIZE5_Pos (21U)
#define DSI_LPMCCR_LPSIZE5_Msk (0x1UL << DSI_LPMCCR_LPSIZE5_Pos) /*!< 0x00200000 */
#define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
#define DSI_LPMCCR_LPSIZE6_Pos (22U)
#define DSI_LPMCCR_LPSIZE6_Msk (0x1UL << DSI_LPMCCR_LPSIZE6_Pos) /*!< 0x00400000 */
#define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
#define DSI_LPMCCR_LPSIZE7_Pos (23U)
#define DSI_LPMCCR_LPSIZE7_Msk (0x1UL << DSI_LPMCCR_LPSIZE7_Pos) /*!< 0x00800000 */
#define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
/******************* Bit definition for DSI_VMCCR register **************/
#define DSI_VMCCR_VMT_Pos (0U)
#define DSI_VMCCR_VMT_Msk (0x3UL << DSI_VMCCR_VMT_Pos) /*!< 0x00000003 */
#define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk /*!< Video Mode Type */
#define DSI_VMCCR_VMT0_Pos (0U)
#define DSI_VMCCR_VMT0_Msk (0x1UL << DSI_VMCCR_VMT0_Pos) /*!< 0x00000001 */
#define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
#define DSI_VMCCR_VMT1_Pos (1U)
#define DSI_VMCCR_VMT1_Msk (0x1UL << DSI_VMCCR_VMT1_Pos) /*!< 0x00000002 */
#define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
#define DSI_VMCCR_LPVSAE_Pos (8U)
#define DSI_VMCCR_LPVSAE_Msk (0x1UL << DSI_VMCCR_LPVSAE_Pos) /*!< 0x00000100 */
#define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Vertical Sync time Enable */
#define DSI_VMCCR_LPVBPE_Pos (9U)
#define DSI_VMCCR_LPVBPE_Msk (0x1UL << DSI_VMCCR_LPVBPE_Pos) /*!< 0x00000200 */
#define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enable */
#define DSI_VMCCR_LPVFPE_Pos (10U)
#define DSI_VMCCR_LPVFPE_Msk (0x1UL << DSI_VMCCR_LPVFPE_Pos) /*!< 0x00000400 */
#define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
#define DSI_VMCCR_LPVAE_Pos (11U)
#define DSI_VMCCR_LPVAE_Msk (0x1UL << DSI_VMCCR_LPVAE_Pos) /*!< 0x00000800 */
#define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Vertical Active Enable */
#define DSI_VMCCR_LPHBPE_Pos (12U)
#define DSI_VMCCR_LPHBPE_Msk (0x1UL << DSI_VMCCR_LPHBPE_Pos) /*!< 0x00001000 */
#define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enable */
#define DSI_VMCCR_LPHFE_Pos (13U)
#define DSI_VMCCR_LPHFE_Msk (0x1UL << DSI_VMCCR_LPHFE_Pos) /*!< 0x00002000 */
#define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enable */
#define DSI_VMCCR_FBTAAE_Pos (14U)
#define DSI_VMCCR_FBTAAE_Msk (0x1UL << DSI_VMCCR_FBTAAE_Pos) /*!< 0x00004000 */
#define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk /*!< Frame BTA Acknowledge Enable */
#define DSI_VMCCR_LPCE_Pos (15U)
#define DSI_VMCCR_LPCE_Msk (0x1UL << DSI_VMCCR_LPCE_Pos) /*!< 0x00008000 */
#define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Command Enable */
/******************* Bit definition for DSI_VPCCR register **************/
#define DSI_VPCCR_VPSIZE_Pos (0U)
#define DSI_VPCCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos) /*!< 0x00003FFF */
#define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk /*!< Video Packet Size */
#define DSI_VPCCR_VPSIZE0_Pos (0U)
#define DSI_VPCCR_VPSIZE0_Msk (0x1UL << DSI_VPCCR_VPSIZE0_Pos) /*!< 0x00000001 */
#define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
#define DSI_VPCCR_VPSIZE1_Pos (1U)
#define DSI_VPCCR_VPSIZE1_Msk (0x1UL << DSI_VPCCR_VPSIZE1_Pos) /*!< 0x00000002 */
#define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
#define DSI_VPCCR_VPSIZE2_Pos (2U)
#define DSI_VPCCR_VPSIZE2_Msk (0x1UL << DSI_VPCCR_VPSIZE2_Pos) /*!< 0x00000004 */
#define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
#define DSI_VPCCR_VPSIZE3_Pos (3U)
#define DSI_VPCCR_VPSIZE3_Msk (0x1UL << DSI_VPCCR_VPSIZE3_Pos) /*!< 0x00000008 */
#define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
#define DSI_VPCCR_VPSIZE4_Pos (4U)
#define DSI_VPCCR_VPSIZE4_Msk (0x1UL << DSI_VPCCR_VPSIZE4_Pos) /*!< 0x00000010 */
#define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
#define DSI_VPCCR_VPSIZE5_Pos (5U)
#define DSI_VPCCR_VPSIZE5_Msk (0x1UL << DSI_VPCCR_VPSIZE5_Pos) /*!< 0x00000020 */
#define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
#define DSI_VPCCR_VPSIZE6_Pos (6U)
#define DSI_VPCCR_VPSIZE6_Msk (0x1UL << DSI_VPCCR_VPSIZE6_Pos) /*!< 0x00000040 */
#define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
#define DSI_VPCCR_VPSIZE7_Pos (7U)
#define DSI_VPCCR_VPSIZE7_Msk (0x1UL << DSI_VPCCR_VPSIZE7_Pos) /*!< 0x00000080 */
#define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
#define DSI_VPCCR_VPSIZE8_Pos (8U)
#define DSI_VPCCR_VPSIZE8_Msk (0x1UL << DSI_VPCCR_VPSIZE8_Pos) /*!< 0x00000100 */
#define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
#define DSI_VPCCR_VPSIZE9_Pos (9U)
#define DSI_VPCCR_VPSIZE9_Msk (0x1UL << DSI_VPCCR_VPSIZE9_Pos) /*!< 0x00000200 */
#define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
#define DSI_VPCCR_VPSIZE10_Pos (10U)
#define DSI_VPCCR_VPSIZE10_Msk (0x1UL << DSI_VPCCR_VPSIZE10_Pos) /*!< 0x00000400 */
#define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
#define DSI_VPCCR_VPSIZE11_Pos (11U)
#define DSI_VPCCR_VPSIZE11_Msk (0x1UL << DSI_VPCCR_VPSIZE11_Pos) /*!< 0x00000800 */
#define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
#define DSI_VPCCR_VPSIZE12_Pos (12U)
#define DSI_VPCCR_VPSIZE12_Msk (0x1UL << DSI_VPCCR_VPSIZE12_Pos) /*!< 0x00001000 */
#define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
#define DSI_VPCCR_VPSIZE13_Pos (13U)
#define DSI_VPCCR_VPSIZE13_Msk (0x1UL << DSI_VPCCR_VPSIZE13_Pos) /*!< 0x00002000 */
#define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
/******************* Bit definition for DSI_VCCCR register **************/
#define DSI_VCCCR_NUMC_Pos (0U)
#define DSI_VCCCR_NUMC_Msk (0x1FFFUL << DSI_VCCCR_NUMC_Pos) /*!< 0x00001FFF */
#define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk /*!< Number of Chunks */
#define DSI_VCCCR_NUMC0_Pos (0U)
#define DSI_VCCCR_NUMC0_Msk (0x1UL << DSI_VCCCR_NUMC0_Pos) /*!< 0x00000001 */
#define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
#define DSI_VCCCR_NUMC1_Pos (1U)
#define DSI_VCCCR_NUMC1_Msk (0x1UL << DSI_VCCCR_NUMC1_Pos) /*!< 0x00000002 */
#define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
#define DSI_VCCCR_NUMC2_Pos (2U)
#define DSI_VCCCR_NUMC2_Msk (0x1UL << DSI_VCCCR_NUMC2_Pos) /*!< 0x00000004 */
#define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
#define DSI_VCCCR_NUMC3_Pos (3U)
#define DSI_VCCCR_NUMC3_Msk (0x1UL << DSI_VCCCR_NUMC3_Pos) /*!< 0x00000008 */
#define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
#define DSI_VCCCR_NUMC4_Pos (4U)
#define DSI_VCCCR_NUMC4_Msk (0x1UL << DSI_VCCCR_NUMC4_Pos) /*!< 0x00000010 */
#define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
#define DSI_VCCCR_NUMC5_Pos (5U)
#define DSI_VCCCR_NUMC5_Msk (0x1UL << DSI_VCCCR_NUMC5_Pos) /*!< 0x00000020 */
#define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
#define DSI_VCCCR_NUMC6_Pos (6U)
#define DSI_VCCCR_NUMC6_Msk (0x1UL << DSI_VCCCR_NUMC6_Pos) /*!< 0x00000040 */
#define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
#define DSI_VCCCR_NUMC7_Pos (7U)
#define DSI_VCCCR_NUMC7_Msk (0x1UL << DSI_VCCCR_NUMC7_Pos) /*!< 0x00000080 */
#define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
#define DSI_VCCCR_NUMC8_Pos (8U)
#define DSI_VCCCR_NUMC8_Msk (0x1UL << DSI_VCCCR_NUMC8_Pos) /*!< 0x00000100 */
#define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
#define DSI_VCCCR_NUMC9_Pos (9U)
#define DSI_VCCCR_NUMC9_Msk (0x1UL << DSI_VCCCR_NUMC9_Pos) /*!< 0x00000200 */
#define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
#define DSI_VCCCR_NUMC10_Pos (10U)
#define DSI_VCCCR_NUMC10_Msk (0x1UL << DSI_VCCCR_NUMC10_Pos) /*!< 0x00000400 */
#define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
#define DSI_VCCCR_NUMC11_Pos (11U)
#define DSI_VCCCR_NUMC11_Msk (0x1UL << DSI_VCCCR_NUMC11_Pos) /*!< 0x00000800 */
#define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
#define DSI_VCCCR_NUMC12_Pos (12U)
#define DSI_VCCCR_NUMC12_Msk (0x1UL << DSI_VCCCR_NUMC12_Pos) /*!< 0x00001000 */
#define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
/******************* Bit definition for DSI_VNPCCR register *************/
#define DSI_VNPCCR_NPSIZE_Pos (0U)
#define DSI_VNPCCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos) /*!< 0x00001FFF */
#define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk /*!< Number of Chunks */
#define DSI_VNPCCR_NPSIZE0_Pos (0U)
#define DSI_VNPCCR_NPSIZE0_Msk (0x1UL << DSI_VNPCCR_NPSIZE0_Pos) /*!< 0x00000001 */
#define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
#define DSI_VNPCCR_NPSIZE1_Pos (1U)
#define DSI_VNPCCR_NPSIZE1_Msk (0x1UL << DSI_VNPCCR_NPSIZE1_Pos) /*!< 0x00000002 */
#define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
#define DSI_VNPCCR_NPSIZE2_Pos (2U)
#define DSI_VNPCCR_NPSIZE2_Msk (0x1UL << DSI_VNPCCR_NPSIZE2_Pos) /*!< 0x00000004 */
#define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
#define DSI_VNPCCR_NPSIZE3_Pos (3U)
#define DSI_VNPCCR_NPSIZE3_Msk (0x1UL << DSI_VNPCCR_NPSIZE3_Pos) /*!< 0x00000008 */
#define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
#define DSI_VNPCCR_NPSIZE4_Pos (4U)
#define DSI_VNPCCR_NPSIZE4_Msk (0x1UL << DSI_VNPCCR_NPSIZE4_Pos) /*!< 0x00000010 */
#define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
#define DSI_VNPCCR_NPSIZE5_Pos (5U)
#define DSI_VNPCCR_NPSIZE5_Msk (0x1UL << DSI_VNPCCR_NPSIZE5_Pos) /*!< 0x00000020 */
#define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
#define DSI_VNPCCR_NPSIZE6_Pos (6U)
#define DSI_VNPCCR_NPSIZE6_Msk (0x1UL << DSI_VNPCCR_NPSIZE6_Pos) /*!< 0x00000040 */
#define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
#define DSI_VNPCCR_NPSIZE7_Pos (7U)
#define DSI_VNPCCR_NPSIZE7_Msk (0x1UL << DSI_VNPCCR_NPSIZE7_Pos) /*!< 0x00000080 */
#define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
#define DSI_VNPCCR_NPSIZE8_Pos (8U)
#define DSI_VNPCCR_NPSIZE8_Msk (0x1UL << DSI_VNPCCR_NPSIZE8_Pos) /*!< 0x00000100 */
#define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
#define DSI_VNPCCR_NPSIZE9_Pos (9U)
#define DSI_VNPCCR_NPSIZE9_Msk (0x1UL << DSI_VNPCCR_NPSIZE9_Pos) /*!< 0x00000200 */
#define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
#define DSI_VNPCCR_NPSIZE10_Pos (10U)
#define DSI_VNPCCR_NPSIZE10_Msk (0x1UL << DSI_VNPCCR_NPSIZE10_Pos) /*!< 0x00000400 */
#define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
#define DSI_VNPCCR_NPSIZE11_Pos (11U)
#define DSI_VNPCCR_NPSIZE11_Msk (0x1UL << DSI_VNPCCR_NPSIZE11_Pos) /*!< 0x00000800 */
#define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
#define DSI_VNPCCR_NPSIZE12_Pos (12U)
#define DSI_VNPCCR_NPSIZE12_Msk (0x1UL << DSI_VNPCCR_NPSIZE12_Pos) /*!< 0x00001000 */
#define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
/******************* Bit definition for DSI_VHSACCR register ************/
#define DSI_VHSACCR_HSA_Pos (0U)
#define DSI_VHSACCR_HSA_Msk (0xFFFUL << DSI_VHSACCR_HSA_Pos) /*!< 0x00000FFF */
#define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk /*!< Horizontal Synchronism Active duration */
#define DSI_VHSACCR_HSA0_Pos (0U)
#define DSI_VHSACCR_HSA0_Msk (0x1UL << DSI_VHSACCR_HSA0_Pos) /*!< 0x00000001 */
#define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
#define DSI_VHSACCR_HSA1_Pos (1U)
#define DSI_VHSACCR_HSA1_Msk (0x1UL << DSI_VHSACCR_HSA1_Pos) /*!< 0x00000002 */
#define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
#define DSI_VHSACCR_HSA2_Pos (2U)
#define DSI_VHSACCR_HSA2_Msk (0x1UL << DSI_VHSACCR_HSA2_Pos) /*!< 0x00000004 */
#define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
#define DSI_VHSACCR_HSA3_Pos (3U)
#define DSI_VHSACCR_HSA3_Msk (0x1UL << DSI_VHSACCR_HSA3_Pos) /*!< 0x00000008 */
#define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
#define DSI_VHSACCR_HSA4_Pos (4U)
#define DSI_VHSACCR_HSA4_Msk (0x1UL << DSI_VHSACCR_HSA4_Pos) /*!< 0x00000010 */
#define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
#define DSI_VHSACCR_HSA5_Pos (5U)
#define DSI_VHSACCR_HSA5_Msk (0x1UL << DSI_VHSACCR_HSA5_Pos) /*!< 0x00000020 */
#define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
#define DSI_VHSACCR_HSA6_Pos (6U)
#define DSI_VHSACCR_HSA6_Msk (0x1UL << DSI_VHSACCR_HSA6_Pos) /*!< 0x00000040 */
#define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
#define DSI_VHSACCR_HSA7_Pos (7U)
#define DSI_VHSACCR_HSA7_Msk (0x1UL << DSI_VHSACCR_HSA7_Pos) /*!< 0x00000080 */
#define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
#define DSI_VHSACCR_HSA8_Pos (8U)
#define DSI_VHSACCR_HSA8_Msk (0x1UL << DSI_VHSACCR_HSA8_Pos) /*!< 0x00000100 */
#define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
#define DSI_VHSACCR_HSA9_Pos (9U)
#define DSI_VHSACCR_HSA9_Msk (0x1UL << DSI_VHSACCR_HSA9_Pos) /*!< 0x00000200 */
#define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
#define DSI_VHSACCR_HSA10_Pos (10U)
#define DSI_VHSACCR_HSA10_Msk (0x1UL << DSI_VHSACCR_HSA10_Pos) /*!< 0x00000400 */
#define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
#define DSI_VHSACCR_HSA11_Pos (11U)
#define DSI_VHSACCR_HSA11_Msk (0x1UL << DSI_VHSACCR_HSA11_Pos) /*!< 0x00000800 */
#define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
/******************* Bit definition for DSI_VHBPCCR register ************/
#define DSI_VHBPCCR_HBP_Pos (0U)
#define DSI_VHBPCCR_HBP_Msk (0xFFFUL << DSI_VHBPCCR_HBP_Pos) /*!< 0x00000FFF */
#define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */
#define DSI_VHBPCCR_HBP0_Pos (0U)
#define DSI_VHBPCCR_HBP0_Msk (0x1UL << DSI_VHBPCCR_HBP0_Pos) /*!< 0x00000001 */
#define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
#define DSI_VHBPCCR_HBP1_Pos (1U)
#define DSI_VHBPCCR_HBP1_Msk (0x1UL << DSI_VHBPCCR_HBP1_Pos) /*!< 0x00000002 */
#define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
#define DSI_VHBPCCR_HBP2_Pos (2U)
#define DSI_VHBPCCR_HBP2_Msk (0x1UL << DSI_VHBPCCR_HBP2_Pos) /*!< 0x00000004 */
#define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
#define DSI_VHBPCCR_HBP3_Pos (3U)
#define DSI_VHBPCCR_HBP3_Msk (0x1UL << DSI_VHBPCCR_HBP3_Pos) /*!< 0x00000008 */
#define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
#define DSI_VHBPCCR_HBP4_Pos (4U)
#define DSI_VHBPCCR_HBP4_Msk (0x1UL << DSI_VHBPCCR_HBP4_Pos) /*!< 0x00000010 */
#define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
#define DSI_VHBPCCR_HBP5_Pos (5U)
#define DSI_VHBPCCR_HBP5_Msk (0x1UL << DSI_VHBPCCR_HBP5_Pos) /*!< 0x00000020 */
#define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
#define DSI_VHBPCCR_HBP6_Pos (6U)
#define DSI_VHBPCCR_HBP6_Msk (0x1UL << DSI_VHBPCCR_HBP6_Pos) /*!< 0x00000040 */
#define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
#define DSI_VHBPCCR_HBP7_Pos (7U)
#define DSI_VHBPCCR_HBP7_Msk (0x1UL << DSI_VHBPCCR_HBP7_Pos) /*!< 0x00000080 */
#define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
#define DSI_VHBPCCR_HBP8_Pos (8U)
#define DSI_VHBPCCR_HBP8_Msk (0x1UL << DSI_VHBPCCR_HBP8_Pos) /*!< 0x00000100 */
#define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
#define DSI_VHBPCCR_HBP9_Pos (9U)
#define DSI_VHBPCCR_HBP9_Msk (0x1UL << DSI_VHBPCCR_HBP9_Pos) /*!< 0x00000200 */
#define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
#define DSI_VHBPCCR_HBP10_Pos (10U)
#define DSI_VHBPCCR_HBP10_Msk (0x1UL << DSI_VHBPCCR_HBP10_Pos) /*!< 0x00000400 */
#define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
#define DSI_VHBPCCR_HBP11_Pos (11U)
#define DSI_VHBPCCR_HBP11_Msk (0x1UL << DSI_VHBPCCR_HBP11_Pos) /*!< 0x00000800 */
#define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
/******************* Bit definition for DSI_VLCCR register **************/
#define DSI_VLCCR_HLINE_Pos (0U)
#define DSI_VLCCR_HLINE_Msk (0x7FFFUL << DSI_VLCCR_HLINE_Pos) /*!< 0x00007FFF */
#define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk /*!< Horizontal Line duration */
#define DSI_VLCCR_HLINE0_Pos (0U)
#define DSI_VLCCR_HLINE0_Msk (0x1UL << DSI_VLCCR_HLINE0_Pos) /*!< 0x00000001 */
#define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
#define DSI_VLCCR_HLINE1_Pos (1U)
#define DSI_VLCCR_HLINE1_Msk (0x1UL << DSI_VLCCR_HLINE1_Pos) /*!< 0x00000002 */
#define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
#define DSI_VLCCR_HLINE2_Pos (2U)
#define DSI_VLCCR_HLINE2_Msk (0x1UL << DSI_VLCCR_HLINE2_Pos) /*!< 0x00000004 */
#define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
#define DSI_VLCCR_HLINE3_Pos (3U)
#define DSI_VLCCR_HLINE3_Msk (0x1UL << DSI_VLCCR_HLINE3_Pos) /*!< 0x00000008 */
#define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
#define DSI_VLCCR_HLINE4_Pos (4U)
#define DSI_VLCCR_HLINE4_Msk (0x1UL << DSI_VLCCR_HLINE4_Pos) /*!< 0x00000010 */
#define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
#define DSI_VLCCR_HLINE5_Pos (5U)
#define DSI_VLCCR_HLINE5_Msk (0x1UL << DSI_VLCCR_HLINE5_Pos) /*!< 0x00000020 */
#define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
#define DSI_VLCCR_HLINE6_Pos (6U)
#define DSI_VLCCR_HLINE6_Msk (0x1UL << DSI_VLCCR_HLINE6_Pos) /*!< 0x00000040 */
#define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
#define DSI_VLCCR_HLINE7_Pos (7U)
#define DSI_VLCCR_HLINE7_Msk (0x1UL << DSI_VLCCR_HLINE7_Pos) /*!< 0x00000080 */
#define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
#define DSI_VLCCR_HLINE8_Pos (8U)
#define DSI_VLCCR_HLINE8_Msk (0x1UL << DSI_VLCCR_HLINE8_Pos) /*!< 0x00000100 */
#define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
#define DSI_VLCCR_HLINE9_Pos (9U)
#define DSI_VLCCR_HLINE9_Msk (0x1UL << DSI_VLCCR_HLINE9_Pos) /*!< 0x00000200 */
#define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
#define DSI_VLCCR_HLINE10_Pos (10U)
#define DSI_VLCCR_HLINE10_Msk (0x1UL << DSI_VLCCR_HLINE10_Pos) /*!< 0x00000400 */
#define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
#define DSI_VLCCR_HLINE11_Pos (11U)
#define DSI_VLCCR_HLINE11_Msk (0x1UL << DSI_VLCCR_HLINE11_Pos) /*!< 0x00000800 */
#define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
#define DSI_VLCCR_HLINE12_Pos (12U)
#define DSI_VLCCR_HLINE12_Msk (0x1UL << DSI_VLCCR_HLINE12_Pos) /*!< 0x00001000 */
#define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
#define DSI_VLCCR_HLINE13_Pos (13U)
#define DSI_VLCCR_HLINE13_Msk (0x1UL << DSI_VLCCR_HLINE13_Pos) /*!< 0x00002000 */
#define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
#define DSI_VLCCR_HLINE14_Pos (14U)
#define DSI_VLCCR_HLINE14_Msk (0x1UL << DSI_VLCCR_HLINE14_Pos) /*!< 0x00004000 */
#define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
/******************* Bit definition for DSI_VVSACCR register ***************/
#define DSI_VVSACCR_VSA_Pos (0U)
#define DSI_VVSACCR_VSA_Msk (0x3FFUL << DSI_VVSACCR_VSA_Pos) /*!< 0x000003FF */
#define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk /*!< Vertical Synchronism Active duration */
#define DSI_VVSACCR_VSA0_Pos (0U)
#define DSI_VVSACCR_VSA0_Msk (0x1UL << DSI_VVSACCR_VSA0_Pos) /*!< 0x00000001 */
#define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
#define DSI_VVSACCR_VSA1_Pos (1U)
#define DSI_VVSACCR_VSA1_Msk (0x1UL << DSI_VVSACCR_VSA1_Pos) /*!< 0x00000002 */
#define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
#define DSI_VVSACCR_VSA2_Pos (2U)
#define DSI_VVSACCR_VSA2_Msk (0x1UL << DSI_VVSACCR_VSA2_Pos) /*!< 0x00000004 */
#define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
#define DSI_VVSACCR_VSA3_Pos (3U)
#define DSI_VVSACCR_VSA3_Msk (0x1UL << DSI_VVSACCR_VSA3_Pos) /*!< 0x00000008 */
#define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
#define DSI_VVSACCR_VSA4_Pos (4U)
#define DSI_VVSACCR_VSA4_Msk (0x1UL << DSI_VVSACCR_VSA4_Pos) /*!< 0x00000010 */
#define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
#define DSI_VVSACCR_VSA5_Pos (5U)
#define DSI_VVSACCR_VSA5_Msk (0x1UL << DSI_VVSACCR_VSA5_Pos) /*!< 0x00000020 */
#define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
#define DSI_VVSACCR_VSA6_Pos (6U)
#define DSI_VVSACCR_VSA6_Msk (0x1UL << DSI_VVSACCR_VSA6_Pos) /*!< 0x00000040 */
#define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
#define DSI_VVSACCR_VSA7_Pos (7U)
#define DSI_VVSACCR_VSA7_Msk (0x1UL << DSI_VVSACCR_VSA7_Pos) /*!< 0x00000080 */
#define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
#define DSI_VVSACCR_VSA8_Pos (8U)
#define DSI_VVSACCR_VSA8_Msk (0x1UL << DSI_VVSACCR_VSA8_Pos) /*!< 0x00000100 */
#define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
#define DSI_VVSACCR_VSA9_Pos (9U)
#define DSI_VVSACCR_VSA9_Msk (0x1UL << DSI_VVSACCR_VSA9_Pos) /*!< 0x00000200 */
#define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
/******************* Bit definition for DSI_VVBPCCR register ************/
#define DSI_VVBPCCR_VBP_Pos (0U)
#define DSI_VVBPCCR_VBP_Msk (0x3FFUL << DSI_VVBPCCR_VBP_Pos) /*!< 0x000003FF */
#define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-Porch duration */
#define DSI_VVBPCCR_VBP0_Pos (0U)
#define DSI_VVBPCCR_VBP0_Msk (0x1UL << DSI_VVBPCCR_VBP0_Pos) /*!< 0x00000001 */
#define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
#define DSI_VVBPCCR_VBP1_Pos (1U)
#define DSI_VVBPCCR_VBP1_Msk (0x1UL << DSI_VVBPCCR_VBP1_Pos) /*!< 0x00000002 */
#define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
#define DSI_VVBPCCR_VBP2_Pos (2U)
#define DSI_VVBPCCR_VBP2_Msk (0x1UL << DSI_VVBPCCR_VBP2_Pos) /*!< 0x00000004 */
#define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
#define DSI_VVBPCCR_VBP3_Pos (3U)
#define DSI_VVBPCCR_VBP3_Msk (0x1UL << DSI_VVBPCCR_VBP3_Pos) /*!< 0x00000008 */
#define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
#define DSI_VVBPCCR_VBP4_Pos (4U)
#define DSI_VVBPCCR_VBP4_Msk (0x1UL << DSI_VVBPCCR_VBP4_Pos) /*!< 0x00000010 */
#define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
#define DSI_VVBPCCR_VBP5_Pos (5U)
#define DSI_VVBPCCR_VBP5_Msk (0x1UL << DSI_VVBPCCR_VBP5_Pos) /*!< 0x00000020 */
#define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
#define DSI_VVBPCCR_VBP6_Pos (6U)
#define DSI_VVBPCCR_VBP6_Msk (0x1UL << DSI_VVBPCCR_VBP6_Pos) /*!< 0x00000040 */
#define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
#define DSI_VVBPCCR_VBP7_Pos (7U)
#define DSI_VVBPCCR_VBP7_Msk (0x1UL << DSI_VVBPCCR_VBP7_Pos) /*!< 0x00000080 */
#define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
#define DSI_VVBPCCR_VBP8_Pos (8U)
#define DSI_VVBPCCR_VBP8_Msk (0x1UL << DSI_VVBPCCR_VBP8_Pos) /*!< 0x00000100 */
#define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
#define DSI_VVBPCCR_VBP9_Pos (9U)
#define DSI_VVBPCCR_VBP9_Msk (0x1UL << DSI_VVBPCCR_VBP9_Pos) /*!< 0x00000200 */
#define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
/******************* Bit definition for DSI_VVFPCCR register ************/
#define DSI_VVFPCCR_VFP_Pos (0U)
#define DSI_VVFPCCR_VFP_Msk (0x3FFUL << DSI_VVFPCCR_VFP_Pos) /*!< 0x000003FF */
#define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-Porch duration */
#define DSI_VVFPCCR_VFP0_Pos (0U)
#define DSI_VVFPCCR_VFP0_Msk (0x1UL << DSI_VVFPCCR_VFP0_Pos) /*!< 0x00000001 */
#define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
#define DSI_VVFPCCR_VFP1_Pos (1U)
#define DSI_VVFPCCR_VFP1_Msk (0x1UL << DSI_VVFPCCR_VFP1_Pos) /*!< 0x00000002 */
#define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
#define DSI_VVFPCCR_VFP2_Pos (2U)
#define DSI_VVFPCCR_VFP2_Msk (0x1UL << DSI_VVFPCCR_VFP2_Pos) /*!< 0x00000004 */
#define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
#define DSI_VVFPCCR_VFP3_Pos (3U)
#define DSI_VVFPCCR_VFP3_Msk (0x1UL << DSI_VVFPCCR_VFP3_Pos) /*!< 0x00000008 */
#define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
#define DSI_VVFPCCR_VFP4_Pos (4U)
#define DSI_VVFPCCR_VFP4_Msk (0x1UL << DSI_VVFPCCR_VFP4_Pos) /*!< 0x00000010 */
#define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
#define DSI_VVFPCCR_VFP5_Pos (5U)
#define DSI_VVFPCCR_VFP5_Msk (0x1UL << DSI_VVFPCCR_VFP5_Pos) /*!< 0x00000020 */
#define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
#define DSI_VVFPCCR_VFP6_Pos (6U)
#define DSI_VVFPCCR_VFP6_Msk (0x1UL << DSI_VVFPCCR_VFP6_Pos) /*!< 0x00000040 */
#define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
#define DSI_VVFPCCR_VFP7_Pos (7U)
#define DSI_VVFPCCR_VFP7_Msk (0x1UL << DSI_VVFPCCR_VFP7_Pos) /*!< 0x00000080 */
#define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
#define DSI_VVFPCCR_VFP8_Pos (8U)
#define DSI_VVFPCCR_VFP8_Msk (0x1UL << DSI_VVFPCCR_VFP8_Pos) /*!< 0x00000100 */
#define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
#define DSI_VVFPCCR_VFP9_Pos (9U)
#define DSI_VVFPCCR_VFP9_Msk (0x1UL << DSI_VVFPCCR_VFP9_Pos) /*!< 0x00000200 */
#define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
/******************* Bit definition for DSI_VVACCR register *************/
#define DSI_VVACCR_VA_Pos (0U)
#define DSI_VVACCR_VA_Msk (0x3FFFUL << DSI_VVACCR_VA_Pos) /*!< 0x00003FFF */
#define DSI_VVACCR_VA DSI_VVACCR_VA_Msk /*!< Vertical Active duration */
#define DSI_VVACCR_VA0_Pos (0U)
#define DSI_VVACCR_VA0_Msk (0x1UL << DSI_VVACCR_VA0_Pos) /*!< 0x00000001 */
#define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
#define DSI_VVACCR_VA1_Pos (1U)
#define DSI_VVACCR_VA1_Msk (0x1UL << DSI_VVACCR_VA1_Pos) /*!< 0x00000002 */
#define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
#define DSI_VVACCR_VA2_Pos (2U)
#define DSI_VVACCR_VA2_Msk (0x1UL << DSI_VVACCR_VA2_Pos) /*!< 0x00000004 */
#define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
#define DSI_VVACCR_VA3_Pos (3U)
#define DSI_VVACCR_VA3_Msk (0x1UL << DSI_VVACCR_VA3_Pos) /*!< 0x00000008 */
#define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
#define DSI_VVACCR_VA4_Pos (4U)
#define DSI_VVACCR_VA4_Msk (0x1UL << DSI_VVACCR_VA4_Pos) /*!< 0x00000010 */
#define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
#define DSI_VVACCR_VA5_Pos (5U)
#define DSI_VVACCR_VA5_Msk (0x1UL << DSI_VVACCR_VA5_Pos) /*!< 0x00000020 */
#define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
#define DSI_VVACCR_VA6_Pos (6U)
#define DSI_VVACCR_VA6_Msk (0x1UL << DSI_VVACCR_VA6_Pos) /*!< 0x00000040 */
#define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
#define DSI_VVACCR_VA7_Pos (7U)
#define DSI_VVACCR_VA7_Msk (0x1UL << DSI_VVACCR_VA7_Pos) /*!< 0x00000080 */
#define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
#define DSI_VVACCR_VA8_Pos (8U)
#define DSI_VVACCR_VA8_Msk (0x1UL << DSI_VVACCR_VA8_Pos) /*!< 0x00000100 */
#define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
#define DSI_VVACCR_VA9_Pos (9U)
#define DSI_VVACCR_VA9_Msk (0x1UL << DSI_VVACCR_VA9_Pos) /*!< 0x00000200 */
#define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
#define DSI_VVACCR_VA10_Pos (10U)
#define DSI_VVACCR_VA10_Msk (0x1UL << DSI_VVACCR_VA10_Pos) /*!< 0x00000400 */
#define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
#define DSI_VVACCR_VA11_Pos (11U)
#define DSI_VVACCR_VA11_Msk (0x1UL << DSI_VVACCR_VA11_Pos) /*!< 0x00000800 */
#define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
#define DSI_VVACCR_VA12_Pos (12U)
#define DSI_VVACCR_VA12_Msk (0x1UL << DSI_VVACCR_VA12_Pos) /*!< 0x00001000 */
#define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
#define DSI_VVACCR_VA13_Pos (13U)
#define DSI_VVACCR_VA13_Msk (0x1UL << DSI_VVACCR_VA13_Pos) /*!< 0x00002000 */
#define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
/******************* Bit definition for DSI_WCFGR register ***************/
#define DSI_WCFGR_DSIM_Pos (0U)
#define DSI_WCFGR_DSIM_Msk (0x1UL << DSI_WCFGR_DSIM_Pos) /*!< 0x00000001 */
#define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk /*!< DSI Mode */
#define DSI_WCFGR_COLMUX_Pos (1U)
#define DSI_WCFGR_COLMUX_Msk (0x7UL << DSI_WCFGR_COLMUX_Pos) /*!< 0x0000000E */
#define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk /*!< Color Multiplexing */
#define DSI_WCFGR_COLMUX0_Pos (1U)
#define DSI_WCFGR_COLMUX0_Msk (0x1UL << DSI_WCFGR_COLMUX0_Pos) /*!< 0x00000002 */
#define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
#define DSI_WCFGR_COLMUX1_Pos (2U)
#define DSI_WCFGR_COLMUX1_Msk (0x1UL << DSI_WCFGR_COLMUX1_Pos) /*!< 0x00000004 */
#define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
#define DSI_WCFGR_COLMUX2_Pos (3U)
#define DSI_WCFGR_COLMUX2_Msk (0x1UL << DSI_WCFGR_COLMUX2_Pos) /*!< 0x00000008 */
#define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
#define DSI_WCFGR_TESRC_Pos (4U)
#define DSI_WCFGR_TESRC_Msk (0x1UL << DSI_WCFGR_TESRC_Pos) /*!< 0x00000010 */
#define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk /*!< Tearing Effect Source */
#define DSI_WCFGR_TEPOL_Pos (5U)
#define DSI_WCFGR_TEPOL_Msk (0x1UL << DSI_WCFGR_TEPOL_Pos) /*!< 0x00000020 */
#define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk /*!< Tearing Effect Polarity */
#define DSI_WCFGR_AR_Pos (6U)
#define DSI_WCFGR_AR_Msk (0x1UL << DSI_WCFGR_AR_Pos) /*!< 0x00000040 */
#define DSI_WCFGR_AR DSI_WCFGR_AR_Msk /*!< Automatic Refresh */
#define DSI_WCFGR_VSPOL_Pos (7U)
#define DSI_WCFGR_VSPOL_Msk (0x1UL << DSI_WCFGR_VSPOL_Pos) /*!< 0x00000080 */
#define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk /*!< VSync Polarity */
/******************* Bit definition for DSI_WCR register *****************/
#define DSI_WCR_COLM_Pos (0U)
#define DSI_WCR_COLM_Msk (0x1UL << DSI_WCR_COLM_Pos) /*!< 0x00000001 */
#define DSI_WCR_COLM DSI_WCR_COLM_Msk /*!< Color Mode */
#define DSI_WCR_SHTDN_Pos (1U)
#define DSI_WCR_SHTDN_Msk (0x1UL << DSI_WCR_SHTDN_Pos) /*!< 0x00000002 */
#define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk /*!< Shutdown */
#define DSI_WCR_LTDCEN_Pos (2U)
#define DSI_WCR_LTDCEN_Msk (0x1UL << DSI_WCR_LTDCEN_Pos) /*!< 0x00000004 */
#define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk /*!< LTDC Enable */
#define DSI_WCR_DSIEN_Pos (3U)
#define DSI_WCR_DSIEN_Msk (0x1UL << DSI_WCR_DSIEN_Pos) /*!< 0x00000008 */
#define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk /*!< DSI Enable */
/******************* Bit definition for DSI_WIER register ****************/
#define DSI_WIER_TEIE_Pos (0U)
#define DSI_WIER_TEIE_Msk (0x1UL << DSI_WIER_TEIE_Pos) /*!< 0x00000001 */
#define DSI_WIER_TEIE DSI_WIER_TEIE_Msk /*!< Tearing Effect Interrupt Enable */
#define DSI_WIER_ERIE_Pos (1U)
#define DSI_WIER_ERIE_Msk (0x1UL << DSI_WIER_ERIE_Pos) /*!< 0x00000002 */
#define DSI_WIER_ERIE DSI_WIER_ERIE_Msk /*!< End of Refresh Interrupt Enable */
#define DSI_WIER_PLLLIE_Pos (9U)
#define DSI_WIER_PLLLIE_Msk (0x1UL << DSI_WIER_PLLLIE_Pos) /*!< 0x00000200 */
#define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk /*!< PLL Lock Interrupt Enable */
#define DSI_WIER_PLLUIE_Pos (10U)
#define DSI_WIER_PLLUIE_Msk (0x1UL << DSI_WIER_PLLUIE_Pos) /*!< 0x00000400 */
#define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk /*!< PLL Unlock Interrupt Enable */
#define DSI_WIER_RRIE_Pos (13U)
#define DSI_WIER_RRIE_Msk (0x1UL << DSI_WIER_RRIE_Pos) /*!< 0x00002000 */
#define DSI_WIER_RRIE DSI_WIER_RRIE_Msk /*!< Regulator Ready Interrupt Enable */
/******************* Bit definition for DSI_WISR register ****************/
#define DSI_WISR_TEIF_Pos (0U)
#define DSI_WISR_TEIF_Msk (0x1UL << DSI_WISR_TEIF_Pos) /*!< 0x00000001 */
#define DSI_WISR_TEIF DSI_WISR_TEIF_Msk /*!< Tearing Effect Interrupt Flag */
#define DSI_WISR_ERIF_Pos (1U)
#define DSI_WISR_ERIF_Msk (0x1UL << DSI_WISR_ERIF_Pos) /*!< 0x00000002 */
#define DSI_WISR_ERIF DSI_WISR_ERIF_Msk /*!< End of Refresh Interrupt Flag */
#define DSI_WISR_BUSY_Pos (2U)
#define DSI_WISR_BUSY_Msk (0x1UL << DSI_WISR_BUSY_Pos) /*!< 0x00000004 */
#define DSI_WISR_BUSY DSI_WISR_BUSY_Msk /*!< Busy Flag */
#define DSI_WISR_PLLLS_Pos (8U)
#define DSI_WISR_PLLLS_Msk (0x1UL << DSI_WISR_PLLLS_Pos) /*!< 0x00000100 */
#define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk /*!< PLL Lock Status */
#define DSI_WISR_PLLLIF_Pos (9U)
#define DSI_WISR_PLLLIF_Msk (0x1UL << DSI_WISR_PLLLIF_Pos) /*!< 0x00000200 */
#define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk /*!< PLL Lock Interrupt Flag */
#define DSI_WISR_PLLUIF_Pos (10U)
#define DSI_WISR_PLLUIF_Msk (0x1UL << DSI_WISR_PLLUIF_Pos) /*!< 0x00000400 */
#define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk /*!< PLL Unlock Interrupt Flag */
#define DSI_WISR_RRS_Pos (12U)
#define DSI_WISR_RRS_Msk (0x1UL << DSI_WISR_RRS_Pos) /*!< 0x00001000 */
#define DSI_WISR_RRS DSI_WISR_RRS_Msk /*!< Regulator Ready Flag */
#define DSI_WISR_RRIF_Pos (13U)
#define DSI_WISR_RRIF_Msk (0x1UL << DSI_WISR_RRIF_Pos) /*!< 0x00002000 */
#define DSI_WISR_RRIF DSI_WISR_RRIF_Msk /*!< Regulator Ready Interrupt Flag */
/******************* Bit definition for DSI_WIFCR register ***************/
#define DSI_WIFCR_CTEIF_Pos (0U)
#define DSI_WIFCR_CTEIF_Msk (0x1UL << DSI_WIFCR_CTEIF_Pos) /*!< 0x00000001 */
#define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk /*!< Clear Tearing Effect Interrupt Flag */
#define DSI_WIFCR_CERIF_Pos (1U)
#define DSI_WIFCR_CERIF_Msk (0x1UL << DSI_WIFCR_CERIF_Pos) /*!< 0x00000002 */
#define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk /*!< Clear End of Refresh Interrupt Flag */
#define DSI_WIFCR_CPLLLIF_Pos (9U)
#define DSI_WIFCR_CPLLLIF_Msk (0x1UL << DSI_WIFCR_CPLLLIF_Pos) /*!< 0x00000200 */
#define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk /*!< Clear PLL Lock Interrupt Flag */
#define DSI_WIFCR_CPLLUIF_Pos (10U)
#define DSI_WIFCR_CPLLUIF_Msk (0x1UL << DSI_WIFCR_CPLLUIF_Pos) /*!< 0x00000400 */
#define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk /*!< Clear PLL Unlock Interrupt Flag */
#define DSI_WIFCR_CRRIF_Pos (13U)
#define DSI_WIFCR_CRRIF_Msk (0x1UL << DSI_WIFCR_CRRIF_Pos) /*!< 0x00002000 */
#define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk /*!< Clear Regulator Ready Interrupt Flag */
/******************* Bit definition for DSI_WPCR0 register ***************/
#define DSI_WPCR0_UIX4_Pos (0U)
#define DSI_WPCR0_UIX4_Msk (0x3FUL << DSI_WPCR0_UIX4_Pos) /*!< 0x0000003F */
#define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk /*!< Unit Interval multiplied by 4 */
#define DSI_WPCR0_UIX4_0 (0x01UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000001 */
#define DSI_WPCR0_UIX4_1 (0x02UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000002 */
#define DSI_WPCR0_UIX4_2 (0x04UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000004 */
#define DSI_WPCR0_UIX4_3 (0x08UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000008 */
#define DSI_WPCR0_UIX4_4 (0x10UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000010 */
#define DSI_WPCR0_UIX4_5 (0x20UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000020 */
#define DSI_WPCR0_SWCL_Pos (6U)
#define DSI_WPCR0_SWCL_Msk (0x1UL << DSI_WPCR0_SWCL_Pos) /*!< 0x00000040 */
#define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk /*!< Swap pins on clock lane */
#define DSI_WPCR0_SWDL0_Pos (7U)
#define DSI_WPCR0_SWDL0_Msk (0x1UL << DSI_WPCR0_SWDL0_Pos) /*!< 0x00000080 */
#define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk /*!< Swap pins on data lane 1 */
#define DSI_WPCR0_SWDL1_Pos (8U)
#define DSI_WPCR0_SWDL1_Msk (0x1UL << DSI_WPCR0_SWDL1_Pos) /*!< 0x00000100 */
#define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk /*!< Swap pins on data lane 2 */
#define DSI_WPCR0_HSICL_Pos (9U)
#define DSI_WPCR0_HSICL_Msk (0x1UL << DSI_WPCR0_HSICL_Pos) /*!< 0x00000200 */
#define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on clock lane */
#define DSI_WPCR0_HSIDL0_Pos (10U)
#define DSI_WPCR0_HSIDL0_Msk (0x1UL << DSI_WPCR0_HSIDL0_Pos) /*!< 0x00000400 */
#define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on lane 1 */
#define DSI_WPCR0_HSIDL1_Pos (11U)
#define DSI_WPCR0_HSIDL1_Msk (0x1UL << DSI_WPCR0_HSIDL1_Pos) /*!< 0x00000800 */
#define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on lane 2 */
#define DSI_WPCR0_FTXSMCL_Pos (12U)
#define DSI_WPCR0_FTXSMCL_Msk (0x1UL << DSI_WPCR0_FTXSMCL_Pos) /*!< 0x00001000 */
#define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk /*!< Force clock lane in TX stop mode */
#define DSI_WPCR0_FTXSMDL_Pos (13U)
#define DSI_WPCR0_FTXSMDL_Msk (0x1UL << DSI_WPCR0_FTXSMDL_Pos) /*!< 0x00002000 */
#define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk /*!< Force data lanes in TX stop mode */
#define DSI_WPCR0_CDOFFDL_Pos (14U)
#define DSI_WPCR0_CDOFFDL_Msk (0x1UL << DSI_WPCR0_CDOFFDL_Pos) /*!< 0x00004000 */
#define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk /*!< Contention detection OFF */
#define DSI_WPCR0_TDDL_Pos (16U)
#define DSI_WPCR0_TDDL_Msk (0x1UL << DSI_WPCR0_TDDL_Pos) /*!< 0x00010000 */
#define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk /*!< Turn Disable Data Lanes */
#define DSI_WPCR0_PDEN_Pos (18U)
#define DSI_WPCR0_PDEN_Msk (0x1UL << DSI_WPCR0_PDEN_Pos) /*!< 0x00040000 */
#define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enable */
#define DSI_WPCR0_TCLKPREPEN_Pos (19U)
#define DSI_WPCR0_TCLKPREPEN_Msk (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos) /*!< 0x00080000 */
#define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLKPREP Enable */
#define DSI_WPCR0_TCLKZEROEN_Pos (20U)
#define DSI_WPCR0_TCLKZEROEN_Msk (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos) /*!< 0x00100000 */
#define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLKZERO Enable */
#define DSI_WPCR0_THSPREPEN_Pos (21U)
#define DSI_WPCR0_THSPREPEN_Msk (0x1UL << DSI_WPCR0_THSPREPEN_Pos) /*!< 0x00200000 */
#define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSPREP Enable */
#define DSI_WPCR0_THSTRAILEN_Pos (22U)
#define DSI_WPCR0_THSTRAILEN_Msk (0x1UL << DSI_WPCR0_THSTRAILEN_Pos) /*!< 0x00400000 */
#define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HSTRAIL Enable */
#define DSI_WPCR0_THSZEROEN_Pos (23U)
#define DSI_WPCR0_THSZEROEN_Msk (0x1UL << DSI_WPCR0_THSZEROEN_Pos) /*!< 0x00800000 */
#define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZERO Enable */
#define DSI_WPCR0_TLPXDEN_Pos (24U)
#define DSI_WPCR0_TLPXDEN_Msk (0x1UL << DSI_WPCR0_TLPXDEN_Pos) /*!< 0x01000000 */
#define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPXD Enable */
#define DSI_WPCR0_THSEXITEN_Pos (25U)
#define DSI_WPCR0_THSEXITEN_Msk (0x1UL << DSI_WPCR0_THSEXITEN_Pos) /*!< 0x02000000 */
#define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSEXIT Enable */
#define DSI_WPCR0_TLPXCEN_Pos (26U)
#define DSI_WPCR0_TLPXCEN_Msk (0x1UL << DSI_WPCR0_TLPXCEN_Pos) /*!< 0x04000000 */
#define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPXC Enable */
#define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
#define DSI_WPCR0_TCLKPOSTEN_Msk (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos) /*!< 0x08000000 */
#define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLKPOST Enable */
/******************* Bit definition for DSI_WPCR1 register ***************/
#define DSI_WPCR1_HSTXDCL_Pos (0U)
#define DSI_WPCR1_HSTXDCL_Msk (0x3UL << DSI_WPCR1_HSTXDCL_Pos) /*!< 0x00000003 */
#define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
#define DSI_WPCR1_HSTXDCL0_Pos (0U)
#define DSI_WPCR1_HSTXDCL0_Msk (0x1UL << DSI_WPCR1_HSTXDCL0_Pos) /*!< 0x00000001 */
#define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
#define DSI_WPCR1_HSTXDCL1_Pos (1U)
#define DSI_WPCR1_HSTXDCL1_Msk (0x1UL << DSI_WPCR1_HSTXDCL1_Pos) /*!< 0x00000002 */
#define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
#define DSI_WPCR1_HSTXDDL_Pos (2U)
#define DSI_WPCR1_HSTXDDL_Msk (0x3UL << DSI_WPCR1_HSTXDDL_Pos) /*!< 0x0000000C */
#define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
#define DSI_WPCR1_HSTXDDL0_Pos (2U)
#define DSI_WPCR1_HSTXDDL0_Msk (0x1UL << DSI_WPCR1_HSTXDDL0_Pos) /*!< 0x00000004 */
#define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
#define DSI_WPCR1_HSTXDDL1_Pos (3U)
#define DSI_WPCR1_HSTXDDL1_Msk (0x1UL << DSI_WPCR1_HSTXDDL1_Pos) /*!< 0x00000008 */
#define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
#define DSI_WPCR1_LPSRCCL_Pos (6U)
#define DSI_WPCR1_LPSRCCL_Msk (0x3UL << DSI_WPCR1_LPSRCCL_Pos) /*!< 0x000000C0 */
#define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
#define DSI_WPCR1_LPSRCCL0_Pos (6U)
#define DSI_WPCR1_LPSRCCL0_Msk (0x1UL << DSI_WPCR1_LPSRCCL0_Pos) /*!< 0x00000040 */
#define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
#define DSI_WPCR1_LPSRCCL1_Pos (7U)
#define DSI_WPCR1_LPSRCCL1_Msk (0x1UL << DSI_WPCR1_LPSRCCL1_Pos) /*!< 0x00000080 */
#define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
#define DSI_WPCR1_LPSRCDL_Pos (8U)
#define DSI_WPCR1_LPSRCDL_Msk (0x3UL << DSI_WPCR1_LPSRCDL_Pos) /*!< 0x00000300 */
#define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
#define DSI_WPCR1_LPSRCDL0_Pos (8U)
#define DSI_WPCR1_LPSRCDL0_Msk (0x1UL << DSI_WPCR1_LPSRCDL0_Pos) /*!< 0x00000100 */
#define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
#define DSI_WPCR1_LPSRCDL1_Pos (9U)
#define DSI_WPCR1_LPSRCDL1_Msk (0x1UL << DSI_WPCR1_LPSRCDL1_Pos) /*!< 0x00000200 */
#define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
#define DSI_WPCR1_SDDC_Pos (12U)
#define DSI_WPCR1_SDDC_Msk (0x1UL << DSI_WPCR1_SDDC_Pos) /*!< 0x00001000 */
#define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk /*!< SDD Control */
#define DSI_WPCR1_LPRXVCDL_Pos (14U)
#define DSI_WPCR1_LPRXVCDL_Msk (0x3UL << DSI_WPCR1_LPRXVCDL_Pos) /*!< 0x0000C000 */
#define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensation on Data Lanes */
#define DSI_WPCR1_LPRXVCDL0_Pos (14U)
#define DSI_WPCR1_LPRXVCDL0_Msk (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos) /*!< 0x00004000 */
#define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
#define DSI_WPCR1_LPRXVCDL1_Pos (15U)
#define DSI_WPCR1_LPRXVCDL1_Msk (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos) /*!< 0x00008000 */
#define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
#define DSI_WPCR1_HSTXSRCCL_Pos (16U)
#define DSI_WPCR1_HSTXSRCCL_Msk (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos) /*!< 0x00030000 */
#define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
#define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
#define DSI_WPCR1_HSTXSRCCL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos) /*!< 0x00010000 */
#define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
#define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
#define DSI_WPCR1_HSTXSRCCL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos) /*!< 0x00020000 */
#define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
#define DSI_WPCR1_HSTXSRCDL_Pos (18U)
#define DSI_WPCR1_HSTXSRCDL_Msk (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos) /*!< 0x000C0000 */
#define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
#define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
#define DSI_WPCR1_HSTXSRCDL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos) /*!< 0x00040000 */
#define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
#define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
#define DSI_WPCR1_HSTXSRCDL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos) /*!< 0x00080000 */
#define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
#define DSI_WPCR1_FLPRXLPM_Pos (22U)
#define DSI_WPCR1_FLPRXLPM_Msk (0x1UL << DSI_WPCR1_FLPRXLPM_Pos) /*!< 0x00400000 */
#define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */
#define DSI_WPCR1_LPRXFT_Pos (25U)
#define DSI_WPCR1_LPRXFT_Msk (0x3UL << DSI_WPCR1_LPRXFT_Pos) /*!< 0x06000000 */
#define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering Tuning */
#define DSI_WPCR1_LPRXFT0_Pos (25U)
#define DSI_WPCR1_LPRXFT0_Msk (0x1UL << DSI_WPCR1_LPRXFT0_Pos) /*!< 0x02000000 */
#define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
#define DSI_WPCR1_LPRXFT1_Pos (26U)
#define DSI_WPCR1_LPRXFT1_Msk (0x1UL << DSI_WPCR1_LPRXFT1_Pos) /*!< 0x04000000 */
#define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
/******************* Bit definition for DSI_WPCR2 register ***************/
#define DSI_WPCR2_TCLKPREP_Pos (0U)
#define DSI_WPCR2_TCLKPREP_Msk (0xFFUL << DSI_WPCR2_TCLKPREP_Pos) /*!< 0x000000FF */
#define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */
#define DSI_WPCR2_TCLKPREP0_Pos (0U)
#define DSI_WPCR2_TCLKPREP0_Msk (0x1UL << DSI_WPCR2_TCLKPREP0_Pos) /*!< 0x00000001 */
#define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
#define DSI_WPCR2_TCLKPREP1_Pos (1U)
#define DSI_WPCR2_TCLKPREP1_Msk (0x1UL << DSI_WPCR2_TCLKPREP1_Pos) /*!< 0x00000002 */
#define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
#define DSI_WPCR2_TCLKPREP2_Pos (2U)
#define DSI_WPCR2_TCLKPREP2_Msk (0x1UL << DSI_WPCR2_TCLKPREP2_Pos) /*!< 0x00000004 */
#define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
#define DSI_WPCR2_TCLKPREP3_Pos (3U)
#define DSI_WPCR2_TCLKPREP3_Msk (0x1UL << DSI_WPCR2_TCLKPREP3_Pos) /*!< 0x00000008 */
#define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
#define DSI_WPCR2_TCLKPREP4_Pos (4U)
#define DSI_WPCR2_TCLKPREP4_Msk (0x1UL << DSI_WPCR2_TCLKPREP4_Pos) /*!< 0x00000010 */
#define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
#define DSI_WPCR2_TCLKPREP5_Pos (5U)
#define DSI_WPCR2_TCLKPREP5_Msk (0x1UL << DSI_WPCR2_TCLKPREP5_Pos) /*!< 0x00000020 */
#define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
#define DSI_WPCR2_TCLKPREP6_Pos (6U)
#define DSI_WPCR2_TCLKPREP6_Msk (0x1UL << DSI_WPCR2_TCLKPREP6_Pos) /*!< 0x00000040 */
#define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
#define DSI_WPCR2_TCLKPREP7_Pos (7U)
#define DSI_WPCR2_TCLKPREP7_Msk (0x1UL << DSI_WPCR2_TCLKPREP7_Pos) /*!< 0x00000080 */
#define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
#define DSI_WPCR2_TCLKZERO_Pos (8U)
#define DSI_WPCR2_TCLKZERO_Msk (0xFFUL << DSI_WPCR2_TCLKZERO_Pos) /*!< 0x0000FF00 */
#define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */
#define DSI_WPCR2_TCLKZERO0_Pos (8U)
#define DSI_WPCR2_TCLKZERO0_Msk (0x1UL << DSI_WPCR2_TCLKZERO0_Pos) /*!< 0x00000100 */
#define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
#define DSI_WPCR2_TCLKZERO1_Pos (9U)
#define DSI_WPCR2_TCLKZERO1_Msk (0x1UL << DSI_WPCR2_TCLKZERO1_Pos) /*!< 0x00000200 */
#define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
#define DSI_WPCR2_TCLKZERO2_Pos (10U)
#define DSI_WPCR2_TCLKZERO2_Msk (0x1UL << DSI_WPCR2_TCLKZERO2_Pos) /*!< 0x00000400 */
#define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
#define DSI_WPCR2_TCLKZERO3_Pos (11U)
#define DSI_WPCR2_TCLKZERO3_Msk (0x1UL << DSI_WPCR2_TCLKZERO3_Pos) /*!< 0x00000800 */
#define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
#define DSI_WPCR2_TCLKZERO4_Pos (12U)
#define DSI_WPCR2_TCLKZERO4_Msk (0x1UL << DSI_WPCR2_TCLKZERO4_Pos) /*!< 0x00001000 */
#define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
#define DSI_WPCR2_TCLKZERO5_Pos (13U)
#define DSI_WPCR2_TCLKZERO5_Msk (0x1UL << DSI_WPCR2_TCLKZERO5_Pos) /*!< 0x00002000 */
#define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
#define DSI_WPCR2_TCLKZERO6_Pos (14U)
#define DSI_WPCR2_TCLKZERO6_Msk (0x1UL << DSI_WPCR2_TCLKZERO6_Pos) /*!< 0x00004000 */
#define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
#define DSI_WPCR2_TCLKZERO7_Pos (15U)
#define DSI_WPCR2_TCLKZERO7_Msk (0x1UL << DSI_WPCR2_TCLKZERO7_Pos) /*!< 0x00008000 */
#define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
#define DSI_WPCR2_THSPREP_Pos (16U)
#define DSI_WPCR2_THSPREP_Msk (0xFFUL << DSI_WPCR2_THSPREP_Pos) /*!< 0x00FF0000 */
#define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */
#define DSI_WPCR2_THSPREP0_Pos (16U)
#define DSI_WPCR2_THSPREP0_Msk (0x1UL << DSI_WPCR2_THSPREP0_Pos) /*!< 0x00010000 */
#define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
#define DSI_WPCR2_THSPREP1_Pos (17U)
#define DSI_WPCR2_THSPREP1_Msk (0x1UL << DSI_WPCR2_THSPREP1_Pos) /*!< 0x00020000 */
#define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
#define DSI_WPCR2_THSPREP2_Pos (18U)
#define DSI_WPCR2_THSPREP2_Msk (0x1UL << DSI_WPCR2_THSPREP2_Pos) /*!< 0x00040000 */
#define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
#define DSI_WPCR2_THSPREP3_Pos (19U)
#define DSI_WPCR2_THSPREP3_Msk (0x1UL << DSI_WPCR2_THSPREP3_Pos) /*!< 0x00080000 */
#define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
#define DSI_WPCR2_THSPREP4_Pos (20U)
#define DSI_WPCR2_THSPREP4_Msk (0x1UL << DSI_WPCR2_THSPREP4_Pos) /*!< 0x00100000 */
#define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
#define DSI_WPCR2_THSPREP5_Pos (21U)
#define DSI_WPCR2_THSPREP5_Msk (0x1UL << DSI_WPCR2_THSPREP5_Pos) /*!< 0x00200000 */
#define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
#define DSI_WPCR2_THSPREP6_Pos (22U)
#define DSI_WPCR2_THSPREP6_Msk (0x1UL << DSI_WPCR2_THSPREP6_Pos) /*!< 0x00400000 */
#define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
#define DSI_WPCR2_THSPREP7_Pos (23U)
#define DSI_WPCR2_THSPREP7_Msk (0x1UL << DSI_WPCR2_THSPREP7_Pos) /*!< 0x00800000 */
#define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
#define DSI_WPCR2_THSTRAIL_Pos (24U)
#define DSI_WPCR2_THSTRAIL_Msk (0xFFUL << DSI_WPCR2_THSTRAIL_Pos) /*!< 0xFF000000 */
#define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */
#define DSI_WPCR2_THSTRAIL0_Pos (24U)
#define DSI_WPCR2_THSTRAIL0_Msk (0x1UL << DSI_WPCR2_THSTRAIL0_Pos) /*!< 0x01000000 */
#define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
#define DSI_WPCR2_THSTRAIL1_Pos (25U)
#define DSI_WPCR2_THSTRAIL1_Msk (0x1UL << DSI_WPCR2_THSTRAIL1_Pos) /*!< 0x02000000 */
#define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
#define DSI_WPCR2_THSTRAIL2_Pos (26U)
#define DSI_WPCR2_THSTRAIL2_Msk (0x1UL << DSI_WPCR2_THSTRAIL2_Pos) /*!< 0x04000000 */
#define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
#define DSI_WPCR2_THSTRAIL3_Pos (27U)
#define DSI_WPCR2_THSTRAIL3_Msk (0x1UL << DSI_WPCR2_THSTRAIL3_Pos) /*!< 0x08000000 */
#define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
#define DSI_WPCR2_THSTRAIL4_Pos (28U)
#define DSI_WPCR2_THSTRAIL4_Msk (0x1UL << DSI_WPCR2_THSTRAIL4_Pos) /*!< 0x10000000 */
#define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
#define DSI_WPCR2_THSTRAIL5_Pos (29U)
#define DSI_WPCR2_THSTRAIL5_Msk (0x1UL << DSI_WPCR2_THSTRAIL5_Pos) /*!< 0x20000000 */
#define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
#define DSI_WPCR2_THSTRAIL6_Pos (30U)
#define DSI_WPCR2_THSTRAIL6_Msk (0x1UL << DSI_WPCR2_THSTRAIL6_Pos) /*!< 0x40000000 */
#define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
#define DSI_WPCR2_THSTRAIL7_Pos (31U)
#define DSI_WPCR2_THSTRAIL7_Msk (0x1UL << DSI_WPCR2_THSTRAIL7_Pos) /*!< 0x80000000 */
#define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
/******************* Bit definition for DSI_WPCR3 register ***************/
#define DSI_WPCR3_THSZERO_Pos (0U)
#define DSI_WPCR3_THSZERO_Msk (0xFFUL << DSI_WPCR3_THSZERO_Pos) /*!< 0x000000FF */
#define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */
#define DSI_WPCR3_THSZERO0_Pos (0U)
#define DSI_WPCR3_THSZERO0_Msk (0x1UL << DSI_WPCR3_THSZERO0_Pos) /*!< 0x00000001 */
#define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
#define DSI_WPCR3_THSZERO1_Pos (1U)
#define DSI_WPCR3_THSZERO1_Msk (0x1UL << DSI_WPCR3_THSZERO1_Pos) /*!< 0x00000002 */
#define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
#define DSI_WPCR3_THSZERO2_Pos (2U)
#define DSI_WPCR3_THSZERO2_Msk (0x1UL << DSI_WPCR3_THSZERO2_Pos) /*!< 0x00000004 */
#define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
#define DSI_WPCR3_THSZERO3_Pos (3U)
#define DSI_WPCR3_THSZERO3_Msk (0x1UL << DSI_WPCR3_THSZERO3_Pos) /*!< 0x00000008 */
#define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
#define DSI_WPCR3_THSZERO4_Pos (4U)
#define DSI_WPCR3_THSZERO4_Msk (0x1UL << DSI_WPCR3_THSZERO4_Pos) /*!< 0x00000010 */
#define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
#define DSI_WPCR3_THSZERO5_Pos (5U)
#define DSI_WPCR3_THSZERO5_Msk (0x1UL << DSI_WPCR3_THSZERO5_Pos) /*!< 0x00000020 */
#define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
#define DSI_WPCR3_THSZERO6_Pos (6U)
#define DSI_WPCR3_THSZERO6_Msk (0x1UL << DSI_WPCR3_THSZERO6_Pos) /*!< 0x00000040 */
#define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
#define DSI_WPCR3_THSZERO7_Pos (7U)
#define DSI_WPCR3_THSZERO7_Msk (0x1UL << DSI_WPCR3_THSZERO7_Pos) /*!< 0x00000080 */
#define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
#define DSI_WPCR3_TLPXD_Pos (8U)
#define DSI_WPCR3_TLPXD_Msk (0xFFUL << DSI_WPCR3_TLPXD_Pos) /*!< 0x0000FF00 */
#define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */
#define DSI_WPCR3_TLPXD0_Pos (8U)
#define DSI_WPCR3_TLPXD0_Msk (0x1UL << DSI_WPCR3_TLPXD0_Pos) /*!< 0x00000100 */
#define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
#define DSI_WPCR3_TLPXD1_Pos (9U)
#define DSI_WPCR3_TLPXD1_Msk (0x1UL << DSI_WPCR3_TLPXD1_Pos) /*!< 0x00000200 */
#define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
#define DSI_WPCR3_TLPXD2_Pos (10U)
#define DSI_WPCR3_TLPXD2_Msk (0x1UL << DSI_WPCR3_TLPXD2_Pos) /*!< 0x00000400 */
#define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
#define DSI_WPCR3_TLPXD3_Pos (11U)
#define DSI_WPCR3_TLPXD3_Msk (0x1UL << DSI_WPCR3_TLPXD3_Pos) /*!< 0x00000800 */
#define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
#define DSI_WPCR3_TLPXD4_Pos (12U)
#define DSI_WPCR3_TLPXD4_Msk (0x1UL << DSI_WPCR3_TLPXD4_Pos) /*!< 0x00001000 */
#define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
#define DSI_WPCR3_TLPXD5_Pos (13U)
#define DSI_WPCR3_TLPXD5_Msk (0x1UL << DSI_WPCR3_TLPXD5_Pos) /*!< 0x00002000 */
#define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
#define DSI_WPCR3_TLPXD6_Pos (14U)
#define DSI_WPCR3_TLPXD6_Msk (0x1UL << DSI_WPCR3_TLPXD6_Pos) /*!< 0x00004000 */
#define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
#define DSI_WPCR3_TLPXD7_Pos (15U)
#define DSI_WPCR3_TLPXD7_Msk (0x1UL << DSI_WPCR3_TLPXD7_Pos) /*!< 0x00008000 */
#define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
#define DSI_WPCR3_THSEXIT_Pos (16U)
#define DSI_WPCR3_THSEXIT_Msk (0xFFUL << DSI_WPCR3_THSEXIT_Pos) /*!< 0x00FF0000 */
#define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */
#define DSI_WPCR3_THSEXIT0_Pos (16U)
#define DSI_WPCR3_THSEXIT0_Msk (0x1UL << DSI_WPCR3_THSEXIT0_Pos) /*!< 0x00010000 */
#define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
#define DSI_WPCR3_THSEXIT1_Pos (17U)
#define DSI_WPCR3_THSEXIT1_Msk (0x1UL << DSI_WPCR3_THSEXIT1_Pos) /*!< 0x00020000 */
#define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
#define DSI_WPCR3_THSEXIT2_Pos (18U)
#define DSI_WPCR3_THSEXIT2_Msk (0x1UL << DSI_WPCR3_THSEXIT2_Pos) /*!< 0x00040000 */
#define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
#define DSI_WPCR3_THSEXIT3_Pos (19U)
#define DSI_WPCR3_THSEXIT3_Msk (0x1UL << DSI_WPCR3_THSEXIT3_Pos) /*!< 0x00080000 */
#define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
#define DSI_WPCR3_THSEXIT4_Pos (20U)
#define DSI_WPCR3_THSEXIT4_Msk (0x1UL << DSI_WPCR3_THSEXIT4_Pos) /*!< 0x00100000 */
#define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
#define DSI_WPCR3_THSEXIT5_Pos (21U)
#define DSI_WPCR3_THSEXIT5_Msk (0x1UL << DSI_WPCR3_THSEXIT5_Pos) /*!< 0x00200000 */
#define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
#define DSI_WPCR3_THSEXIT6_Pos (22U)
#define DSI_WPCR3_THSEXIT6_Msk (0x1UL << DSI_WPCR3_THSEXIT6_Pos) /*!< 0x00400000 */
#define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
#define DSI_WPCR3_THSEXIT7_Pos (23U)
#define DSI_WPCR3_THSEXIT7_Msk (0x1UL << DSI_WPCR3_THSEXIT7_Pos) /*!< 0x00800000 */
#define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
#define DSI_WPCR3_TLPXC_Pos (24U)
#define DSI_WPCR3_TLPXC_Msk (0xFFUL << DSI_WPCR3_TLPXC_Pos) /*!< 0xFF000000 */
#define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */
#define DSI_WPCR3_TLPXC0_Pos (24U)
#define DSI_WPCR3_TLPXC0_Msk (0x1UL << DSI_WPCR3_TLPXC0_Pos) /*!< 0x01000000 */
#define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
#define DSI_WPCR3_TLPXC1_Pos (25U)
#define DSI_WPCR3_TLPXC1_Msk (0x1UL << DSI_WPCR3_TLPXC1_Pos) /*!< 0x02000000 */
#define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
#define DSI_WPCR3_TLPXC2_Pos (26U)
#define DSI_WPCR3_TLPXC2_Msk (0x1UL << DSI_WPCR3_TLPXC2_Pos) /*!< 0x04000000 */
#define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
#define DSI_WPCR3_TLPXC3_Pos (27U)
#define DSI_WPCR3_TLPXC3_Msk (0x1UL << DSI_WPCR3_TLPXC3_Pos) /*!< 0x08000000 */
#define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
#define DSI_WPCR3_TLPXC4_Pos (28U)
#define DSI_WPCR3_TLPXC4_Msk (0x1UL << DSI_WPCR3_TLPXC4_Pos) /*!< 0x10000000 */
#define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
#define DSI_WPCR3_TLPXC5_Pos (29U)
#define DSI_WPCR3_TLPXC5_Msk (0x1UL << DSI_WPCR3_TLPXC5_Pos) /*!< 0x20000000 */
#define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
#define DSI_WPCR3_TLPXC6_Pos (30U)
#define DSI_WPCR3_TLPXC6_Msk (0x1UL << DSI_WPCR3_TLPXC6_Pos) /*!< 0x40000000 */
#define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
#define DSI_WPCR3_TLPXC7_Pos (31U)
#define DSI_WPCR3_TLPXC7_Msk (0x1UL << DSI_WPCR3_TLPXC7_Pos) /*!< 0x80000000 */
#define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
/******************* Bit definition for DSI_WPCR4 register ***************/
#define DSI_WPCR4_TCLKPOST_Pos (0U)
#define DSI_WPCR4_TCLKPOST_Msk (0xFFUL << DSI_WPCR4_TCLKPOST_Pos) /*!< 0x000000FF */
#define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */
#define DSI_WPCR4_TCLKPOST0_Pos (0U)
#define DSI_WPCR4_TCLKPOST0_Msk (0x1UL << DSI_WPCR4_TCLKPOST0_Pos) /*!< 0x00000001 */
#define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
#define DSI_WPCR4_TCLKPOST1_Pos (1U)
#define DSI_WPCR4_TCLKPOST1_Msk (0x1UL << DSI_WPCR4_TCLKPOST1_Pos) /*!< 0x00000002 */
#define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
#define DSI_WPCR4_TCLKPOST2_Pos (2U)
#define DSI_WPCR4_TCLKPOST2_Msk (0x1UL << DSI_WPCR4_TCLKPOST2_Pos) /*!< 0x00000004 */
#define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
#define DSI_WPCR4_TCLKPOST3_Pos (3U)
#define DSI_WPCR4_TCLKPOST3_Msk (0x1UL << DSI_WPCR4_TCLKPOST3_Pos) /*!< 0x00000008 */
#define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
#define DSI_WPCR4_TCLKPOST4_Pos (4U)
#define DSI_WPCR4_TCLKPOST4_Msk (0x1UL << DSI_WPCR4_TCLKPOST4_Pos) /*!< 0x00000010 */
#define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
#define DSI_WPCR4_TCLKPOST5_Pos (5U)
#define DSI_WPCR4_TCLKPOST5_Msk (0x1UL << DSI_WPCR4_TCLKPOST5_Pos) /*!< 0x00000020 */
#define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
#define DSI_WPCR4_TCLKPOST6_Pos (6U)
#define DSI_WPCR4_TCLKPOST6_Msk (0x1UL << DSI_WPCR4_TCLKPOST6_Pos) /*!< 0x00000040 */
#define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
#define DSI_WPCR4_TCLKPOST7_Pos (7U)
#define DSI_WPCR4_TCLKPOST7_Msk (0x1UL << DSI_WPCR4_TCLKPOST7_Pos) /*!< 0x00000080 */
#define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
/******************* Bit definition for DSI_WRPCR register ***************/
#define DSI_WRPCR_PLLEN_Pos (0U)
#define DSI_WRPCR_PLLEN_Msk (0x1UL << DSI_WRPCR_PLLEN_Pos) /*!< 0x00000001 */
#define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk /*!< PLL Enable */
#define DSI_WRPCR_PLL_NDIV_Pos (2U)
#define DSI_WRPCR_PLL_NDIV_Msk (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos) /*!< 0x000001FC */
#define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk /*!< PLL Loop Division Factor */
#define DSI_WRPCR_PLL_NDIV0_Pos (2U)
#define DSI_WRPCR_PLL_NDIV0_Msk (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos) /*!< 0x00000004 */
#define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
#define DSI_WRPCR_PLL_NDIV1_Pos (3U)
#define DSI_WRPCR_PLL_NDIV1_Msk (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos) /*!< 0x00000008 */
#define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
#define DSI_WRPCR_PLL_NDIV2_Pos (4U)
#define DSI_WRPCR_PLL_NDIV2_Msk (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos) /*!< 0x00000010 */
#define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
#define DSI_WRPCR_PLL_NDIV3_Pos (5U)
#define DSI_WRPCR_PLL_NDIV3_Msk (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos) /*!< 0x00000020 */
#define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
#define DSI_WRPCR_PLL_NDIV4_Pos (6U)
#define DSI_WRPCR_PLL_NDIV4_Msk (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos) /*!< 0x00000040 */
#define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
#define DSI_WRPCR_PLL_NDIV5_Pos (7U)
#define DSI_WRPCR_PLL_NDIV5_Msk (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos) /*!< 0x00000080 */
#define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
#define DSI_WRPCR_PLL_NDIV6_Pos (8U)
#define DSI_WRPCR_PLL_NDIV6_Msk (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos) /*!< 0x00000100 */
#define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
#define DSI_WRPCR_PLL_IDF_Pos (11U)
#define DSI_WRPCR_PLL_IDF_Msk (0xFUL << DSI_WRPCR_PLL_IDF_Pos) /*!< 0x00007800 */
#define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk /*!< PLL Input Division Factor */
#define DSI_WRPCR_PLL_IDF0_Pos (11U)
#define DSI_WRPCR_PLL_IDF0_Msk (0x1UL << DSI_WRPCR_PLL_IDF0_Pos) /*!< 0x00000800 */
#define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
#define DSI_WRPCR_PLL_IDF1_Pos (12U)
#define DSI_WRPCR_PLL_IDF1_Msk (0x1UL << DSI_WRPCR_PLL_IDF1_Pos) /*!< 0x00001000 */
#define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
#define DSI_WRPCR_PLL_IDF2_Pos (13U)
#define DSI_WRPCR_PLL_IDF2_Msk (0x1UL << DSI_WRPCR_PLL_IDF2_Pos) /*!< 0x00002000 */
#define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
#define DSI_WRPCR_PLL_IDF3_Pos (14U)
#define DSI_WRPCR_PLL_IDF3_Msk (0x1UL << DSI_WRPCR_PLL_IDF3_Pos) /*!< 0x00004000 */
#define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
#define DSI_WRPCR_PLL_ODF_Pos (16U)
#define DSI_WRPCR_PLL_ODF_Msk (0x3UL << DSI_WRPCR_PLL_ODF_Pos) /*!< 0x00030000 */
#define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk /*!< PLL Output Division Factor */
#define DSI_WRPCR_PLL_ODF0_Pos (16U)
#define DSI_WRPCR_PLL_ODF0_Msk (0x1UL << DSI_WRPCR_PLL_ODF0_Pos) /*!< 0x00010000 */
#define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
#define DSI_WRPCR_PLL_ODF1_Pos (17U)
#define DSI_WRPCR_PLL_ODF1_Msk (0x1UL << DSI_WRPCR_PLL_ODF1_Pos) /*!< 0x00020000 */
#define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
#define DSI_WRPCR_REGEN_Pos (24U)
#define DSI_WRPCR_REGEN_Msk (0x1UL << DSI_WRPCR_REGEN_Pos) /*!< 0x01000000 */
#define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk /*!< Regulator Enable */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR1 register ******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos (1U)
#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos (2U)
#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos (3U)
#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos (4U)
#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos (5U)
#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos (6U)
#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos (7U)
#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos (8U)
#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos (9U)
#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos (10U)
#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos (11U)
#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos (12U)
#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos (13U)
#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos (14U)
#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos (16U)
#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos (17U)
#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos (18U)
#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos (20U)
#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos (21U)
#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos (22U)
#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos (24U)
#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos (29U)
#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos (30U)
#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM31_Pos (31U)
#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
#define EXTI_IMR1_IM_Pos (0U)
#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR1 register ******************/
#define EXTI_EMR1_EM0_Pos (0U)
#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos (1U)
#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos (2U)
#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos (3U)
#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos (4U)
#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos (5U)
#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos (6U)
#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos (7U)
#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos (8U)
#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos (9U)
#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos (10U)
#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos (11U)
#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos (12U)
#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos (13U)
#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos (14U)
#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos (15U)
#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos (16U)
#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos (17U)
#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos (18U)
#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM19_Pos (19U)
#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR1_EM20_Pos (20U)
#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos (21U)
#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos (22U)
#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos (24U)
#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos (26U)
#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos (27U)
#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos (28U)
#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM29_Pos (29U)
#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR1_EM30_Pos (30U)
#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
#define EXTI_EMR1_EM31_Pos (31U)
#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/****************** Bit definition for EXTI_RTSR1 register ******************/
#define EXTI_RTSR1_RT0_Pos (0U)
#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR1_RT1_Pos (1U)
#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR1_RT2_Pos (2U)
#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR1_RT3_Pos (3U)
#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR1_RT4_Pos (4U)
#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR1_RT5_Pos (5U)
#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR1_RT6_Pos (6U)
#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR1_RT7_Pos (7U)
#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR1_RT8_Pos (8U)
#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR1_RT9_Pos (9U)
#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR1_RT10_Pos (10U)
#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR1_RT11_Pos (11U)
#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR1_RT12_Pos (12U)
#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR1_RT13_Pos (13U)
#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR1_RT14_Pos (14U)
#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR1_RT15_Pos (15U)
#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR1_RT16_Pos (16U)
#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_RT18_Pos (18U)
#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR1_RT19_Pos (19U)
#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR1_RT20_Pos (20U)
#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR1_RT21_Pos (21U)
#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR1_RT22_Pos (22U)
#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_FTSR1 register ******************/
#define EXTI_FTSR1_FT0_Pos (0U)
#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR1_FT1_Pos (1U)
#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR1_FT2_Pos (2U)
#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR1_FT3_Pos (3U)
#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR1_FT4_Pos (4U)
#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR1_FT5_Pos (5U)
#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR1_FT6_Pos (6U)
#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR1_FT7_Pos (7U)
#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR1_FT8_Pos (8U)
#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR1_FT9_Pos (9U)
#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR1_FT10_Pos (10U)
#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR1_FT11_Pos (11U)
#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR1_FT12_Pos (12U)
#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR1_FT13_Pos (13U)
#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR1_FT14_Pos (14U)
#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR1_FT15_Pos (15U)
#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR1_FT16_Pos (16U)
#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR1_FT18_Pos (18U)
#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR1_FT19_Pos (19U)
#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR1_FT20_Pos (20U)
#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR1_FT21_Pos (21U)
#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR1_FT22_Pos (22U)
#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
/****************** Bit definition for EXTI_SWIER1 register *****************/
#define EXTI_SWIER1_SWI0_Pos (0U)
#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWI1_Pos (1U)
#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWI2_Pos (2U)
#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWI3_Pos (3U)
#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWI4_Pos (4U)
#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWI5_Pos (5U)
#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWI6_Pos (6U)
#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWI7_Pos (7U)
#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWI8_Pos (8U)
#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWI9_Pos (9U)
#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWI10_Pos (10U)
#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWI11_Pos (11U)
#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWI12_Pos (12U)
#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWI13_Pos (13U)
#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWI14_Pos (14U)
#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWI15_Pos (15U)
#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWI16_Pos (16U)
#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWI18_Pos (18U)
#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
#define EXTI_SWIER1_SWI19_Pos (19U)
#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWI20_Pos (20U)
#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWI21_Pos (21U)
#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER1_SWI22_Pos (22U)
#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
/******************* Bit definition for EXTI_PR1 register *******************/
#define EXTI_PR1_PIF0_Pos (0U)
#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
#define EXTI_PR1_PIF1_Pos (1U)
#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
#define EXTI_PR1_PIF2_Pos (2U)
#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
#define EXTI_PR1_PIF3_Pos (3U)
#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
#define EXTI_PR1_PIF4_Pos (4U)
#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
#define EXTI_PR1_PIF5_Pos (5U)
#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
#define EXTI_PR1_PIF6_Pos (6U)
#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
#define EXTI_PR1_PIF7_Pos (7U)
#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
#define EXTI_PR1_PIF8_Pos (8U)
#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
#define EXTI_PR1_PIF9_Pos (9U)
#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
#define EXTI_PR1_PIF10_Pos (10U)
#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
#define EXTI_PR1_PIF11_Pos (11U)
#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
#define EXTI_PR1_PIF12_Pos (12U)
#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
#define EXTI_PR1_PIF13_Pos (13U)
#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
#define EXTI_PR1_PIF14_Pos (14U)
#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
#define EXTI_PR1_PIF15_Pos (15U)
#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
#define EXTI_PR1_PIF16_Pos (16U)
#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
#define EXTI_PR1_PIF18_Pos (18U)
#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
#define EXTI_PR1_PIF19_Pos (19U)
#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR1_PIF20_Pos (20U)
#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR1_PIF21_Pos (21U)
#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR1_PIF22_Pos (22U)
#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
/******************* Bit definition for EXTI_IMR2 register ******************/
#define EXTI_IMR2_IM32_Pos (0U)
#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x17BUL << EXTI_IMR2_IM_Pos) /*!< 0x0000017B */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
#define EXTI_EMR2_EM32_Pos (0U)
#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
#define EXTI_EMR2_EM33_Pos (1U)
#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
#define EXTI_EMR2_EM35_Pos (3U)
#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x17BUL << EXTI_EMR2_EM_Pos) /*!< 0x0000017B */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT35_Pos (3U)
#define EXTI_RTSR2_RT35_Msk (0x1UL << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
#define EXTI_RTSR2_RT36_Pos (4U)
#define EXTI_RTSR2_RT36_Msk (0x1UL << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
#define EXTI_RTSR2_RT37_Pos (5U)
#define EXTI_RTSR2_RT37_Msk (0x1UL << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
#define EXTI_RTSR2_RT38_Pos (6U)
#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_FT35_Pos (3U)
#define EXTI_FTSR2_FT35_Msk (0x1UL << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
#define EXTI_FTSR2_FT36_Pos (4U)
#define EXTI_FTSR2_FT36_Msk (0x1UL << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
#define EXTI_FTSR2_FT37_Pos (5U)
#define EXTI_FTSR2_FT37_Msk (0x1UL << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
#define EXTI_FTSR2_FT38_Pos (6U)
#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWI35_Pos (3U)
#define EXTI_SWIER2_SWI35_Msk (0x1UL << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
#define EXTI_SWIER2_SWI36_Pos (4U)
#define EXTI_SWIER2_SWI36_Msk (0x1UL << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
#define EXTI_SWIER2_SWI37_Pos (5U)
#define EXTI_SWIER2_SWI37_Msk (0x1UL << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
#define EXTI_SWIER2_SWI38_Pos (6U)
#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PIF35_Pos (3U)
#define EXTI_PR2_PIF35_Msk (0x1UL << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
#define EXTI_PR2_PIF36_Pos (4U)
#define EXTI_PR2_PIF36_Msk (0x1UL << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
#define EXTI_PR2_PIF37_Pos (5U)
#define EXTI_PR2_PIF37_Msk (0x1UL << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
#define EXTI_PR2_PIF38_Pos (6U)
#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
#define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
#define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
#define FLASH_ACR_ICEN_Pos (9U)
#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
#define FLASH_ACR_DCEN_Pos (10U)
#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
#define FLASH_ACR_ICRST_Pos (11U)
#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
#define FLASH_ACR_DCRST_Pos (12U)
#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
#define FLASH_ACR_RUN_PD_Pos (13U)
#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
#define FLASH_ACR_SLEEP_PD_Pos (14U)
#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
/******************* Bits definition for FLASH_SR register ******************/
#define FLASH_SR_EOP_Pos (0U)
#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_OPERR_Pos (1U)
#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
#define FLASH_SR_PROGERR_Pos (3U)
#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
#define FLASH_SR_WRPERR_Pos (4U)
#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_PGAERR_Pos (5U)
#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
#define FLASH_SR_SIZERR_Pos (6U)
#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
#define FLASH_SR_PGSERR_Pos (7U)
#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_MISERR_Pos (8U)
#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
#define FLASH_SR_FASTERR_Pos (9U)
#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
#define FLASH_SR_RDERR_Pos (14U)
#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
#define FLASH_SR_OPTVERR_Pos (15U)
#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
#define FLASH_SR_BSY_Pos (16U)
#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
#define FLASH_SR_PEMPTY_Pos (17U)
#define FLASH_SR_PEMPTY_Msk (0x1UL << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */
#define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk
/******************* Bits definition for FLASH_CR register ******************/
#define FLASH_CR_PG_Pos (0U)
#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_PER_Pos (1U)
#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
#define FLASH_CR_PER FLASH_CR_PER_Msk
#define FLASH_CR_MER1_Pos (2U)
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
#define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_BKER_Pos (11U)
#define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
#define FLASH_CR_BKER FLASH_CR_BKER_Msk
#define FLASH_CR_MER2_Pos (15U)
#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
#define FLASH_CR_STRT FLASH_CR_STRT_Msk
#define FLASH_CR_OPTSTRT_Pos (17U)
#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
#define FLASH_CR_FSTPG_Pos (18U)
#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
#define FLASH_CR_EOPIE_Pos (24U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_ERRIE_Pos (25U)
#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
#define FLASH_CR_RDERRIE_Pos (26U)
#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
#define FLASH_CR_OBL_LAUNCH_Pos (27U)
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
#define FLASH_CR_OPTLOCK_Pos (30U)
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
#define FLASH_CR_LOCK_Pos (31U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
/******************* Bits definition for FLASH_ECCR register ***************/
#define FLASH_ECCR_ADDR_ECC_Pos (0U)
#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */
#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
#define FLASH_ECCR_BK_ECC_Pos (21U)
#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
#define FLASH_ECCR_SYSF_ECC_Pos (22U)
#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
#define FLASH_ECCR_ECCIE_Pos (24U)
#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
#define FLASH_ECCR_ECCC2_Pos (28U)
#define FLASH_ECCR_ECCC2_Msk (0x1UL << FLASH_ECCR_ECCC2_Pos) /*!< 0x10000000 */
#define FLASH_ECCR_ECCC2 FLASH_ECCR_ECCC2_Msk
#define FLASH_ECCR_ECCD2_Pos (29U)
#define FLASH_ECCR_ECCD2_Msk (0x1UL << FLASH_ECCR_ECCD2_Pos) /*!< 0x20000000 */
#define FLASH_ECCR_ECCD2 FLASH_ECCR_ECCD2_Msk
#define FLASH_ECCR_ECCC_Pos (30U)
#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
#define FLASH_ECCR_ECCD_Pos (31U)
#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
/******************* Bits definition for FLASH_OPTR register ***************/
#define FLASH_OPTR_RDP_Pos (0U)
#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
#define FLASH_OPTR_BOR_LEV_Pos (8U)
#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
#define FLASH_OPTR_nRST_STOP_Pos (12U)
#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
#define FLASH_OPTR_nRST_STDBY_Pos (13U)
#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
#define FLASH_OPTR_nRST_SHDW_Pos (14U)
#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
#define FLASH_OPTR_IWDG_SW_Pos (16U)
#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
#define FLASH_OPTR_IWDG_STOP_Pos (17U)
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
#define FLASH_OPTR_WWDG_SW_Pos (19U)
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
#define FLASH_OPTR_BFB2_Pos (20U)
#define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
#define FLASH_OPTR_DB1M_Pos (21U)
#define FLASH_OPTR_DB1M_Msk (0x1UL << FLASH_OPTR_DB1M_Pos) /*!< 0x00200000 */
#define FLASH_OPTR_DB1M FLASH_OPTR_DB1M_Msk
#define FLASH_OPTR_DBANK_Pos (22U)
#define FLASH_OPTR_DBANK_Msk (0x1UL << FLASH_OPTR_DBANK_Pos) /*!< 0x00400000 */
#define FLASH_OPTR_DBANK FLASH_OPTR_DBANK_Msk
#define FLASH_OPTR_nBOOT1_Pos (23U)
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
#define FLASH_OPTR_SRAM2_PE_Pos (24U)
#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
#define FLASH_OPTR_SRAM2_RST_Pos (25U)
#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
#define FLASH_OPTR_nSWBOOT0_Pos (26U)
#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
#define FLASH_OPTR_nBOOT0_Pos (27U)
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
/****************** Bits definition for FLASH_PCROP1SR register **********/
#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x1FFFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0001FFFF */
#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
/****************** Bits definition for FLASH_PCROP1ER register ***********/
#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
#define FLASH_PCROP1ER_PCROP1_END_Msk (0x1FFFFUL << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0001FFFF */
#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
/****************** Bits definition for FLASH_WRP1AR register ***************/
#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
/****************** Bits definition for FLASH_PCROP2SR register **********/
#define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
#define FLASH_PCROP2SR_PCROP2_STRT_Msk (0x1FFFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0001FFFF */
#define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
/****************** Bits definition for FLASH_PCROP2ER register ***********/
#define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
#define FLASH_PCROP2ER_PCROP2_END_Msk (0x1FFFFUL << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0001FFFF */
#define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
/****************** Bits definition for FLASH_WRP2AR register ***************/
#define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
#define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
#define FLASH_WRP2AR_WRP2A_END_Pos (16U)
#define FLASH_WRP2AR_WRP2A_END_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
/****************** Bits definition for FLASH_WRP2BR register ***************/
#define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
#define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
#define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
#define FLASH_WRP2BR_WRP2B_END_Pos (16U)
#define FLASH_WRP2BR_WRP2B_END_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
#define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
/****************** Bits definition for FLASH_CFGR register *****************/
#define FLASH_CFGR_LVEN_Pos (0U)
#define FLASH_CFGR_LVEN_Msk (0x1UL << FLASH_CFGR_LVEN_Pos) /*!< 0x00000001 */
#define FLASH_CFGR_LVEN FLASH_CFGR_LVEN_Msk /*!< Flash low voltage enable */
/******************************************************************************/
/* */
/* Flexible Memory Controller */
/* */
/******************************************************************************/
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
#define FMC_BCRx_MBKEN_Pos (0U)
#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCRx_MUXEN_Pos (1U)
#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCRx_MTYP_Pos (2U)
#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCRx_MWID_Pos (4U)
#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCRx_FACCEN_Pos (6U)
#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCRx_BURSTEN_Pos (8U)
#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCRx_WAITPOL_Pos (9U)
#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCRx_WAITCFG_Pos (11U)
#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCRx_WREN_Pos (12U)
#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
#define FMC_BCRx_WAITEN_Pos (13U)
#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCRx_EXTMOD_Pos (14U)
#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCRx_ASYNCWAIT_Pos (15U)
#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCRx_CPSIZE_Pos (16U)
#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCRx_CBURSTRW_Pos (19U)
#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
#define FMC_BCRx_NBLSET_Pos (22U)
#define FMC_BCRx_NBLSET_Msk (0x3UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00C00000 */
#define FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk /*!<Byte lane (NBL) setup */
#define FMC_BCRx_NBLSET_0 (0x1UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00500000 */
#define FMC_BCRx_NBLSET_1 (0x2UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00800000 */
/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
#define FMC_BTRx_ADDSET_Pos (0U)
#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTRx_ADDHLD_Pos (4U)
#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTRx_DATAST_Pos (8U)
#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTRx_BUSTURN_Pos (16U)
#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTRx_CLKDIV_Pos (20U)
#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTRx_DATLAT_Pos (24U)
#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTRx_ACCMOD_Pos (28U)
#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BTRx_DATAHLD_Pos (30U)
#define FMC_BTRx_DATAHLD_Msk (0x3UL << FMC_BTRx_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
#define FMC_BTRx_DATAHLD_0 (0x1UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BTRx_DATAHLD_1 (0x2UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
#define FMC_BWTRx_ADDSET_Pos (0U)
#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTRx_ADDHLD_Pos (4U)
#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTRx_DATAST_Pos (8U)
#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTRx_BUSTURN_Pos (16U)
#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BWTRx_ACCMOD_Pos (28U)
#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BWTRx_DATAHLD_Pos (30U)
#define FMC_BWTRx_DATAHLD_Msk (0x3UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
#define FMC_BWTRx_DATAHLD_0 (0x1UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BWTRx_DATAHLD_1 (0x2UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PCR register ********************/
#define FMC_PCR_PWAITEN_Pos (1U)
#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
#define FMC_PCR_PBKEN_Pos (2U)
#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
#define FMC_PCR_PTYP_Pos (3U)
#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
#define FMC_PCR_PWID_Pos (4U)
#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
#define FMC_PCR_ECCEN_Pos (6U)
#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
#define FMC_PCR_TCLR_Pos (9U)
#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
#define FMC_PCR_TAR_Pos (13U)
#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
#define FMC_PCR_ECCPS_Pos (17U)
#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
/******************* Bit definition for FMC_SR register ********************/
#define FMC_SR_IRS_Pos (0U)
#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
#define FMC_SR_ILS_Pos (1U)
#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
#define FMC_SR_IFS_Pos (2U)
#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
#define FMC_SR_IREN_Pos (3U)
#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
#define FMC_SR_ILEN_Pos (4U)
#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
#define FMC_SR_IFEN_Pos (5U)
#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
#define FMC_SR_FEMPT_Pos (6U)
#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
/****************** Bit definition for FMC_PMEM register ******************/
#define FMC_PMEM_MEMSET_Pos (0U)
#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
#define FMC_PMEM_MEMWAIT_Pos (8U)
#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
#define FMC_PMEM_MEMHOLD_Pos (16U)
#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
#define FMC_PMEM_MEMHIZ_Pos (24U)
#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PATT register *******************/
#define FMC_PATT_ATTSET_Pos (0U)
#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
#define FMC_PATT_ATTWAIT_Pos (8U)
#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
#define FMC_PATT_ATTHOLD_Pos (16U)
#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
#define FMC_PATT_ATTHIZ_Pos (24U)
#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_ECCR register *******************/
#define FMC_ECCR_ECC_Pos (0U)
#define FMC_ECCR_ECC_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
/******************************************************************************/
/* */
/* Graphic MMU (GFXMMU) */
/* */
/******************************************************************************/
/****************** Bits definition for GFXMMU_CR register ********************/
#define GFXMMU_CR_B0OIE_Pos (0U)
#define GFXMMU_CR_B0OIE_Msk (0x1UL << GFXMMU_CR_B0OIE_Pos) /*!< 0x00000001 */
#define GFXMMU_CR_B0OIE GFXMMU_CR_B0OIE_Msk /*!< Buffer 0 overflow interrupt enable */
#define GFXMMU_CR_B1OIE_Pos (1U)
#define GFXMMU_CR_B1OIE_Msk (0x1UL << GFXMMU_CR_B1OIE_Pos) /*!< 0x00000002 */
#define GFXMMU_CR_B1OIE GFXMMU_CR_B1OIE_Msk /*!< Buffer 1 overflow interrupt enable */
#define GFXMMU_CR_B2OIE_Pos (2U)
#define GFXMMU_CR_B2OIE_Msk (0x1UL << GFXMMU_CR_B2OIE_Pos) /*!< 0x00000004 */
#define GFXMMU_CR_B2OIE GFXMMU_CR_B2OIE_Msk /*!< Buffer 2 overflow interrupt enable */
#define GFXMMU_CR_B3OIE_Pos (3U)
#define GFXMMU_CR_B3OIE_Msk (0x1UL << GFXMMU_CR_B3OIE_Pos) /*!< 0x00000008 */
#define GFXMMU_CR_B3OIE GFXMMU_CR_B3OIE_Msk /*!< Buffer 3 overflow interrupt enable */
#define GFXMMU_CR_AMEIE_Pos (4U)
#define GFXMMU_CR_AMEIE_Msk (0x1UL << GFXMMU_CR_AMEIE_Pos) /*!< 0x00000010 */
#define GFXMMU_CR_AMEIE GFXMMU_CR_AMEIE_Msk /*!< AHB master error interrupt enable */
#define GFXMMU_CR_192BM_Pos (6U)
#define GFXMMU_CR_192BM_Msk (0x1UL << GFXMMU_CR_192BM_Pos) /*!< 0x00000040 */
#define GFXMMU_CR_192BM GFXMMU_CR_192BM_Msk /*!< 192 block mode */
/****************** Bits definition for GFXMMU_SR register ********************/
#define GFXMMU_SR_B0OF_Pos (0U)
#define GFXMMU_SR_B0OF_Msk (0x1UL << GFXMMU_SR_B0OF_Pos) /*!< 0x00000001 */
#define GFXMMU_SR_B0OF GFXMMU_SR_B0OF_Msk /*!< Buffer 0 overflow flag */
#define GFXMMU_SR_B1OF_Pos (1U)
#define GFXMMU_SR_B1OF_Msk (0x1UL << GFXMMU_SR_B1OF_Pos) /*!< 0x00000002 */
#define GFXMMU_SR_B1OF GFXMMU_SR_B1OF_Msk /*!< Buffer 1 overflow flag */
#define GFXMMU_SR_B2OF_Pos (2U)
#define GFXMMU_SR_B2OF_Msk (0x1UL << GFXMMU_SR_B2OF_Pos) /*!< 0x00000004 */
#define GFXMMU_SR_B2OF GFXMMU_SR_B2OF_Msk /*!< Buffer 2 overflow flag */
#define GFXMMU_SR_B3OF_Pos (3U)
#define GFXMMU_SR_B3OF_Msk (0x1UL << GFXMMU_SR_B3OF_Pos) /*!< 0x00000008 */
#define GFXMMU_SR_B3OF GFXMMU_SR_B3OF_Msk /*!< Buffer 3 overflow flag */
#define GFXMMU_SR_AMEF_Pos (4U)
#define GFXMMU_SR_AMEF_Msk (0x1UL << GFXMMU_SR_AMEF_Pos) /*!< 0x00000010 */
#define GFXMMU_SR_AMEF GFXMMU_SR_AMEF_Msk /*!< AHB master error flag */
/****************** Bits definition for GFXMMU_FCR register *******************/
#define GFXMMU_FCR_CB0OF_Pos (0U)
#define GFXMMU_FCR_CB0OF_Msk (0x1UL << GFXMMU_FCR_CB0OF_Pos) /*!< 0x00000001 */
#define GFXMMU_FCR_CB0OF GFXMMU_FCR_CB0OF_Msk /*!< Clear buffer 0 overflow flag */
#define GFXMMU_FCR_CB1OF_Pos (1U)
#define GFXMMU_FCR_CB1OF_Msk (0x1UL << GFXMMU_FCR_CB1OF_Pos) /*!< 0x00000002 */
#define GFXMMU_FCR_CB1OF GFXMMU_FCR_CB1OF_Msk /*!< Clear buffer 1 overflow flag */
#define GFXMMU_FCR_CB2OF_Pos (2U)
#define GFXMMU_FCR_CB2OF_Msk (0x1UL << GFXMMU_FCR_CB2OF_Pos) /*!< 0x00000004 */
#define GFXMMU_FCR_CB2OF GFXMMU_FCR_CB2OF_Msk /*!< Clear buffer 2 overflow flag */
#define GFXMMU_FCR_CB3OF_Pos (3U)
#define GFXMMU_FCR_CB3OF_Msk (0x1UL << GFXMMU_FCR_CB3OF_Pos) /*!< 0x00000008 */
#define GFXMMU_FCR_CB3OF GFXMMU_FCR_CB3OF_Msk /*!< Clear buffer 3 overflow flag */
#define GFXMMU_FCR_CAMEF_Pos (4U)
#define GFXMMU_FCR_CAMEF_Msk (0x1UL << GFXMMU_FCR_CAMEF_Pos) /*!< 0x00000010 */
#define GFXMMU_FCR_CAMEF GFXMMU_FCR_CAMEF_Msk /*!< Clear AHB master error flag */
/****************** Bits definition for GFXMMU_DVR register *******************/
#define GFXMMU_DVR_DV_Pos (0U)
#define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_DVR_DV GFXMMU_DVR_DV_Msk /*!< DV[31:0] bits (Default value) */
/****************** Bits definition for GFXMMU_B0CR register ******************/
#define GFXMMU_B0CR_PBO_Pos (4U)
#define GFXMMU_B0CR_PBO_Msk (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos) /*!< 0x007FFFF0 */
#define GFXMMU_B0CR_PBO GFXMMU_B0CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B0CR_PBBA_Pos (23U)
#define GFXMMU_B0CR_PBBA_Msk (0x1FFUL << GFXMMU_B0CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B0CR_PBBA GFXMMU_B0CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_B1CR register ******************/
#define GFXMMU_B1CR_PBO_Pos (4U)
#define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
#define GFXMMU_B1CR_PBO GFXMMU_B1CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B1CR_PBBA_Pos (23U)
#define GFXMMU_B1CR_PBBA_Msk (0x1FFUL << GFXMMU_B1CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B1CR_PBBA GFXMMU_B1CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_B2CR register ******************/
#define GFXMMU_B2CR_PBO_Pos (4U)
#define GFXMMU_B2CR_PBO_Msk (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos) /*!< 0x007FFFF0 */
#define GFXMMU_B2CR_PBO GFXMMU_B2CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B2CR_PBBA_Pos (23U)
#define GFXMMU_B2CR_PBBA_Msk (0x1FFUL << GFXMMU_B2CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B2CR_PBBA GFXMMU_B2CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_B3CR register ******************/
#define GFXMMU_B3CR_PBO_Pos (4U)
#define GFXMMU_B3CR_PBO_Msk (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos) /*!< 0x007FFFF0 */
#define GFXMMU_B3CR_PBO GFXMMU_B3CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B3CR_PBBA_Pos (23U)
#define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
#define GFXMMU_LUTxL_EN GFXMMU_LUTxL_EN_Msk /*!< Enable */
#define GFXMMU_LUTxL_FVB_Pos (8U)
#define GFXMMU_LUTxL_FVB_Msk (0xFFUL << GFXMMU_LUTxL_FVB_Pos) /*!< 0x0000FF00 */
#define GFXMMU_LUTxL_FVB GFXMMU_LUTxL_FVB_Msk /*!< FVB[7:0] bits (First visible block) */
#define GFXMMU_LUTxL_LVB_Pos (16U)
#define GFXMMU_LUTxL_LVB_Msk (0xFFUL << GFXMMU_LUTxL_LVB_Pos) /*!< 0x00FF0000 */
#define GFXMMU_LUTxL_LVB GFXMMU_LUTxL_LVB_Msk /*!< LVB[7:0] bits (Last visible block) */
/****************** Bits definition for GFXMMU_LUTxH register *****************/
#define GFXMMU_LUTxH_LO_Pos (4U)
#define GFXMMU_LUTxH_LO_Msk (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos) /*!< 0x003FFFF0 */
#define GFXMMU_LUTxH_LO GFXMMU_LUTxH_LO_Msk /*!< LO[21:4] bits (Line offset) */
/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODE0_Pos (0U)
#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos (2U)
#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos (4U)
#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos (6U)
#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos (8U)
#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos (10U)
#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos (12U)
#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos (14U)
#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos (16U)
#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos (18U)
#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos (20U)
#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos (22U)
#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos (24U)
#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos (26U)
#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos (28U)
#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos (30U)
#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPD0_Pos (0U)
#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos (2U)
#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos (4U)
#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos (6U)
#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos (8U)
#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos (10U)
#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos (12U)
#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos (14U)
#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos (16U)
#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos (18U)
#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos (20U)
#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */