Release v1.0.2
diff --git a/Include/stm32l552xx.h b/Include/stm32l552xx.h index 82f3342..79da587 100644 --- a/Include/stm32l552xx.h +++ b/Include/stm32l552xx.h
@@ -444,7 +444,7 @@ } DFSDM_Channel_TypeDef; /** - * @brief Debug MCU - TODO review for STM32L5 to be done + * @brief Debug MCU */ typedef struct { @@ -452,7 +452,7 @@ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ } DBGMCU_TypeDef; /** @@ -1669,22 +1669,88 @@ #define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) #define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) -/* Debug MCU registers base address */ +/*!< Debug MCU registers base address */ #define DBGMCU_BASE (0xE0044000UL) #define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ #define UID_BASE (0x0BFA0590UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x0BFA05E0UL) /*!< Flash size data register base address */ -/* Internal Flash size */ +/*!< Internal Flash size */ #define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x80000U : \ ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x80000U : \ (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x0FFFU)) << 10U))) -/* OTP Area */ +/*!< OTP Area */ #define OTP_BASE (0x0BFA0000UL) #define OTP_SIZE (0x200U) +/*!< Bootloader Area */ +#define BL_ID_ADDR (0x0BF97FFEUL) /*!< Bootloader ID address */ +#define BL_ID (*(uint8_t*)BL_ID_ADDR) /*!< Bootloader ID */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF97F40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF97FFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x0BF97F40UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL90; /*!< RSSLIB Bootloader ID90 Close and exit HDP Address offset: 0x20 */ + __IM uint32_t Reserved2; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL91; /*!< RSSLIB Bootloader ID91 Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + /** @} */ /* End of group STM32L5xx_Peripheral_peripheralAddr */ @@ -4510,21 +4576,21 @@ #define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk /******************** Bit definition for DBGMCU_APB2FZ register ************/ -#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U) -#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */ -#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U) -#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */ -#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U) -#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */ -#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U) -#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */ -#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U) -#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ -#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk /******************************************************************************/ /* */ @@ -16294,13 +16360,11 @@ /****************** Bit definition for SYSCFG_RSSCMDR register **************/ #define SYSCFG_RSSCMDR_RSSCMD_Pos (0U) -#if defined(USE_CUT2_0) #define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ -#else -#define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x000000FF */ -#endif #define SYSCFG_RSSCMDR_RSSCMD SYSCFG_RSSCMDR_RSSCMD_Msk /*!< RSS commands */ +#define SYSCFG_RSSCMDR_RSSCMD_BOOTLOADER ((uint16_t)0x01C0U) + /*****************************************************************************/ /* */ /* Global TrustZone Control */
diff --git a/Include/stm32l562xx.h b/Include/stm32l562xx.h index 71ac086..0e730d6 100644 --- a/Include/stm32l562xx.h +++ b/Include/stm32l562xx.h
@@ -478,7 +478,7 @@ } DFSDM_Channel_TypeDef; /** - * @brief Debug MCU - TODO review for STM32L5 to be done + * @brief Debug MCU */ typedef struct { @@ -486,7 +486,7 @@ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ } DBGMCU_TypeDef; /** @@ -1757,22 +1757,88 @@ #define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) #define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) -/* Debug MCU registers base address */ +/*!< Debug MCU registers base address */ #define DBGMCU_BASE (0xE0044000UL) #define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ #define UID_BASE (0x0BFA0590UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x0BFA05E0UL) /*!< Flash size data register base address */ -/* Internal Flash size */ +/*!< Internal Flash size */ #define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x80000U : \ ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x80000U : \ (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x0FFFU)) << 10U))) -/* OTP Area */ +/*!< OTP Area */ #define OTP_BASE (0x0BFA0000UL) #define OTP_SIZE (0x200U) +/*!< Bootloader Area */ +#define BL_ID_ADDR (0x0BF97FFEUL) /*!< Bootloader ID address */ +#define BL_ID (*(uint8_t*)BL_ID_ADDR) /*!< Bootloader ID */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF97F40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF97FFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x0BF97F40UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL90; /*!< RSSLIB Bootloader ID90 Close and exit HDP Address offset: 0x20 */ + __IM uint32_t Reserved2; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP_BL91; /*!< RSSLIB Bootloader ID91 Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + /** @} */ /* End of group STM32L5xx_Peripheral_peripheralAddr */ @@ -4842,21 +4908,21 @@ #define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk /******************** Bit definition for DBGMCU_APB2FZ register ************/ -#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U) -#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */ -#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U) -#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */ -#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U) -#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */ -#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U) -#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */ -#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk -#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U) -#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ -#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) +#define DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */ +#define DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */ +#define DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */ +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk /******************************************************************************/ /* */ @@ -17033,13 +17099,11 @@ /****************** Bit definition for SYSCFG_RSSCMDR register **************/ #define SYSCFG_RSSCMDR_RSSCMD_Pos (0U) -#if defined(USE_CUT2_0) #define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ -#else -#define SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) /*!< 0x000000FF */ -#endif #define SYSCFG_RSSCMDR_RSSCMD SYSCFG_RSSCMDR_RSSCMD_Msk /*!< RSS commands */ +#define SYSCFG_RSSCMDR_RSSCMD_BOOTLOADER ((uint16_t)0x01C0U) + /*****************************************************************************/ /* */ /* Global TrustZone Control */
diff --git a/Include/stm32l5xx.h b/Include/stm32l5xx.h index f8415bf..7eab4c7 100644 --- a/Include/stm32l5xx.h +++ b/Include/stm32l5xx.h
@@ -79,7 +79,7 @@ */ #define __STM32L5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32L5_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define __STM32L5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32L5_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ #define __STM32L5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32L5_CMSIS_VERSION ((__STM32L5_CMSIS_VERSION_MAIN << 24U)\ |(__STM32L5_CMSIS_VERSION_SUB1 << 16U)\
diff --git a/README.md b/README.md index a4494db..9c1244a 100644 --- a/README.md +++ b/README.md
@@ -26,10 +26,11 @@ CMSIS Device L5 | CMSIS Core | Was delivered in the full MCU package --------------- | ---------- | ------------------------------------- Tag v1.0.0 | Tag v5.4.0_cm33 | Tag v1.1.0 +Tag v1.0.2 | Tag v5.4.0_cm33 | Tag v1.2.0 The full **STM32CubeL5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL5). ## Troubleshooting -If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_l5/issues/new). +If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_l5/issues/new/choose). For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
diff --git a/Release_Notes.html b/Release_Notes.html index 13f63b1..b64cc4b 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
@@ -37,10 +37,10 @@ <p>This driver is composed of the descriptions of the registers under “Include” directory.</p> <p>Various template file are provided to easily build an application. They can be adapted to fit applications requirements.</p> <ul> -<li>Include/Templates/partition_stm32l552xx.h and partition_stm32l562xx.h contain a default Secure Attribute Unit (SAU) set up from SystemInit() for secure application when the security is enabled (TZEN=1).</li> -<li>Source/Templates/system_stm32l5xx.c contains the initialization code referred as SystemInit() when there is no security enabled (TZEN=0).</li> -<li>Source/Templates/system_stm32l5xx_s.c contains the initialization code referred as SystemInit() for secure application when the security is enabled (TZEN=1).</li> -<li>Source/Templates/system_stm32l5xx_ns.c contains the initialization code referred as SystemInit() for non-secure application when the security is enabled (TZEN=1).</li> +<li>Include/Templates/partition_stm32l552xx.h and partition_stm32l562xx.h contain a default Secure Attribute Unit (SAU) set up from SystemInit() for secure application when the TrustZone-M security is enabled (TZEN=1).</li> +<li>Source/Templates/system_stm32l5xx.c contains the initialization code referred as SystemInit() when there is no TrustZone-M security enabled (TZEN=0).</li> +<li>Source/Templates/system_stm32l5xx_s.c contains the initialization code referred as SystemInit() for secure application when the TrustZone-M security is enabled (TZEN=1).</li> +<li>Source/Templates/system_stm32l5xx_ns.c contains the initialization code referred as SystemInit() for non-secure application when the TrustZone-M security is enabled (TZEN=1).</li> <li>Startup files are provided as example for IAR, KEIL and STM32CubeIDE.</li> <li>Linker files are provided as example for IAR, KEIL and STM32CubeIDE.</li> </ul> @@ -48,11 +48,77 @@ <div class="col-sm-12 col-lg-8"> <h1 id="update-history">Update History</h1> <div class="collapse"> -<input type="checkbox" id="collapse-section1" checked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 13-December-2019</strong></label> +<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.0.2 / 12-February-2020</strong></label> <div> <h2 id="main-changes">Main Changes</h2> -<p><strong>First release</strong></p> +<p><strong>Third release</strong></p> <h2 id="contents">Contents</h2> +<p>Third official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p> +<ul> +<li>stm32l552xx.h and stm32l562xx.h updates +<ul> +<li>Add root secure services library (RSSLIB) definitions</li> +<li>Add bootloader id address</li> +<li>Align DBGMCU_APB2FZR register and bits definitions with RM0438</li> +</ul></li> +</ul> +<h2 id="notes">Notes</h2> +<p>Reminder:</p> +<ul> +<li>When TrustZone is enabled in the system (Flash option bit TZEN=1) +<ul> +<li>template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core).</li> +<li>default Security Attribute Unit (SAU) configuration in the partition_stm32l552xx.h and partition_stm32l562xx.h: +<ul> +<li>SAU region 0: 0x0C03E000-0x0C03FFFF (Secure, Non-Secure Callable)</li> +<li>SAU region 1: 0x08040000-0x0807FFFF (Non-Secure FLASH Bank2 (256 Kbytes))</li> +<li>SAU region 2: 0x20018000-0x2003FFFF (Non-Secure RAM (2nd half SRAM1 + SRAM2 (160 Kbytes)))</li> +<li>SAU region 3: 0x40000000-0x4FFFFFFF (Non-Secure Peripheral mapped memory)</li> +<li>SAU region 4: 0x60000000-0x9FFFFFFF (Non-Secure external memories)</li> +<li>SAU region 5: 0x0BF90000-0x0BFA8FFF (Non-Secure System memory)</li> +</ul></li> +</ul></li> +</ul> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section2" unchecked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.0.1 / 22-January-2020</strong></label> +<div> +<h2 id="main-changes-1">Main Changes</h2> +<p><strong>Second release</strong></p> +<h2 id="contents-1">Contents</h2> +<p>Second official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p> +<ul> +<li>Templates system_stm32l5xx.c, system_stm32l5xx_s.c and system_stm32l5xx_ns.c +<ul> +<li>Add vector table relocation capability with conditional USER_VECT_TAB_ADDRESS</li> +</ul></li> +</ul> +<h2 id="notes-1">Notes</h2> +<p>Reminder:</p> +<ul> +<li>When TrustZone is enabled in the system (Flash option bit TZEN=1) +<ul> +<li>template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core).</li> +<li>default Security Attribute Unit (SAU) configuration in the partition_stm32l552xx.h and partition_stm32l562xx.h: +<ul> +<li>SAU region 0: 0x0C03E000-0x0C03FFFF (Secure, Non-Secure Callable)</li> +<li>SAU region 1: 0x08040000-0x0807FFFF (Non-Secure FLASH Bank2 (256 Kbytes))</li> +<li>SAU region 2: 0x20018000-0x2003FFFF (Non-Secure RAM (2nd half SRAM1 + SRAM2 (160 Kbytes)))</li> +<li>SAU region 3: 0x40000000-0x4FFFFFFF (Non-Secure Peripheral mapped memory)</li> +<li>SAU region 4: 0x60000000-0x9FFFFFFF (Non-Secure external memories)</li> +<li>SAU region 5: 0x0BF90000-0x0BFA8FFF (Non-Secure System memory)</li> +</ul></li> +</ul></li> +</ul> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section1" unchecked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 13-December-2019</strong></label> +<div> +<h2 id="main-changes-2">Main Changes</h2> +<p><strong>First release</strong></p> +<h2 id="contents-2">Contents</h2> <p>First official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p> <ul> <li>Templates @@ -70,7 +136,7 @@ <li>Linker files for 256 and 512 Kbytes Flash device configurations</li> </ul></li> </ul> -<h2 id="notes">Notes</h2> +<h2 id="notes-2">Notes</h2> <p>When TrustZone is enabled in the system (Flash option bit TZEN=1), template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core)</p> </div> </div>
diff --git a/Source/Templates/system_stm32l5xx.c b/Source/Templates/system_stm32l5xx.c index 9c70c55..c311a3b 100644 --- a/Source/Templates/system_stm32l5xx.c +++ b/Source/Templates/system_stm32l5xx.c
@@ -91,7 +91,7 @@ * @{ */ -/** @addtogroup STM32L5xx_system +/** @addtogroup STM32L5xx_System * @{ */ @@ -101,18 +101,6 @@ #include "stm32l5xx.h" -#if !defined (HSE_VALUE) - #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (MSI_VALUE) - #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - /** * @} */ @@ -129,12 +117,43 @@ * @{ */ -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ + +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + /******************************************************************************/ /** * @} @@ -189,15 +208,15 @@ void SystemInit(void) { + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#endif + /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ #endif - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#endif } /**
diff --git a/Source/Templates/system_stm32l5xx_ns.c b/Source/Templates/system_stm32l5xx_ns.c index c8f9098..4129c41 100644 --- a/Source/Templates/system_stm32l5xx_ns.c +++ b/Source/Templates/system_stm32l5xx_ns.c
@@ -4,13 +4,13 @@ * @author MCD Application Team * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File * to be used in non-secure application when the system implements - * the security. + * the TrustZone-M security. * * This file provides two functions and one global variable to be called from * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l5xx.s" file. + * - SystemInit(): This function is called at non-secure startup before + * branch to non-secure main program. + * This call is made inside the "startup_stm32l5xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick @@ -21,60 +21,12 @@ * during program execution. * * After each device reset the MSI (4 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32l5xx_s" file, to - * configure the system clock before to branch to main program. + * Then SystemInit() function is called, in "startup_stm32l5xx.s" file, to + * configure the system clock before to branch to main secure program. + * Later, when non-secure SystemInit() function is called, in "startup_stm32l5xx.s" + * file, the system clock may have been updated from reset value by the main + * secure program. * - * This file configures the system clock as follows: - *============================================================================= - *----------------------------------------------------------------------------- - * System Clock source | MSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * PLL_SRC | No clock - *----------------------------------------------------------------------------- - * PLL_M | 1 - *----------------------------------------------------------------------------- - * PLL_N | 8 - *----------------------------------------------------------------------------- - * PLL_P | 7 - *----------------------------------------------------------------------------- - * PLL_Q | 2 - *----------------------------------------------------------------------------- - * PLL_R | 2 - *----------------------------------------------------------------------------- - * PLLSAI1_SRC | NA - *----------------------------------------------------------------------------- - * PLLSAI1_M | NA - *----------------------------------------------------------------------------- - * PLLSAI1_N | NA - *----------------------------------------------------------------------------- - * PLLSAI1_P | NA - *----------------------------------------------------------------------------- - * PLLSAI1_Q | NA - *----------------------------------------------------------------------------- - * PLLSAI1_R | NA - *----------------------------------------------------------------------------- - * PLLSAI2_SRC | NA - *----------------------------------------------------------------------------- - * PLLSAI2_M | NA - *----------------------------------------------------------------------------- - * PLLSAI2_N | NA - *----------------------------------------------------------------------------- - * PLLSAI2_P | NA - *----------------------------------------------------------------------------- - * Require 48MHz for USB FS, | Disabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= ****************************************************************************** * @attention * @@ -131,6 +83,32 @@ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ + +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM1_BASE_NS /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00018000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE_NS /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00040000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ /** * @} */ @@ -184,7 +162,12 @@ void SystemInit(void) { - /* Nothing done in non-secure */ + /* Vector table location and FPU setup done by secure application */ + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#endif /* Non-secure main application shall call SystemCoreClockUpdate() to update */ /* the SystemCoreClock variable to insure non-secure application relies on */
diff --git a/Source/Templates/system_stm32l5xx_s.c b/Source/Templates/system_stm32l5xx_s.c index d08b594..96d2c41 100644 --- a/Source/Templates/system_stm32l5xx_s.c +++ b/Source/Templates/system_stm32l5xx_s.c
@@ -4,13 +4,13 @@ * @author MCD Application Team * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File * to be used in secure application when the system implements - * the security. + * the TrustZone-M security. * * This file provides two functions and one global variable to be called from * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l5xx.s" file. + * - SystemInit(): This function is called at secure startup just after reset + * and before branch to secure main program. + * This call is made inside the "startup_stm32l5xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick @@ -31,7 +31,7 @@ * Then SystemInit() function is called, in "startup_stm32l5xx.s" file, to * configure the system clock before to branch to main program. * - * This file configures the system clock as follows: + * This file insures the system clock as follows: *============================================================================= *----------------------------------------------------------------------------- * System Clock source | MSI @@ -145,12 +145,31 @@ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ + +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM1_BASE_S /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE_S /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + /******************************************************************************/ /** * @} @@ -208,18 +227,17 @@ /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */ TZ_SAU_Setup(); + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; +#endif + /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ #endif - - /* Configure the Vector Table location add offset address ------------------*/ - /* Secure memory space */ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE_S | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#endif } /**