Release v1.10.0
diff --git a/Include/stm32wb10xx.h b/Include/stm32wb10xx.h
index 063adf3..488328f 100644
--- a/Include/stm32wb10xx.h
+++ b/Include/stm32wb10xx.h
@@ -380,7 +380,7 @@
__IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
- __IO uint32_t SMPSCR; /*!< RCC SMPS step-down converter control register, Address offset: 0x24 */
+uint32_t RESERVED11; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */
@@ -413,7 +413,7 @@
__IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
__IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
-uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
+uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
__IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
__IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
__IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
@@ -755,10 +755,10 @@
/*!< Memory, OTP and Option bytes */
/* Base addresses */
-#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 0x1FFF787F) */
-#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 - 0x1FFF787F) */
+#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 12 KB) base address */
#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
@@ -771,14 +771,14 @@
#define SRAM2B_SIZE 0x00001000UL /*!< SRAM2b default size : 4 KB */
/* End addresses */
-#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 0x20002FFF) */
-#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */
-#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 0x20038FFF) */
+#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 - 0x20002FFF) */
+#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */
+#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 - 0x20038FFF) */
-#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
@@ -1086,7 +1086,7 @@
#define ADC_CFGR1_ALIGN_Pos (5U)
#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR1_EXTSEL_Pos (6U)
#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
@@ -1136,7 +1136,7 @@
#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
-/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec accross STM32WB serie */
+/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec across STM32WB series */
#define ADC_CFGR_DMAEN_Pos ADC_CFGR1_DMAEN_Pos
#define ADC_CFGR_DMAEN_Msk ADC_CFGR1_DMAEN_Msk
#define ADC_CFGR_DMAEN ADC_CFGR1_DMAEN
@@ -1477,7 +1477,7 @@
#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */
#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */
-/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec accross STM32WB serie */
+/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec across STM32WB series */
#define ADC_DR_RDATA_Pos ADC_DR_DATA_Pos
#define ADC_DR_RDATA_Msk ADC_DR_DATA_Msk
#define ADC_DR_RDATA ADC_DR_DATA
@@ -3040,12 +3040,12 @@
/* Arithmetic addition output data */
#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Arithmetic substraction input data */
+/* Arithmetic subtraction input data */
#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
-/* Arithmetic substraction output data */
+/* Arithmetic subtraction output data */
#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Arithmetic multiplication input data */
@@ -3081,13 +3081,13 @@
/* Modular inversion output data */
#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Modular substraction input data */
+/* Modular subtraction input data */
#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
-/* Modular substraction output data */
+/* Modular subtraction output data */
#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Montgomery multiplication input data */
@@ -5498,13 +5498,6 @@
#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Internal wakeup interrupt flag */
/******************** Bit definition for PWR_SR2 register ********************/
-#define PWR_SR2_SMPSBF_Pos (0U)
-#define PWR_SR2_SMPSBF_Msk (0x1UL << PWR_SR2_SMPSBF_Pos) /*!< 0x00000001 */
-#define PWR_SR2_SMPSBF PWR_SR2_SMPSBF_Msk /*!< SMPS step down converter in operating mode bypass flag */
-#define PWR_SR2_SMPSF_Pos (1U)
-#define PWR_SR2_SMPSF_Msk (0x1UL << PWR_SR2_SMPSF_Pos) /*!< 0x00000002 */
-#define PWR_SR2_SMPSF PWR_SR2_SMPSF_Msk /*!< SMPS step down converter in operating mode step down flag */
-
#define PWR_SR2_REGLPS_Pos (8U)
#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regulator started */
@@ -5531,10 +5524,6 @@
#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Pin 4 [Flag 3] */
-#define PWR_SCR_CSMPSFBF_Pos (7U)
-#define PWR_SCR_CSMPSFBF_Msk (0x1UL << PWR_SCR_CSMPSFBF_Pos) /*!< 0x00000080 */
-#define PWR_SCR_CSMPSFBF PWR_SCR_CSMPSFBF_Msk /*!< Clear SMPS Step Down converter forced in bypass mode interrupt flag */
-
#define PWR_SCR_CBORHF_Pos (8U)
#define PWR_SCR_CBORHF_Msk (0x1UL << PWR_SCR_CBORHF_Pos) /*!< 0x00000100 */
#define PWR_SCR_CBORHF PWR_SCR_CBORHF_Msk /*!< Clear BORH interrupt flag */
@@ -5554,30 +5543,6 @@
#define PWR_SCR_CC2HF_Msk (0x1UL << PWR_SCR_CC2HF_Pos) /*!< 0x00004000 */
#define PWR_SCR_CC2HF PWR_SCR_CC2HF_Msk /*!< Clear CPU2 Hold interrupt flag */
-/******************** Bit definition for PWR_CR5 register ********************/
-#define PWR_CR5_SMPSVOS_Pos (0U)
-#define PWR_CR5_SMPSVOS_Msk (0xFUL << PWR_CR5_SMPSVOS_Pos) /*!< 0x0000000F */
-#define PWR_CR5_SMPSVOS PWR_CR5_SMPSVOS_Msk /*!< SMPS step down converter voltage output scaling voltage level */
-#define PWR_CR5_SMPSVOS_0 (0x01U << PWR_CR5_SMPSVOS_Pos) /*!< 0x00000001 */
-#define PWR_CR5_SMPSVOS_1 (0x02U << PWR_CR5_SMPSVOS_Pos) /*!< 0x00000002 */
-#define PWR_CR5_SMPSVOS_2 (0x04U << PWR_CR5_SMPSVOS_Pos) /*!< 0x00000004 */
-#define PWR_CR5_SMPSVOS_3 (0x08U << PWR_CR5_SMPSVOS_Pos) /*!< 0x00000008 */
-
-#define PWR_CR5_SMPSSC_Pos (4U)
-#define PWR_CR5_SMPSSC_Msk (0x7UL << PWR_CR5_SMPSSC_Pos) /*!< 0x00000070 */
-#define PWR_CR5_SMPSSC PWR_CR5_SMPSSC_Msk /*!< SMPS step down converter supply startup current selection */
-#define PWR_CR5_SMPSSC_0 (0x01U << PWR_CR5_SMPSSC_Pos) /*!< 0x00000010 */
-#define PWR_CR5_SMPSSC_1 (0x02U << PWR_CR5_SMPSSC_Pos) /*!< 0x00000020 */
-#define PWR_CR5_SMPSSC_2 (0x04U << PWR_CR5_SMPSSC_Pos) /*!< 0x00000040 */
-
-#define PWR_CR5_BORHC_Pos (8U)
-#define PWR_CR5_BORHC_Msk (0x1UL << PWR_CR5_BORHC_Pos) /*!< 0x00000100 */
-#define PWR_CR5_BORHC PWR_CR5_BORHC_Msk /*!< BORH configuration selection */
-
-#define PWR_CR5_SMPSEN_Pos (15U)
-#define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */
-#define PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk /*!< Enable SMPS Step Down converter SMPS mode enable */
-
/******************** Bit definition for PWR_PUCRA register *****************/
#define PWR_PUCRA_PA0_Pos (0U)
#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
@@ -5852,7 +5817,6 @@
/*
* @brief Specific device feature definitions
*/
-#define RCC_SMPS_SUPPORT
/******************** Bit definition for RCC_CR register *****************/
#define RCC_CR_MSION_Pos (0U)
@@ -6189,25 +6153,6 @@
#define RCC_CICR_LSI2RDYC_Msk (0x1UL << RCC_CICR_LSI2RDYC_Pos) /*!< 0x00000800 */
#define RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC_Msk
-/******************** Bit definition for RCC_SMPSCR register ******************/
-#define RCC_SMPSCR_SMPSSEL_Pos (0U)
-#define RCC_SMPSCR_SMPSSEL_Msk (0x3UL << RCC_SMPSCR_SMPSSEL_Pos) /*!< 0x00000003 */
-#define RCC_SMPSCR_SMPSSEL RCC_SMPSCR_SMPSSEL_Msk
-#define RCC_SMPSCR_SMPSSEL_0 (0x1U << RCC_SMPSCR_SMPSSEL_Pos) /*!< 0x00000001 */
-#define RCC_SMPSCR_SMPSSEL_1 (0x2U << RCC_SMPSCR_SMPSSEL_Pos) /*!< 0x00000002 */
-
-#define RCC_SMPSCR_SMPSDIV_Pos (4U)
-#define RCC_SMPSCR_SMPSDIV_Msk (0x3UL << RCC_SMPSCR_SMPSDIV_Pos) /*!< 0x00000030 */
-#define RCC_SMPSCR_SMPSDIV RCC_SMPSCR_SMPSDIV_Msk
-#define RCC_SMPSCR_SMPSDIV_0 (0x1U << RCC_SMPSCR_SMPSDIV_Pos) /*!< 0x00000010 */
-#define RCC_SMPSCR_SMPSDIV_1 (0x2U << RCC_SMPSCR_SMPSDIV_Pos) /*!< 0x00000020 */
-
-#define RCC_SMPSCR_SMPSSWS_Pos (8U)
-#define RCC_SMPSCR_SMPSSWS_Msk (0x3UL << RCC_SMPSCR_SMPSSWS_Pos) /*!< 0x00000300 */
-#define RCC_SMPSCR_SMPSSWS RCC_SMPSCR_SMPSSWS_Msk
-#define RCC_SMPSCR_SMPSSWS_0 (0x1U << RCC_SMPSCR_SMPSSWS_Pos) /*!< 0x00000100 */
-#define RCC_SMPSCR_SMPSSWS_1 (0x2U << RCC_SMPSCR_SMPSSWS_Pos) /*!< 0x00000200 */
-
/******************** Bit definition for RCC_AHB1RSTR register **************/
#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
@@ -7009,10 +6954,10 @@
#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
-#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
-#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */
@@ -7281,7 +7226,7 @@
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */
@@ -8427,100 +8372,100 @@
/***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/
#define SYSCFG_SWPR1_PAGE0_Pos (0U)
#define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */
+#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */
#define SYSCFG_SWPR1_PAGE1_Pos (1U)
#define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */
+#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */
#define SYSCFG_SWPR1_PAGE2_Pos (2U)
#define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */
+#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */
#define SYSCFG_SWPR1_PAGE3_Pos (3U)
#define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */
+#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */
#define SYSCFG_SWPR1_PAGE4_Pos (4U)
#define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */
+#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */
#define SYSCFG_SWPR1_PAGE5_Pos (5U)
#define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */
+#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */
#define SYSCFG_SWPR1_PAGE6_Pos (6U)
#define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */
+#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */
#define SYSCFG_SWPR1_PAGE7_Pos (7U)
#define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */
+#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */
#define SYSCFG_SWPR1_PAGE8_Pos (8U)
#define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */
+#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */
#define SYSCFG_SWPR1_PAGE9_Pos (9U)
#define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */
+#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */
#define SYSCFG_SWPR1_PAGE10_Pos (10U)
#define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */
+#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */
#define SYSCFG_SWPR1_PAGE11_Pos (11U)
#define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */
+#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */
#define SYSCFG_SWPR1_PAGE12_Pos (12U)
#define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */
+#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */
#define SYSCFG_SWPR1_PAGE13_Pos (13U)
#define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */
+#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */
#define SYSCFG_SWPR1_PAGE14_Pos (14U)
#define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */
+#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */
#define SYSCFG_SWPR1_PAGE15_Pos (15U)
#define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */
+#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */
#define SYSCFG_SWPR1_PAGE16_Pos (16U)
#define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */
+#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */
#define SYSCFG_SWPR1_PAGE17_Pos (17U)
#define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */
+#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */
#define SYSCFG_SWPR1_PAGE18_Pos (18U)
#define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */
+#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */
#define SYSCFG_SWPR1_PAGE19_Pos (19U)
#define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */
+#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */
#define SYSCFG_SWPR1_PAGE20_Pos (20U)
#define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */
+#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */
#define SYSCFG_SWPR1_PAGE21_Pos (21U)
#define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */
+#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */
#define SYSCFG_SWPR1_PAGE22_Pos (22U)
#define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */
+#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */
#define SYSCFG_SWPR1_PAGE23_Pos (23U)
#define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */
+#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */
#define SYSCFG_SWPR1_PAGE24_Pos (24U)
#define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */
+#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */
#define SYSCFG_SWPR1_PAGE25_Pos (25U)
#define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */
+#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */
#define SYSCFG_SWPR1_PAGE26_Pos (26U)
#define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */
+#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */
#define SYSCFG_SWPR1_PAGE27_Pos (27U)
#define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */
+#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */
#define SYSCFG_SWPR1_PAGE28_Pos (28U)
#define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */
+#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */
#define SYSCFG_SWPR1_PAGE29_Pos (29U)
#define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */
+#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */
#define SYSCFG_SWPR1_PAGE30_Pos (30U)
#define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */
+#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */
#define SYSCFG_SWPR1_PAGE31_Pos (31U)
#define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */
+#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */
/***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/
#define SYSCFG_SKR_KEY_Pos (0U)
@@ -8530,16 +8475,16 @@
/***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/
#define SYSCFG_SWPR2_PAGE32_Pos (0U)
#define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */
+#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */
#define SYSCFG_SWPR2_PAGE33_Pos (1U)
#define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */
+#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */
#define SYSCFG_SWPR2_PAGE34_Pos (2U)
#define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */
+#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */
#define SYSCFG_SWPR2_PAGE35_Pos (3U)
#define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */
+#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */
/***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/
#define SYSCFG_IMR1_TIM1IM_Pos (13U)
@@ -10864,5 +10809,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32wb15xx.h b/Include/stm32wb15xx.h
index 13d350b..07601f7 100644
--- a/Include/stm32wb15xx.h
+++ b/Include/stm32wb15xx.h
@@ -423,7 +423,7 @@
__IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
__IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
-uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
+uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
__IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
__IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
__IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
@@ -765,10 +765,10 @@
/*!< Memory, OTP and Option bytes */
/* Base addresses */
-#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 0x1FFF787F) */
-#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 - 0x1FFF787F) */
+#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 12 KB) base address */
#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
@@ -781,14 +781,14 @@
#define SRAM2B_SIZE 0x00001000UL /*!< SRAM2b default size : 4 KB */
/* End addresses */
-#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 0x20002FFF) */
-#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */
-#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 0x20038FFF) */
+#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 - 0x20002FFF) */
+#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */
+#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 - 0x20038FFF) */
-#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
@@ -1101,7 +1101,7 @@
#define ADC_CFGR1_ALIGN_Pos (5U)
#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR1_EXTSEL_Pos (6U)
#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
@@ -1151,7 +1151,7 @@
#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
-/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec accross STM32WB serie */
+/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec across STM32WB series */
#define ADC_CFGR_DMAEN_Pos ADC_CFGR1_DMAEN_Pos
#define ADC_CFGR_DMAEN_Msk ADC_CFGR1_DMAEN_Msk
#define ADC_CFGR_DMAEN ADC_CFGR1_DMAEN
@@ -1492,7 +1492,7 @@
#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */
#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */
-/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec accross STM32WB serie */
+/* Definitions for cohabitation of ADC peripherals 2.5Ms/sec and 5Ms/sec across STM32WB series */
#define ADC_DR_RDATA_Pos ADC_DR_DATA_Pos
#define ADC_DR_RDATA_Msk ADC_DR_DATA_Msk
#define ADC_DR_RDATA ADC_DR_DATA
@@ -3136,12 +3136,12 @@
/* Arithmetic addition output data */
#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Arithmetic substraction input data */
+/* Arithmetic subtraction input data */
#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
-/* Arithmetic substraction output data */
+/* Arithmetic subtraction output data */
#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Arithmetic multiplication input data */
@@ -3177,13 +3177,13 @@
/* Modular inversion output data */
#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Modular substraction input data */
+/* Modular subtraction input data */
#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
-/* Modular substraction output data */
+/* Modular subtraction output data */
#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Montgomery multiplication input data */
@@ -7126,10 +7126,10 @@
#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
-#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
-#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */
@@ -7398,7 +7398,7 @@
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */
@@ -8544,100 +8544,100 @@
/***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/
#define SYSCFG_SWPR1_PAGE0_Pos (0U)
#define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */
+#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */
#define SYSCFG_SWPR1_PAGE1_Pos (1U)
#define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */
+#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */
#define SYSCFG_SWPR1_PAGE2_Pos (2U)
#define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */
+#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */
#define SYSCFG_SWPR1_PAGE3_Pos (3U)
#define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */
+#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */
#define SYSCFG_SWPR1_PAGE4_Pos (4U)
#define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */
+#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */
#define SYSCFG_SWPR1_PAGE5_Pos (5U)
#define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */
+#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */
#define SYSCFG_SWPR1_PAGE6_Pos (6U)
#define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */
+#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */
#define SYSCFG_SWPR1_PAGE7_Pos (7U)
#define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */
+#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */
#define SYSCFG_SWPR1_PAGE8_Pos (8U)
#define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */
+#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */
#define SYSCFG_SWPR1_PAGE9_Pos (9U)
#define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */
+#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */
#define SYSCFG_SWPR1_PAGE10_Pos (10U)
#define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */
+#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */
#define SYSCFG_SWPR1_PAGE11_Pos (11U)
#define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */
+#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */
#define SYSCFG_SWPR1_PAGE12_Pos (12U)
#define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */
+#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */
#define SYSCFG_SWPR1_PAGE13_Pos (13U)
#define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */
+#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */
#define SYSCFG_SWPR1_PAGE14_Pos (14U)
#define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */
+#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */
#define SYSCFG_SWPR1_PAGE15_Pos (15U)
#define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */
+#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */
#define SYSCFG_SWPR1_PAGE16_Pos (16U)
#define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */
+#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */
#define SYSCFG_SWPR1_PAGE17_Pos (17U)
#define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */
+#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */
#define SYSCFG_SWPR1_PAGE18_Pos (18U)
#define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */
+#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */
#define SYSCFG_SWPR1_PAGE19_Pos (19U)
#define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */
+#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */
#define SYSCFG_SWPR1_PAGE20_Pos (20U)
#define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */
+#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */
#define SYSCFG_SWPR1_PAGE21_Pos (21U)
#define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */
+#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */
#define SYSCFG_SWPR1_PAGE22_Pos (22U)
#define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */
+#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */
#define SYSCFG_SWPR1_PAGE23_Pos (23U)
#define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */
+#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */
#define SYSCFG_SWPR1_PAGE24_Pos (24U)
#define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */
+#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */
#define SYSCFG_SWPR1_PAGE25_Pos (25U)
#define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */
+#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */
#define SYSCFG_SWPR1_PAGE26_Pos (26U)
#define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */
+#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */
#define SYSCFG_SWPR1_PAGE27_Pos (27U)
#define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */
+#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */
#define SYSCFG_SWPR1_PAGE28_Pos (28U)
#define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */
+#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */
#define SYSCFG_SWPR1_PAGE29_Pos (29U)
#define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */
+#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */
#define SYSCFG_SWPR1_PAGE30_Pos (30U)
#define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */
+#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */
#define SYSCFG_SWPR1_PAGE31_Pos (31U)
#define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */
+#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */
/***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/
#define SYSCFG_SKR_KEY_Pos (0U)
@@ -8647,16 +8647,16 @@
/***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/
#define SYSCFG_SWPR2_PAGE32_Pos (0U)
#define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */
+#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */
#define SYSCFG_SWPR2_PAGE33_Pos (1U)
#define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */
+#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */
#define SYSCFG_SWPR2_PAGE34_Pos (2U)
#define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */
+#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */
#define SYSCFG_SWPR2_PAGE35_Pos (3U)
#define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */
+#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */
/***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/
#define SYSCFG_IMR1_TIM1IM_Pos (13U)
@@ -10994,5 +10994,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32wb30xx.h b/Include/stm32wb30xx.h
index d0abd1c..3851367 100644
--- a/Include/stm32wb30xx.h
+++ b/Include/stm32wb30xx.h
@@ -431,7 +431,7 @@
__IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
__IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
-uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
+uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
__IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
__IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
__IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
@@ -752,10 +752,10 @@
/*!< Memory, OTP and Option bytes */
/* Base addresses */
-#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 32 KB) base address */
#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
@@ -768,14 +768,14 @@
#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */
/* End addresses */
-#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 0x20007FFF) */
-#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */
-#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */
+#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 - 0x20007FFF) */
+#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */
+#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */
-#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
@@ -1100,7 +1100,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -3521,12 +3521,12 @@
/* Arithmetic addition output data */
#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Arithmetic substraction input data */
+/* Arithmetic subtraction input data */
#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
-/* Arithmetic substraction output data */
+/* Arithmetic subtraction output data */
#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Arithmetic multiplication input data */
@@ -3562,13 +3562,13 @@
/* Modular inversion output data */
#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Modular substraction input data */
+/* Modular subtraction input data */
#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
-/* Modular substraction output data */
+/* Modular subtraction output data */
#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Montgomery multiplication input data */
@@ -7494,10 +7494,10 @@
#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
-#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
-#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */
@@ -7766,7 +7766,7 @@
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */
@@ -8466,100 +8466,100 @@
/***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/
#define SYSCFG_SWPR1_PAGE0_Pos (0U)
#define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */
+#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */
#define SYSCFG_SWPR1_PAGE1_Pos (1U)
#define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */
+#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */
#define SYSCFG_SWPR1_PAGE2_Pos (2U)
#define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */
+#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */
#define SYSCFG_SWPR1_PAGE3_Pos (3U)
#define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */
+#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */
#define SYSCFG_SWPR1_PAGE4_Pos (4U)
#define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */
+#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */
#define SYSCFG_SWPR1_PAGE5_Pos (5U)
#define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */
+#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */
#define SYSCFG_SWPR1_PAGE6_Pos (6U)
#define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */
+#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */
#define SYSCFG_SWPR1_PAGE7_Pos (7U)
#define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */
+#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */
#define SYSCFG_SWPR1_PAGE8_Pos (8U)
#define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */
+#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */
#define SYSCFG_SWPR1_PAGE9_Pos (9U)
#define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */
+#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */
#define SYSCFG_SWPR1_PAGE10_Pos (10U)
#define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */
+#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */
#define SYSCFG_SWPR1_PAGE11_Pos (11U)
#define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */
+#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */
#define SYSCFG_SWPR1_PAGE12_Pos (12U)
#define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */
+#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */
#define SYSCFG_SWPR1_PAGE13_Pos (13U)
#define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */
+#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */
#define SYSCFG_SWPR1_PAGE14_Pos (14U)
#define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */
+#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */
#define SYSCFG_SWPR1_PAGE15_Pos (15U)
#define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */
+#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */
#define SYSCFG_SWPR1_PAGE16_Pos (16U)
#define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */
+#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */
#define SYSCFG_SWPR1_PAGE17_Pos (17U)
#define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */
+#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */
#define SYSCFG_SWPR1_PAGE18_Pos (18U)
#define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */
+#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */
#define SYSCFG_SWPR1_PAGE19_Pos (19U)
#define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */
+#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */
#define SYSCFG_SWPR1_PAGE20_Pos (20U)
#define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */
+#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */
#define SYSCFG_SWPR1_PAGE21_Pos (21U)
#define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */
+#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */
#define SYSCFG_SWPR1_PAGE22_Pos (22U)
#define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */
+#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */
#define SYSCFG_SWPR1_PAGE23_Pos (23U)
#define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */
+#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */
#define SYSCFG_SWPR1_PAGE24_Pos (24U)
#define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */
+#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */
#define SYSCFG_SWPR1_PAGE25_Pos (25U)
#define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */
+#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */
#define SYSCFG_SWPR1_PAGE26_Pos (26U)
#define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */
+#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */
#define SYSCFG_SWPR1_PAGE27_Pos (27U)
#define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */
+#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */
#define SYSCFG_SWPR1_PAGE28_Pos (28U)
#define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */
+#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */
#define SYSCFG_SWPR1_PAGE29_Pos (29U)
#define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */
+#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */
#define SYSCFG_SWPR1_PAGE30_Pos (30U)
#define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */
+#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */
#define SYSCFG_SWPR1_PAGE31_Pos (31U)
#define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */
+#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */
/***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/
#define SYSCFG_SKR_KEY_Pos (0U)
@@ -8569,100 +8569,100 @@
/***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/
#define SYSCFG_SWPR2_PAGE32_Pos (0U)
#define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */
+#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */
#define SYSCFG_SWPR2_PAGE33_Pos (1U)
#define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */
+#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */
#define SYSCFG_SWPR2_PAGE34_Pos (2U)
#define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */
+#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */
#define SYSCFG_SWPR2_PAGE35_Pos (3U)
#define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */
+#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */
#define SYSCFG_SWPR2_PAGE36_Pos (4U)
#define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 0x200393FF) */
+#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */
#define SYSCFG_SWPR2_PAGE37_Pos (5U)
#define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 0x200397FF) */
+#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */
#define SYSCFG_SWPR2_PAGE38_Pos (6U)
#define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 0x20039BFF) */
+#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */
#define SYSCFG_SWPR2_PAGE39_Pos (7U)
#define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 0x20039FFF) */
+#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */
#define SYSCFG_SWPR2_PAGE40_Pos (8U)
#define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 0x2003A3FF) */
+#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */
#define SYSCFG_SWPR2_PAGE41_Pos (9U)
#define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 0x2003A7FF) */
+#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */
#define SYSCFG_SWPR2_PAGE42_Pos (10U)
#define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 0x2003ABFF) */
+#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */
#define SYSCFG_SWPR2_PAGE43_Pos (11U)
#define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 0x2003AFFF) */
+#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */
#define SYSCFG_SWPR2_PAGE44_Pos (12U)
#define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 0x2003B3FF) */
+#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */
#define SYSCFG_SWPR2_PAGE45_Pos (13U)
#define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 0x2003B7FF) */
+#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */
#define SYSCFG_SWPR2_PAGE46_Pos (14U)
#define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 0x2003BBFF) */
+#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */
#define SYSCFG_SWPR2_PAGE47_Pos (15U)
#define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 0x2003BFFF) */
+#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */
#define SYSCFG_SWPR2_PAGE48_Pos (16U)
#define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 0x2003C3FF) */
+#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */
#define SYSCFG_SWPR2_PAGE49_Pos (17U)
#define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 0x2003C7FF) */
+#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */
#define SYSCFG_SWPR2_PAGE50_Pos (18U)
#define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 0x2003CBFF) */
+#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */
#define SYSCFG_SWPR2_PAGE51_Pos (19U)
#define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 0x2003CFFF) */
+#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */
#define SYSCFG_SWPR2_PAGE52_Pos (20U)
#define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 0x2003D3FF) */
+#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */
#define SYSCFG_SWPR2_PAGE53_Pos (21U)
#define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 0x2003D7FF) */
+#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */
#define SYSCFG_SWPR2_PAGE54_Pos (22U)
#define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 0x2003DBFF) */
+#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */
#define SYSCFG_SWPR2_PAGE55_Pos (23U)
#define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 0x2003DFFF) */
+#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */
#define SYSCFG_SWPR2_PAGE56_Pos (24U)
#define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 0x2003E3FF) */
+#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */
#define SYSCFG_SWPR2_PAGE57_Pos (25U)
#define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 0x2003E7FF) */
+#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */
#define SYSCFG_SWPR2_PAGE58_Pos (26U)
#define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 0x2003EBFF) */
+#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */
#define SYSCFG_SWPR2_PAGE59_Pos (27U)
#define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 0x2003EFFF) */
+#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */
#define SYSCFG_SWPR2_PAGE60_Pos (28U)
#define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 0x2003F3FF) */
+#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */
#define SYSCFG_SWPR2_PAGE61_Pos (29U)
#define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 0x2003F7FF) */
+#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */
#define SYSCFG_SWPR2_PAGE62_Pos (30U)
#define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 0x2003FBFF) */
+#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */
#define SYSCFG_SWPR2_PAGE63_Pos (31U)
#define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 0x2003FFFF) */
+#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */
/***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/
#define SYSCFG_IMR1_TIM1IM_Pos (13U)
@@ -11033,5 +11033,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32wb35xx.h b/Include/stm32wb35xx.h
index bcbbfc6..4b01c5c 100644
--- a/Include/stm32wb35xx.h
+++ b/Include/stm32wb35xx.h
@@ -483,7 +483,7 @@
__IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
__IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
-uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
+uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
__IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
__IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
__IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
@@ -884,10 +884,10 @@
/*!< Memory, OTP and Option bytes */
/* Base addresses */
-#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 32 KB) base address */
#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
@@ -900,14 +900,14 @@
#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */
/* End addresses */
-#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 0x20007FFF) */
-#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */
-#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */
+#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 - 0x20007FFF) */
+#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */
+#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */
-#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
@@ -1292,7 +1292,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -3899,12 +3899,12 @@
/* Arithmetic addition output data */
#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Arithmetic substraction input data */
+/* Arithmetic subtraction input data */
#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
-/* Arithmetic substraction output data */
+/* Arithmetic subtraction output data */
#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Arithmetic multiplication input data */
@@ -3940,13 +3940,13 @@
/* Modular inversion output data */
#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Modular substraction input data */
+/* Modular subtraction input data */
#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
-/* Modular substraction output data */
+/* Modular subtraction output data */
#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Montgomery multiplication input data */
@@ -8495,10 +8495,10 @@
#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
-#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
-#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */
@@ -8773,7 +8773,7 @@
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */
@@ -9815,100 +9815,100 @@
/***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/
#define SYSCFG_SWPR1_PAGE0_Pos (0U)
#define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */
+#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */
#define SYSCFG_SWPR1_PAGE1_Pos (1U)
#define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */
+#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */
#define SYSCFG_SWPR1_PAGE2_Pos (2U)
#define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */
+#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */
#define SYSCFG_SWPR1_PAGE3_Pos (3U)
#define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */
+#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */
#define SYSCFG_SWPR1_PAGE4_Pos (4U)
#define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */
+#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */
#define SYSCFG_SWPR1_PAGE5_Pos (5U)
#define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */
+#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */
#define SYSCFG_SWPR1_PAGE6_Pos (6U)
#define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */
+#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */
#define SYSCFG_SWPR1_PAGE7_Pos (7U)
#define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */
+#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */
#define SYSCFG_SWPR1_PAGE8_Pos (8U)
#define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */
+#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */
#define SYSCFG_SWPR1_PAGE9_Pos (9U)
#define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */
+#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */
#define SYSCFG_SWPR1_PAGE10_Pos (10U)
#define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */
+#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */
#define SYSCFG_SWPR1_PAGE11_Pos (11U)
#define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */
+#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */
#define SYSCFG_SWPR1_PAGE12_Pos (12U)
#define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */
+#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */
#define SYSCFG_SWPR1_PAGE13_Pos (13U)
#define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */
+#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */
#define SYSCFG_SWPR1_PAGE14_Pos (14U)
#define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */
+#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */
#define SYSCFG_SWPR1_PAGE15_Pos (15U)
#define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */
+#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */
#define SYSCFG_SWPR1_PAGE16_Pos (16U)
#define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */
+#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */
#define SYSCFG_SWPR1_PAGE17_Pos (17U)
#define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */
+#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */
#define SYSCFG_SWPR1_PAGE18_Pos (18U)
#define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */
+#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */
#define SYSCFG_SWPR1_PAGE19_Pos (19U)
#define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */
+#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */
#define SYSCFG_SWPR1_PAGE20_Pos (20U)
#define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */
+#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */
#define SYSCFG_SWPR1_PAGE21_Pos (21U)
#define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */
+#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */
#define SYSCFG_SWPR1_PAGE22_Pos (22U)
#define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */
+#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */
#define SYSCFG_SWPR1_PAGE23_Pos (23U)
#define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */
+#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */
#define SYSCFG_SWPR1_PAGE24_Pos (24U)
#define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */
+#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */
#define SYSCFG_SWPR1_PAGE25_Pos (25U)
#define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */
+#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */
#define SYSCFG_SWPR1_PAGE26_Pos (26U)
#define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */
+#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */
#define SYSCFG_SWPR1_PAGE27_Pos (27U)
#define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */
+#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */
#define SYSCFG_SWPR1_PAGE28_Pos (28U)
#define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */
+#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */
#define SYSCFG_SWPR1_PAGE29_Pos (29U)
#define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */
+#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */
#define SYSCFG_SWPR1_PAGE30_Pos (30U)
#define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */
+#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */
#define SYSCFG_SWPR1_PAGE31_Pos (31U)
#define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */
+#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */
/***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/
#define SYSCFG_SKR_KEY_Pos (0U)
@@ -9918,100 +9918,100 @@
/***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/
#define SYSCFG_SWPR2_PAGE32_Pos (0U)
#define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */
+#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */
#define SYSCFG_SWPR2_PAGE33_Pos (1U)
#define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */
+#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */
#define SYSCFG_SWPR2_PAGE34_Pos (2U)
#define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */
+#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */
#define SYSCFG_SWPR2_PAGE35_Pos (3U)
#define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */
+#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */
#define SYSCFG_SWPR2_PAGE36_Pos (4U)
#define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 0x200393FF) */
+#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */
#define SYSCFG_SWPR2_PAGE37_Pos (5U)
#define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 0x200397FF) */
+#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */
#define SYSCFG_SWPR2_PAGE38_Pos (6U)
#define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 0x20039BFF) */
+#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */
#define SYSCFG_SWPR2_PAGE39_Pos (7U)
#define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 0x20039FFF) */
+#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */
#define SYSCFG_SWPR2_PAGE40_Pos (8U)
#define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 0x2003A3FF) */
+#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */
#define SYSCFG_SWPR2_PAGE41_Pos (9U)
#define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 0x2003A7FF) */
+#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */
#define SYSCFG_SWPR2_PAGE42_Pos (10U)
#define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 0x2003ABFF) */
+#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */
#define SYSCFG_SWPR2_PAGE43_Pos (11U)
#define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 0x2003AFFF) */
+#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */
#define SYSCFG_SWPR2_PAGE44_Pos (12U)
#define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 0x2003B3FF) */
+#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */
#define SYSCFG_SWPR2_PAGE45_Pos (13U)
#define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 0x2003B7FF) */
+#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */
#define SYSCFG_SWPR2_PAGE46_Pos (14U)
#define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 0x2003BBFF) */
+#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */
#define SYSCFG_SWPR2_PAGE47_Pos (15U)
#define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 0x2003BFFF) */
+#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */
#define SYSCFG_SWPR2_PAGE48_Pos (16U)
#define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 0x2003C3FF) */
+#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */
#define SYSCFG_SWPR2_PAGE49_Pos (17U)
#define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 0x2003C7FF) */
+#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */
#define SYSCFG_SWPR2_PAGE50_Pos (18U)
#define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 0x2003CBFF) */
+#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */
#define SYSCFG_SWPR2_PAGE51_Pos (19U)
#define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 0x2003CFFF) */
+#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */
#define SYSCFG_SWPR2_PAGE52_Pos (20U)
#define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 0x2003D3FF) */
+#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */
#define SYSCFG_SWPR2_PAGE53_Pos (21U)
#define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 0x2003D7FF) */
+#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */
#define SYSCFG_SWPR2_PAGE54_Pos (22U)
#define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 0x2003DBFF) */
+#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */
#define SYSCFG_SWPR2_PAGE55_Pos (23U)
#define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 0x2003DFFF) */
+#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */
#define SYSCFG_SWPR2_PAGE56_Pos (24U)
#define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 0x2003E3FF) */
+#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */
#define SYSCFG_SWPR2_PAGE57_Pos (25U)
#define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 0x2003E7FF) */
+#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */
#define SYSCFG_SWPR2_PAGE58_Pos (26U)
#define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 0x2003EBFF) */
+#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */
#define SYSCFG_SWPR2_PAGE59_Pos (27U)
#define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 0x2003EFFF) */
+#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */
#define SYSCFG_SWPR2_PAGE60_Pos (28U)
#define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 0x2003F3FF) */
+#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */
#define SYSCFG_SWPR2_PAGE61_Pos (29U)
#define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 0x2003F7FF) */
+#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */
#define SYSCFG_SWPR2_PAGE62_Pos (30U)
#define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 0x2003FBFF) */
+#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */
#define SYSCFG_SWPR2_PAGE63_Pos (31U)
#define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 0x2003FFFF) */
+#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */
/***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/
#define SYSCFG_IMR1_TIM1IM_Pos (13U)
@@ -12777,5 +12777,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32wb50xx.h b/Include/stm32wb50xx.h
index 0e4077b..2527fdc 100644
--- a/Include/stm32wb50xx.h
+++ b/Include/stm32wb50xx.h
@@ -432,7 +432,7 @@
__IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
__IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
-uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
+uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
__IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
__IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
__IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
@@ -753,10 +753,10 @@
/*!< Memory, OTP and Option bytes */
/* Base addresses */
-#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 64 KB) base address */
#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
@@ -769,14 +769,14 @@
#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */
/* End addresses */
-#define SRAM1_END_ADDR (0x2000FFFFUL) /*!< SRAM1 : 64KB (0x20000000 0x2000FFFF) */
-#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */
-#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */
+#define SRAM1_END_ADDR (0x2000FFFFUL) /*!< SRAM1 : 64KB (0x20000000 - 0x2000FFFF) */
+#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */
+#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */
-#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
@@ -1101,7 +1101,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -3522,12 +3522,12 @@
/* Arithmetic addition output data */
#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Arithmetic substraction input data */
+/* Arithmetic subtraction input data */
#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
-/* Arithmetic substraction output data */
+/* Arithmetic subtraction output data */
#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Arithmetic multiplication input data */
@@ -3563,13 +3563,13 @@
/* Modular inversion output data */
#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Modular substraction input data */
+/* Modular subtraction input data */
#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
-/* Modular substraction output data */
+/* Modular subtraction output data */
#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Montgomery multiplication input data */
@@ -7495,10 +7495,10 @@
#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
-#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
-#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */
@@ -7767,7 +7767,7 @@
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */
@@ -8467,100 +8467,100 @@
/***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/
#define SYSCFG_SWPR1_PAGE0_Pos (0U)
#define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */
+#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */
#define SYSCFG_SWPR1_PAGE1_Pos (1U)
#define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */
+#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */
#define SYSCFG_SWPR1_PAGE2_Pos (2U)
#define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */
+#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */
#define SYSCFG_SWPR1_PAGE3_Pos (3U)
#define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */
+#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */
#define SYSCFG_SWPR1_PAGE4_Pos (4U)
#define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */
+#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */
#define SYSCFG_SWPR1_PAGE5_Pos (5U)
#define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */
+#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */
#define SYSCFG_SWPR1_PAGE6_Pos (6U)
#define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */
+#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */
#define SYSCFG_SWPR1_PAGE7_Pos (7U)
#define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */
+#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */
#define SYSCFG_SWPR1_PAGE8_Pos (8U)
#define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */
+#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */
#define SYSCFG_SWPR1_PAGE9_Pos (9U)
#define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */
+#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */
#define SYSCFG_SWPR1_PAGE10_Pos (10U)
#define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */
+#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */
#define SYSCFG_SWPR1_PAGE11_Pos (11U)
#define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */
+#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */
#define SYSCFG_SWPR1_PAGE12_Pos (12U)
#define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */
+#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */
#define SYSCFG_SWPR1_PAGE13_Pos (13U)
#define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */
+#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */
#define SYSCFG_SWPR1_PAGE14_Pos (14U)
#define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */
+#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */
#define SYSCFG_SWPR1_PAGE15_Pos (15U)
#define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */
+#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */
#define SYSCFG_SWPR1_PAGE16_Pos (16U)
#define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */
+#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */
#define SYSCFG_SWPR1_PAGE17_Pos (17U)
#define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */
+#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */
#define SYSCFG_SWPR1_PAGE18_Pos (18U)
#define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */
+#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */
#define SYSCFG_SWPR1_PAGE19_Pos (19U)
#define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */
+#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */
#define SYSCFG_SWPR1_PAGE20_Pos (20U)
#define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */
+#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */
#define SYSCFG_SWPR1_PAGE21_Pos (21U)
#define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */
+#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */
#define SYSCFG_SWPR1_PAGE22_Pos (22U)
#define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */
+#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */
#define SYSCFG_SWPR1_PAGE23_Pos (23U)
#define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */
+#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */
#define SYSCFG_SWPR1_PAGE24_Pos (24U)
#define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */
+#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */
#define SYSCFG_SWPR1_PAGE25_Pos (25U)
#define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */
+#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */
#define SYSCFG_SWPR1_PAGE26_Pos (26U)
#define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */
+#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */
#define SYSCFG_SWPR1_PAGE27_Pos (27U)
#define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */
+#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */
#define SYSCFG_SWPR1_PAGE28_Pos (28U)
#define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */
+#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */
#define SYSCFG_SWPR1_PAGE29_Pos (29U)
#define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */
+#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */
#define SYSCFG_SWPR1_PAGE30_Pos (30U)
#define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */
+#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */
#define SYSCFG_SWPR1_PAGE31_Pos (31U)
#define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */
+#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */
/***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/
#define SYSCFG_SKR_KEY_Pos (0U)
@@ -8570,100 +8570,100 @@
/***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/
#define SYSCFG_SWPR2_PAGE32_Pos (0U)
#define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */
+#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */
#define SYSCFG_SWPR2_PAGE33_Pos (1U)
#define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */
+#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */
#define SYSCFG_SWPR2_PAGE34_Pos (2U)
#define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */
+#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */
#define SYSCFG_SWPR2_PAGE35_Pos (3U)
#define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */
+#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */
#define SYSCFG_SWPR2_PAGE36_Pos (4U)
#define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 0x200393FF) */
+#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */
#define SYSCFG_SWPR2_PAGE37_Pos (5U)
#define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 0x200397FF) */
+#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */
#define SYSCFG_SWPR2_PAGE38_Pos (6U)
#define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 0x20039BFF) */
+#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */
#define SYSCFG_SWPR2_PAGE39_Pos (7U)
#define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 0x20039FFF) */
+#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */
#define SYSCFG_SWPR2_PAGE40_Pos (8U)
#define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 0x2003A3FF) */
+#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */
#define SYSCFG_SWPR2_PAGE41_Pos (9U)
#define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 0x2003A7FF) */
+#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */
#define SYSCFG_SWPR2_PAGE42_Pos (10U)
#define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 0x2003ABFF) */
+#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */
#define SYSCFG_SWPR2_PAGE43_Pos (11U)
#define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 0x2003AFFF) */
+#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */
#define SYSCFG_SWPR2_PAGE44_Pos (12U)
#define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 0x2003B3FF) */
+#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */
#define SYSCFG_SWPR2_PAGE45_Pos (13U)
#define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 0x2003B7FF) */
+#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */
#define SYSCFG_SWPR2_PAGE46_Pos (14U)
#define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 0x2003BBFF) */
+#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */
#define SYSCFG_SWPR2_PAGE47_Pos (15U)
#define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 0x2003BFFF) */
+#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */
#define SYSCFG_SWPR2_PAGE48_Pos (16U)
#define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 0x2003C3FF) */
+#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */
#define SYSCFG_SWPR2_PAGE49_Pos (17U)
#define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 0x2003C7FF) */
+#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */
#define SYSCFG_SWPR2_PAGE50_Pos (18U)
#define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 0x2003CBFF) */
+#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */
#define SYSCFG_SWPR2_PAGE51_Pos (19U)
#define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 0x2003CFFF) */
+#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */
#define SYSCFG_SWPR2_PAGE52_Pos (20U)
#define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 0x2003D3FF) */
+#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */
#define SYSCFG_SWPR2_PAGE53_Pos (21U)
#define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 0x2003D7FF) */
+#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */
#define SYSCFG_SWPR2_PAGE54_Pos (22U)
#define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 0x2003DBFF) */
+#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */
#define SYSCFG_SWPR2_PAGE55_Pos (23U)
#define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 0x2003DFFF) */
+#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */
#define SYSCFG_SWPR2_PAGE56_Pos (24U)
#define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 0x2003E3FF) */
+#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */
#define SYSCFG_SWPR2_PAGE57_Pos (25U)
#define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 0x2003E7FF) */
+#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */
#define SYSCFG_SWPR2_PAGE58_Pos (26U)
#define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 0x2003EBFF) */
+#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */
#define SYSCFG_SWPR2_PAGE59_Pos (27U)
#define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 0x2003EFFF) */
+#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */
#define SYSCFG_SWPR2_PAGE60_Pos (28U)
#define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 0x2003F3FF) */
+#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */
#define SYSCFG_SWPR2_PAGE61_Pos (29U)
#define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 0x2003F7FF) */
+#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */
#define SYSCFG_SWPR2_PAGE62_Pos (30U)
#define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 0x2003FBFF) */
+#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */
#define SYSCFG_SWPR2_PAGE63_Pos (31U)
#define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 0x2003FFFF) */
+#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */
/***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/
#define SYSCFG_IMR1_TIM1IM_Pos (13U)
@@ -11037,5 +11037,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32wb55xx.h b/Include/stm32wb55xx.h
index 196faab..b3e0bb8 100644
--- a/Include/stm32wb55xx.h
+++ b/Include/stm32wb55xx.h
@@ -487,7 +487,7 @@
__IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
__IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
-uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
+uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
__IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
__IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
__IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
@@ -922,10 +922,10 @@
/*!< Memory, OTP and Option bytes */
/* Base addresses */
-#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 192 KB) base address */
#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
@@ -938,14 +938,14 @@
#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */
/* End addresses */
-#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 0x2002FFFF) */
-#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */
-#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */
+#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 - 0x2002FFFF) */
+#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */
+#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */
-#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
@@ -1338,7 +1338,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -3951,12 +3951,12 @@
/* Arithmetic addition output data */
#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Arithmetic substraction input data */
+/* Arithmetic subtraction input data */
#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
-/* Arithmetic substraction output data */
+/* Arithmetic subtraction output data */
#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Arithmetic multiplication input data */
@@ -3992,13 +3992,13 @@
/* Modular inversion output data */
#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Modular substraction input data */
+/* Modular subtraction input data */
#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
-/* Modular substraction output data */
+/* Modular subtraction output data */
#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Montgomery multiplication input data */
@@ -8746,10 +8746,10 @@
#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
-#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
-#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */
@@ -9024,7 +9024,7 @@
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */
@@ -10714,100 +10714,100 @@
/***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/
#define SYSCFG_SWPR1_PAGE0_Pos (0U)
#define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */
+#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */
#define SYSCFG_SWPR1_PAGE1_Pos (1U)
#define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */
+#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */
#define SYSCFG_SWPR1_PAGE2_Pos (2U)
#define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */
+#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */
#define SYSCFG_SWPR1_PAGE3_Pos (3U)
#define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */
+#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */
#define SYSCFG_SWPR1_PAGE4_Pos (4U)
#define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */
+#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */
#define SYSCFG_SWPR1_PAGE5_Pos (5U)
#define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */
+#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */
#define SYSCFG_SWPR1_PAGE6_Pos (6U)
#define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */
+#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */
#define SYSCFG_SWPR1_PAGE7_Pos (7U)
#define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */
+#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */
#define SYSCFG_SWPR1_PAGE8_Pos (8U)
#define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */
+#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */
#define SYSCFG_SWPR1_PAGE9_Pos (9U)
#define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */
+#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */
#define SYSCFG_SWPR1_PAGE10_Pos (10U)
#define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */
+#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */
#define SYSCFG_SWPR1_PAGE11_Pos (11U)
#define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */
+#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */
#define SYSCFG_SWPR1_PAGE12_Pos (12U)
#define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */
+#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */
#define SYSCFG_SWPR1_PAGE13_Pos (13U)
#define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */
+#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */
#define SYSCFG_SWPR1_PAGE14_Pos (14U)
#define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */
+#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */
#define SYSCFG_SWPR1_PAGE15_Pos (15U)
#define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */
+#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */
#define SYSCFG_SWPR1_PAGE16_Pos (16U)
#define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */
+#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */
#define SYSCFG_SWPR1_PAGE17_Pos (17U)
#define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */
+#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */
#define SYSCFG_SWPR1_PAGE18_Pos (18U)
#define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */
+#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */
#define SYSCFG_SWPR1_PAGE19_Pos (19U)
#define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */
+#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */
#define SYSCFG_SWPR1_PAGE20_Pos (20U)
#define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */
+#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */
#define SYSCFG_SWPR1_PAGE21_Pos (21U)
#define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */
+#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */
#define SYSCFG_SWPR1_PAGE22_Pos (22U)
#define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */
+#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */
#define SYSCFG_SWPR1_PAGE23_Pos (23U)
#define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */
+#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */
#define SYSCFG_SWPR1_PAGE24_Pos (24U)
#define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */
+#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */
#define SYSCFG_SWPR1_PAGE25_Pos (25U)
#define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */
+#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */
#define SYSCFG_SWPR1_PAGE26_Pos (26U)
#define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */
+#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */
#define SYSCFG_SWPR1_PAGE27_Pos (27U)
#define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */
+#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */
#define SYSCFG_SWPR1_PAGE28_Pos (28U)
#define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */
+#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */
#define SYSCFG_SWPR1_PAGE29_Pos (29U)
#define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */
+#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */
#define SYSCFG_SWPR1_PAGE30_Pos (30U)
#define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */
+#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */
#define SYSCFG_SWPR1_PAGE31_Pos (31U)
#define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */
+#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */
/***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/
#define SYSCFG_SKR_KEY_Pos (0U)
@@ -10817,100 +10817,100 @@
/***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/
#define SYSCFG_SWPR2_PAGE32_Pos (0U)
#define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */
+#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */
#define SYSCFG_SWPR2_PAGE33_Pos (1U)
#define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */
+#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */
#define SYSCFG_SWPR2_PAGE34_Pos (2U)
#define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */
+#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */
#define SYSCFG_SWPR2_PAGE35_Pos (3U)
#define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */
+#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */
#define SYSCFG_SWPR2_PAGE36_Pos (4U)
#define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 0x200393FF) */
+#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */
#define SYSCFG_SWPR2_PAGE37_Pos (5U)
#define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 0x200397FF) */
+#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */
#define SYSCFG_SWPR2_PAGE38_Pos (6U)
#define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 0x20039BFF) */
+#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */
#define SYSCFG_SWPR2_PAGE39_Pos (7U)
#define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 0x20039FFF) */
+#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */
#define SYSCFG_SWPR2_PAGE40_Pos (8U)
#define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 0x2003A3FF) */
+#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */
#define SYSCFG_SWPR2_PAGE41_Pos (9U)
#define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 0x2003A7FF) */
+#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */
#define SYSCFG_SWPR2_PAGE42_Pos (10U)
#define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 0x2003ABFF) */
+#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */
#define SYSCFG_SWPR2_PAGE43_Pos (11U)
#define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 0x2003AFFF) */
+#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */
#define SYSCFG_SWPR2_PAGE44_Pos (12U)
#define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 0x2003B3FF) */
+#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */
#define SYSCFG_SWPR2_PAGE45_Pos (13U)
#define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 0x2003B7FF) */
+#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */
#define SYSCFG_SWPR2_PAGE46_Pos (14U)
#define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 0x2003BBFF) */
+#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */
#define SYSCFG_SWPR2_PAGE47_Pos (15U)
#define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 0x2003BFFF) */
+#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */
#define SYSCFG_SWPR2_PAGE48_Pos (16U)
#define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 0x2003C3FF) */
+#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */
#define SYSCFG_SWPR2_PAGE49_Pos (17U)
#define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 0x2003C7FF) */
+#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */
#define SYSCFG_SWPR2_PAGE50_Pos (18U)
#define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 0x2003CBFF) */
+#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */
#define SYSCFG_SWPR2_PAGE51_Pos (19U)
#define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 0x2003CFFF) */
+#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */
#define SYSCFG_SWPR2_PAGE52_Pos (20U)
#define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 0x2003D3FF) */
+#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */
#define SYSCFG_SWPR2_PAGE53_Pos (21U)
#define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 0x2003D7FF) */
+#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */
#define SYSCFG_SWPR2_PAGE54_Pos (22U)
#define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 0x2003DBFF) */
+#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */
#define SYSCFG_SWPR2_PAGE55_Pos (23U)
#define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 0x2003DFFF) */
+#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */
#define SYSCFG_SWPR2_PAGE56_Pos (24U)
#define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 0x2003E3FF) */
+#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */
#define SYSCFG_SWPR2_PAGE57_Pos (25U)
#define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 0x2003E7FF) */
+#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */
#define SYSCFG_SWPR2_PAGE58_Pos (26U)
#define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 0x2003EBFF) */
+#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */
#define SYSCFG_SWPR2_PAGE59_Pos (27U)
#define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 0x2003EFFF) */
+#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */
#define SYSCFG_SWPR2_PAGE60_Pos (28U)
#define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 0x2003F3FF) */
+#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */
#define SYSCFG_SWPR2_PAGE61_Pos (29U)
#define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 0x2003F7FF) */
+#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */
#define SYSCFG_SWPR2_PAGE62_Pos (30U)
#define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 0x2003FBFF) */
+#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */
#define SYSCFG_SWPR2_PAGE63_Pos (31U)
#define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 0x2003FFFF) */
+#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */
/***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/
#define SYSCFG_IMR1_TIM1IM_Pos (13U)
@@ -13690,5 +13690,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32wb5mxx.h b/Include/stm32wb5mxx.h
index f02d68c..334d3b8 100644
--- a/Include/stm32wb5mxx.h
+++ b/Include/stm32wb5mxx.h
@@ -487,7 +487,7 @@
__IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
__IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
-uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
+uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
__IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
__IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
__IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
@@ -922,10 +922,10 @@
/*!< Memory, OTP and Option bytes */
/* Base addresses */
-#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 192 KB) base address */
#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
@@ -938,14 +938,14 @@
#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */
/* End addresses */
-#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 0x2002FFFF) */
-#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */
-#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */
+#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 - 0x2002FFFF) */
+#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */
+#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */
-#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */
-#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */
-#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */
-#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */
+#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */
+#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */
+#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */
+#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
@@ -1338,7 +1338,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -3951,12 +3951,12 @@
/* Arithmetic addition output data */
#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Arithmetic substraction input data */
+/* Arithmetic subtraction input data */
#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
-/* Arithmetic substraction output data */
+/* Arithmetic subtraction output data */
#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Arithmetic multiplication input data */
@@ -3992,13 +3992,13 @@
/* Modular inversion output data */
#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Modular substraction input data */
+/* Modular subtraction input data */
#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
-/* Modular substraction output data */
+/* Modular subtraction output data */
#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Montgomery multiplication input data */
@@ -8746,10 +8746,10 @@
#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
-#define RTC_CR_POL RTC_CR_POL_Msk /*!< Ouput polarity */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< Output polarity */
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
-#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration ouput selection */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< Calibration output selection */
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< Backup */
@@ -9024,7 +9024,7 @@
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Substract a fraction of a second */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< Subtract a fraction of a second */
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< Add on second */
@@ -10714,100 +10714,100 @@
/***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/
#define SYSCFG_SWPR1_PAGE0_Pos (0U)
#define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */
+#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */
#define SYSCFG_SWPR1_PAGE1_Pos (1U)
#define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */
+#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */
#define SYSCFG_SWPR1_PAGE2_Pos (2U)
#define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */
+#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */
#define SYSCFG_SWPR1_PAGE3_Pos (3U)
#define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */
+#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */
#define SYSCFG_SWPR1_PAGE4_Pos (4U)
#define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */
+#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */
#define SYSCFG_SWPR1_PAGE5_Pos (5U)
#define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */
+#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */
#define SYSCFG_SWPR1_PAGE6_Pos (6U)
#define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */
+#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */
#define SYSCFG_SWPR1_PAGE7_Pos (7U)
#define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */
+#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */
#define SYSCFG_SWPR1_PAGE8_Pos (8U)
#define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */
+#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */
#define SYSCFG_SWPR1_PAGE9_Pos (9U)
#define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */
+#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */
#define SYSCFG_SWPR1_PAGE10_Pos (10U)
#define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */
+#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */
#define SYSCFG_SWPR1_PAGE11_Pos (11U)
#define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */
+#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */
#define SYSCFG_SWPR1_PAGE12_Pos (12U)
#define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */
+#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */
#define SYSCFG_SWPR1_PAGE13_Pos (13U)
#define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */
+#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */
#define SYSCFG_SWPR1_PAGE14_Pos (14U)
#define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */
+#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */
#define SYSCFG_SWPR1_PAGE15_Pos (15U)
#define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */
+#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */
#define SYSCFG_SWPR1_PAGE16_Pos (16U)
#define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */
+#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */
#define SYSCFG_SWPR1_PAGE17_Pos (17U)
#define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */
+#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */
#define SYSCFG_SWPR1_PAGE18_Pos (18U)
#define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */
+#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */
#define SYSCFG_SWPR1_PAGE19_Pos (19U)
#define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */
+#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */
#define SYSCFG_SWPR1_PAGE20_Pos (20U)
#define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */
+#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */
#define SYSCFG_SWPR1_PAGE21_Pos (21U)
#define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */
+#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */
#define SYSCFG_SWPR1_PAGE22_Pos (22U)
#define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */
+#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */
#define SYSCFG_SWPR1_PAGE23_Pos (23U)
#define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */
+#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */
#define SYSCFG_SWPR1_PAGE24_Pos (24U)
#define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */
+#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */
#define SYSCFG_SWPR1_PAGE25_Pos (25U)
#define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */
+#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */
#define SYSCFG_SWPR1_PAGE26_Pos (26U)
#define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */
+#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */
#define SYSCFG_SWPR1_PAGE27_Pos (27U)
#define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */
+#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */
#define SYSCFG_SWPR1_PAGE28_Pos (28U)
#define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */
+#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */
#define SYSCFG_SWPR1_PAGE29_Pos (29U)
#define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */
+#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */
#define SYSCFG_SWPR1_PAGE30_Pos (30U)
#define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */
+#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */
#define SYSCFG_SWPR1_PAGE31_Pos (31U)
#define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */
+#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */
/***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/
#define SYSCFG_SKR_KEY_Pos (0U)
@@ -10817,100 +10817,100 @@
/***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/
#define SYSCFG_SWPR2_PAGE32_Pos (0U)
#define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */
-#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */
+#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */
#define SYSCFG_SWPR2_PAGE33_Pos (1U)
#define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */
-#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */
+#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */
#define SYSCFG_SWPR2_PAGE34_Pos (2U)
#define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */
-#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */
+#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */
#define SYSCFG_SWPR2_PAGE35_Pos (3U)
#define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */
-#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */
+#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */
#define SYSCFG_SWPR2_PAGE36_Pos (4U)
#define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */
-#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 0x200393FF) */
+#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */
#define SYSCFG_SWPR2_PAGE37_Pos (5U)
#define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */
-#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 0x200397FF) */
+#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */
#define SYSCFG_SWPR2_PAGE38_Pos (6U)
#define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */
-#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 0x20039BFF) */
+#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */
#define SYSCFG_SWPR2_PAGE39_Pos (7U)
#define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */
-#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 0x20039FFF) */
+#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */
#define SYSCFG_SWPR2_PAGE40_Pos (8U)
#define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */
-#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 0x2003A3FF) */
+#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */
#define SYSCFG_SWPR2_PAGE41_Pos (9U)
#define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */
-#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 0x2003A7FF) */
+#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */
#define SYSCFG_SWPR2_PAGE42_Pos (10U)
#define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */
-#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 0x2003ABFF) */
+#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */
#define SYSCFG_SWPR2_PAGE43_Pos (11U)
#define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */
-#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 0x2003AFFF) */
+#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */
#define SYSCFG_SWPR2_PAGE44_Pos (12U)
#define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */
-#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 0x2003B3FF) */
+#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */
#define SYSCFG_SWPR2_PAGE45_Pos (13U)
#define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */
-#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 0x2003B7FF) */
+#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */
#define SYSCFG_SWPR2_PAGE46_Pos (14U)
#define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */
-#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 0x2003BBFF) */
+#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */
#define SYSCFG_SWPR2_PAGE47_Pos (15U)
#define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */
-#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 0x2003BFFF) */
+#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */
#define SYSCFG_SWPR2_PAGE48_Pos (16U)
#define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */
-#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 0x2003C3FF) */
+#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */
#define SYSCFG_SWPR2_PAGE49_Pos (17U)
#define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */
-#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 0x2003C7FF) */
+#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */
#define SYSCFG_SWPR2_PAGE50_Pos (18U)
#define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */
-#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 0x2003CBFF) */
+#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */
#define SYSCFG_SWPR2_PAGE51_Pos (19U)
#define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */
-#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 0x2003CFFF) */
+#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */
#define SYSCFG_SWPR2_PAGE52_Pos (20U)
#define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */
-#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 0x2003D3FF) */
+#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */
#define SYSCFG_SWPR2_PAGE53_Pos (21U)
#define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */
-#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 0x2003D7FF) */
+#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */
#define SYSCFG_SWPR2_PAGE54_Pos (22U)
#define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */
-#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 0x2003DBFF) */
+#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */
#define SYSCFG_SWPR2_PAGE55_Pos (23U)
#define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */
-#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 0x2003DFFF) */
+#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */
#define SYSCFG_SWPR2_PAGE56_Pos (24U)
#define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */
-#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 0x2003E3FF) */
+#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */
#define SYSCFG_SWPR2_PAGE57_Pos (25U)
#define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */
-#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 0x2003E7FF) */
+#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */
#define SYSCFG_SWPR2_PAGE58_Pos (26U)
#define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */
-#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 0x2003EBFF) */
+#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */
#define SYSCFG_SWPR2_PAGE59_Pos (27U)
#define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */
-#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 0x2003EFFF) */
+#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */
#define SYSCFG_SWPR2_PAGE60_Pos (28U)
#define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */
-#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 0x2003F3FF) */
+#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */
#define SYSCFG_SWPR2_PAGE61_Pos (29U)
#define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */
-#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 0x2003F7FF) */
+#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */
#define SYSCFG_SWPR2_PAGE62_Pos (30U)
#define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */
-#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 0x2003FBFF) */
+#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */
#define SYSCFG_SWPR2_PAGE63_Pos (31U)
#define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */
-#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 0x2003FFFF) */
+#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */
/***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/
#define SYSCFG_IMR1_TIM1IM_Pos (13U)
@@ -13690,5 +13690,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32wbxx.h b/Include/stm32wbxx.h
index 1970597..c9b60bf 100644
--- a/Include/stm32wbxx.h
+++ b/Include/stm32wbxx.h
@@ -68,7 +68,7 @@
* @brief CMSIS Device version number
*/
#define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x09U) /*!< [23:16] sub1 version */
+#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x0AU) /*!< [23:16] sub1 version */
#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\
@@ -226,8 +226,3 @@
/**
* @}
*/
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/system_stm32wbxx.h b/Include/system_stm32wbxx.h
index 24dcb93..5915e83 100644
--- a/Include/system_stm32wbxx.h
+++ b/Include/system_stm32wbxx.h
@@ -63,7 +63,7 @@
extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */
-#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB10xx)
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx)
extern const uint32_t SmpsPrescalerTable[4][6]; /*!< SMPS factor ranges table values */
#endif
/**
@@ -108,5 +108,4 @@
/**
* @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+ */
diff --git a/LICENSE.md b/LICENSE.md
index 1a68e07..10aad3e 100644
--- a/LICENSE.md
+++ b/LICENSE.md
@@ -175,6 +175,16 @@
END OF TERMS AND CONDITIONS
+ APPENDIX: How to apply the Apache License to your work.
+
+ To apply the Apache License to your work, attach the following
+ boilerplate notice, with the fields enclosed by brackets "[]"
+ replaced with your own identifying information. (Don't include
+ the brackets!) The text should be enclosed in the appropriate
+ comment syntax for the file format. We also recommend that a
+ file or class name and description of purpose be included on the
+ same "printed page" as the copyright notice for easier
+ identification within third-party archives.
Copyright 2019 STMicroelectronics
diff --git a/README.md b/README.md
index 80816e3..6f10f0f 100644
--- a/README.md
+++ b/README.md
@@ -40,6 +40,7 @@
Tag v1.7.0 | Tag v5.6.0_cm4 | Tag v1.10.0
Tag v1.8.0 | Tag v5.6.0_cm4 | Tag v1.11.0
Tag v1.9.0 | Tag v5.6.0_cm4 | Tag v1.12.0
+Tag v1.10.0 | Tag v5.6.0_cm4 | Tag v1.13.0
The full **STM32CubeWB** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWB).
diff --git a/Release_Notes.html b/Release_Notes.html
index 4964b92..74db9dd 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -89,10 +89,25 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section9" checked aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.9.0 / 24-June-2021</label>
+<input type="checkbox" id="collapse-section10" checked aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.10.0 / 12-November-2021</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
+<li>Update CMSIS devices drivers for all value lines not supporting SMPS</li>
+<li>All source files and templates: update disclaimer to add reference to the new license agreement</li>
+<li>Correct English spelling typos and remove non UTF-8 characters in comments</li>
+</ul>
+<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<ul>
+<li>STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.9.0 / 24-June-2021</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
<li>Add atomic register access services:
<ul>
<li>32-bit register access: ATOMIC_SET_BIT(), ATOMIC_CLEAR_BIT(), ATOMIC_MODIFY_REG()</li>
@@ -105,7 +120,7 @@
<li>Add define LSI_STARTUP_TIME used in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT)</li>
<li>Add define FLASH_ECCR_CPUID bits for new macro __HAL_FLASH_ECC_CPUID() macro</li>
</ul>
-<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
<ul>
<li>STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.</li>
</ul>
@@ -114,7 +129,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.8.0 / 09-February-2021</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<h3 id="add-support-for-stm32wb15xx-and-stm32wb10xx">Add support for STM32WB15xx and STM32WB10xx</h3>
<ul>
<li>Change how to adapt VTOR for user</li>
@@ -125,7 +140,7 @@
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
</ul>
-<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
<ul>
<li>STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx and STM32WB10xx devices.</li>
</ul>
@@ -134,7 +149,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.7.0 / 30-October-2020</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<p>Maintenance release for <strong>STM32WBxx</strong> devices (stm32wb55xx, stm32wb50xx, stm32wb35xx and stm32wb30xx devices)</p>
<table>
@@ -164,7 +179,7 @@
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
</ul>
-<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2>
<ul>
<li>STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.</li>
</ul>
@@ -173,7 +188,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">v1.6.0 / 05-June-2020</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<h3 id="maintenance-release-1">Maintenance release</h3>
<p>Maintenance release for <strong>STM32WBxx</strong> devices (stm32wb55xx, stm32wb50xx, stm32wb35xx and stm32wb30xx devices)</p>
<table>
@@ -212,7 +227,7 @@
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
</ul>
-<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-4">Supported Devices and boards</h2>
<ul>
<li>STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.</li>
</ul>
@@ -221,7 +236,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.4.0 / 12-February-2020</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<h3 id="introduction-of-stm32wb35xx-stm32wb30xx-and-stm32wb5mxx-product">Introduction of STM32WB35xx, STM32WB30xx and STM32WB5Mxx product</h3>
<p>This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.</p>
<p>Added features:</p>
@@ -239,7 +254,7 @@
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
</ul>
-<h2 id="supported-devices-and-boards-4">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-5">Supported Devices and boards</h2>
<ul>
<li>STM32WB55xx, STM32WB5Mxx, STM32WB50xx, STM32WB35xx and STM32WB30xx devices.</li>
</ul>
@@ -248,7 +263,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.3.0 / 11-September-2019</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<p>Maintenance release for <strong>STM32WBxx</strong> devices (stm32wb55xx and stm32wb50xx devices)</p>
<table>
<thead>
@@ -277,7 +292,7 @@
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
</ul>
-<h2 id="supported-devices-and-boards-5">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-6">Supported Devices and boards</h2>
<ul>
<li>STM32WB55xx, STM32WB50xx devices</li>
</ul>
@@ -286,7 +301,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<h3 id="introduction-of-stm32wb50xx-device">Introduction of STM32WB50xx device</h3>
<p>First release for STM32WBxx CMSIS introducing <strong>stm32wb50xx</strong> devices.</p>
<h2 id="contents">Contents</h2>
@@ -297,7 +312,7 @@
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
</ul>
-<h2 id="supported-devices-and-boards-6">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-7">Supported Devices and boards</h2>
<ul>
<li>STM32WB55xx and STM32WB50xx devices</li>
</ul>
@@ -306,7 +321,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<h3 id="maintenance-release-2">Maintenance release</h3>
<p>Maintenance release for <strong>STM32WBxx</strong> devices (stm32wb55xx devices)</p>
<table>
@@ -330,7 +345,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>Add support of STM32WB55xx.</p>
</div>
diff --git a/Source/Templates/arm/startup_stm32wb10xx_cm0.s b/Source/Templates/arm/startup_stm32wb10xx_cm0.s
deleted file mode 100644
index c476b3c..0000000
--- a/Source/Templates/arm/startup_stm32wb10xx_cm0.s
+++ /dev/null
@@ -1,235 +0,0 @@
-;******************************************************************************
-;* File Name : startup_stm32wb10xx_cm0.s
-;* Author : MCD Application Team
-;* Description : STM32WB10xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0+ processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2019-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
- DCD 0 ; Reserved
-
- ; External Interrupts
- DCD PVD_PVM_IRQHandler ; PVD and PVM detector
- DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) and LSECSS Interrupts
- DCD 0 ; Reserved
- DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
- DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
- DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
- DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
- DCD TSC_IRQHandler ; TSC Interrupt
- DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
- DCD DMAMUX1_OVR_IRQHandler ; DMAMUX Overrun Interrupts
- DCD ADC1_IRQHandler ; ADC1 Interrupt
- DCD LPTIM1_IRQHandler ; LPTIM1 Channel 5 Interrupt
- DCD LPTIM2_IRQHandler ; LPTIM2 Channel 6 Interrupt
- DCD TIM1_IRQHandler ; TIM1 Interrupt
- DCD TIM2_IRQHandler ; TIM2 Interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD IPCC_C2_RX_C2_TX_HSEM_IRQHandler ; IPCC RX Occupied and TX Free Interrupt and Semaphore Interrupt
- DCD RNG_PKA_IRQHandler ; RNG and PKA Interrupt
- DCD AES2_IRQHandler ; AES2 Interrupt
- DCD 0 ; Reserved
- DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
- DCD 0 ; Reserved
- DCD SPI1_IRQHandler ; SPI1 Interrupts
- DCD 0 ; Reserved
- DCD USART1_IRQHandler ; USART1 Interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD BLE_IRQHandler ; BLE Interrupt
- DCD 0 ; Reserved
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
- EXPORT PVD_PVM_IRQHandler [WEAK]
- EXPORT RTC_LSECSS_IRQHandler [WEAK]
- EXPORT USB_CRS_IRQHandler [WEAK]
- EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
- EXPORT EXTI1_0_IRQHandler [WEAK]
- EXPORT EXTI3_2_IRQHandler [WEAK]
- EXPORT EXTI15_4_IRQHandler [WEAK]
- EXPORT TSC_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
- EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
- EXPORT ADC1_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
- EXPORT LPTIM2_IRQHandler [WEAK]
- EXPORT TIM1_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT IPCC_C2_RX_C2_TX_HSEM_IRQHandler [WEAK]
- EXPORT RNG_PKA_IRQHandler [WEAK]
- EXPORT AES2_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT BLE_IRQHandler [WEAK]
-
-PVD_PVM_IRQHandler
-RTC_LSECSS_IRQHandler
-USB_CRS_IRQHandler
-RCC_FLASH_C1SEV_IRQHandler
-EXTI1_0_IRQHandler
-EXTI3_2_IRQHandler
-EXTI15_4_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-DMAMUX1_OVR_IRQHandler
-ADC1_IRQHandler
-LPTIM1_IRQHandler
-LPTIM2_IRQHandler
-TIM1_IRQHandler
-TIM2_IRQHandler
-IPCC_C2_RX_C2_TX_HSEM_IRQHandler
-RNG_PKA_IRQHandler
-AES2_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-BLE_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32wb10xx_cm4.s b/Source/Templates/arm/startup_stm32wb10xx_cm4.s
index 3f29cc6..589d3fb 100644
--- a/Source/Templates/arm/startup_stm32wb10xx_cm4.s
+++ b/Source/Templates/arm/startup_stm32wb10xx_cm4.s
@@ -84,7 +84,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -329,4 +329,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32wb15xx_cm0.s b/Source/Templates/arm/startup_stm32wb15xx_cm0.s
deleted file mode 100644
index 6b1e33b..0000000
--- a/Source/Templates/arm/startup_stm32wb15xx_cm0.s
+++ /dev/null
@@ -1,237 +0,0 @@
-;******************************************************************************
-;* File Name : startup_stm32wb15xx_cm0.s
-;* Author : MCD Application Team
-;* Description : STM32WB15xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0+ processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2019-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
- DCD 0 ; Reserved
-
- ; External Interrupts
- DCD PVD_PVM_IRQHandler ; PVD and PVM detector
- DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) and LSECSS Interrupts
- DCD 0 ; Reserved
- DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
- DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
- DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
- DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
- DCD TSC_IRQHandler ; TSC Interrupt
- DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
- DCD DMAMUX1_OVR_IRQHandler ; DMAMUX Overrun Interrupts
- DCD ADC1_COMP_IRQHandler ; ADC1 and COMP1 Interrupt
- DCD LPTIM1_IRQHandler ; LPTIM1 Channel 5 Interrupt
- DCD LPTIM2_IRQHandler ; LPTIM2 Channel 6 Interrupt
- DCD TIM1_IRQHandler ; TIM1 Interrupt
- DCD TIM2_IRQHandler ; TIM2 Interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD IPCC_C2_RX_C2_TX_HSEM_IRQHandler ; IPCC RX Occupied and TX Free Interrupt and Semaphore Interrupt
- DCD RNG_PKA_IRQHandler ; RNG and PKA Interrupt
- DCD AES2_IRQHandler ; AES2 Interrupt
- DCD 0 ; Reserved
- DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
- DCD 0 ; Reserved
- DCD SPI1_IRQHandler ; SPI1 Interrupts
- DCD 0 ; Reserved
- DCD USART1_IRQHandler ; USART1 Interrupt
- DCD LPUART1_IRQHandler ; LPUART1 Interrupt
- DCD 0 ; Reserved
- DCD BLE_IRQHandler ; BLE Interrupt
- DCD 0 ; Reserved
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
- EXPORT PVD_PVM_IRQHandler [WEAK]
- EXPORT RTC_LSECSS_IRQHandler [WEAK]
- EXPORT USB_CRS_IRQHandler [WEAK]
- EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
- EXPORT EXTI1_0_IRQHandler [WEAK]
- EXPORT EXTI3_2_IRQHandler [WEAK]
- EXPORT EXTI15_4_IRQHandler [WEAK]
- EXPORT TSC_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
- EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
- EXPORT ADC1_COMP_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
- EXPORT LPTIM2_IRQHandler [WEAK]
- EXPORT TIM1_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT IPCC_C2_RX_C2_TX_HSEM_IRQHandler [WEAK]
- EXPORT RNG_PKA_IRQHandler [WEAK]
- EXPORT AES2_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT LPUART1_IRQHandler [WEAK]
- EXPORT BLE_IRQHandler [WEAK]
-
-PVD_PVM_IRQHandler
-RTC_LSECSS_IRQHandler
-USB_CRS_IRQHandler
-RCC_FLASH_C1SEV_IRQHandler
-EXTI1_0_IRQHandler
-EXTI3_2_IRQHandler
-EXTI15_4_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-DMAMUX1_OVR_IRQHandler
-ADC1_COMP_IRQHandler
-LPTIM1_IRQHandler
-LPTIM2_IRQHandler
-TIM1_IRQHandler
-TIM2_IRQHandler
-IPCC_C2_RX_C2_TX_HSEM_IRQHandler
-RNG_PKA_IRQHandler
-AES2_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-LPUART1_IRQHandler
-BLE_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32wb15xx_cm4.s b/Source/Templates/arm/startup_stm32wb15xx_cm4.s
index bdd4a9e..fa891d1 100644
--- a/Source/Templates/arm/startup_stm32wb15xx_cm4.s
+++ b/Source/Templates/arm/startup_stm32wb15xx_cm4.s
@@ -84,7 +84,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -333,4 +333,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32wb30xx_cm4.s b/Source/Templates/arm/startup_stm32wb30xx_cm4.s
index b33359a..9313457 100644
--- a/Source/Templates/arm/startup_stm32wb30xx_cm4.s
+++ b/Source/Templates/arm/startup_stm32wb30xx_cm4.s
@@ -84,7 +84,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -325,4 +325,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32wb35xx_cm0.s b/Source/Templates/arm/startup_stm32wb35xx_cm0.s
deleted file mode 100644
index 66f6ff7..0000000
--- a/Source/Templates/arm/startup_stm32wb35xx_cm0.s
+++ /dev/null
@@ -1,246 +0,0 @@
-;******************************************************************************
-;* File Name : startup_stm32wb35xx_cm0.s
-;* Author : MCD Application Team
-;* Description : STM32WB35xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0+ processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2019-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
- DCD 0 ; Reserved
-
- ; External Interrupts
- DCD PVD_PVM_IRQHandler ; PVD and PVM detector
- DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) and LSECSS Interrupts
- DCD USB_CRS_IRQHandler ; USB High Priority, Low Priority (including USB wakeup) and CRS Interrupts
- DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupt
- DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
- DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
- DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
- DCD _802_0_IRQHandler ; 802.15.4 Interrupt 0
- DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
- DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
- DCD ADC1_COMP_IRQHandler ; ADC1 and COMP1 COMP2 Interrupt
- DCD LPTIM1_IRQHandler ; LPTIM1 Channel 5 Interrupt
- DCD LPTIM2_IRQHandler ; LPTIM2 Channel 6 Interrupt
- DCD TIM1_IRQHandler ; TIM1 Interrupt
- DCD TIM2_IRQHandler ; TIM2 Interrupt
- DCD TIM16_IRQHandler ; TIM16 Interrupt
- DCD TIM17_IRQHandler ; TIM17 Interrupt
- DCD IPCC_C2_RX_C2_TX_HSEM_IRQHandler ; IPCC RX Occupied and TX Free Interrupt and Semaphore Interrupt
- DCD AES1_RNG_PKA_IRQHandler ; AES1,RNG and PKA Interrupt
- DCD AES2_IRQHandler ; AES2 Interrupt
- DCD _802_1_IRQHandler ; 802.15.4 interrupt 1
- DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
- DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
- DCD SPI1_IRQHandler ; SPI1 Interrupts
- DCD USART1_IRQHandler ; USART1 Interrupt
- DCD LPUART1_IRQHandler ; LPUART1 Interrupt
- DCD 0 ; Reserved
- DCD BLE_IRQHandler ; BLE Interrupt
- DCD _802_2_HOST_WKUP_IRQHandler ; 802.15.4 Interrupt
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
- EXPORT PVD_PVM_IRQHandler [WEAK]
- EXPORT RTC_LSECSS_IRQHandler [WEAK]
- EXPORT USB_CRS_IRQHandler [WEAK]
- EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
- EXPORT EXTI1_0_IRQHandler [WEAK]
- EXPORT EXTI3_2_IRQHandler [WEAK]
- EXPORT EXTI15_4_IRQHandler [WEAK]
- EXPORT _802_0_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
- EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
- EXPORT ADC1_COMP_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
- EXPORT LPTIM2_IRQHandler [WEAK]
- EXPORT TIM1_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT IPCC_C2_RX_C2_TX_HSEM_IRQHandler [WEAK]
- EXPORT AES1_RNG_PKA_IRQHandler [WEAK]
- EXPORT AES2_IRQHandler [WEAK]
- EXPORT _802_1_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT I2C3_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT LPUART1_IRQHandler [WEAK]
- EXPORT BLE_IRQHandler [WEAK]
- EXPORT _802_2_HOST_WKUP_IRQHandler [WEAK]
-
-PVD_PVM_IRQHandler
-RTC_LSECSS_IRQHandler
-USB_CRS_IRQHandler
-RCC_FLASH_C1SEV_IRQHandler
-EXTI1_0_IRQHandler
-EXTI3_2_IRQHandler
-EXTI15_4_IRQHandler
-_802_0_IRQHandler
-DMA1_Channel1_2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-DMA2_DMAMUX1_OVR_IRQHandler
-ADC1_COMP_IRQHandler
-LPTIM1_IRQHandler
-LPTIM2_IRQHandler
-TIM1_IRQHandler
-TIM2_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-IPCC_C2_RX_C2_TX_HSEM_IRQHandler
-AES1_RNG_PKA_IRQHandler
-AES2_IRQHandler
-_802_1_IRQHandler
-I2C1_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-LPUART1_IRQHandler
-BLE_IRQHandler
-_802_2_HOST_WKUP_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32wb35xx_cm4.s b/Source/Templates/arm/startup_stm32wb35xx_cm4.s
index d045d5d..2c2c129 100644
--- a/Source/Templates/arm/startup_stm32wb35xx_cm4.s
+++ b/Source/Templates/arm/startup_stm32wb35xx_cm4.s
@@ -84,7 +84,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -357,4 +357,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32wb50xx_cm4.s b/Source/Templates/arm/startup_stm32wb50xx_cm4.s
index b48c38e..39bb66f 100644
--- a/Source/Templates/arm/startup_stm32wb50xx_cm4.s
+++ b/Source/Templates/arm/startup_stm32wb50xx_cm4.s
@@ -84,7 +84,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -325,4 +325,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32wb55xx_cm0.s b/Source/Templates/arm/startup_stm32wb55xx_cm0.s
deleted file mode 100644
index b2232c2..0000000
--- a/Source/Templates/arm/startup_stm32wb55xx_cm0.s
+++ /dev/null
@@ -1,251 +0,0 @@
-;******************************************************************************
-;* File Name : startup_stm32wb55xx_cm0.s
-;* Author : MCD Application Team
-;* Description : STM32WB55xx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0+ processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2019-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
- DCD 0 ; Reserved
-
- ; External Interrupts
- DCD PVD_PVM_IRQHandler ; PVD and PVM detector
- DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) and LSECSS Interrupts
- DCD USB_CRS_IRQHandler ; USB High Priority, Low Priority (including USB wakeup) and CRS Interrupts
- DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
- DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
- DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
- DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
- DCD TSC_802_0_IRQHandler ; TSC Interrupt
- DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
- DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
- DCD ADC1_COMP_IRQHandler ; ADC1 and COMP1 COMP2 Interrupt
- DCD LPTIM1_IRQHandler ; LPTIM1 Channel 5 Interrupt
- DCD LPTIM2_IRQHandler ; LPTIM2 Channel 6 Interrupt
- DCD TIM1_IRQHandler ; TIM1 Interrupt
- DCD TIM2_IRQHandler ; TIM2 Interrupt
- DCD TIM16_IRQHandler ; TIM16 Interrupt
- DCD TIM17_IRQHandler ; TIM17 Interrupt
- DCD IPCC_C2_RX_C2_TX_HSEM_IRQHandler ; IPCC RX Occupied and TX Free Interrupt and Semaphore Interrupt
- DCD AES1_RNG_PKA_IRQHandler ; AES1, RNG and PKA Interrupt
- DCD AES2_IRQHandler ; AES2 Interrupt
- DCD LCD_802_1_IRQHandler ; LCD Interrupt and 802.15.4 interrupt 1
- DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
- DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
- DCD SPI1_IRQHandler ; SPI1 Interrupts
- DCD SPI2_IRQHandler ; SPI2 Interrupt
- DCD USART1_IRQHandler ; USART1 Interrupt
- DCD LPUART1_IRQHandler ; LPUART1 Interrupt
- DCD SAI1_IRQHandler ; SAI1 Interrupt
- DCD BLE_IRQHandler ; BLE Interrupt
- DCD _802_2_HOST_WKUP_IRQHandler ; 802.15.4 Interrupt
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
- EXPORT PVD_PVM_IRQHandler [WEAK]
- EXPORT RTC_LSECSS_IRQHandler [WEAK]
- EXPORT USB_CRS_IRQHandler [WEAK]
- EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
- EXPORT EXTI1_0_IRQHandler [WEAK]
- EXPORT EXTI3_2_IRQHandler [WEAK]
- EXPORT EXTI15_4_IRQHandler [WEAK]
- EXPORT TSC_802_0_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
- EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
- EXPORT ADC1_COMP_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
- EXPORT LPTIM2_IRQHandler [WEAK]
- EXPORT TIM1_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT IPCC_C2_RX_C2_TX_HSEM_IRQHandler [WEAK]
- EXPORT AES1_RNG_PKA_IRQHandler [WEAK]
- EXPORT AES2_IRQHandler [WEAK]
- EXPORT LCD_802_1_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT I2C3_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT LPUART1_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT BLE_IRQHandler [WEAK]
- EXPORT _802_2_HOST_WKUP_IRQHandler [WEAK]
-
-PVD_PVM_IRQHandler
-RTC_LSECSS_IRQHandler
-USB_CRS_IRQHandler
-RCC_FLASH_C1SEV_IRQHandler
-EXTI1_0_IRQHandler
-EXTI3_2_IRQHandler
-EXTI15_4_IRQHandler
-TSC_802_0_IRQHandler
-DMA1_Channel1_2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-DMA2_DMAMUX1_OVR_IRQHandler
-ADC1_COMP_IRQHandler
-LPTIM1_IRQHandler
-LPTIM2_IRQHandler
-TIM1_IRQHandler
-TIM2_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-IPCC_C2_RX_C2_TX_HSEM_IRQHandler
-AES1_RNG_PKA_IRQHandler
-AES2_IRQHandler
-LCD_802_1_IRQHandler
-I2C1_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-LPUART1_IRQHandler
-SAI1_IRQHandler
-BLE_IRQHandler
-_802_2_HOST_WKUP_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32wb55xx_cm4.s b/Source/Templates/arm/startup_stm32wb55xx_cm4.s
index 08143df..b42b6d1 100644
--- a/Source/Templates/arm/startup_stm32wb55xx_cm4.s
+++ b/Source/Templates/arm/startup_stm32wb55xx_cm4.s
@@ -84,7 +84,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -365,4 +365,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32wb5mxx_cm0.s b/Source/Templates/arm/startup_stm32wb5mxx_cm0.s
deleted file mode 100644
index 4a13b2a..0000000
--- a/Source/Templates/arm/startup_stm32wb5mxx_cm0.s
+++ /dev/null
@@ -1,251 +0,0 @@
-;******************************************************************************
-;* File Name : startup_stm32wb5mxx_cm0.s
-;* Author : MCD Application Team
-;* Description : STM32WB5Mxx devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0+ processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2019-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
- DCD 0 ; Reserved
-
- ; External Interrupts
- DCD PVD_PVM_IRQHandler ; PVD and PVM detector
- DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) and LSECSS Interrupts
- DCD USB_CRS_IRQHandler ; USB High Priority, Low Priority (including USB wakeup) and CRS Interrupts
- DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupt
- DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
- DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
- DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
- DCD TSC_802_0_IRQHandler ; TSC Interrupt
- DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
- DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
- DCD ADC1_COMP_IRQHandler ; ADC1 and COMP1 COMP2 Interrupt
- DCD LPTIM1_IRQHandler ; LPTIM1 Channel 5 Interrupt
- DCD LPTIM2_IRQHandler ; LPTIM2 Channel 6 Interrupt
- DCD TIM1_IRQHandler ; TIM1 Interrupt
- DCD TIM2_IRQHandler ; TIM2 Interrupt
- DCD TIM16_IRQHandler ; TIM16 Interrupt
- DCD TIM17_IRQHandler ; TIM17 Interrupt
- DCD IPCC_C2_RX_C2_TX_HSEM_IRQHandler ; IPCC RX Occupied and TX Free Interrupt and Semaphore Interrupt
- DCD AES1_RNG_PKA_IRQHandler ; AES1,RNG and PKA Interrupt
- DCD AES2_IRQHandler ; AES2 Interrupt
- DCD LCD_802_1_IRQHandler ; LCD Interrupt and 802.15.4 interrupt 1
- DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
- DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
- DCD SPI1_IRQHandler ; SPI1 Interrupts
- DCD SPI2_IRQHandler ; SPI2 Interrupt
- DCD USART1_IRQHandler ; USART1 Interrupt
- DCD LPUART1_IRQHandler ; LPUART1 Interrupt
- DCD SAI1_IRQHandler ; SAI1 Interrupt
- DCD BLE_IRQHandler ; BLE Interrupt
- DCD _802_2_HOST_WKUP_IRQHandler ; 802.15.4 Interrupt
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
- EXPORT PVD_PVM_IRQHandler [WEAK]
- EXPORT RTC_LSECSS_IRQHandler [WEAK]
- EXPORT USB_CRS_IRQHandler [WEAK]
- EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
- EXPORT EXTI1_0_IRQHandler [WEAK]
- EXPORT EXTI3_2_IRQHandler [WEAK]
- EXPORT EXTI15_4_IRQHandler [WEAK]
- EXPORT TSC_802_0_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
- EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
- EXPORT ADC1_COMP_IRQHandler [WEAK]
- EXPORT LPTIM1_IRQHandler [WEAK]
- EXPORT LPTIM2_IRQHandler [WEAK]
- EXPORT TIM1_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT IPCC_C2_RX_C2_TX_HSEM_IRQHandler [WEAK]
- EXPORT AES1_RNG_PKA_IRQHandler [WEAK]
- EXPORT AES2_IRQHandler [WEAK]
- EXPORT LCD_802_1_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT I2C3_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT LPUART1_IRQHandler [WEAK]
- EXPORT SAI1_IRQHandler [WEAK]
- EXPORT BLE_IRQHandler [WEAK]
- EXPORT _802_2_HOST_WKUP_IRQHandler [WEAK]
-
-PVD_PVM_IRQHandler
-RTC_LSECSS_IRQHandler
-USB_CRS_IRQHandler
-RCC_FLASH_C1SEV_IRQHandler
-EXTI1_0_IRQHandler
-EXTI3_2_IRQHandler
-EXTI15_4_IRQHandler
-TSC_802_0_IRQHandler
-DMA1_Channel1_2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-DMA2_DMAMUX1_OVR_IRQHandler
-ADC1_COMP_IRQHandler
-LPTIM1_IRQHandler
-LPTIM2_IRQHandler
-TIM1_IRQHandler
-TIM2_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-IPCC_C2_RX_C2_TX_HSEM_IRQHandler
-AES1_RNG_PKA_IRQHandler
-AES2_IRQHandler
-LCD_802_1_IRQHandler
-I2C1_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-LPUART1_IRQHandler
-SAI1_IRQHandler
-BLE_IRQHandler
-_802_2_HOST_WKUP_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32wb5mxx_cm4.s b/Source/Templates/arm/startup_stm32wb5mxx_cm4.s
index 041c26a..70adf04 100644
--- a/Source/Templates/arm/startup_stm32wb5mxx_cm4.s
+++ b/Source/Templates/arm/startup_stm32wb5mxx_cm4.s
@@ -84,7 +84,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -365,4 +365,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/gcc/linker/stm32wb10xx_flash_cm4.ld b/Source/Templates/gcc/linker/stm32wb10xx_flash_cm4.ld
index 7f4d1e3..e6aa078 100644
--- a/Source/Templates/gcc/linker/stm32wb10xx_flash_cm4.ld
+++ b/Source/Templates/gcc/linker/stm32wb10xx_flash_cm4.ld
@@ -22,13 +22,12 @@
*****************************************************************************
** @attention
**
-** <h2><center>© Copyright (c) 2020 STMicroelectronics.
-** All rights reserved.</center></h2>
+** Copyright (c) 2020 STMicroelectronics.
+** All rights reserved.
**
-** This software component is licensed by ST under BSD 3-Clause license,
-** the "License"; You may not use this file except in compliance with the
-** License. You may obtain a copy of the License at:
-** opensource.org/licenses/BSD-3-Clause
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
**
*****************************************************************************
*/
@@ -137,7 +136,7 @@
. = ALIGN(4);
.bss :
{
- /* This is used by the startup in order to initialize the .bss secion */
+ /* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
diff --git a/Source/Templates/gcc/linker/stm32wb15xx_flash_cm4.ld b/Source/Templates/gcc/linker/stm32wb15xx_flash_cm4.ld
index 7f4d1e3..e6aa078 100644
--- a/Source/Templates/gcc/linker/stm32wb15xx_flash_cm4.ld
+++ b/Source/Templates/gcc/linker/stm32wb15xx_flash_cm4.ld
@@ -22,13 +22,12 @@
*****************************************************************************
** @attention
**
-** <h2><center>© Copyright (c) 2020 STMicroelectronics.
-** All rights reserved.</center></h2>
+** Copyright (c) 2020 STMicroelectronics.
+** All rights reserved.
**
-** This software component is licensed by ST under BSD 3-Clause license,
-** the "License"; You may not use this file except in compliance with the
-** License. You may obtain a copy of the License at:
-** opensource.org/licenses/BSD-3-Clause
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
**
*****************************************************************************
*/
@@ -137,7 +136,7 @@
. = ALIGN(4);
.bss :
{
- /* This is used by the startup in order to initialize the .bss secion */
+ /* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
diff --git a/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld b/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld
index 79be458..7743fd9 100644
--- a/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld
+++ b/Source/Templates/gcc/linker/stm32wb30xx_flash_cm4.ld
@@ -15,30 +15,14 @@
** of any kind.
**
*****************************************************************************
+** @attention
**
-** <h2><center>© COPYRIGHT(c) 2019 Ac6</center></h2>
+** Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.
**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-** 1. Redistributions of source code must retain the above copyright notice,
-** this list of conditions and the following disclaimer.
-** 2. Redistributions in binary form must reproduce the above copyright notice,
-** this list of conditions and the following disclaimer in the documentation
-** and/or other materials provided with the distribution.
-** 3. Neither the name of Ac6 nor the names of its contributors
-** may be used to endorse or promote products derived from this software
-** without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
**
*****************************************************************************
*/
@@ -145,7 +129,7 @@
. = ALIGN(4);
.bss :
{
- /* This is used by the startup in order to initialize the .bss secion */
+ /* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
diff --git a/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld b/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld
index 18b3958..dead7a9 100644
--- a/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld
+++ b/Source/Templates/gcc/linker/stm32wb35xx_flash_cm4.ld
@@ -15,30 +15,14 @@
** of any kind.
**
*****************************************************************************
+** @attention
**
-** <h2><center>© COPYRIGHT(c) 2019 Ac6</center></h2>
+** Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.
**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-** 1. Redistributions of source code must retain the above copyright notice,
-** this list of conditions and the following disclaimer.
-** 2. Redistributions in binary form must reproduce the above copyright notice,
-** this list of conditions and the following disclaimer in the documentation
-** and/or other materials provided with the distribution.
-** 3. Neither the name of Ac6 nor the names of its contributors
-** may be used to endorse or promote products derived from this software
-** without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
**
*****************************************************************************
*/
@@ -145,7 +129,7 @@
. = ALIGN(4);
.bss :
{
- /* This is used by the startup in order to initialize the .bss secion */
+ /* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
diff --git a/Source/Templates/gcc/linker/stm32wb50xx_flash_cm4.ld b/Source/Templates/gcc/linker/stm32wb50xx_flash_cm4.ld
index cad41e0..4a8bd3f 100644
--- a/Source/Templates/gcc/linker/stm32wb50xx_flash_cm4.ld
+++ b/Source/Templates/gcc/linker/stm32wb50xx_flash_cm4.ld
@@ -15,30 +15,14 @@
** of any kind.
**
*****************************************************************************
+** @attention
**
-** <h2><center>© COPYRIGHT(c) 2019 Ac6</center></h2>
+** Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.
**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-** 1. Redistributions of source code must retain the above copyright notice,
-** this list of conditions and the following disclaimer.
-** 2. Redistributions in binary form must reproduce the above copyright notice,
-** this list of conditions and the following disclaimer in the documentation
-** and/or other materials provided with the distribution.
-** 3. Neither the name of Ac6 nor the names of its contributors
-** may be used to endorse or promote products derived from this software
-** without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
**
*****************************************************************************
*/
@@ -145,7 +129,7 @@
. = ALIGN(4);
.bss :
{
- /* This is used by the startup in order to initialize the .bss secion */
+ /* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
diff --git a/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld b/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld
index 840a642..660f301 100644
--- a/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld
+++ b/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld
@@ -15,30 +15,14 @@
** of any kind.
**
*****************************************************************************
+** @attention
**
-** <h2><center>© COPYRIGHT(c) 2019 Ac6</center></h2>
+** Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.
**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-** 1. Redistributions of source code must retain the above copyright notice,
-** this list of conditions and the following disclaimer.
-** 2. Redistributions in binary form must reproduce the above copyright notice,
-** this list of conditions and the following disclaimer in the documentation
-** and/or other materials provided with the distribution.
-** 3. Neither the name of Ac6 nor the names of its contributors
-** may be used to endorse or promote products derived from this software
-** without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
**
*****************************************************************************
*/
@@ -145,7 +129,7 @@
. = ALIGN(4);
.bss :
{
- /* This is used by the startup in order to initialize the .bss secion */
+ /* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
diff --git a/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld b/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld
index eab2c6e..d1d82de 100644
--- a/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld
+++ b/Source/Templates/gcc/linker/stm32wb5mxx_flash_cm4.ld
@@ -15,30 +15,14 @@
** of any kind.
**
*****************************************************************************
+** @attention
**
-** <h2><center>© COPYRIGHT(c) 2019 Ac6</center></h2>
+** Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.
**
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-** 1. Redistributions of source code must retain the above copyright notice,
-** this list of conditions and the following disclaimer.
-** 2. Redistributions in binary form must reproduce the above copyright notice,
-** this list of conditions and the following disclaimer in the documentation
-** and/or other materials provided with the distribution.
-** 3. Neither the name of Ac6 nor the names of its contributors
-** may be used to endorse or promote products derived from this software
-** without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
**
*****************************************************************************
*/
@@ -145,7 +129,7 @@
. = ALIGN(4);
.bss :
{
- /* This is used by the startup in order to initialize the .bss secion */
+ /* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
diff --git a/Source/Templates/gcc/startup_stm32wb10xx_cm0.s b/Source/Templates/gcc/startup_stm32wb10xx_cm0.s
deleted file mode 100644
index 28eda2f..0000000
--- a/Source/Templates/gcc/startup_stm32wb10xx_cm0.s
+++ /dev/null
@@ -1,259 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32wb10xx_cm0.s
- * @author MCD Application Team
- * @brief STM32WB10xx devices vector table GCC toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0+ processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019-2021 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
- bl SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
- ldr r0, =_sdata
- ldr r1, =_edata
- ldr r2, =_sidata
- movs r3, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r4, [r2, r3]
- str r4, [r0, r3]
- adds r3, r3, #4
-
-LoopCopyDataInit:
- adds r4, r0, r3
- cmp r4, r1
- bcc CopyDataInit
-
-/* Zero fill the bss segment. */
- ldr r2, =_sbss
- ldr r4, =_ebss
- movs r3, #0
- b LoopFillZerobss
-
-FillZerobss:
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZerobss:
- cmp r2, r4
- bcc FillZerobss
-
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application s entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word 0
- .word PVD_PVM_IRQHandler
- .word RTC_LSECSS_IRQHandler
- .word 0
- .word RCC_FLASH_C1SEV_IRQHandler
- .word EXTI1_0_IRQHandler
- .word EXTI3_2_IRQHandler
- .word EXTI15_4_IRQHandler
- .word TSC_IRQHandler
- .word DMA1_Channel1_2_3_IRQHandler
- .word DMA1_Channel4_5_6_7_IRQHandler
- .word DMAMUX1_OVR_IRQHandler
- .word ADC1_IRQHandler
- .word LPTIM1_IRQHandler
- .word LPTIM2_IRQHandler
- .word TIM1_IRQHandler
- .word TIM2_IRQHandler
- .word 0
- .word 0
- .word IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- .word RNG_PKA_IRQHandler
- .word AES2_IRQHandler
- .word 0
- .word I2C1_IRQHandler
- .word 0
- .word SPI1_IRQHandler
- .word 0
- .word USART1_IRQHandler
- .word 0
- .word 0
- .word BLE_IRQHandler
- .word 0
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak PVD_PVM_IRQHandler
- .thumb_set PVD_PVM_IRQHandler,Default_Handler
-
- .weak RTC_LSECSS_IRQHandler
- .thumb_set RTC_LSECSS_IRQHandler,Default_Handler
-
- .weak RCC_FLASH_C1SEV_IRQHandler
- .thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
-
- .weak EXTI1_0_IRQHandler
- .thumb_set EXTI1_0_IRQHandler,Default_Handler
-
- .weak EXTI3_2_IRQHandler
- .thumb_set EXTI3_2_IRQHandler,Default_Handler
-
- .weak EXTI15_4_IRQHandler
- .thumb_set EXTI15_4_IRQHandler,Default_Handler
-
- .weak TSC_IRQHandler
- .thumb_set TSC_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_2_3_IRQHandler
- .thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_6_7_IRQHandler
- .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
- .weak DMAMUX1_OVR_IRQHandler
- .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-
- .weak ADC1_IRQHandler
- .thumb_set ADC1_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
- .thumb_set LPTIM1_IRQHandler,Default_Handler
-
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
-
- .weak TIM1_IRQHandler
- .thumb_set TIM1_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- .thumb_set IPCC_C2_RX_C2_TX_HSEM_IRQHandler,Default_Handler
-
- .weak RNG_PKA_IRQHandler
- .thumb_set RNG_PKA_IRQHandler,Default_Handler
-
- .weak AES2_IRQHandler
- .thumb_set AES2_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak BLE_IRQHandler
- .thumb_set BLE_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32wb10xx_cm4.s b/Source/Templates/gcc/startup_stm32wb10xx_cm4.s
index ee25adc..9be0cca 100644
--- a/Source/Templates/gcc/startup_stm32wb10xx_cm4.s
+++ b/Source/Templates/gcc/startup_stm32wb10xx_cm4.s
@@ -92,7 +92,7 @@
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
+/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
@@ -384,4 +384,3 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32wb15xx_cm0.s b/Source/Templates/gcc/startup_stm32wb15xx_cm0.s
deleted file mode 100644
index 49aadea..0000000
--- a/Source/Templates/gcc/startup_stm32wb15xx_cm0.s
+++ /dev/null
@@ -1,262 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32wb15xx_cm0.s
- * @author MCD Application Team
- * @brief STM32WB15xx devices vector table GCC toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0+ processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019-2021 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
- bl SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
- ldr r0, =_sdata
- ldr r1, =_edata
- ldr r2, =_sidata
- movs r3, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r4, [r2, r3]
- str r4, [r0, r3]
- adds r3, r3, #4
-
-LoopCopyDataInit:
- adds r4, r0, r3
- cmp r4, r1
- bcc CopyDataInit
-
-/* Zero fill the bss segment. */
- ldr r2, =_sbss
- ldr r4, =_ebss
- movs r3, #0
- b LoopFillZerobss
-
-FillZerobss:
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZerobss:
- cmp r2, r4
- bcc FillZerobss
-
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application s entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word 0
- .word PVD_PVM_IRQHandler
- .word RTC_LSECSS_IRQHandler
- .word 0
- .word RCC_FLASH_C1SEV_IRQHandler
- .word EXTI1_0_IRQHandler
- .word EXTI3_2_IRQHandler
- .word EXTI15_4_IRQHandler
- .word TSC_IRQHandler
- .word DMA1_Channel1_2_3_IRQHandler
- .word DMA1_Channel4_5_6_7_IRQHandler
- .word DMAMUX1_OVR_IRQHandler
- .word ADC1_COMP_IRQHandler
- .word LPTIM1_IRQHandler
- .word LPTIM2_IRQHandler
- .word TIM1_IRQHandler
- .word TIM2_IRQHandler
- .word 0
- .word 0
- .word IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- .word RNG_PKA_IRQHandler
- .word AES2_IRQHandler
- .word 0
- .word I2C1_IRQHandler
- .word 0
- .word SPI1_IRQHandler
- .word 0
- .word USART1_IRQHandler
- .word LPUART1_IRQHandler
- .word 0
- .word BLE_IRQHandler
- .word 0
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak PVD_PVM_IRQHandler
- .thumb_set PVD_PVM_IRQHandler,Default_Handler
-
- .weak RTC_LSECSS_IRQHandler
- .thumb_set RTC_LSECSS_IRQHandler,Default_Handler
-
- .weak RCC_FLASH_C1SEV_IRQHandler
- .thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
-
- .weak EXTI1_0_IRQHandler
- .thumb_set EXTI1_0_IRQHandler,Default_Handler
-
- .weak EXTI3_2_IRQHandler
- .thumb_set EXTI3_2_IRQHandler,Default_Handler
-
- .weak EXTI15_4_IRQHandler
- .thumb_set EXTI15_4_IRQHandler,Default_Handler
-
- .weak TSC_IRQHandler
- .thumb_set TSC_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_2_3_IRQHandler
- .thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_6_7_IRQHandler
- .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
- .weak DMAMUX1_OVR_IRQHandler
- .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-
- .weak ADC1_COMP_IRQHandler
- .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
- .thumb_set LPTIM1_IRQHandler,Default_Handler
-
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
-
- .weak TIM1_IRQHandler
- .thumb_set TIM1_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- .thumb_set IPCC_C2_RX_C2_TX_HSEM_IRQHandler,Default_Handler
-
- .weak RNG_PKA_IRQHandler
- .thumb_set RNG_PKA_IRQHandler,Default_Handler
-
- .weak AES2_IRQHandler
- .thumb_set AES2_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak LPUART1_IRQHandler
- .thumb_set LPUART1_IRQHandler,Default_Handler
-
- .weak BLE_IRQHandler
- .thumb_set BLE_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32wb15xx_cm4.s b/Source/Templates/gcc/startup_stm32wb15xx_cm4.s
index 75ae40a..5e1a465 100644
--- a/Source/Templates/gcc/startup_stm32wb15xx_cm4.s
+++ b/Source/Templates/gcc/startup_stm32wb15xx_cm4.s
@@ -92,7 +92,7 @@
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
+/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
@@ -390,4 +390,3 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32wb30xx_cm4.s b/Source/Templates/gcc/startup_stm32wb30xx_cm4.s
index 979c0ab..2c1110e 100644
--- a/Source/Templates/gcc/startup_stm32wb30xx_cm4.s
+++ b/Source/Templates/gcc/startup_stm32wb30xx_cm4.s
@@ -92,7 +92,7 @@
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
+/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
@@ -381,4 +381,3 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32wb35xx_cm0.s b/Source/Templates/gcc/startup_stm32wb35xx_cm0.s
deleted file mode 100644
index e653ed4..0000000
--- a/Source/Templates/gcc/startup_stm32wb35xx_cm0.s
+++ /dev/null
@@ -1,279 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32wb35xx_cm0.s
- * @author MCD Application Team
- * @brief STM32WB35xx devices vector table GCC toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0+ processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019-2021 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
- bl SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
- ldr r0, =_sdata
- ldr r1, =_edata
- ldr r2, =_sidata
- movs r3, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r4, [r2, r3]
- str r4, [r0, r3]
- adds r3, r3, #4
-
-LoopCopyDataInit:
- adds r4, r0, r3
- cmp r4, r1
- bcc CopyDataInit
-
-/* Zero fill the bss segment. */
- ldr r2, =_sbss
- ldr r4, =_ebss
- movs r3, #0
- b LoopFillZerobss
-
-FillZerobss:
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZerobss:
- cmp r2, r4
- bcc FillZerobss
-
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application s entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word 0
- .word PVD_PVM_IRQHandler
- .word RTC_LSECSS_IRQHandler
- .word USB_CRS_IRQHandler
- .word RCC_FLASH_C1SEV_IRQHandler
- .word EXTI1_0_IRQHandler
- .word EXTI3_2_IRQHandler
- .word EXTI15_4_IRQHandler
- .word _802_0_IRQHandler
- .word DMA1_Channel1_2_3_IRQHandler
- .word DMA1_Channel4_5_6_7_IRQHandler
- .word DMA2_DMAMUX1_OVR_IRQHandler
- .word ADC1_COMP_IRQHandler
- .word LPTIM1_IRQHandler
- .word LPTIM2_IRQHandler
- .word TIM1_IRQHandler
- .word TIM2_IRQHandler
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- .word AES1_RNG_PKA_IRQHandler
- .word AES2_IRQHandler
- .word _802_1_IRQHandler
- .word I2C1_IRQHandler
- .word I2C3_IRQHandler
- .word SPI1_IRQHandler
- .word USART1_IRQHandler
- .word LPUART1_IRQHandler
- .word 0
- .word BLE_IRQHandler
- .word _802_2_HOST_WKUP_IRQHandler
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak PVD_PVM_IRQHandler
- .thumb_set PVD_PVM_IRQHandler,Default_Handler
-
- .weak RTC_LSECSS_IRQHandler
- .thumb_set RTC_LSECSS_IRQHandler,Default_Handler
-
- .weak USB_CRS_IRQHandler
- .thumb_set USB_CRS_IRQHandler,Default_Handler
-
- .weak RCC_FLASH_C1SEV_IRQHandler
- .thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
-
- .weak EXTI1_0_IRQHandler
- .thumb_set EXTI1_0_IRQHandler,Default_Handler
-
- .weak EXTI3_2_IRQHandler
- .thumb_set EXTI3_2_IRQHandler,Default_Handler
-
- .weak EXTI15_4_IRQHandler
- .thumb_set EXTI15_4_IRQHandler,Default_Handler
-
- .weak _802_0_IRQHandler
- .thumb_set _802_0_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_2_3_IRQHandler
- .thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_6_7_IRQHandler
- .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
- .weak DMA2_DMAMUX1_OVR_IRQHandler
- .thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
-
- .weak ADC1_COMP_IRQHandler
- .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
- .thumb_set LPTIM1_IRQHandler,Default_Handler
-
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
-
- .weak TIM1_IRQHandler
- .thumb_set TIM1_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- .thumb_set IPCC_C2_RX_C2_TX_HSEM_IRQHandler,Default_Handler
-
- .weak AES1_RNG_PKA_IRQHandler
- .thumb_set AES1_RNG_PKA_IRQHandler,Default_Handler
-
- .weak AES2_IRQHandler
- .thumb_set AES2_IRQHandler,Default_Handler
-
- .weak _802_1_IRQHandler
- .thumb_set _802_1_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C3_IRQHandler
- .thumb_set I2C3_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak LPUART1_IRQHandler
- .thumb_set LPUART1_IRQHandler,Default_Handler
-
- .weak BLE_IRQHandler
- .thumb_set BLE_IRQHandler,Default_Handler
-
- .weak _802_2_HOST_WKUP_IRQHandler
- .thumb_set _802_2_HOST_WKUP_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32wb35xx_cm4.s b/Source/Templates/gcc/startup_stm32wb35xx_cm4.s
index 1c85892..52cbc69 100644
--- a/Source/Templates/gcc/startup_stm32wb35xx_cm4.s
+++ b/Source/Templates/gcc/startup_stm32wb35xx_cm4.s
@@ -92,7 +92,7 @@
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
+/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
@@ -429,4 +429,3 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32wb50xx_cm4.s b/Source/Templates/gcc/startup_stm32wb50xx_cm4.s
index 7c49da8..9430dfd 100644
--- a/Source/Templates/gcc/startup_stm32wb50xx_cm4.s
+++ b/Source/Templates/gcc/startup_stm32wb50xx_cm4.s
@@ -92,7 +92,7 @@
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
+/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
@@ -384,4 +384,3 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32wb55xx_cm0.s b/Source/Templates/gcc/startup_stm32wb55xx_cm0.s
deleted file mode 100644
index 6a40709..0000000
--- a/Source/Templates/gcc/startup_stm32wb55xx_cm0.s
+++ /dev/null
@@ -1,286 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32wb55xx_cm0.s
- * @author MCD Application Team
- * @brief STM32WB55xx devices vector table GCC toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0+ processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019-2021 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
- bl SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
- ldr r0, =_sdata
- ldr r1, =_edata
- ldr r2, =_sidata
- movs r3, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r4, [r2, r3]
- str r4, [r0, r3]
- adds r3, r3, #4
-
-LoopCopyDataInit:
- adds r4, r0, r3
- cmp r4, r1
- bcc CopyDataInit
-
-/* Zero fill the bss segment. */
- ldr r2, =_sbss
- ldr r4, =_ebss
- movs r3, #0
- b LoopFillZerobss
-
-FillZerobss:
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZerobss:
- cmp r2, r4
- bcc FillZerobss
-
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application s entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word 0
- .word PVD_PVM_IRQHandler
- .word RTC_LSECSS_IRQHandler
- .word USB_CRS_IRQHandler
- .word RCC_FLASH_C1SEV_IRQHandler
- .word EXTI1_0_IRQHandler
- .word EXTI3_2_IRQHandler
- .word EXTI15_4_IRQHandler
- .word TSC_802_0_IRQHandler
- .word DMA1_Channel1_2_3_IRQHandler
- .word DMA1_Channel4_5_6_7_IRQHandler
- .word DMA2_DMAMUX1_OVR_IRQHandler
- .word ADC1_COMP_IRQHandler
- .word LPTIM1_IRQHandler
- .word LPTIM2_IRQHandler
- .word TIM1_IRQHandler
- .word TIM2_IRQHandler
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- .word AES1_RNG_PKA_IRQHandler
- .word AES2_IRQHandler
- .word LCD_802_1_IRQHandler
- .word I2C1_IRQHandler
- .word I2C3_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word LPUART1_IRQHandler
- .word SAI1_IRQHandler
- .word BLE_IRQHandler
- .word _802_2_HOST_WKUP_IRQHandler
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak PVD_PVM_IRQHandler
- .thumb_set PVD_PVM_IRQHandler,Default_Handler
-
- .weak RTC_LSECSS_IRQHandler
- .thumb_set RTC_LSECSS_IRQHandler,Default_Handler
-
- .weak USB_CRS_IRQHandler
- .thumb_set USB_CRS_IRQHandler,Default_Handler
-
- .weak RCC_FLASH_C1SEV_IRQHandler
- .thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
-
- .weak EXTI1_0_IRQHandler
- .thumb_set EXTI1_0_IRQHandler,Default_Handler
-
- .weak EXTI3_2_IRQHandler
- .thumb_set EXTI3_2_IRQHandler,Default_Handler
-
- .weak EXTI15_4_IRQHandler
- .thumb_set EXTI15_4_IRQHandler,Default_Handler
-
- .weak TSC_802_0_IRQHandler
- .thumb_set TSC_802_0_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_2_3_IRQHandler
- .thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_6_7_IRQHandler
- .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
- .weak DMA2_DMAMUX1_OVR_IRQHandler
- .thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
-
- .weak ADC1_COMP_IRQHandler
- .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
- .thumb_set LPTIM1_IRQHandler,Default_Handler
-
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
-
- .weak TIM1_IRQHandler
- .thumb_set TIM1_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- .thumb_set IPCC_C2_RX_C2_TX_HSEM_IRQHandler,Default_Handler
-
- .weak AES1_RNG_PKA_IRQHandler
- .thumb_set AES1_RNG_PKA_IRQHandler,Default_Handler
-
- .weak AES2_IRQHandler
- .thumb_set AES2_IRQHandler,Default_Handler
-
- .weak LCD_802_1_IRQHandler
- .thumb_set LCD_802_1_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C3_IRQHandler
- .thumb_set I2C3_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak LPUART1_IRQHandler
- .thumb_set LPUART1_IRQHandler,Default_Handler
-
- .weak SAI1_IRQHandler
- .thumb_set SAI1_IRQHandler,Default_Handler
-
- .weak BLE_IRQHandler
- .thumb_set BLE_IRQHandler,Default_Handler
-
- .weak _802_2_HOST_WKUP_IRQHandler
- .thumb_set _802_2_HOST_WKUP_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32wb55xx_cm4.s b/Source/Templates/gcc/startup_stm32wb55xx_cm4.s
index c5c2b3f..77c2e05 100644
--- a/Source/Templates/gcc/startup_stm32wb55xx_cm4.s
+++ b/Source/Templates/gcc/startup_stm32wb55xx_cm4.s
@@ -92,7 +92,7 @@
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
+/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
@@ -441,4 +441,3 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32wb5mxx_cm0.s b/Source/Templates/gcc/startup_stm32wb5mxx_cm0.s
deleted file mode 100644
index b8eec5c..0000000
--- a/Source/Templates/gcc/startup_stm32wb5mxx_cm0.s
+++ /dev/null
@@ -1,286 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32wb5mxx_cm0.s
- * @author MCD Application Team
- * @brief STM32WB5Mxx devices vector table GCC toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0+ processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2019-2021 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
- bl SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
- ldr r0, =_sdata
- ldr r1, =_edata
- ldr r2, =_sidata
- movs r3, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r4, [r2, r3]
- str r4, [r0, r3]
- adds r3, r3, #4
-
-LoopCopyDataInit:
- adds r4, r0, r3
- cmp r4, r1
- bcc CopyDataInit
-
-/* Zero fill the bss segment. */
- ldr r2, =_sbss
- ldr r4, =_ebss
- movs r3, #0
- b LoopFillZerobss
-
-FillZerobss:
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZerobss:
- cmp r2, r4
- bcc FillZerobss
-
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application s entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word 0
- .word PVD_PVM_IRQHandler
- .word RTC_LSECSS_IRQHandler
- .word USB_CRS_IRQHandler
- .word RCC_FLASH_C1SEV_IRQHandler
- .word EXTI1_0_IRQHandler
- .word EXTI3_2_IRQHandler
- .word EXTI15_4_IRQHandler
- .word TSC_802_0_IRQHandler
- .word DMA1_Channel1_2_3_IRQHandler
- .word DMA1_Channel4_5_6_7_IRQHandler
- .word DMA2_DMAMUX1_OVR_IRQHandler
- .word ADC1_COMP_IRQHandler
- .word LPTIM1_IRQHandler
- .word LPTIM2_IRQHandler
- .word TIM1_IRQHandler
- .word TIM2_IRQHandler
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- .word AES1_RNG_PKA_IRQHandler
- .word AES2_IRQHandler
- .word LCD_802_1_IRQHandler
- .word I2C1_IRQHandler
- .word I2C3_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word LPUART1_IRQHandler
- .word SAI1_IRQHandler
- .word BLE_IRQHandler
- .word _802_2_HOST_WKUP_IRQHandler
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak PVD_PVM_IRQHandler
- .thumb_set PVD_PVM_IRQHandler,Default_Handler
-
- .weak RTC_LSECSS_IRQHandler
- .thumb_set RTC_LSECSS_IRQHandler,Default_Handler
-
- .weak USB_CRS_IRQHandler
- .thumb_set USB_CRS_IRQHandler,Default_Handler
-
- .weak RCC_FLASH_C1SEV_IRQHandler
- .thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
-
- .weak EXTI1_0_IRQHandler
- .thumb_set EXTI1_0_IRQHandler,Default_Handler
-
- .weak EXTI3_2_IRQHandler
- .thumb_set EXTI3_2_IRQHandler,Default_Handler
-
- .weak EXTI15_4_IRQHandler
- .thumb_set EXTI15_4_IRQHandler,Default_Handler
-
- .weak TSC_802_0_IRQHandler
- .thumb_set TSC_802_0_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_2_3_IRQHandler
- .thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_6_7_IRQHandler
- .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
- .weak DMA2_DMAMUX1_OVR_IRQHandler
- .thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
-
- .weak ADC1_COMP_IRQHandler
- .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
- .thumb_set LPTIM1_IRQHandler,Default_Handler
-
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
-
- .weak TIM1_IRQHandler
- .thumb_set TIM1_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- .thumb_set IPCC_C2_RX_C2_TX_HSEM_IRQHandler,Default_Handler
-
- .weak AES1_RNG_PKA_IRQHandler
- .thumb_set AES1_RNG_PKA_IRQHandler,Default_Handler
-
- .weak AES2_IRQHandler
- .thumb_set AES2_IRQHandler,Default_Handler
-
- .weak LCD_802_1_IRQHandler
- .thumb_set LCD_802_1_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C3_IRQHandler
- .thumb_set I2C3_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak LPUART1_IRQHandler
- .thumb_set LPUART1_IRQHandler,Default_Handler
-
- .weak SAI1_IRQHandler
- .thumb_set SAI1_IRQHandler,Default_Handler
-
- .weak BLE_IRQHandler
- .thumb_set BLE_IRQHandler,Default_Handler
-
- .weak _802_2_HOST_WKUP_IRQHandler
- .thumb_set _802_2_HOST_WKUP_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s b/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s
index 6ac953f..94be63d 100644
--- a/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s
+++ b/Source/Templates/gcc/startup_stm32wb5mxx_cm4.s
@@ -92,7 +92,7 @@
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
-/* Call the clock system intitialization function.*/
+/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
@@ -441,4 +441,3 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/iar/linker/stm32wb10xx_flash_cm0.icf b/Source/Templates/iar/linker/stm32wb10xx_flash_cm0.icf
deleted file mode 100644
index baeb009..0000000
--- a/Source/Templates/iar/linker/stm32wb10xx_flash_cm0.icf
+++ /dev/null
@@ -1,40 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08028000 ;
-/*-Memory Regions-*/
-/******************/
-/***** FLASH Part dedicated to M0 *****/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08028000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0804FFFF;
-/***** RAM2b dedicated to M0 *****/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20030000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2003AFFF;
-/***** RAM2a *****/
-define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000 ;
-define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x2003AFFF ;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
-
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32wb10xx_sram_cm0.icf b/Source/Templates/iar/linker/stm32wb10xx_sram_cm0.icf
deleted file mode 100644
index b63e15c..0000000
--- a/Source/Templates/iar/linker/stm32wb10xx_sram_cm0.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20030000 ;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20030000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2000AFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x2000B000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32wb15xx_flash_cm0.icf b/Source/Templates/iar/linker/stm32wb15xx_flash_cm0.icf
deleted file mode 100644
index baeb009..0000000
--- a/Source/Templates/iar/linker/stm32wb15xx_flash_cm0.icf
+++ /dev/null
@@ -1,40 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08028000 ;
-/*-Memory Regions-*/
-/******************/
-/***** FLASH Part dedicated to M0 *****/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08028000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0804FFFF;
-/***** RAM2b dedicated to M0 *****/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20030000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2003AFFF;
-/***** RAM2a *****/
-define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000 ;
-define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x2003AFFF ;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
-
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32wb15xx_sram_cm0.icf b/Source/Templates/iar/linker/stm32wb15xx_sram_cm0.icf
deleted file mode 100644
index b63e15c..0000000
--- a/Source/Templates/iar/linker/stm32wb15xx_sram_cm0.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20030000 ;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20030000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2000AFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x2000B000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32wb35xx_flash_cm0.icf b/Source/Templates/iar/linker/stm32wb35xx_flash_cm0.icf
deleted file mode 100644
index 11f0663..0000000
--- a/Source/Templates/iar/linker/stm32wb35xx_flash_cm0.icf
+++ /dev/null
@@ -1,40 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08040000 ;
-/*-Memory Regions-*/
-/******************/
-/***** FLASH Part dedicated to M0 *****/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08040000 ;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF ;
-/***** RAM2b dedicated to M0 *****/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20008000 ;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF ;
-/***** RAM2a *****/
-define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000 ;
-define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x20037FFF ;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
-
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32wb35xx_sram_cm0.icf b/Source/Templates/iar/linker/stm32wb35xx_sram_cm0.icf
deleted file mode 100644
index 6bc7e82..0000000
--- a/Source/Templates/iar/linker/stm32wb35xx_sram_cm0.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20008000 ;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20008000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x2000BFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x2000C000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32wb55xx_flash_cm0.icf b/Source/Templates/iar/linker/stm32wb55xx_flash_cm0.icf
deleted file mode 100644
index b2d9daa..0000000
--- a/Source/Templates/iar/linker/stm32wb55xx_flash_cm0.icf
+++ /dev/null
@@ -1,40 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08080000 ;
-/*-Memory Regions-*/
-/******************/
-/***** FLASH Part dedicated to M0 *****/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08080000 ;
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF ;
-/***** RAM2b dedicated to M0 *****/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20038000 ;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF ;
-/***** RAM2a *****/
-define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000 ;
-define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x20037FFF ;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
-
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32wb55xx_sram_cm0.icf b/Source/Templates/iar/linker/stm32wb55xx_sram_cm0.icf
deleted file mode 100644
index b1070a0..0000000
--- a/Source/Templates/iar/linker/stm32wb55xx_sram_cm0.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20030000 ;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20030000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x20037FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20038000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32wb5mxx_flash_cm0.icf b/Source/Templates/iar/linker/stm32wb5mxx_flash_cm0.icf
deleted file mode 100644
index b2d9daa..0000000
--- a/Source/Templates/iar/linker/stm32wb5mxx_flash_cm0.icf
+++ /dev/null
@@ -1,40 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08080000 ;
-/*-Memory Regions-*/
-/******************/
-/***** FLASH Part dedicated to M0 *****/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08080000 ;
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF ;
-/***** RAM2b dedicated to M0 *****/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20038000 ;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF ;
-/***** RAM2a *****/
-define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000 ;
-define symbol __ICFEDIT_region_RAM_SHARED_end__ = 0x20037FFF ;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__ to __ICFEDIT_region_RAM_SHARED_end__];
-
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Source/Templates/iar/linker/stm32wb5mxx_sram_cm0.icf b/Source/Templates/iar/linker/stm32wb5mxx_sram_cm0.icf
deleted file mode 100644
index b1070a0..0000000
--- a/Source/Templates/iar/linker/stm32wb5mxx_sram_cm0.icf
+++ /dev/null
@@ -1,33 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20030000 ;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20030000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x20037FFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20038000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Source/Templates/iar/startup_stm32wb10xx_cm0.s b/Source/Templates/iar/startup_stm32wb10xx_cm0.s
deleted file mode 100644
index 4023888..0000000
--- a/Source/Templates/iar/startup_stm32wb10xx_cm0.s
+++ /dev/null
@@ -1,261 +0,0 @@
-;******************************************************************************
-;* File Name : startup_stm32wb10xx_cm0.s
-;* Author : MCD Application Team
-;* Description : MO+ core vector table of the STM32WB10xx devices for the
-;* IAR (EWARM) toolchain.
-;*
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0+ processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2019-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD 0 ; Reserved
- DCD PVD_PVM_IRQHandler ; PVD and PVM detector
- DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) and LSECSS Interrupts
- DCD 0 ; Reserved
- DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
- DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
- DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
- DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
- DCD TSC_IRQHandler ; TSC Interrupt
- DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
- DCD DMAMUX1_OVR_IRQHandler ; DMAMUX Overrun Interrupts
- DCD ADC1_IRQHandler ; ADC1 Interrupt
- DCD LPTIM1_IRQHandler ; LPTIM1 Channel 5 Interrupt
- DCD LPTIM2_IRQHandler ; LPTIM2 Channel 6 Interrupt
- DCD TIM1_IRQHandler ; TIM1 Interrupt
- DCD TIM2_IRQHandler ; TIM2 Interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD IPCC_C2_RX_C2_TX_HSEM_IRQHandler ; IPCC RX Occupied and TX Free Interrupt and Semaphore Interrupt
- DCD RNG_PKA_IRQHandler ; RNG and PKA Interrupt
- DCD AES2_IRQHandler ; AES2 Interrupt
- DCD 0 ; Reserved
- DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
- DCD 0 ; Reserved
- DCD SPI1_IRQHandler ; SPI1 Interrupts
- DCD 0 ; Reserved
- DCD USART1_IRQHandler ; USART1 Interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD BLE_IRQHandler ; BLE Interrupt
- DCD 0 ; Reserved
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK PVD_PVM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_PVM_IRQHandler
- B PVD_PVM_IRQHandler
-
- PUBWEAK RTC_LSECSS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_LSECSS_IRQHandler
- B RTC_LSECSS_IRQHandler
-
- PUBWEAK RCC_FLASH_C1SEV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_FLASH_C1SEV_IRQHandler
- B RCC_FLASH_C1SEV_IRQHandler
-
- PUBWEAK EXTI1_0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_0_IRQHandler
- B EXTI1_0_IRQHandler
-
- PUBWEAK EXTI3_2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_2_IRQHandler
- B EXTI3_2_IRQHandler
-
- PUBWEAK EXTI15_4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_4_IRQHandler
- B EXTI15_4_IRQHandler
-
- PUBWEAK TSC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
- B TSC_IRQHandler
-
- PUBWEAK DMA1_Channel1_2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_2_3_IRQHandler
- B DMA1_Channel1_2_3_IRQHandler
-
- PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
- B DMA1_Channel4_5_6_7_IRQHandler
-
- PUBWEAK DMAMUX1_OVR_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX1_OVR_IRQHandler
- B DMAMUX1_OVR_IRQHandler
-
- PUBWEAK ADC1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_IRQHandler
- B ADC1_IRQHandler
-
- PUBWEAK LPTIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
- B LPTIM1_IRQHandler
-
- PUBWEAK LPTIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
- B LPTIM2_IRQHandler
-
- PUBWEAK TIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_IRQHandler
- B TIM1_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- B IPCC_C2_RX_C2_TX_HSEM_IRQHandler
-
- PUBWEAK RNG_PKA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_PKA_IRQHandler
- B RNG_PKA_IRQHandler
-
- PUBWEAK AES2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-AES2_IRQHandler
- B AES2_IRQHandler
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK BLE_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BLE_IRQHandler
- B BLE_IRQHandler
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32wb10xx_cm4.s b/Source/Templates/iar/startup_stm32wb10xx_cm4.s
index aa19e50..b92dc29 100644
--- a/Source/Templates/iar/startup_stm32wb10xx_cm4.s
+++ b/Source/Templates/iar/startup_stm32wb10xx_cm4.s
@@ -82,7 +82,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -418,4 +418,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32wb15xx_cm0.s b/Source/Templates/iar/startup_stm32wb15xx_cm0.s
deleted file mode 100644
index 2bc3ebd..0000000
--- a/Source/Templates/iar/startup_stm32wb15xx_cm0.s
+++ /dev/null
@@ -1,266 +0,0 @@
-;******************************************************************************
-;* File Name : startup_stm32wb15xx_cm0.s
-;* Author : MCD Application Team
-;* Description : MO+ core vector table of the STM32WB15xx devices for the
-;* IAR (EWARM) toolchain.
-;*
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0+ processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2019-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD 0 ; Reserved
- DCD PVD_PVM_IRQHandler ; PVD and PVM detector
- DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) and LSECSS Interrupts
- DCD 0 ; Reserved
- DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
- DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
- DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
- DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
- DCD TSC_IRQHandler ; TSC Interrupt
- DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
- DCD DMAMUX1_OVR_IRQHandler ; DMAMUX Overrun Interrupts
- DCD ADC1_COMP_IRQHandler ; ADC1 and COMP1 Interrupt
- DCD LPTIM1_IRQHandler ; LPTIM1 Channel 5 Interrupt
- DCD LPTIM2_IRQHandler ; LPTIM2 Channel 6 Interrupt
- DCD TIM1_IRQHandler ; TIM1 Interrupt
- DCD TIM2_IRQHandler ; TIM2 Interrupt
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD IPCC_C2_RX_C2_TX_HSEM_IRQHandler ; IPCC RX Occupied and TX Free Interrupt and Semaphore Interrupt
- DCD RNG_PKA_IRQHandler ; RNG and PKA Interrupt
- DCD AES2_IRQHandler ; AES2 Interrupt
- DCD 0 ; Reserved
- DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
- DCD 0 ; Reserved
- DCD SPI1_IRQHandler ; SPI1 Interrupts
- DCD 0 ; Reserved
- DCD USART1_IRQHandler ; USART1 Interrupt
- DCD LPUART1_IRQHandler ; LPUART1 Interrupt
- DCD 0 ; Reserved
- DCD BLE_IRQHandler ; BLE Interrupt
- DCD 0 ; Reserved
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK PVD_PVM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_PVM_IRQHandler
- B PVD_PVM_IRQHandler
-
- PUBWEAK RTC_LSECSS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_LSECSS_IRQHandler
- B RTC_LSECSS_IRQHandler
-
- PUBWEAK RCC_FLASH_C1SEV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_FLASH_C1SEV_IRQHandler
- B RCC_FLASH_C1SEV_IRQHandler
-
- PUBWEAK EXTI1_0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_0_IRQHandler
- B EXTI1_0_IRQHandler
-
- PUBWEAK EXTI3_2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_2_IRQHandler
- B EXTI3_2_IRQHandler
-
- PUBWEAK EXTI15_4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_4_IRQHandler
- B EXTI15_4_IRQHandler
-
- PUBWEAK TSC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
- B TSC_IRQHandler
-
- PUBWEAK DMA1_Channel1_2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_2_3_IRQHandler
- B DMA1_Channel1_2_3_IRQHandler
-
- PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
- B DMA1_Channel4_5_6_7_IRQHandler
-
- PUBWEAK DMAMUX1_OVR_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX1_OVR_IRQHandler
- B DMAMUX1_OVR_IRQHandler
-
- PUBWEAK ADC1_COMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
- B ADC1_COMP_IRQHandler
-
- PUBWEAK LPTIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
- B LPTIM1_IRQHandler
-
- PUBWEAK LPTIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
- B LPTIM2_IRQHandler
-
- PUBWEAK TIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_IRQHandler
- B TIM1_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- B IPCC_C2_RX_C2_TX_HSEM_IRQHandler
-
- PUBWEAK RNG_PKA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_PKA_IRQHandler
- B RNG_PKA_IRQHandler
-
- PUBWEAK AES2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-AES2_IRQHandler
- B AES2_IRQHandler
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK LPUART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
- B LPUART1_IRQHandler
-
- PUBWEAK BLE_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BLE_IRQHandler
- B BLE_IRQHandler
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32wb15xx_cm4.s b/Source/Templates/iar/startup_stm32wb15xx_cm4.s
index 457d335..f8b3013 100644
--- a/Source/Templates/iar/startup_stm32wb15xx_cm4.s
+++ b/Source/Templates/iar/startup_stm32wb15xx_cm4.s
@@ -82,7 +82,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -428,4 +428,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32wb30xx_cm4.s b/Source/Templates/iar/startup_stm32wb30xx_cm4.s
index d6a42dc..d0528d4 100644
--- a/Source/Templates/iar/startup_stm32wb30xx_cm4.s
+++ b/Source/Templates/iar/startup_stm32wb30xx_cm4.s
@@ -82,7 +82,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -413,4 +413,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32wb35xx_cm0.s b/Source/Templates/iar/startup_stm32wb35xx_cm0.s
deleted file mode 100644
index 99f9a81..0000000
--- a/Source/Templates/iar/startup_stm32wb35xx_cm0.s
+++ /dev/null
@@ -1,294 +0,0 @@
-;******************************************************************************
-;* File Name : startup_stm32wb35xx_cm0.s
-;* Author : MCD Application Team
-;* Description : MO+ core vector table of the STM32WB35xx devices for the
-;* IAR (EWARM) toolchain.
-;*
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0+ processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2019-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD 0 ; Reserved
- DCD PVD_PVM_IRQHandler ; PVD and PVM detector
- DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) and LSECSS Interrupts
- DCD USB_CRS_IRQHandler ; USB High Priority, Low Priority (including USB wakeup) and CRS Interrupts
- DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
- DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
- DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
- DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
- DCD _802_0_IRQHandler ; 802.15.4 interrupt 0
- DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
- DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
- DCD ADC1_COMP_IRQHandler ; ADC1 and COMP1 COMP2 Interrupt
- DCD LPTIM1_IRQHandler ; LPTIM1 Channel 5 Interrupt
- DCD LPTIM2_IRQHandler ; LPTIM2 Channel 6 Interrupt
- DCD TIM1_IRQHandler ; TIM1 Interrupt
- DCD TIM2_IRQHandler ; TIM2 Interrupt
- DCD TIM16_IRQHandler ; TIM16 Interrupt
- DCD TIM17_IRQHandler ; TIM17 Interrupt
- DCD IPCC_C2_RX_C2_TX_HSEM_IRQHandler ; IPCC RX Occupied and TX Free Interrupt and Semaphore Interrupt
- DCD AES1_RNG_PKA_IRQHandler ; AES1,RNG and PKA Interrupt
- DCD AES2_IRQHandler ; AES2 Interrupt
- DCD _802_1_IRQHandler ; 802.15.4 interrupt 1
- DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
- DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
- DCD SPI1_IRQHandler ; SPI1 Interrupts
- DCD USART1_IRQHandler ; USART1 Interrupt
- DCD LPUART1_IRQHandler ; LPUART1 Interrupt
- DCD 0 ; Reserved
- DCD BLE_IRQHandler ; BLE Interrupt
- DCD _802_2_HOST_WKUP_IRQHandler ; 802.15.4 Interrupt
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK PVD_PVM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_PVM_IRQHandler
- B PVD_PVM_IRQHandler
-
- PUBWEAK RTC_LSECSS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_LSECSS_IRQHandler
- B RTC_LSECSS_IRQHandler
-
- PUBWEAK USB_CRS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USB_CRS_IRQHandler
- B USB_CRS_IRQHandler
-
- PUBWEAK RCC_FLASH_C1SEV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_FLASH_C1SEV_IRQHandler
- B RCC_FLASH_C1SEV_IRQHandler
-
- PUBWEAK EXTI1_0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_0_IRQHandler
- B EXTI1_0_IRQHandler
-
- PUBWEAK EXTI3_2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_2_IRQHandler
- B EXTI3_2_IRQHandler
-
- PUBWEAK EXTI15_4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_4_IRQHandler
- B EXTI15_4_IRQHandler
-
- PUBWEAK _802_0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-_802_0_IRQHandler
- B _802_0_IRQHandler
-
- PUBWEAK DMA1_Channel1_2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_2_3_IRQHandler
- B DMA1_Channel1_2_3_IRQHandler
-
- PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
- B DMA1_Channel4_5_6_7_IRQHandler
-
- PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_DMAMUX1_OVR_IRQHandler
- B DMA2_DMAMUX1_OVR_IRQHandler
-
- PUBWEAK ADC1_COMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
- B ADC1_COMP_IRQHandler
-
- PUBWEAK LPTIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
- B LPTIM1_IRQHandler
-
- PUBWEAK LPTIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
- B LPTIM2_IRQHandler
-
- PUBWEAK TIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_IRQHandler
- B TIM1_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
- PUBWEAK IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- B IPCC_C2_RX_C2_TX_HSEM_IRQHandler
-
- PUBWEAK AES1_RNG_PKA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-AES1_RNG_PKA_IRQHandler
- B AES1_RNG_PKA_IRQHandler
-
- PUBWEAK AES2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-AES2_IRQHandler
- B AES2_IRQHandler
-
- PUBWEAK _802_1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-_802_1_IRQHandler
- B _802_1_IRQHandler
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
- PUBWEAK I2C3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
- B I2C3_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK LPUART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
- B LPUART1_IRQHandler
-
- PUBWEAK BLE_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BLE_IRQHandler
- B BLE_IRQHandler
-
- PUBWEAK _802_2_HOST_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-_802_2_HOST_WKUP_IRQHandler
- B _802_2_HOST_WKUP_IRQHandler
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32wb35xx_cm4.s b/Source/Templates/iar/startup_stm32wb35xx_cm4.s
index 0b8d9e6..aa5cfa6 100644
--- a/Source/Templates/iar/startup_stm32wb35xx_cm4.s
+++ b/Source/Templates/iar/startup_stm32wb35xx_cm4.s
@@ -82,7 +82,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -493,4 +493,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32wb50xx_cm4.s b/Source/Templates/iar/startup_stm32wb50xx_cm4.s
index 1d9c911..e9dcd9c 100644
--- a/Source/Templates/iar/startup_stm32wb50xx_cm4.s
+++ b/Source/Templates/iar/startup_stm32wb50xx_cm4.s
@@ -82,7 +82,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -413,4 +413,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32wb55xx_cm0.s b/Source/Templates/iar/startup_stm32wb55xx_cm0.s
deleted file mode 100644
index 6361c4f..0000000
--- a/Source/Templates/iar/startup_stm32wb55xx_cm0.s
+++ /dev/null
@@ -1,305 +0,0 @@
-;******************************************************************************
-;* File Name : startup_stm32wb55xx_cm0.s
-;* Author : MCD Application Team
-;* Description : MO+ core vector table of the STM32WB55xx devices for the
-;* IAR (EWARM) toolchain.
-;*
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0+ processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2019-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD 0 ; Reserved
- DCD PVD_PVM_IRQHandler ; PVD and PVM detector
- DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) and LSECSS Interrupts
- DCD USB_CRS_IRQHandler ; USB High Priority, Low Priority (including USB wakeup) and CRS Interrupts
- DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
- DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
- DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
- DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
- DCD TSC_802_0_IRQHandler ; TSC Interrupt
- DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
- DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
- DCD ADC1_COMP_IRQHandler ; ADC1 and COMP1 COMP2 Interrupt
- DCD LPTIM1_IRQHandler ; LPTIM1 Channel 5 Interrupt
- DCD LPTIM2_IRQHandler ; LPTIM2 Channel 6 Interrupt
- DCD TIM1_IRQHandler ; TIM1 Interrupt
- DCD TIM2_IRQHandler ; TIM2 Interrupt
- DCD TIM16_IRQHandler ; TIM16 Interrupt
- DCD TIM17_IRQHandler ; TIM17 Interrupt
- DCD IPCC_C2_RX_C2_TX_HSEM_IRQHandler ; IPCC RX Occupied and TX Free Interrupt and Semaphore Interrupt
- DCD AES1_RNG_PKA_IRQHandler ; AES1,RNG and PKA Interrupt
- DCD AES2_IRQHandler ; AES2 Interrupt
- DCD LCD_802_1_IRQHandler ; LCD Interrupt and 802.15.4 interrupt 1
- DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
- DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
- DCD SPI1_IRQHandler ; SPI1 Interrupts
- DCD SPI2_IRQHandler ; SPI2 Interrupt
- DCD USART1_IRQHandler ; USART1 Interrupt
- DCD LPUART1_IRQHandler ; LPUART1 Interrupt
- DCD SAI1_IRQHandler ; SAI1 Interrupt
- DCD BLE_IRQHandler ; BLE Interrupt
- DCD _802_2_HOST_WKUP_IRQHandler ; 802.15.4 Interrupt
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK PVD_PVM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_PVM_IRQHandler
- B PVD_PVM_IRQHandler
-
- PUBWEAK RTC_LSECSS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_LSECSS_IRQHandler
- B RTC_LSECSS_IRQHandler
-
- PUBWEAK USB_CRS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USB_CRS_IRQHandler
- B USB_CRS_IRQHandler
-
- PUBWEAK RCC_FLASH_C1SEV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_FLASH_C1SEV_IRQHandler
- B RCC_FLASH_C1SEV_IRQHandler
-
- PUBWEAK EXTI1_0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_0_IRQHandler
- B EXTI1_0_IRQHandler
-
- PUBWEAK EXTI3_2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_2_IRQHandler
- B EXTI3_2_IRQHandler
-
- PUBWEAK EXTI15_4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_4_IRQHandler
- B EXTI15_4_IRQHandler
-
- PUBWEAK TSC_802_0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_802_0_IRQHandler
- B TSC_802_0_IRQHandler
-
- PUBWEAK DMA1_Channel1_2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_2_3_IRQHandler
- B DMA1_Channel1_2_3_IRQHandler
-
- PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
- B DMA1_Channel4_5_6_7_IRQHandler
-
- PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_DMAMUX1_OVR_IRQHandler
- B DMA2_DMAMUX1_OVR_IRQHandler
-
- PUBWEAK ADC1_COMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
- B ADC1_COMP_IRQHandler
-
- PUBWEAK LPTIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
- B LPTIM1_IRQHandler
-
- PUBWEAK LPTIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
- B LPTIM2_IRQHandler
-
- PUBWEAK TIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_IRQHandler
- B TIM1_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
- PUBWEAK IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- B IPCC_C2_RX_C2_TX_HSEM_IRQHandler
-
- PUBWEAK AES1_RNG_PKA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-AES1_RNG_PKA_IRQHandler
- B AES1_RNG_PKA_IRQHandler
-
- PUBWEAK AES2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-AES2_IRQHandler
- B AES2_IRQHandler
-
- PUBWEAK LCD_802_1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_802_1_IRQHandler
- B LCD_802_1_IRQHandler
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
- PUBWEAK I2C3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
- B I2C3_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK LPUART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
- B LPUART1_IRQHandler
-
- PUBWEAK SAI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI1_IRQHandler
- B SAI1_IRQHandler
-
- PUBWEAK BLE_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BLE_IRQHandler
- B BLE_IRQHandler
-
- PUBWEAK _802_2_HOST_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-_802_2_HOST_WKUP_IRQHandler
- B _802_2_HOST_WKUP_IRQHandler
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32wb55xx_cm4.s b/Source/Templates/iar/startup_stm32wb55xx_cm4.s
index 124fea4..c33c16a 100644
--- a/Source/Templates/iar/startup_stm32wb55xx_cm4.s
+++ b/Source/Templates/iar/startup_stm32wb55xx_cm4.s
@@ -82,7 +82,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -513,4 +513,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32wb5mxx_cm0.s b/Source/Templates/iar/startup_stm32wb5mxx_cm0.s
deleted file mode 100644
index ed1284e..0000000
--- a/Source/Templates/iar/startup_stm32wb5mxx_cm0.s
+++ /dev/null
@@ -1,305 +0,0 @@
-;******************************************************************************
-;* File Name : startup_stm32wb5mxx_cm0.s
-;* Author : MCD Application Team
-;* Description : MO+ core vector table of the STM32WB5Mxx devices for the
-;* IAR (EWARM) toolchain.
-;*
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0+ processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2019-2021 STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD 0 ; Reserved
- DCD PVD_PVM_IRQHandler ; PVD and PVM detector
- DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) and LSECSS Interrupts
- DCD USB_CRS_IRQHandler ; USB High Priority, Low Priority (including USB wakeup) and CRS Interrupts
- DCD RCC_FLASH_C1SEV_IRQHandler ; RCC and FLASH and CPU1 M4 SEV Interrupt
- DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupt
- DCD EXTI3_2_IRQHandler ; EXTI Line 3:2 Interrupt
- DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupt
- DCD TSC_802_0_IRQHandler ; TSC Interrupt
- DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupt
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4,5,6,7 Interrupt
- DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
- DCD ADC1_COMP_IRQHandler ; ADC1 and COMP1 COMP2 Interrupt
- DCD LPTIM1_IRQHandler ; LPTIM1 Channel 5 Interrupt
- DCD LPTIM2_IRQHandler ; LPTIM2 Channel 6 Interrupt
- DCD TIM1_IRQHandler ; TIM1 Interrupt
- DCD TIM2_IRQHandler ; TIM2 Interrupt
- DCD TIM16_IRQHandler ; TIM16 Interrupt
- DCD TIM17_IRQHandler ; TIM17 Interrupt
- DCD IPCC_C2_RX_C2_TX_HSEM_IRQHandler ; IPCC RX Occupied and TX Free Interrupt and Semaphore Interrupt
- DCD AES1_RNG_PKA_IRQHandler ; AES1,RNG and PKA Interrupt
- DCD AES2_IRQHandler ; AES2 Interrupt
- DCD LCD_802_1_IRQHandler ; LCD Interrupt and 802.15.4 interrupt 1
- DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
- DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
- DCD SPI1_IRQHandler ; SPI1 Interrupts
- DCD SPI2_IRQHandler ; SPI2 Interrupt
- DCD USART1_IRQHandler ; USART1 Interrupt
- DCD LPUART1_IRQHandler ; LPUART1 Interrupt
- DCD SAI1_IRQHandler ; SAI1 Interrupt
- DCD BLE_IRQHandler ; BLE Interrupt
- DCD _802_2_HOST_WKUP_IRQHandler ; 802.15.4 Interrupt
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK PVD_PVM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_PVM_IRQHandler
- B PVD_PVM_IRQHandler
-
- PUBWEAK RTC_LSECSS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_LSECSS_IRQHandler
- B RTC_LSECSS_IRQHandler
-
- PUBWEAK USB_CRS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USB_CRS_IRQHandler
- B USB_CRS_IRQHandler
-
- PUBWEAK RCC_FLASH_C1SEV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_FLASH_C1SEV_IRQHandler
- B RCC_FLASH_C1SEV_IRQHandler
-
- PUBWEAK EXTI1_0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_0_IRQHandler
- B EXTI1_0_IRQHandler
-
- PUBWEAK EXTI3_2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_2_IRQHandler
- B EXTI3_2_IRQHandler
-
- PUBWEAK EXTI15_4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_4_IRQHandler
- B EXTI15_4_IRQHandler
-
- PUBWEAK TSC_802_0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_802_0_IRQHandler
- B TSC_802_0_IRQHandler
-
- PUBWEAK DMA1_Channel1_2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_2_3_IRQHandler
- B DMA1_Channel1_2_3_IRQHandler
-
- PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
- B DMA1_Channel4_5_6_7_IRQHandler
-
- PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_DMAMUX1_OVR_IRQHandler
- B DMA2_DMAMUX1_OVR_IRQHandler
-
- PUBWEAK ADC1_COMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
- B ADC1_COMP_IRQHandler
-
- PUBWEAK LPTIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
- B LPTIM1_IRQHandler
-
- PUBWEAK LPTIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
- B LPTIM2_IRQHandler
-
- PUBWEAK TIM1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_IRQHandler
- B TIM1_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
- PUBWEAK IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-IPCC_C2_RX_C2_TX_HSEM_IRQHandler
- B IPCC_C2_RX_C2_TX_HSEM_IRQHandler
-
- PUBWEAK AES1_RNG_PKA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-AES1_RNG_PKA_IRQHandler
- B AES1_RNG_PKA_IRQHandler
-
- PUBWEAK AES2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-AES2_IRQHandler
- B AES2_IRQHandler
-
- PUBWEAK LCD_802_1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_802_1_IRQHandler
- B LCD_802_1_IRQHandler
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
- PUBWEAK I2C3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
- B I2C3_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK LPUART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
- B LPUART1_IRQHandler
-
- PUBWEAK SAI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SAI1_IRQHandler
- B SAI1_IRQHandler
-
- PUBWEAK BLE_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BLE_IRQHandler
- B BLE_IRQHandler
-
- PUBWEAK _802_2_HOST_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-_802_2_HOST_WKUP_IRQHandler
- B _802_2_HOST_WKUP_IRQHandler
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32wb5mxx_cm4.s b/Source/Templates/iar/startup_stm32wb5mxx_cm4.s
index e5981a7..63d084a 100644
--- a/Source/Templates/iar/startup_stm32wb5mxx_cm4.s
+++ b/Source/Templates/iar/startup_stm32wb5mxx_cm4.s
@@ -82,7 +82,7 @@
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
- DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
+ DCD EXTI3_IRQHandler ; EXTI Line 3 Interrupt
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
@@ -513,4 +513,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/system_stm32wbxx.c b/Source/Templates/system_stm32wbxx.c
index d0ff7d2..4bfa00f 100644
--- a/Source/Templates/system_stm32wbxx.c
+++ b/Source/Templates/system_stm32wbxx.c
@@ -175,7 +175,7 @@
const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
-#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB10xx)
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx)
const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
{2UL,6UL,4UL,3UL,2UL,4UL}, \
{4UL,12UL,8UL,6UL,4UL,8UL}, \
@@ -364,5 +364,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
