Release v11.2.0_20250620
diff --git a/Source/portable/IAR/ARM_CA9/port.c b/Source/portable/IAR/ARM_CA9/port.c index b9126a9..9940833 100644 --- a/Source/portable/IAR/ARM_CA9/port.c +++ b/Source/portable/IAR/ARM_CA9/port.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -37,43 +37,43 @@ #include "task.h" #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS - #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET - #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configUNIQUE_INTERRUPT_PRIORITIES - #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #ifndef configSETUP_TICK_INTERRUPT - #error configSETUP_TICK_INTERRUPT() must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif /* configSETUP_TICK_INTERRUPT */ #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0 - #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0 + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0" #endif #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority" #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 /* Check the configuration. */ - #if( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #if ( configMAX_PRIORITIES > 32 ) + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." #endif #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /* In case security extensions are implemented. */ #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) - #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 ) + #error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )" #endif #ifndef configCLEAR_TICK_INTERRUPT @@ -81,45 +81,45 @@ #endif /* A critical section is exited when the critical section nesting count reaches -this value. */ -#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) + * this value. */ +#define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 ) /* In all GICs 255 can be written to the priority mask register to unmask all -(but the lowest) interrupt priority. */ -#define portUNMASK_VALUE ( 0xFFUL ) + * (but the lowest) interrupt priority. */ +#define portUNMASK_VALUE ( 0xFFUL ) /* Tasks are not created with a floating point context, but can be given a -floating point context after they have been created. A variable is stored as -part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task -does not have an FPU context, or any other value if the task does have an FPU -context. */ -#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) + * floating point context after they have been created. A variable is stored as + * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task + * does not have an FPU context, or any other value if the task does have an FPU + * context. */ +#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 ) /* Constants required to setup the initial task context. */ -#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) -#define portTHUMB_MODE_ADDRESS ( 0x01UL ) +#define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ +#define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 ) +#define portTHUMB_MODE_ADDRESS ( 0x01UL ) /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary -point is zero. */ -#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) + * point is zero. */ +#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 ) /* Masks all bits in the APSR other than the mode bits. */ -#define portAPSR_MODE_BITS_MASK ( 0x1F ) +#define portAPSR_MODE_BITS_MASK ( 0x1F ) /* The value of the mode bits in the APSR when the CPU is executing in user -mode. */ -#define portAPSR_USER_MODE ( 0x10 ) + * mode. */ +#define portAPSR_USER_MODE ( 0x10 ) /* Macro to unmask all interrupt priorities. */ -#define portCLEAR_INTERRUPT_MASK() \ -{ \ - __disable_irq(); \ - portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ - __asm( "DSB \n" \ - "ISB \n" ); \ - __enable_irq(); \ -} +#define portCLEAR_INTERRUPT_MASK() \ + { \ + __disable_irq(); \ + portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \ + __asm( "DSB \n" \ + "ISB \n" ); \ + __enable_irq(); \ + } /*-----------------------------------------------------------*/ @@ -137,21 +137,21 @@ /*-----------------------------------------------------------*/ /* A variable is used to keep track of the critical section nesting. This -variable has to be stored as part of the task context and must be initialised to -a non zero value to ensure interrupts don't inadvertently become unmasked before -the scheduler starts. As it is stored as part of the task context it will -automatically be set to 0 when the first task is started. */ + * variable has to be stored as part of the task context and must be initialised to + * a non zero value to ensure interrupts don't inadvertently become unmasked before + * the scheduler starts. As it is stored as part of the task context it will + * automatically be set to 0 when the first task is started. */ volatile uint32_t ulCriticalNesting = 9999UL; /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero -then a floating point context must be saved and restored for the task. */ + * then a floating point context must be saved and restored for the task. */ uint32_t ulPortTaskHasFPUContext = pdFALSE; /* Set to 1 to pend a context switch from an ISR. */ uint32_t ulPortYieldRequired = pdFALSE; /* Counts the interrupt nesting depth. A context switch is only performed if -if the nesting depth is 0. */ + * if the nesting depth is 0. */ uint32_t ulPortInterruptNesting = 0UL; @@ -160,14 +160,16 @@ /* * See header file for description. */ -StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) { /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. - - The fist real value on the stack is the status register, which is set for - system mode, with interrupts enabled. A few NULLs are added first to ensure - GDB does not try decoding a non-existent return address. */ + * expected by the portRESTORE_CONTEXT() macro. + * + * The fist real value on the stack is the status register, which is set for + * system mode, with interrupts enabled. A few NULLs are added first to ensure + * GDB does not try decoding a non-existent return address. */ *pxTopOfStack = NULL; pxTopOfStack--; *pxTopOfStack = NULL; @@ -189,43 +191,43 @@ pxTopOfStack--; /* Next all the registers other than the stack pointer. */ - *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ + *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ + *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ + *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ + *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ + *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ + *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ + *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ + *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ + *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ + *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ + *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ + *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ + *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ + *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ pxTopOfStack--; /* The task will start with a critical nesting count of 0 as interrupts are - enabled. */ + * enabled. */ *pxTopOfStack = portNO_CRITICAL_NESTING; pxTopOfStack--; /* The task will start without a floating point context. A task that uses - the floating point hardware must call vPortTaskUsesFPU() before executing - any floating point instructions. */ + * the floating point hardware must call vPortTaskUsesFPU() before executing + * any floating point instructions. */ *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT; return pxTopOfStack; @@ -235,32 +237,36 @@ static void prvTaskExitError( void ) { /* A function that implements a task must not exit or attempt to return to - its caller as there is nothing to return to. If a task wants to exit it - should instead call vTaskDelete( NULL ). - - Artificially force an assert() to be triggered if configASSERT() is - defined, then stop here so application writers can catch the error. */ + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ configASSERT( ulPortInterruptNesting == ~0UL ); portDISABLE_INTERRUPTS(); - for( ;; ); + + for( ; ; ) + { + } } /*-----------------------------------------------------------*/ BaseType_t xPortStartScheduler( void ) { -uint32_t ulAPSR; + uint32_t ulAPSR; /* Only continue if the CPU is not in User mode. The CPU must be in a - Privileged mode for the scheduler to start. */ + * Privileged mode for the scheduler to start. */ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) ); + ulAPSR &= portAPSR_MODE_BITS_MASK; configASSERT( ulAPSR != portAPSR_USER_MODE ); if( ulAPSR != portAPSR_USER_MODE ) { /* Only continue if the binary point value is set to its lowest possible - setting. See the comments in vPortValidateInterruptPriority() below for - more information. */ + * setting. See the comments in vPortValidateInterruptPriority() below for + * more information. */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ) @@ -274,8 +280,8 @@ } /* Will only get here if vTaskStartScheduler() was called with the CPU in - a non-privileged mode or the binary point register was not set to its lowest - possible value. */ + * a non-privileged mode or the binary point register was not set to its lowest + * possible value. */ return 0; } /*-----------------------------------------------------------*/ @@ -283,7 +289,7 @@ void vPortEndScheduler( void ) { /* Not implemented in ports where there is nothing to return to. - Artificially force an assert. */ + * Artificially force an assert. */ configASSERT( ulCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ @@ -293,16 +299,16 @@ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ ulPortSetInterruptMask(); - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ + /* Now that interrupts are disabled, ulCriticalNesting can be accessed + * directly. Increment ulCriticalNesting to keep a count of how many times + * portENTER_CRITICAL() has been called. */ ulCriticalNesting++; /* This is not the interrupt safe version of the enter critical function so - assert() if it is being called from an interrupt context. Only API - functions that end in "FromISR" can be used in an interrupt. Only assert if - the critical nesting count is 1 to protect against recursive calls if the - assert function also uses a critical section. */ + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ if( ulCriticalNesting == 1 ) { configASSERT( ulPortInterruptNesting == 0 ); @@ -315,15 +321,15 @@ if( ulCriticalNesting > portNO_CRITICAL_NESTING ) { /* Decrement the nesting count as the critical section is being - exited. */ + * exited. */ ulCriticalNesting--; /* If the nesting level has reached zero then all interrupt - priorities must be re-enabled. */ + * priorities must be re-enabled. */ if( ulCriticalNesting == portNO_CRITICAL_NESTING ) { /* Critical nesting has reached zero so all interrupt priorities - should be unmasked. */ + * should be unmasked. */ portCLEAR_INTERRUPT_MASK(); } } @@ -333,12 +339,12 @@ void FreeRTOS_Tick_Handler( void ) { /* Set interrupt mask before altering scheduler structures. The tick - handler runs at the lowest priority, so interrupts cannot already be masked, - so there is no need to save and restore the current mask value. */ + * handler runs at the lowest priority, so interrupts cannot already be masked, + * so there is no need to save and restore the current mask value. */ __disable_irq(); portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); - __asm( "DSB \n" - "ISB \n" ); + __asm( "DSB \n" + "ISB \n" ); __enable_irq(); /* Increment the RTOS tick. */ @@ -355,14 +361,14 @@ void vPortTaskUsesFPU( void ) { -uint32_t ulInitialFPSCR = 0; + uint32_t ulInitialFPSCR = 0; /* A task is registering the fact that it needs an FPU context. Set the - FPU flag (which is saved as part of the task context). */ + * FPU flag (which is saved as part of the task context). */ ulPortTaskHasFPUContext = pdTRUE; /* Initialise the floating point status register. */ - __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) ); + __asm( "FMXR FPSCR, %0" ::"r" ( ulInitialFPSCR ) ); } /*-----------------------------------------------------------*/ @@ -377,9 +383,10 @@ uint32_t ulPortSetInterruptMask( void ) { -uint32_t ulReturn; + uint32_t ulReturn; __disable_irq(); + if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) { /* Interrupts were already masked. */ @@ -389,49 +396,50 @@ { ulReturn = pdFALSE; portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); - __asm( "DSB \n" - "ISB \n" ); + __asm( "DSB \n" + "ISB \n" ); } + __enable_irq(); return ulReturn; } /*-----------------------------------------------------------*/ -#if( configASSERT_DEFINED == 1 ) +#if ( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { /* The following assertion will fail if a service routine (ISR) for - an interrupt that has been assigned a priority above - configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API - function. ISR safe FreeRTOS API functions must *only* be called - from interrupts that have been assigned a priority at or below - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - Numerically low interrupt priority numbers represent logically high - interrupt priorities, therefore the priority of the interrupt must - be set to a value equal to or numerically *higher* than - configMAX_SYSCALL_INTERRUPT_PRIORITY. - - FreeRTOS maintains separate thread and ISR API functions to ensure - interrupt entry is as fast and simple as possible. - - The following links provide detailed information: - https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - https://www.FreeRTOS.org/FAQHelp.html */ + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ); /* Priority grouping: The interrupt controller (GIC) allows the bits - that define each interrupt's priority to be split between bits that - define the interrupt's pre-emption priority bits and bits that define - the interrupt's sub-priority. For simplicity all bits must be defined - to be pre-emption priority bits. The following assertion will fail if - this is not the case (if some bits represent a sub-priority). - - The priority grouping is configured by the GIC's binary point register - (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest - possible value (which may be above 0). */ + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * The priority grouping is configured by the GIC's binary point register + * (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest + * possible value (which may be above 0). */ configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE ); }
diff --git a/Source/portable/IAR/ARM_CA9/portASM.h b/Source/portable/IAR/ARM_CA9/portASM.h index 31229b7..2855a0c 100644 --- a/Source/portable/IAR/ARM_CA9/portASM.h +++ b/Source/portable/IAR/ARM_CA9/portASM.h
@@ -1,6 +1,6 @@ ;/* -; * FreeRTOS Kernel V10.6.2 -; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * FreeRTOS Kernel V11.2.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT ; *
diff --git a/Source/portable/IAR/ARM_CA9/portASM.s b/Source/portable/IAR/ARM_CA9/portASM.s index e9c87c6..ebb86e9 100644 --- a/Source/portable/IAR/ARM_CA9/portASM.s +++ b/Source/portable/IAR/ARM_CA9/portASM.s
@@ -1,6 +1,6 @@ ;/* -; * FreeRTOS Kernel V10.6.2 -; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * FreeRTOS Kernel V11.2.0 +; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. ; * ; * SPDX-License-Identifier: MIT ; *
diff --git a/Source/portable/IAR/ARM_CA9/portmacro.h b/Source/portable/IAR/ARM_CA9/portmacro.h index 244fd41..f218e60 100644 --- a/Source/portable/IAR/ARM_CA9/portmacro.h +++ b/Source/portable/IAR/ARM_CA9/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -40,127 +40,127 @@ #include <intrinsics.h> - /*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the given hardware - * and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the given hardware + * and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ - /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long +/* Type definitions. */ + #define portCHAR char + #define portFLOAT float + #define portDOUBLE double + #define portLONG long + #define portSHORT short + #define portSTACK_TYPE uint32_t + #define portBASE_TYPE long - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; + typedef portSTACK_TYPE StackType_t; + typedef long BaseType_t; + typedef unsigned long UBaseType_t; - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL - /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do - not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - /* Hardware specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +/* Hardware specifics. */ + #define portSTACK_GROWTH ( -1 ) + #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) + #define portBYTE_ALIGNMENT 8 - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - /* Task utilities. */ +/* Task utilities. */ - /* Called at the end of an ISR that can cause a context switch. */ - #define portEND_SWITCHING_ISR( xSwitchRequired )\ - { \ - extern uint32_t ulPortYieldRequired; \ - \ - if( xSwitchRequired != pdFALSE ) \ - { \ - ulPortYieldRequired = pdTRUE; \ - } \ +/* Called at the end of an ISR that can cause a context switch. */ + #define portEND_SWITCHING_ISR( xSwitchRequired ) \ + { \ + extern uint32_t ulPortYieldRequired; \ + \ + if( xSwitchRequired != pdFALSE ) \ + { \ + ulPortYieldRequired = pdTRUE; \ + } \ } - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) - #define portYIELD() __asm( "SWI 0" ); + #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) + #define portYIELD() __asm( "SWI 0" ); - /*----------------------------------------------------------- - * Critical section control - *----------------------------------------------------------*/ +/*----------------------------------------------------------- +* Critical section control +*----------------------------------------------------------*/ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); extern uint32_t ulPortSetInterruptMask( void ); extern void vPortClearInterruptMask( uint32_t ulNewMaskValue ); - /* These macros do not globally disable/enable interrupts. They do mask off - interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ - #define portENTER_CRITICAL() vPortEnterCritical(); - #define portEXIT_CRITICAL() vPortExitCritical(); - #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() - #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) - #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x) +/* These macros do not globally disable/enable interrupts. They do mask off + * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */ + #define portENTER_CRITICAL() vPortEnterCritical(); + #define portEXIT_CRITICAL() vPortExitCritical(); + #define portDISABLE_INTERRUPTS() ulPortSetInterruptMask() + #define portENABLE_INTERRUPTS() vPortClearInterruptMask( 0 ) + #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask() + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortClearInterruptMask( x ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - /* Task function macros as described on the FreeRTOS.org WEB site. These are - not required for this port but included in case common demo code that uses these - macros is used. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not required for this port but included in case common demo code that uses these + * macros is used. */ + #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) + #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) - /* Prototype of the FreeRTOS tick handler. This must be installed as the - handler for whichever peripheral is used to generate the RTOS tick. */ +/* Prototype of the FreeRTOS tick handler. This must be installed as the + * handler for whichever peripheral is used to generate the RTOS tick. */ void FreeRTOS_Tick_Handler( void ); - /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() - before any floating point instructions are executed. */ +/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU() + * before any floating point instructions are executed. */ void vPortTaskUsesFPU( void ); - #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() + #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU() - #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) - #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) + #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL ) + #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL ) - /* Architecture specific optimisations. */ +/* Architecture specific optimisations. */ #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #endif #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 - /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) +/* Store/clear the ready priorities in a bit map. */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) - /*-----------------------------------------------------------*/ +/*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) ) #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ - #ifdef configASSERT + #if ( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif /* configASSERT */ - #define portNOP() __asm volatile( "NOP" ) + #define portNOP() __asm volatile ( "NOP" ) - /* Suppress warnings that are generated by the IAR tools, but cannot be - fixed in the source code because to do so would cause other compilers to - generate warnings. */ +/* Suppress warnings that are generated by the IAR tools, but cannot be + * fixed in the source code because to do so would cause other compilers to + * generate warnings. */ #pragma diag_suppress=Pe191 #pragma diag_suppress=Pa082 @@ -168,40 +168,40 @@ /* The number of bits to shift for an interrupt priority is dependent on the -number of bits implemented by the interrupt controller. */ + * number of bits implemented by the interrupt controller. */ #if configUNIQUE_INTERRUPT_PRIORITIES == 16 - #define portPRIORITY_SHIFT 4 - #define portMAX_BINARY_POINT_VALUE 3 + #define portPRIORITY_SHIFT 4 + #define portMAX_BINARY_POINT_VALUE 3 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32 - #define portPRIORITY_SHIFT 3 - #define portMAX_BINARY_POINT_VALUE 2 + #define portPRIORITY_SHIFT 3 + #define portMAX_BINARY_POINT_VALUE 2 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64 - #define portPRIORITY_SHIFT 2 - #define portMAX_BINARY_POINT_VALUE 1 + #define portPRIORITY_SHIFT 2 + #define portMAX_BINARY_POINT_VALUE 1 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128 - #define portPRIORITY_SHIFT 1 - #define portMAX_BINARY_POINT_VALUE 0 + #define portPRIORITY_SHIFT 1 + #define portMAX_BINARY_POINT_VALUE 0 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256 - #define portPRIORITY_SHIFT 0 - #define portMAX_BINARY_POINT_VALUE 0 -#else + #define portPRIORITY_SHIFT 0 + #define portMAX_BINARY_POINT_VALUE 0 +#else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware -#endif +#endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */ /* Interrupt controller access addresses. */ -#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) -#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) -#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) -#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) -#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) +#define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C ) +#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) +#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) +#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) -#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) -#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) -#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) -#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) -#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) -#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) -#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) +#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) ) +#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ) +#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET ) +#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) +#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) ) +#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) ) /* *INDENT-OFF* */ #ifdef __cplusplus
diff --git a/Source/portable/IAR/ARM_CM0/port.c b/Source/portable/IAR/ARM_CM0/port.c index b9999a0..6f7c899 100644 --- a/Source/portable/IAR/ARM_CM0/port.c +++ b/Source/portable/IAR/ARM_CM0/port.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -37,6 +37,9 @@ #include "FreeRTOS.h" #include "task.h" +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the NVIC. */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) @@ -53,6 +56,10 @@ #define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL ) #define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to set up the initial stack. */ #define portINITIAL_XPSR ( 0x01000000 ) @@ -121,6 +128,10 @@ */ static void prvTaskExitError( void ); +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void xPortPendSVHandler( void ); /*-----------------------------------------------------------*/ /* @@ -168,6 +179,41 @@ */ BaseType_t xPortStartScheduler( void ) { + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the function xPortPendSVHandler for PendSV + * interrupt. + * 2. Indirect Routing - Install separate handler for PendSV interrupt and + * route program control from that handler to xPortPendSVHandler function. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + /* Point pxVectorTable to the interrupt vector table. Systems without + * a VTOR register provide the value zero in the VTOR register and + * the vector table itself is located at the address 0x00000000. */ + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handler for PendSV interrupt. We do not check the installation of the + * SysTick handler because the application may choose to drive the RTOS + * tick using a timer other than the SysTick timer by overriding the + * weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handler. For help installing the FreeRTOS handler, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; @@ -233,13 +279,19 @@ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); }
diff --git a/Source/portable/IAR/ARM_CM0/portasm.s b/Source/portable/IAR/ARM_CM0/portasm.s index 8b5caf2..bc33363 100644 --- a/Source/portable/IAR/ARM_CM0/portasm.s +++ b/Source/portable/IAR/ARM_CM0/portasm.s
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -91,15 +91,15 @@ vPortSVCHandler; /* This function is no longer used, but retained for backward - compatibility. */ + * compatibility. */ bx lr /*-----------------------------------------------------------*/ vPortStartFirstTask - /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector - table offset register that can be used to locate the initial stack value. - Not all M0 parts have the application vector table at address 0. */ + /* Don't reset the MSP stack as is done on CM3/4 devices. The vector table + * in some CM0 devices cannot be modified and thus may not hold the + * application's initial MSP value. */ ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */ ldr r1, [r3]
diff --git a/Source/portable/IAR/ARM_CM0/portmacro.h b/Source/portable/IAR/ARM_CM0/portmacro.h index e0ccf6b..e384e59 100644 --- a/Source/portable/IAR/ARM_CM0/portmacro.h +++ b/Source/portable/IAR/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -86,9 +86,21 @@ extern void vPortYield( void ); #define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 ) #define portNVIC_PENDSVSET 0x10000000 -#define portYIELD() vPortYield() -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portYIELD() vPortYield() +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S index 4d805f3..eaafcee 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -48,12 +48,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskDelayUntil_Unpriv MPU_xTaskDelayUntil_Priv: - pop {r0, r1} b MPU_xTaskDelayUntilImpl MPU_xTaskDelayUntil_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskDelayUntil /*-----------------------------------------------------------*/ @@ -63,12 +62,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskAbortDelay_Unpriv MPU_xTaskAbortDelay_Priv: - pop {r0, r1} b MPU_xTaskAbortDelayImpl MPU_xTaskAbortDelay_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskAbortDelay /*-----------------------------------------------------------*/ @@ -78,12 +76,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskDelay_Unpriv MPU_vTaskDelay_Priv: - pop {r0, r1} b MPU_vTaskDelayImpl MPU_vTaskDelay_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskDelay /*-----------------------------------------------------------*/ @@ -93,12 +90,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTaskPriorityGet_Unpriv MPU_uxTaskPriorityGet_Priv: - pop {r0, r1} b MPU_uxTaskPriorityGetImpl MPU_uxTaskPriorityGet_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTaskPriorityGet /*-----------------------------------------------------------*/ @@ -108,12 +104,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_eTaskGetState_Unpriv MPU_eTaskGetState_Priv: - pop {r0, r1} b MPU_eTaskGetStateImpl MPU_eTaskGetState_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_eTaskGetState /*-----------------------------------------------------------*/ @@ -123,12 +118,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskGetInfo_Unpriv MPU_vTaskGetInfo_Priv: - pop {r0, r1} b MPU_vTaskGetInfoImpl MPU_vTaskGetInfo_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskGetInfo /*-----------------------------------------------------------*/ @@ -138,12 +132,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGetIdleTaskHandle_Unpriv MPU_xTaskGetIdleTaskHandle_Priv: - pop {r0, r1} b MPU_xTaskGetIdleTaskHandleImpl MPU_xTaskGetIdleTaskHandle_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGetIdleTaskHandle /*-----------------------------------------------------------*/ @@ -153,12 +146,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskSuspend_Unpriv MPU_vTaskSuspend_Priv: - pop {r0, r1} b MPU_vTaskSuspendImpl MPU_vTaskSuspend_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskSuspend /*-----------------------------------------------------------*/ @@ -168,12 +160,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskResume_Unpriv MPU_vTaskResume_Priv: - pop {r0, r1} b MPU_vTaskResumeImpl MPU_vTaskResume_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskResume /*-----------------------------------------------------------*/ @@ -183,12 +174,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGetTickCount_Unpriv MPU_xTaskGetTickCount_Priv: - pop {r0, r1} b MPU_xTaskGetTickCountImpl MPU_xTaskGetTickCount_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGetTickCount /*-----------------------------------------------------------*/ @@ -198,42 +188,25 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTaskGetNumberOfTasks_Unpriv MPU_uxTaskGetNumberOfTasks_Priv: - pop {r0, r1} b MPU_uxTaskGetNumberOfTasksImpl MPU_uxTaskGetNumberOfTasks_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0, r1} - mrs r0, control - movs r1, #1 - tst r0, r1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0, r1} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0, r1} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0, r1} mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGetRunTimeCounter_Unpriv MPU_ulTaskGetRunTimeCounter_Priv: - pop {r0, r1} b MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounter_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGetRunTimeCounter /*-----------------------------------------------------------*/ @@ -243,12 +216,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGetRunTimePercent_Unpriv MPU_ulTaskGetRunTimePercent_Priv: - pop {r0, r1} b MPU_ulTaskGetRunTimePercentImpl MPU_ulTaskGetRunTimePercent_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGetRunTimePercent /*-----------------------------------------------------------*/ @@ -258,12 +230,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGetIdleRunTimePercent_Unpriv MPU_ulTaskGetIdleRunTimePercent_Priv: - pop {r0, r1} b MPU_ulTaskGetIdleRunTimePercentImpl MPU_ulTaskGetIdleRunTimePercent_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent /*-----------------------------------------------------------*/ @@ -273,12 +244,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv MPU_ulTaskGetIdleRunTimeCounter_Priv: - pop {r0, r1} b MPU_ulTaskGetIdleRunTimeCounterImpl MPU_ulTaskGetIdleRunTimeCounter_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter /*-----------------------------------------------------------*/ @@ -288,12 +258,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskSetApplicationTaskTag_Unpriv MPU_vTaskSetApplicationTaskTag_Priv: - pop {r0, r1} b MPU_vTaskSetApplicationTaskTagImpl MPU_vTaskSetApplicationTaskTag_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskSetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -303,12 +272,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGetApplicationTaskTag_Unpriv MPU_xTaskGetApplicationTaskTag_Priv: - pop {r0, r1} b MPU_xTaskGetApplicationTaskTagImpl MPU_xTaskGetApplicationTaskTag_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -318,12 +286,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv MPU_vTaskSetThreadLocalStoragePointer_Priv: - pop {r0, r1} b MPU_vTaskSetThreadLocalStoragePointerImpl MPU_vTaskSetThreadLocalStoragePointer_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -333,12 +300,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv MPU_pvTaskGetThreadLocalStoragePointer_Priv: - pop {r0, r1} b MPU_pvTaskGetThreadLocalStoragePointerImpl MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -348,12 +314,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTaskGetSystemState_Unpriv MPU_uxTaskGetSystemState_Priv: - pop {r0, r1} b MPU_uxTaskGetSystemStateImpl MPU_uxTaskGetSystemState_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTaskGetSystemState /*-----------------------------------------------------------*/ @@ -363,12 +328,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTaskGetStackHighWaterMark_Unpriv MPU_uxTaskGetStackHighWaterMark_Priv: - pop {r0, r1} b MPU_uxTaskGetStackHighWaterMarkImpl MPU_uxTaskGetStackHighWaterMark_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark /*-----------------------------------------------------------*/ @@ -378,12 +342,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTaskGetStackHighWaterMark2_Unpriv MPU_uxTaskGetStackHighWaterMark2_Priv: - pop {r0, r1} b MPU_uxTaskGetStackHighWaterMark2Impl MPU_uxTaskGetStackHighWaterMark2_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 /*-----------------------------------------------------------*/ @@ -393,12 +356,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGetCurrentTaskHandle_Unpriv MPU_xTaskGetCurrentTaskHandle_Priv: - pop {r0, r1} b MPU_xTaskGetCurrentTaskHandleImpl MPU_xTaskGetCurrentTaskHandle_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle /*-----------------------------------------------------------*/ @@ -408,12 +370,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGetSchedulerState_Unpriv MPU_xTaskGetSchedulerState_Priv: - pop {r0, r1} b MPU_xTaskGetSchedulerStateImpl MPU_xTaskGetSchedulerState_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGetSchedulerState /*-----------------------------------------------------------*/ @@ -423,12 +384,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskSetTimeOutState_Unpriv MPU_vTaskSetTimeOutState_Priv: - pop {r0, r1} b MPU_vTaskSetTimeOutStateImpl MPU_vTaskSetTimeOutState_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskSetTimeOutState /*-----------------------------------------------------------*/ @@ -438,12 +398,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskCheckForTimeOut_Unpriv MPU_xTaskCheckForTimeOut_Priv: - pop {r0, r1} b MPU_xTaskCheckForTimeOutImpl MPU_xTaskCheckForTimeOut_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskCheckForTimeOut /*-----------------------------------------------------------*/ @@ -453,12 +412,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGenericNotify_Unpriv MPU_xTaskGenericNotify_Priv: - pop {r0, r1} b MPU_xTaskGenericNotifyImpl MPU_xTaskGenericNotify_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGenericNotify /*-----------------------------------------------------------*/ @@ -468,12 +426,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGenericNotifyWait_Unpriv MPU_xTaskGenericNotifyWait_Priv: - pop {r0, r1} b MPU_xTaskGenericNotifyWaitImpl MPU_xTaskGenericNotifyWait_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGenericNotifyWait /*-----------------------------------------------------------*/ @@ -483,12 +440,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGenericNotifyTake_Unpriv MPU_ulTaskGenericNotifyTake_Priv: - pop {r0, r1} b MPU_ulTaskGenericNotifyTakeImpl MPU_ulTaskGenericNotifyTake_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGenericNotifyTake /*-----------------------------------------------------------*/ @@ -498,12 +454,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGenericNotifyStateClear_Unpriv MPU_xTaskGenericNotifyStateClear_Priv: - pop {r0, r1} b MPU_xTaskGenericNotifyStateClearImpl MPU_xTaskGenericNotifyStateClear_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGenericNotifyStateClear /*-----------------------------------------------------------*/ @@ -513,12 +468,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGenericNotifyValueClear_Unpriv MPU_ulTaskGenericNotifyValueClear_Priv: - pop {r0, r1} b MPU_ulTaskGenericNotifyValueClearImpl MPU_ulTaskGenericNotifyValueClear_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear /*-----------------------------------------------------------*/ @@ -528,12 +482,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueGenericSend_Unpriv MPU_xQueueGenericSend_Priv: - pop {r0, r1} b MPU_xQueueGenericSendImpl MPU_xQueueGenericSend_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueGenericSend /*-----------------------------------------------------------*/ @@ -543,12 +496,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxQueueMessagesWaiting_Unpriv MPU_uxQueueMessagesWaiting_Priv: - pop {r0, r1} b MPU_uxQueueMessagesWaitingImpl MPU_uxQueueMessagesWaiting_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxQueueMessagesWaiting /*-----------------------------------------------------------*/ @@ -558,12 +510,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxQueueSpacesAvailable_Unpriv MPU_uxQueueSpacesAvailable_Priv: - pop {r0, r1} b MPU_uxQueueSpacesAvailableImpl MPU_uxQueueSpacesAvailable_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxQueueSpacesAvailable /*-----------------------------------------------------------*/ @@ -573,12 +524,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueReceive_Unpriv MPU_xQueueReceive_Priv: - pop {r0, r1} b MPU_xQueueReceiveImpl MPU_xQueueReceive_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueReceive /*-----------------------------------------------------------*/ @@ -588,12 +538,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueuePeek_Unpriv MPU_xQueuePeek_Priv: - pop {r0, r1} b MPU_xQueuePeekImpl MPU_xQueuePeek_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueuePeek /*-----------------------------------------------------------*/ @@ -603,12 +552,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueSemaphoreTake_Unpriv MPU_xQueueSemaphoreTake_Priv: - pop {r0, r1} b MPU_xQueueSemaphoreTakeImpl MPU_xQueueSemaphoreTake_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueSemaphoreTake /*-----------------------------------------------------------*/ @@ -618,12 +566,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueGetMutexHolder_Unpriv MPU_xQueueGetMutexHolder_Priv: - pop {r0, r1} b MPU_xQueueGetMutexHolderImpl MPU_xQueueGetMutexHolder_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueGetMutexHolder /*-----------------------------------------------------------*/ @@ -633,12 +580,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueTakeMutexRecursive_Unpriv MPU_xQueueTakeMutexRecursive_Priv: - pop {r0, r1} b MPU_xQueueTakeMutexRecursiveImpl MPU_xQueueTakeMutexRecursive_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueTakeMutexRecursive /*-----------------------------------------------------------*/ @@ -648,12 +594,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueGiveMutexRecursive_Unpriv MPU_xQueueGiveMutexRecursive_Priv: - pop {r0, r1} b MPU_xQueueGiveMutexRecursiveImpl MPU_xQueueGiveMutexRecursive_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueGiveMutexRecursive /*-----------------------------------------------------------*/ @@ -663,12 +608,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueSelectFromSet_Unpriv MPU_xQueueSelectFromSet_Priv: - pop {r0, r1} b MPU_xQueueSelectFromSetImpl MPU_xQueueSelectFromSet_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueSelectFromSet /*-----------------------------------------------------------*/ @@ -678,12 +622,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueAddToSet_Unpriv MPU_xQueueAddToSet_Priv: - pop {r0, r1} b MPU_xQueueAddToSetImpl MPU_xQueueAddToSet_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueAddToSet /*-----------------------------------------------------------*/ @@ -693,12 +636,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vQueueAddToRegistry_Unpriv MPU_vQueueAddToRegistry_Priv: - pop {r0, r1} b MPU_vQueueAddToRegistryImpl MPU_vQueueAddToRegistry_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vQueueAddToRegistry /*-----------------------------------------------------------*/ @@ -708,12 +650,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vQueueUnregisterQueue_Unpriv MPU_vQueueUnregisterQueue_Priv: - pop {r0, r1} b MPU_vQueueUnregisterQueueImpl MPU_vQueueUnregisterQueue_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vQueueUnregisterQueue /*-----------------------------------------------------------*/ @@ -723,12 +664,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_pcQueueGetName_Unpriv MPU_pcQueueGetName_Priv: - pop {r0, r1} b MPU_pcQueueGetNameImpl MPU_pcQueueGetName_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_pcQueueGetName /*-----------------------------------------------------------*/ @@ -738,12 +678,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_pvTimerGetTimerID_Unpriv MPU_pvTimerGetTimerID_Priv: - pop {r0, r1} b MPU_pvTimerGetTimerIDImpl MPU_pvTimerGetTimerID_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_pvTimerGetTimerID /*-----------------------------------------------------------*/ @@ -753,12 +692,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTimerSetTimerID_Unpriv MPU_vTimerSetTimerID_Priv: - pop {r0, r1} b MPU_vTimerSetTimerIDImpl MPU_vTimerSetTimerID_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTimerSetTimerID /*-----------------------------------------------------------*/ @@ -768,12 +706,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTimerIsTimerActive_Unpriv MPU_xTimerIsTimerActive_Priv: - pop {r0, r1} b MPU_xTimerIsTimerActiveImpl MPU_xTimerIsTimerActive_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTimerIsTimerActive /*-----------------------------------------------------------*/ @@ -783,34 +720,26 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv MPU_xTimerGetTimerDaemonTaskHandle_Priv: - pop {r0, r1} b MPU_xTimerGetTimerDaemonTaskHandleImpl MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0, r1} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control movs r1, #1 tst r0, r1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: - pop {r0, r1} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: - pop {r0, r1} - b MPU_xTimerGenericCommandPrivImpl - + pop {r0, r1} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -819,12 +748,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_pcTimerGetName_Unpriv MPU_pcTimerGetName_Priv: - pop {r0, r1} b MPU_pcTimerGetNameImpl MPU_pcTimerGetName_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_pcTimerGetName /*-----------------------------------------------------------*/ @@ -834,12 +762,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTimerSetReloadMode_Unpriv MPU_vTimerSetReloadMode_Priv: - pop {r0, r1} b MPU_vTimerSetReloadModeImpl MPU_vTimerSetReloadMode_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTimerSetReloadMode /*-----------------------------------------------------------*/ @@ -849,12 +776,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTimerGetReloadMode_Unpriv MPU_xTimerGetReloadMode_Priv: - pop {r0, r1} b MPU_xTimerGetReloadModeImpl MPU_xTimerGetReloadMode_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -864,12 +790,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTimerGetReloadMode_Unpriv MPU_uxTimerGetReloadMode_Priv: - pop {r0, r1} b MPU_uxTimerGetReloadModeImpl MPU_uxTimerGetReloadMode_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -879,12 +804,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTimerGetPeriod_Unpriv MPU_xTimerGetPeriod_Priv: - pop {r0, r1} b MPU_xTimerGetPeriodImpl MPU_xTimerGetPeriod_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTimerGetPeriod /*-----------------------------------------------------------*/ @@ -894,12 +818,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTimerGetExpiryTime_Unpriv MPU_xTimerGetExpiryTime_Priv: - pop {r0, r1} b MPU_xTimerGetExpiryTimeImpl MPU_xTimerGetExpiryTime_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTimerGetExpiryTime /*-----------------------------------------------------------*/ @@ -909,12 +832,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xEventGroupWaitBits_Unpriv MPU_xEventGroupWaitBits_Priv: - pop {r0, r1} b MPU_xEventGroupWaitBitsImpl MPU_xEventGroupWaitBits_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xEventGroupWaitBits /*-----------------------------------------------------------*/ @@ -924,12 +846,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xEventGroupClearBits_Unpriv MPU_xEventGroupClearBits_Priv: - pop {r0, r1} b MPU_xEventGroupClearBitsImpl MPU_xEventGroupClearBits_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xEventGroupClearBits /*-----------------------------------------------------------*/ @@ -939,12 +860,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xEventGroupSetBits_Unpriv MPU_xEventGroupSetBits_Priv: - pop {r0, r1} b MPU_xEventGroupSetBitsImpl MPU_xEventGroupSetBits_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xEventGroupSetBits /*-----------------------------------------------------------*/ @@ -954,12 +874,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xEventGroupSync_Unpriv MPU_xEventGroupSync_Priv: - pop {r0, r1} b MPU_xEventGroupSyncImpl MPU_xEventGroupSync_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xEventGroupSync /*-----------------------------------------------------------*/ @@ -969,12 +888,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxEventGroupGetNumber_Unpriv MPU_uxEventGroupGetNumber_Priv: - pop {r0, r1} b MPU_uxEventGroupGetNumberImpl MPU_uxEventGroupGetNumber_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxEventGroupGetNumber /*-----------------------------------------------------------*/ @@ -984,12 +902,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vEventGroupSetNumber_Unpriv MPU_vEventGroupSetNumber_Priv: - pop {r0, r1} b MPU_vEventGroupSetNumberImpl MPU_vEventGroupSetNumber_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vEventGroupSetNumber /*-----------------------------------------------------------*/ @@ -999,12 +916,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferSend_Unpriv MPU_xStreamBufferSend_Priv: - pop {r0, r1} b MPU_xStreamBufferSendImpl MPU_xStreamBufferSend_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferSend /*-----------------------------------------------------------*/ @@ -1014,12 +930,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferReceive_Unpriv MPU_xStreamBufferReceive_Priv: - pop {r0, r1} b MPU_xStreamBufferReceiveImpl MPU_xStreamBufferReceive_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferReceive /*-----------------------------------------------------------*/ @@ -1029,12 +944,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferIsFull_Unpriv MPU_xStreamBufferIsFull_Priv: - pop {r0, r1} b MPU_xStreamBufferIsFullImpl MPU_xStreamBufferIsFull_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferIsFull /*-----------------------------------------------------------*/ @@ -1044,12 +958,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferIsEmpty_Unpriv MPU_xStreamBufferIsEmpty_Priv: - pop {r0, r1} b MPU_xStreamBufferIsEmptyImpl MPU_xStreamBufferIsEmpty_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferIsEmpty /*-----------------------------------------------------------*/ @@ -1059,12 +972,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferSpacesAvailable_Unpriv MPU_xStreamBufferSpacesAvailable_Priv: - pop {r0, r1} b MPU_xStreamBufferSpacesAvailableImpl MPU_xStreamBufferSpacesAvailable_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferSpacesAvailable /*-----------------------------------------------------------*/ @@ -1074,12 +986,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferBytesAvailable_Unpriv MPU_xStreamBufferBytesAvailable_Priv: - pop {r0, r1} b MPU_xStreamBufferBytesAvailableImpl MPU_xStreamBufferBytesAvailable_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferBytesAvailable /*-----------------------------------------------------------*/ @@ -1089,12 +1000,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferSetTriggerLevel_Unpriv MPU_xStreamBufferSetTriggerLevel_Priv: - pop {r0, r1} b MPU_xStreamBufferSetTriggerLevelImpl MPU_xStreamBufferSetTriggerLevel_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel /*-----------------------------------------------------------*/ @@ -1104,12 +1014,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv MPU_xStreamBufferNextMessageLengthBytes_Priv: - pop {r0, r1} b MPU_xStreamBufferNextMessageLengthBytesImpl MPU_xStreamBufferNextMessageLengthBytes_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes /*-----------------------------------------------------------*/ @@ -1160,10 +1069,6 @@ MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1316,9 +1221,9 @@ MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/port.c b/Source/portable/IAR/ARM_CM23/non_secure/port.c index 9712ac3..f16a343 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM23/non_secure/port.c
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -54,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 @@ -68,6 +70,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,8 +109,17 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) /*-----------------------------------------------------------*/ /** @@ -111,8 +138,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,72 +161,79 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + +/* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ /* Enable privileged access to unmapped region. */ #define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) @@ -343,6 +377,20 @@ * any secure calls. */ #define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ /** @@ -351,7 +399,7 @@ */ static void prvTaskExitError( void ); -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief Extract MPU region's access permissions from the Region Base Address @@ -362,7 +410,7 @@ * @return uint32_t Access permissions. */ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; -#endif /* configENABLE_MPU */ +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ #if ( configENABLE_MPU == 1 ) @@ -380,6 +428,26 @@ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_FPU */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + +/** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + /** * @brief Setup the timer to generate the tick interrupts. * @@ -448,13 +516,13 @@ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,24 +530,24 @@ #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ -#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief This variable is set to pdTRUE when the scheduler is started. */ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; -#endif +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /** * @brief Each task maintains its own interrupt status in the critical nesting @@ -501,13 +569,13 @@ * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -531,6 +599,7 @@ /*-----------------------------------------------------------*/ #if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) { uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; @@ -746,6 +815,7 @@ __asm volatile ( "cpsie i" ::: "memory" ); } } + #endif /* configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ @@ -760,8 +830,15 @@ } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -795,7 +872,8 @@ } /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ { uint32_t ulAccessPermissions = 0; @@ -812,13 +890,16 @@ return ulAccessPermissions; } -#endif /* configENABLE_MPU */ + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -903,10 +984,12 @@ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ #if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ { #if ( configENABLE_TRUSTZONE == 1 ) @@ -928,6 +1011,7 @@ * LSPEN = 1 ==> Enable lazy context save of FP state. */ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); } + #endif /* configENABLE_FPU */ /*-----------------------------------------------------------*/ @@ -972,13 +1056,19 @@ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1078,7 @@ { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1174,24 @@ vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1116,6 +1213,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1154,12 +1252,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1268,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1190,11 +1287,19 @@ /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; @@ -1224,14 +1329,13 @@ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1259,6 +1363,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -1293,12 +1398,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1414,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1436,11 @@ /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1458,13 @@ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1392,6 +1499,7 @@ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ { uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ ulIndex++; @@ -1410,21 +1518,21 @@ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,20 +1543,30 @@ #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ ulIndex++; } else { xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1469,6 +1587,20 @@ } #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + return &( xMPUSettings->ulContext[ ulIndex ] ); } @@ -1483,7 +1615,7 @@ * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1637,7 @@ } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1672,7 @@ pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1551,6 +1683,20 @@ } #endif /* portPRELOAD_REGISTERS */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + return pxTopOfStack; } @@ -1559,22 +1705,52 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) { - volatile uint32_t ulOriginalPriority; + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1769,10 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1810,22 @@ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ #if ( configENABLE_MPU == 1 ) { @@ -1660,11 +1841,11 @@ /* Initialize the critical nesting count ready for the first task. */ ulCriticalNesting = 0; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { xSchedulerRunning = pdTRUE; } - #endif + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /* Start the first task. */ vStartFirstTask(); @@ -1692,15 +1873,17 @@ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, - uint32_t ulStackDepth ) + configSTACK_DEPTH_TYPE uxStackDepth ) { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1719,10 +1902,10 @@ * which case the stack region parameters will be valid. At all other * times the stack parameters will not be valid and it is assumed that * the stack region has already been configured. */ - if( ulStackDepth > 0 ) + if( uxStackDepth > 0 ) { ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; - ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; /* If the stack is within the privileged SRAM, do not protect it * using a separate MPU region. This is needed because privileged @@ -1790,6 +1973,16 @@ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | ( portMPU_RLAR_REGION_ENABLE ); + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + /* Normal memory/ Device memory. */ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) { @@ -1812,10 +2005,12 @@ lIndex++; } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, uint32_t ulBufferLength, uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ @@ -1825,7 +2020,15 @@ BaseType_t xAccessGranted = pdFALSE; const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ - if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) { xAccessGranted = pdTRUE; } @@ -1860,7 +2063,8 @@ return xAccessGranted; } -#endif /* configENABLE_MPU */ + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /*-----------------------------------------------------------*/ BaseType_t xPortIsInsideInterrupt( void ) @@ -1886,7 +2090,7 @@ } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1924,7 +2128,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); } @@ -1944,7 +2148,7 @@ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) @@ -2041,3 +2245,38 @@ #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portasm.h b/Source/portable/IAR/ARM_CM23/non_secure/portasm.h index f64ceb5..53b4b6e 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -52,7 +52,7 @@ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portasm.s b/Source/portable/IAR/ARM_CM23/non_secure/portasm.s index 3c17889..6b25588 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -40,6 +40,7 @@ #define configUSE_MPU_WRAPPERS_V1 0 #endif + EXTERN pxCurrentTCB EXTERN xSecureContext EXTERN vTaskSwitchContext @@ -169,7 +170,6 @@ ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ subs r2, #20 msr psp, r3 - msr psplim, r4 msr control, r5 mov lr, r6 ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ @@ -205,7 +205,6 @@ ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ ldr r4, =xSecureContext str r1, [r4] /* Set xSecureContext to this task's value for the same. */ - msr psplim, r2 /* Set this task's PSPLIM value. */ movs r1, #2 /* r1 = 2. */ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ adds r0, #32 /* Discard everything up to r0. */ @@ -281,7 +280,7 @@ save_special_regs: mrs r3, psp /* r3 = PSP. */ - mrs r4, psplim /* r4 = PSPLIM. */ + movs r4, #0 /* r4 = 0. 0 is stored in the PSPLIM slot. */ mrs r5, control /* r5 = CONTROL. */ mov r6, lr /* r6 = LR. */ stmia r2!, {r0, r3-r6} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ @@ -349,7 +348,6 @@ ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */ subs r2, #20 msr psp, r3 - msr psplim, r4 msr control, r5 mov lr, r6 ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ @@ -408,7 +406,7 @@ subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ str r2, [r1] /* Save the new top of stack in TCB. */ - mrs r1, psplim /* r1 = PSPLIM. */ + movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */ mov r3, lr /* r3 = LR/EXC_RETURN. */ stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ @@ -419,7 +417,7 @@ ldr r1, [r3] /* Read pxCurrentTCB. */ subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ str r2, [r1] /* Save the new top of stack in TCB. */ - mrs r1, psplim /* r1 = PSPLIM. */ + movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */ mov r3, lr /* r3 = LR/EXC_RETURN. */ stmia r2!, {r0, r1, r3-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */ mov r4, r8 /* r4 = r8. */ @@ -438,7 +436,6 @@ ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ - msr psplim, r1 /* Restore the PSPLIM register value for the task. */ mov lr, r4 /* LR = r4. */ ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ str r0, [r3] /* Restore the task's xSecureContext. */
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h index 19d7556..6cf50c5 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -48,9 +48,10 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M23" -#define portHAS_BASEPRI 0 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -60,6 +61,12 @@ #if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23. +#endif /*-----------------------------------------------------------*/ /**
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h index 6f666da..2dfac6a 100644 --- a/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM23/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -117,7 +119,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -125,6 +127,18 @@ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; #endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ /*-----------------------------------------------------------*/ /** @@ -137,7 +151,7 @@ #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) @@ -193,8 +207,8 @@ */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -223,7 +237,20 @@ */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +-----------+---------------+----------+-----------------+------------------------------+-----+ @@ -232,11 +259,24 @@ * +-----------+---------------+----------+-----------------+------------------------------+-----+ * * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 + * 16 17 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 54 + #define MAX_CONTEXT_SIZE 55 - #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ /* * +-----------+---------------+----------+-----------------+----------------------+-----+ @@ -245,15 +285,28 @@ * +-----------+---------------+----------+-----------------+----------------------+-----+ * * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 + * 16 17 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 53 + #define MAX_CONTEXT_SIZE 54 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +----------+-----------------+------------------------------+-----+ @@ -264,7 +317,20 @@ * <---------><----------------><------------------------------><----> * 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 22 + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ @@ -277,17 +343,17 @@ * <---------><----------------><----------------------><----> * 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 21 + #define MAX_CONTEXT_SIZE 21 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) -/* Size of an Access Control List (ACL) entry in bits. */ + /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) typedef struct MPU_SETTINGS @@ -312,8 +378,8 @@ * @brief Validate priority of ISRs that are allowed to call FreeRTOS * system calls. */ -#ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +399,29 @@ /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +507,12 @@ extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +523,56 @@ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus }
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context.c b/Source/portable/IAR/ARM_CM23/secure/secure_context.c index e37dd96..62bcfa1 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_context.c +++ b/Source/portable/IAR/ARM_CM23/secure/secure_context.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -207,7 +207,7 @@ * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ @@ -219,16 +219,16 @@ if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } #else /* configENABLE_MPU */ - { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; - } + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex;
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context.h b/Source/portable/IAR/ARM_CM23/secure/secure_context.h index 2220ea6..8b93857 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_context.h +++ b/Source/portable/IAR/ARM_CM23/secure/secure_context.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s index 1e4b3a5..e3ff975 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s +++ b/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_heap.c b/Source/portable/IAR/ARM_CM23/secure/secure_heap.c index 19f7c23..b0e83b4 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_heap.c +++ b/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -29,6 +29,9 @@ /* Standard includes. */ #include <stdint.h> +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + /* Secure context heap includes. */ #include "secure_heap.h" @@ -62,6 +65,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +142,6 @@ static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +186,6 @@ /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -229,7 +237,7 @@ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; } - /* If the block being inserted plugged a gab, so was merged with the block + /* If the block being inserted plugged a gap, so was merged with the block * before and the block after, then it's pxNextFreeBlock pointer will have * already been set, and should not be set here as that would make it point * to itself. */ @@ -250,6 +258,8 @@ BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +272,29 @@ mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +303,20 @@ } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +359,8 @@ pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -352,9 +378,11 @@ mtCOVERAGE_TEST_MARKER(); } + xAllocatedBlockSize = pxBlock->xBlockSize; + /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -372,20 +400,23 @@ mtCOVERAGE_TEST_MARKER(); } - traceMALLOC( pvReturn, xWantedSize ); + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +439,16 @@ pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); {
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_heap.h b/Source/portable/IAR/ARM_CM23/secure/secure_heap.h index 75c9cb0..61a96da 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_heap.h +++ b/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_init.c b/Source/portable/IAR/ARM_CM23/secure/secure_init.c index f93bfce..f7f7e67 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_init.c +++ b/Source/portable/IAR/ARM_CM23/secure/secure_init.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -93,7 +93,7 @@ * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_init.h b/Source/portable/IAR/ARM_CM23/secure/secure_init.h index e6c9da0..46ffbd9 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_init.h +++ b/Source/portable/IAR/ARM_CM23/secure/secure_init.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h index d7ac583..34494e1 100644 --- a/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h +++ b/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S index 4d805f3..eaafcee 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -48,12 +48,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskDelayUntil_Unpriv MPU_xTaskDelayUntil_Priv: - pop {r0, r1} b MPU_xTaskDelayUntilImpl MPU_xTaskDelayUntil_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskDelayUntil /*-----------------------------------------------------------*/ @@ -63,12 +62,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskAbortDelay_Unpriv MPU_xTaskAbortDelay_Priv: - pop {r0, r1} b MPU_xTaskAbortDelayImpl MPU_xTaskAbortDelay_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskAbortDelay /*-----------------------------------------------------------*/ @@ -78,12 +76,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskDelay_Unpriv MPU_vTaskDelay_Priv: - pop {r0, r1} b MPU_vTaskDelayImpl MPU_vTaskDelay_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskDelay /*-----------------------------------------------------------*/ @@ -93,12 +90,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTaskPriorityGet_Unpriv MPU_uxTaskPriorityGet_Priv: - pop {r0, r1} b MPU_uxTaskPriorityGetImpl MPU_uxTaskPriorityGet_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTaskPriorityGet /*-----------------------------------------------------------*/ @@ -108,12 +104,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_eTaskGetState_Unpriv MPU_eTaskGetState_Priv: - pop {r0, r1} b MPU_eTaskGetStateImpl MPU_eTaskGetState_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_eTaskGetState /*-----------------------------------------------------------*/ @@ -123,12 +118,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskGetInfo_Unpriv MPU_vTaskGetInfo_Priv: - pop {r0, r1} b MPU_vTaskGetInfoImpl MPU_vTaskGetInfo_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskGetInfo /*-----------------------------------------------------------*/ @@ -138,12 +132,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGetIdleTaskHandle_Unpriv MPU_xTaskGetIdleTaskHandle_Priv: - pop {r0, r1} b MPU_xTaskGetIdleTaskHandleImpl MPU_xTaskGetIdleTaskHandle_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGetIdleTaskHandle /*-----------------------------------------------------------*/ @@ -153,12 +146,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskSuspend_Unpriv MPU_vTaskSuspend_Priv: - pop {r0, r1} b MPU_vTaskSuspendImpl MPU_vTaskSuspend_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskSuspend /*-----------------------------------------------------------*/ @@ -168,12 +160,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskResume_Unpriv MPU_vTaskResume_Priv: - pop {r0, r1} b MPU_vTaskResumeImpl MPU_vTaskResume_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskResume /*-----------------------------------------------------------*/ @@ -183,12 +174,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGetTickCount_Unpriv MPU_xTaskGetTickCount_Priv: - pop {r0, r1} b MPU_xTaskGetTickCountImpl MPU_xTaskGetTickCount_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGetTickCount /*-----------------------------------------------------------*/ @@ -198,42 +188,25 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTaskGetNumberOfTasks_Unpriv MPU_uxTaskGetNumberOfTasks_Priv: - pop {r0, r1} b MPU_uxTaskGetNumberOfTasksImpl MPU_uxTaskGetNumberOfTasks_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0, r1} - mrs r0, control - movs r1, #1 - tst r0, r1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0, r1} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0, r1} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0, r1} mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGetRunTimeCounter_Unpriv MPU_ulTaskGetRunTimeCounter_Priv: - pop {r0, r1} b MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounter_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGetRunTimeCounter /*-----------------------------------------------------------*/ @@ -243,12 +216,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGetRunTimePercent_Unpriv MPU_ulTaskGetRunTimePercent_Priv: - pop {r0, r1} b MPU_ulTaskGetRunTimePercentImpl MPU_ulTaskGetRunTimePercent_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGetRunTimePercent /*-----------------------------------------------------------*/ @@ -258,12 +230,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGetIdleRunTimePercent_Unpriv MPU_ulTaskGetIdleRunTimePercent_Priv: - pop {r0, r1} b MPU_ulTaskGetIdleRunTimePercentImpl MPU_ulTaskGetIdleRunTimePercent_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent /*-----------------------------------------------------------*/ @@ -273,12 +244,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv MPU_ulTaskGetIdleRunTimeCounter_Priv: - pop {r0, r1} b MPU_ulTaskGetIdleRunTimeCounterImpl MPU_ulTaskGetIdleRunTimeCounter_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter /*-----------------------------------------------------------*/ @@ -288,12 +258,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskSetApplicationTaskTag_Unpriv MPU_vTaskSetApplicationTaskTag_Priv: - pop {r0, r1} b MPU_vTaskSetApplicationTaskTagImpl MPU_vTaskSetApplicationTaskTag_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskSetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -303,12 +272,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGetApplicationTaskTag_Unpriv MPU_xTaskGetApplicationTaskTag_Priv: - pop {r0, r1} b MPU_xTaskGetApplicationTaskTagImpl MPU_xTaskGetApplicationTaskTag_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -318,12 +286,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv MPU_vTaskSetThreadLocalStoragePointer_Priv: - pop {r0, r1} b MPU_vTaskSetThreadLocalStoragePointerImpl MPU_vTaskSetThreadLocalStoragePointer_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -333,12 +300,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv MPU_pvTaskGetThreadLocalStoragePointer_Priv: - pop {r0, r1} b MPU_pvTaskGetThreadLocalStoragePointerImpl MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -348,12 +314,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTaskGetSystemState_Unpriv MPU_uxTaskGetSystemState_Priv: - pop {r0, r1} b MPU_uxTaskGetSystemStateImpl MPU_uxTaskGetSystemState_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTaskGetSystemState /*-----------------------------------------------------------*/ @@ -363,12 +328,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTaskGetStackHighWaterMark_Unpriv MPU_uxTaskGetStackHighWaterMark_Priv: - pop {r0, r1} b MPU_uxTaskGetStackHighWaterMarkImpl MPU_uxTaskGetStackHighWaterMark_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark /*-----------------------------------------------------------*/ @@ -378,12 +342,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTaskGetStackHighWaterMark2_Unpriv MPU_uxTaskGetStackHighWaterMark2_Priv: - pop {r0, r1} b MPU_uxTaskGetStackHighWaterMark2Impl MPU_uxTaskGetStackHighWaterMark2_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 /*-----------------------------------------------------------*/ @@ -393,12 +356,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGetCurrentTaskHandle_Unpriv MPU_xTaskGetCurrentTaskHandle_Priv: - pop {r0, r1} b MPU_xTaskGetCurrentTaskHandleImpl MPU_xTaskGetCurrentTaskHandle_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle /*-----------------------------------------------------------*/ @@ -408,12 +370,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGetSchedulerState_Unpriv MPU_xTaskGetSchedulerState_Priv: - pop {r0, r1} b MPU_xTaskGetSchedulerStateImpl MPU_xTaskGetSchedulerState_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGetSchedulerState /*-----------------------------------------------------------*/ @@ -423,12 +384,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTaskSetTimeOutState_Unpriv MPU_vTaskSetTimeOutState_Priv: - pop {r0, r1} b MPU_vTaskSetTimeOutStateImpl MPU_vTaskSetTimeOutState_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTaskSetTimeOutState /*-----------------------------------------------------------*/ @@ -438,12 +398,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskCheckForTimeOut_Unpriv MPU_xTaskCheckForTimeOut_Priv: - pop {r0, r1} b MPU_xTaskCheckForTimeOutImpl MPU_xTaskCheckForTimeOut_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskCheckForTimeOut /*-----------------------------------------------------------*/ @@ -453,12 +412,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGenericNotify_Unpriv MPU_xTaskGenericNotify_Priv: - pop {r0, r1} b MPU_xTaskGenericNotifyImpl MPU_xTaskGenericNotify_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGenericNotify /*-----------------------------------------------------------*/ @@ -468,12 +426,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGenericNotifyWait_Unpriv MPU_xTaskGenericNotifyWait_Priv: - pop {r0, r1} b MPU_xTaskGenericNotifyWaitImpl MPU_xTaskGenericNotifyWait_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGenericNotifyWait /*-----------------------------------------------------------*/ @@ -483,12 +440,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGenericNotifyTake_Unpriv MPU_ulTaskGenericNotifyTake_Priv: - pop {r0, r1} b MPU_ulTaskGenericNotifyTakeImpl MPU_ulTaskGenericNotifyTake_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGenericNotifyTake /*-----------------------------------------------------------*/ @@ -498,12 +454,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTaskGenericNotifyStateClear_Unpriv MPU_xTaskGenericNotifyStateClear_Priv: - pop {r0, r1} b MPU_xTaskGenericNotifyStateClearImpl MPU_xTaskGenericNotifyStateClear_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTaskGenericNotifyStateClear /*-----------------------------------------------------------*/ @@ -513,12 +468,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_ulTaskGenericNotifyValueClear_Unpriv MPU_ulTaskGenericNotifyValueClear_Priv: - pop {r0, r1} b MPU_ulTaskGenericNotifyValueClearImpl MPU_ulTaskGenericNotifyValueClear_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear /*-----------------------------------------------------------*/ @@ -528,12 +482,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueGenericSend_Unpriv MPU_xQueueGenericSend_Priv: - pop {r0, r1} b MPU_xQueueGenericSendImpl MPU_xQueueGenericSend_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueGenericSend /*-----------------------------------------------------------*/ @@ -543,12 +496,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxQueueMessagesWaiting_Unpriv MPU_uxQueueMessagesWaiting_Priv: - pop {r0, r1} b MPU_uxQueueMessagesWaitingImpl MPU_uxQueueMessagesWaiting_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxQueueMessagesWaiting /*-----------------------------------------------------------*/ @@ -558,12 +510,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxQueueSpacesAvailable_Unpriv MPU_uxQueueSpacesAvailable_Priv: - pop {r0, r1} b MPU_uxQueueSpacesAvailableImpl MPU_uxQueueSpacesAvailable_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxQueueSpacesAvailable /*-----------------------------------------------------------*/ @@ -573,12 +524,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueReceive_Unpriv MPU_xQueueReceive_Priv: - pop {r0, r1} b MPU_xQueueReceiveImpl MPU_xQueueReceive_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueReceive /*-----------------------------------------------------------*/ @@ -588,12 +538,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueuePeek_Unpriv MPU_xQueuePeek_Priv: - pop {r0, r1} b MPU_xQueuePeekImpl MPU_xQueuePeek_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueuePeek /*-----------------------------------------------------------*/ @@ -603,12 +552,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueSemaphoreTake_Unpriv MPU_xQueueSemaphoreTake_Priv: - pop {r0, r1} b MPU_xQueueSemaphoreTakeImpl MPU_xQueueSemaphoreTake_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueSemaphoreTake /*-----------------------------------------------------------*/ @@ -618,12 +566,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueGetMutexHolder_Unpriv MPU_xQueueGetMutexHolder_Priv: - pop {r0, r1} b MPU_xQueueGetMutexHolderImpl MPU_xQueueGetMutexHolder_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueGetMutexHolder /*-----------------------------------------------------------*/ @@ -633,12 +580,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueTakeMutexRecursive_Unpriv MPU_xQueueTakeMutexRecursive_Priv: - pop {r0, r1} b MPU_xQueueTakeMutexRecursiveImpl MPU_xQueueTakeMutexRecursive_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueTakeMutexRecursive /*-----------------------------------------------------------*/ @@ -648,12 +594,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueGiveMutexRecursive_Unpriv MPU_xQueueGiveMutexRecursive_Priv: - pop {r0, r1} b MPU_xQueueGiveMutexRecursiveImpl MPU_xQueueGiveMutexRecursive_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueGiveMutexRecursive /*-----------------------------------------------------------*/ @@ -663,12 +608,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueSelectFromSet_Unpriv MPU_xQueueSelectFromSet_Priv: - pop {r0, r1} b MPU_xQueueSelectFromSetImpl MPU_xQueueSelectFromSet_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueSelectFromSet /*-----------------------------------------------------------*/ @@ -678,12 +622,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xQueueAddToSet_Unpriv MPU_xQueueAddToSet_Priv: - pop {r0, r1} b MPU_xQueueAddToSetImpl MPU_xQueueAddToSet_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xQueueAddToSet /*-----------------------------------------------------------*/ @@ -693,12 +636,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vQueueAddToRegistry_Unpriv MPU_vQueueAddToRegistry_Priv: - pop {r0, r1} b MPU_vQueueAddToRegistryImpl MPU_vQueueAddToRegistry_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vQueueAddToRegistry /*-----------------------------------------------------------*/ @@ -708,12 +650,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vQueueUnregisterQueue_Unpriv MPU_vQueueUnregisterQueue_Priv: - pop {r0, r1} b MPU_vQueueUnregisterQueueImpl MPU_vQueueUnregisterQueue_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vQueueUnregisterQueue /*-----------------------------------------------------------*/ @@ -723,12 +664,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_pcQueueGetName_Unpriv MPU_pcQueueGetName_Priv: - pop {r0, r1} b MPU_pcQueueGetNameImpl MPU_pcQueueGetName_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_pcQueueGetName /*-----------------------------------------------------------*/ @@ -738,12 +678,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_pvTimerGetTimerID_Unpriv MPU_pvTimerGetTimerID_Priv: - pop {r0, r1} b MPU_pvTimerGetTimerIDImpl MPU_pvTimerGetTimerID_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_pvTimerGetTimerID /*-----------------------------------------------------------*/ @@ -753,12 +692,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTimerSetTimerID_Unpriv MPU_vTimerSetTimerID_Priv: - pop {r0, r1} b MPU_vTimerSetTimerIDImpl MPU_vTimerSetTimerID_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTimerSetTimerID /*-----------------------------------------------------------*/ @@ -768,12 +706,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTimerIsTimerActive_Unpriv MPU_xTimerIsTimerActive_Priv: - pop {r0, r1} b MPU_xTimerIsTimerActiveImpl MPU_xTimerIsTimerActive_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTimerIsTimerActive /*-----------------------------------------------------------*/ @@ -783,34 +720,26 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv MPU_xTimerGetTimerDaemonTaskHandle_Priv: - pop {r0, r1} b MPU_xTimerGetTimerDaemonTaskHandleImpl MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0, r1} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control movs r1, #1 tst r0, r1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: - pop {r0, r1} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: - pop {r0, r1} - b MPU_xTimerGenericCommandPrivImpl - + pop {r0, r1} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -819,12 +748,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_pcTimerGetName_Unpriv MPU_pcTimerGetName_Priv: - pop {r0, r1} b MPU_pcTimerGetNameImpl MPU_pcTimerGetName_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_pcTimerGetName /*-----------------------------------------------------------*/ @@ -834,12 +762,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vTimerSetReloadMode_Unpriv MPU_vTimerSetReloadMode_Priv: - pop {r0, r1} b MPU_vTimerSetReloadModeImpl MPU_vTimerSetReloadMode_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vTimerSetReloadMode /*-----------------------------------------------------------*/ @@ -849,12 +776,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTimerGetReloadMode_Unpriv MPU_xTimerGetReloadMode_Priv: - pop {r0, r1} b MPU_xTimerGetReloadModeImpl MPU_xTimerGetReloadMode_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -864,12 +790,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxTimerGetReloadMode_Unpriv MPU_uxTimerGetReloadMode_Priv: - pop {r0, r1} b MPU_uxTimerGetReloadModeImpl MPU_uxTimerGetReloadMode_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -879,12 +804,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTimerGetPeriod_Unpriv MPU_xTimerGetPeriod_Priv: - pop {r0, r1} b MPU_xTimerGetPeriodImpl MPU_xTimerGetPeriod_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTimerGetPeriod /*-----------------------------------------------------------*/ @@ -894,12 +818,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xTimerGetExpiryTime_Unpriv MPU_xTimerGetExpiryTime_Priv: - pop {r0, r1} b MPU_xTimerGetExpiryTimeImpl MPU_xTimerGetExpiryTime_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xTimerGetExpiryTime /*-----------------------------------------------------------*/ @@ -909,12 +832,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xEventGroupWaitBits_Unpriv MPU_xEventGroupWaitBits_Priv: - pop {r0, r1} b MPU_xEventGroupWaitBitsImpl MPU_xEventGroupWaitBits_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xEventGroupWaitBits /*-----------------------------------------------------------*/ @@ -924,12 +846,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xEventGroupClearBits_Unpriv MPU_xEventGroupClearBits_Priv: - pop {r0, r1} b MPU_xEventGroupClearBitsImpl MPU_xEventGroupClearBits_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xEventGroupClearBits /*-----------------------------------------------------------*/ @@ -939,12 +860,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xEventGroupSetBits_Unpriv MPU_xEventGroupSetBits_Priv: - pop {r0, r1} b MPU_xEventGroupSetBitsImpl MPU_xEventGroupSetBits_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xEventGroupSetBits /*-----------------------------------------------------------*/ @@ -954,12 +874,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xEventGroupSync_Unpriv MPU_xEventGroupSync_Priv: - pop {r0, r1} b MPU_xEventGroupSyncImpl MPU_xEventGroupSync_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xEventGroupSync /*-----------------------------------------------------------*/ @@ -969,12 +888,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_uxEventGroupGetNumber_Unpriv MPU_uxEventGroupGetNumber_Priv: - pop {r0, r1} b MPU_uxEventGroupGetNumberImpl MPU_uxEventGroupGetNumber_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_uxEventGroupGetNumber /*-----------------------------------------------------------*/ @@ -984,12 +902,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_vEventGroupSetNumber_Unpriv MPU_vEventGroupSetNumber_Priv: - pop {r0, r1} b MPU_vEventGroupSetNumberImpl MPU_vEventGroupSetNumber_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_vEventGroupSetNumber /*-----------------------------------------------------------*/ @@ -999,12 +916,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferSend_Unpriv MPU_xStreamBufferSend_Priv: - pop {r0, r1} b MPU_xStreamBufferSendImpl MPU_xStreamBufferSend_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferSend /*-----------------------------------------------------------*/ @@ -1014,12 +930,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferReceive_Unpriv MPU_xStreamBufferReceive_Priv: - pop {r0, r1} b MPU_xStreamBufferReceiveImpl MPU_xStreamBufferReceive_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferReceive /*-----------------------------------------------------------*/ @@ -1029,12 +944,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferIsFull_Unpriv MPU_xStreamBufferIsFull_Priv: - pop {r0, r1} b MPU_xStreamBufferIsFullImpl MPU_xStreamBufferIsFull_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferIsFull /*-----------------------------------------------------------*/ @@ -1044,12 +958,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferIsEmpty_Unpriv MPU_xStreamBufferIsEmpty_Priv: - pop {r0, r1} b MPU_xStreamBufferIsEmptyImpl MPU_xStreamBufferIsEmpty_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferIsEmpty /*-----------------------------------------------------------*/ @@ -1059,12 +972,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferSpacesAvailable_Unpriv MPU_xStreamBufferSpacesAvailable_Priv: - pop {r0, r1} b MPU_xStreamBufferSpacesAvailableImpl MPU_xStreamBufferSpacesAvailable_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferSpacesAvailable /*-----------------------------------------------------------*/ @@ -1074,12 +986,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferBytesAvailable_Unpriv MPU_xStreamBufferBytesAvailable_Priv: - pop {r0, r1} b MPU_xStreamBufferBytesAvailableImpl MPU_xStreamBufferBytesAvailable_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferBytesAvailable /*-----------------------------------------------------------*/ @@ -1089,12 +1000,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferSetTriggerLevel_Unpriv MPU_xStreamBufferSetTriggerLevel_Priv: - pop {r0, r1} b MPU_xStreamBufferSetTriggerLevelImpl MPU_xStreamBufferSetTriggerLevel_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel /*-----------------------------------------------------------*/ @@ -1104,12 +1014,11 @@ mrs r0, control movs r1, #1 tst r0, r1 + pop {r0, r1} bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv MPU_xStreamBufferNextMessageLengthBytes_Priv: - pop {r0, r1} b MPU_xStreamBufferNextMessageLengthBytesImpl MPU_xStreamBufferNextMessageLengthBytes_Unpriv: - pop {r0, r1} svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes /*-----------------------------------------------------------*/ @@ -1160,10 +1069,6 @@ MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1316,9 +1221,9 @@ MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c index 9712ac3..f16a343 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -54,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 @@ -68,6 +70,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,8 +109,17 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) /*-----------------------------------------------------------*/ /** @@ -111,8 +138,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,72 +161,79 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + +/* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ /* Enable privileged access to unmapped region. */ #define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) @@ -343,6 +377,20 @@ * any secure calls. */ #define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ /** @@ -351,7 +399,7 @@ */ static void prvTaskExitError( void ); -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief Extract MPU region's access permissions from the Region Base Address @@ -362,7 +410,7 @@ * @return uint32_t Access permissions. */ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; -#endif /* configENABLE_MPU */ +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ #if ( configENABLE_MPU == 1 ) @@ -380,6 +428,26 @@ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_FPU */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + +/** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + /** * @brief Setup the timer to generate the tick interrupts. * @@ -448,13 +516,13 @@ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,24 +530,24 @@ #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ -#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief This variable is set to pdTRUE when the scheduler is started. */ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; -#endif +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /** * @brief Each task maintains its own interrupt status in the critical nesting @@ -501,13 +569,13 @@ * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -531,6 +599,7 @@ /*-----------------------------------------------------------*/ #if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) { uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; @@ -746,6 +815,7 @@ __asm volatile ( "cpsie i" ::: "memory" ); } } + #endif /* configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ @@ -760,8 +830,15 @@ } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -795,7 +872,8 @@ } /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ { uint32_t ulAccessPermissions = 0; @@ -812,13 +890,16 @@ return ulAccessPermissions; } -#endif /* configENABLE_MPU */ + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -903,10 +984,12 @@ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ #if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ { #if ( configENABLE_TRUSTZONE == 1 ) @@ -928,6 +1011,7 @@ * LSPEN = 1 ==> Enable lazy context save of FP state. */ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); } + #endif /* configENABLE_FPU */ /*-----------------------------------------------------------*/ @@ -972,13 +1056,19 @@ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1078,7 @@ { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1174,24 @@ vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1116,6 +1213,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1154,12 +1252,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1268,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1190,11 +1287,19 @@ /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; @@ -1224,14 +1329,13 @@ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1259,6 +1363,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -1293,12 +1398,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1414,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1436,11 @@ /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1458,13 @@ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1392,6 +1499,7 @@ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ { uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ ulIndex++; @@ -1410,21 +1518,21 @@ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,20 +1543,30 @@ #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ ulIndex++; } else { xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1469,6 +1587,20 @@ } #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + return &( xMPUSettings->ulContext[ ulIndex ] ); } @@ -1483,7 +1615,7 @@ * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1637,7 @@ } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1672,7 @@ pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1551,6 +1683,20 @@ } #endif /* portPRELOAD_REGISTERS */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + return pxTopOfStack; } @@ -1559,22 +1705,52 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) { - volatile uint32_t ulOriginalPriority; + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1769,10 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1810,22 @@ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ #if ( configENABLE_MPU == 1 ) { @@ -1660,11 +1841,11 @@ /* Initialize the critical nesting count ready for the first task. */ ulCriticalNesting = 0; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { xSchedulerRunning = pdTRUE; } - #endif + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /* Start the first task. */ vStartFirstTask(); @@ -1692,15 +1873,17 @@ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, - uint32_t ulStackDepth ) + configSTACK_DEPTH_TYPE uxStackDepth ) { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1719,10 +1902,10 @@ * which case the stack region parameters will be valid. At all other * times the stack parameters will not be valid and it is assumed that * the stack region has already been configured. */ - if( ulStackDepth > 0 ) + if( uxStackDepth > 0 ) { ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; - ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; /* If the stack is within the privileged SRAM, do not protect it * using a separate MPU region. This is needed because privileged @@ -1790,6 +1973,16 @@ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | ( portMPU_RLAR_REGION_ENABLE ); + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + /* Normal memory/ Device memory. */ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) { @@ -1812,10 +2005,12 @@ lIndex++; } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, uint32_t ulBufferLength, uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ @@ -1825,7 +2020,15 @@ BaseType_t xAccessGranted = pdFALSE; const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ - if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) { xAccessGranted = pdTRUE; } @@ -1860,7 +2063,8 @@ return xAccessGranted; } -#endif /* configENABLE_MPU */ + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /*-----------------------------------------------------------*/ BaseType_t xPortIsInsideInterrupt( void ) @@ -1886,7 +2090,7 @@ } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1924,7 +2128,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); } @@ -1944,7 +2148,7 @@ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) @@ -2041,3 +2245,38 @@ #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h index f64ceb5..53b4b6e 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -52,7 +52,7 @@ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s index cef6b8a..200751b 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -39,6 +39,10 @@ #define configUSE_MPU_WRAPPERS_V1 0 #endif +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + EXTERN pxCurrentTCB EXTERN vTaskSwitchContext EXTERN vPortSVCHandler_C @@ -159,7 +163,9 @@ ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ subs r1, #16 msr psp, r2 + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r3 + #endif msr control, r4 mov lr, r5 @@ -191,7 +197,9 @@ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r1 /* Set this task's PSPLIM value. */ +#endif movs r1, #2 /* r1 = 2. */ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ adds r0, #32 /* Discard everything up to r0. */ @@ -255,7 +263,11 @@ save_special_regs: mrs r2, psp /* r2 = PSP. */ + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) mrs r3, psplim /* r3 = PSPLIM. */ + #else + movs r3, #0 /* r3 = 0. 0 is stored in the PSPLIM slot. */ + #endif mrs r4, control /* r4 = CONTROL. */ mov r5, lr /* r5 = LR. */ stmia r1!, {r2-r5} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ @@ -323,7 +335,9 @@ ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */ subs r1, #16 msr psp, r2 + #if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r3 + #endif msr control, r4 mov lr, r5 @@ -356,7 +370,11 @@ subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */ str r0, [r1] /* Save the new top of stack in TCB. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) mrs r2, psplim /* r2 = PSPLIM. */ +#else + movs r2, #0 /* r0 = 0. 0 is stored in the PSPLIM slot. */ +#endif mov r3, lr /* r3 = LR/EXC_RETURN. */ stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */ mov r4, r8 /* r4 = r8. */ @@ -382,7 +400,9 @@ msr psp, r0 /* Remember the new top of stack for the task. */ subs r0, r0, #40 /* Move to the starting of the saved context. */ ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */ +#if ( configRUN_FREERTOS_SECURE_ONLY == 1 ) msr psplim, r2 /* Restore the PSPLIM register value for the task. */ +#endif bx r3 #endif /* configENABLE_MPU */
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h index 19d7556..6cf50c5 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -48,9 +48,10 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M23" -#define portHAS_BASEPRI 0 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M23" +#define portHAS_ARMV8M_MAIN_EXTENSION 0 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -60,6 +61,12 @@ #if ( configTOTAL_MPU_REGIONS == 16 ) #error 16 MPU regions are not yet supported for this port. #endif + +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23. +#endif /*-----------------------------------------------------------*/ /**
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h index 6f666da..2dfac6a 100644 --- a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -117,7 +119,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -125,6 +127,18 @@ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; #endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ /*-----------------------------------------------------------*/ /** @@ -137,7 +151,7 @@ #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) @@ -193,8 +207,8 @@ */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -223,7 +237,20 @@ */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +-----------+---------------+----------+-----------------+------------------------------+-----+ @@ -232,11 +259,24 @@ * +-----------+---------------+----------+-----------------+------------------------------+-----+ * * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 + * 16 17 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 54 + #define MAX_CONTEXT_SIZE 55 - #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ /* * +-----------+---------------+----------+-----------------+----------------------+-----+ @@ -245,15 +285,28 @@ * +-----------+---------------+----------+-----------------+----------------------+-----+ * * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 + * 16 17 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 53 + #define MAX_CONTEXT_SIZE 54 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +----------+-----------------+------------------------------+-----+ @@ -264,7 +317,20 @@ * <---------><----------------><------------------------------><----> * 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 22 + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ @@ -277,17 +343,17 @@ * <---------><----------------><----------------------><----> * 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 21 + #define MAX_CONTEXT_SIZE 21 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) -/* Size of an Access Control List (ACL) entry in bits. */ + /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) typedef struct MPU_SETTINGS @@ -312,8 +378,8 @@ * @brief Validate priority of ISRs that are allowed to call FreeRTOS * system calls. */ -#ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +399,29 @@ /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +507,12 @@ extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +523,56 @@ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus }
diff --git a/Source/portable/IAR/ARM_CM3/port.c b/Source/portable/IAR/ARM_CM3/port.c index 10ce863..e706a6d 100644 --- a/Source/portable/IAR/ARM_CM3/port.c +++ b/Source/portable/IAR/ARM_CM3/port.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -41,10 +41,14 @@ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) /* ...then bits in the registers. */ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) @@ -59,6 +63,11 @@ #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -121,6 +130,11 @@ */ static void prvTaskExitError( void ); +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ); +extern void xPortPendSVHandler( void ); /*-----------------------------------------------------------*/ /* Each task maintains its own interrupt status in the critical nesting @@ -208,6 +222,40 @@ */ BaseType_t xPortStartScheduler( void ) { + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -243,7 +291,7 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -257,22 +305,22 @@ if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -292,9 +340,11 @@ } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the lowest priority interrupts. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Start the timer that generates the tick ISR. Interrupts are disabled * here already. */ @@ -355,14 +405,21 @@ * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } @@ -652,7 +709,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); }
diff --git a/Source/portable/IAR/ARM_CM3/portasm.s b/Source/portable/IAR/ARM_CM3/portasm.s index dfaabc3..0344b9c 100644 --- a/Source/portable/IAR/ARM_CM3/portasm.s +++ b/Source/portable/IAR/ARM_CM3/portasm.s
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM3/portmacro.h b/Source/portable/IAR/ARM_CM3/portmacro.h index 3e67345..26b976a 100644 --- a/Source/portable/IAR/ARM_CM3/portmacro.h +++ b/Source/portable/IAR/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -28,7 +28,7 @@ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -47,50 +47,50 @@ */ /* IAR includes. */ - #include <intrinsics.h> +#include <intrinsics.h> /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Compiler directives. */ - #define portWEAK_SYMBOL __attribute__( ( weak ) ) +#define portWEAK_SYMBOL __attribute__( ( weak ) ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -98,112 +98,124 @@ __ISB(); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); - #define portDISABLE_INTERRUPTS() \ +#define portDISABLE_INTERRUPTS() \ { \ __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ __DSB(); \ __ISB(); \ } - #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() - #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif /*-----------------------------------------------------------*/ - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdFALSE; } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in * the source code because to do so would cause other compilers to generate * warnings. */ - #pragma diag_suppress=Pe191 - #pragma diag_suppress=Pa082 +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 /* *INDENT-OFF* */ #ifdef __cplusplus
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S index ef180bd..68192e4 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -47,12 +47,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskDelayUntil_Unpriv MPU_xTaskDelayUntil_Priv: - pop {r0} b MPU_xTaskDelayUntilImpl MPU_xTaskDelayUntil_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskDelayUntil /*-----------------------------------------------------------*/ @@ -61,12 +60,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskAbortDelay_Unpriv MPU_xTaskAbortDelay_Priv: - pop {r0} b MPU_xTaskAbortDelayImpl MPU_xTaskAbortDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskAbortDelay /*-----------------------------------------------------------*/ @@ -75,12 +73,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskDelay_Unpriv MPU_vTaskDelay_Priv: - pop {r0} b MPU_vTaskDelayImpl MPU_vTaskDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskDelay /*-----------------------------------------------------------*/ @@ -89,12 +86,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskPriorityGet_Unpriv MPU_uxTaskPriorityGet_Priv: - pop {r0} b MPU_uxTaskPriorityGetImpl MPU_uxTaskPriorityGet_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskPriorityGet /*-----------------------------------------------------------*/ @@ -103,12 +99,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_eTaskGetState_Unpriv MPU_eTaskGetState_Priv: - pop {r0} b MPU_eTaskGetStateImpl MPU_eTaskGetState_Unpriv: - pop {r0} svc #SYSTEM_CALL_eTaskGetState /*-----------------------------------------------------------*/ @@ -117,12 +112,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskGetInfo_Unpriv MPU_vTaskGetInfo_Priv: - pop {r0} b MPU_vTaskGetInfoImpl MPU_vTaskGetInfo_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskGetInfo /*-----------------------------------------------------------*/ @@ -131,12 +125,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetIdleTaskHandle_Unpriv MPU_xTaskGetIdleTaskHandle_Priv: - pop {r0} b MPU_xTaskGetIdleTaskHandleImpl MPU_xTaskGetIdleTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetIdleTaskHandle /*-----------------------------------------------------------*/ @@ -145,12 +138,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSuspend_Unpriv MPU_vTaskSuspend_Priv: - pop {r0} b MPU_vTaskSuspendImpl MPU_vTaskSuspend_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSuspend /*-----------------------------------------------------------*/ @@ -159,12 +151,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskResume_Unpriv MPU_vTaskResume_Priv: - pop {r0} b MPU_vTaskResumeImpl MPU_vTaskResume_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskResume /*-----------------------------------------------------------*/ @@ -173,12 +164,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetTickCount_Unpriv MPU_xTaskGetTickCount_Priv: - pop {r0} b MPU_xTaskGetTickCountImpl MPU_xTaskGetTickCount_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetTickCount /*-----------------------------------------------------------*/ @@ -187,40 +177,24 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetNumberOfTasks_Unpriv MPU_uxTaskGetNumberOfTasks_Priv: - pop {r0} b MPU_uxTaskGetNumberOfTasksImpl MPU_uxTaskGetNumberOfTasks_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimeCounter_Unpriv MPU_ulTaskGetRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimeCounter /*-----------------------------------------------------------*/ @@ -229,12 +203,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimePercent_Unpriv MPU_ulTaskGetRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetRunTimePercentImpl MPU_ulTaskGetRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimePercent /*-----------------------------------------------------------*/ @@ -243,12 +216,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimePercent_Unpriv MPU_ulTaskGetIdleRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimePercentImpl MPU_ulTaskGetIdleRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent /*-----------------------------------------------------------*/ @@ -257,12 +229,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv MPU_ulTaskGetIdleRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimeCounterImpl MPU_ulTaskGetIdleRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter /*-----------------------------------------------------------*/ @@ -271,12 +242,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetApplicationTaskTag_Unpriv MPU_vTaskSetApplicationTaskTag_Priv: - pop {r0} b MPU_vTaskSetApplicationTaskTagImpl MPU_vTaskSetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -285,12 +255,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetApplicationTaskTag_Unpriv MPU_xTaskGetApplicationTaskTag_Priv: - pop {r0} b MPU_xTaskGetApplicationTaskTagImpl MPU_xTaskGetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -299,12 +268,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv MPU_vTaskSetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_vTaskSetThreadLocalStoragePointerImpl MPU_vTaskSetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -313,12 +281,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv MPU_pvTaskGetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_pvTaskGetThreadLocalStoragePointerImpl MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -327,12 +294,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetSystemState_Unpriv MPU_uxTaskGetSystemState_Priv: - pop {r0} b MPU_uxTaskGetSystemStateImpl MPU_uxTaskGetSystemState_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetSystemState /*-----------------------------------------------------------*/ @@ -341,12 +307,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark_Unpriv MPU_uxTaskGetStackHighWaterMark_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMarkImpl MPU_uxTaskGetStackHighWaterMark_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark /*-----------------------------------------------------------*/ @@ -355,12 +320,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark2_Unpriv MPU_uxTaskGetStackHighWaterMark2_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMark2Impl MPU_uxTaskGetStackHighWaterMark2_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 /*-----------------------------------------------------------*/ @@ -369,12 +333,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetCurrentTaskHandle_Unpriv MPU_xTaskGetCurrentTaskHandle_Priv: - pop {r0} b MPU_xTaskGetCurrentTaskHandleImpl MPU_xTaskGetCurrentTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle /*-----------------------------------------------------------*/ @@ -383,12 +346,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetSchedulerState_Unpriv MPU_xTaskGetSchedulerState_Priv: - pop {r0} b MPU_xTaskGetSchedulerStateImpl MPU_xTaskGetSchedulerState_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetSchedulerState /*-----------------------------------------------------------*/ @@ -397,12 +359,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetTimeOutState_Unpriv MPU_vTaskSetTimeOutState_Priv: - pop {r0} b MPU_vTaskSetTimeOutStateImpl MPU_vTaskSetTimeOutState_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetTimeOutState /*-----------------------------------------------------------*/ @@ -411,12 +372,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskCheckForTimeOut_Unpriv MPU_xTaskCheckForTimeOut_Priv: - pop {r0} b MPU_xTaskCheckForTimeOutImpl MPU_xTaskCheckForTimeOut_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskCheckForTimeOut /*-----------------------------------------------------------*/ @@ -425,12 +385,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotify_Unpriv MPU_xTaskGenericNotify_Priv: - pop {r0} b MPU_xTaskGenericNotifyImpl MPU_xTaskGenericNotify_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotify /*-----------------------------------------------------------*/ @@ -439,12 +398,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyWait_Unpriv MPU_xTaskGenericNotifyWait_Priv: - pop {r0} b MPU_xTaskGenericNotifyWaitImpl MPU_xTaskGenericNotifyWait_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyWait /*-----------------------------------------------------------*/ @@ -453,12 +411,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyTake_Unpriv MPU_ulTaskGenericNotifyTake_Priv: - pop {r0} b MPU_ulTaskGenericNotifyTakeImpl MPU_ulTaskGenericNotifyTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyTake /*-----------------------------------------------------------*/ @@ -467,12 +424,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyStateClear_Unpriv MPU_xTaskGenericNotifyStateClear_Priv: - pop {r0} b MPU_xTaskGenericNotifyStateClearImpl MPU_xTaskGenericNotifyStateClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyStateClear /*-----------------------------------------------------------*/ @@ -481,12 +437,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyValueClear_Unpriv MPU_ulTaskGenericNotifyValueClear_Priv: - pop {r0} b MPU_ulTaskGenericNotifyValueClearImpl MPU_ulTaskGenericNotifyValueClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear /*-----------------------------------------------------------*/ @@ -495,12 +450,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGenericSend_Unpriv MPU_xQueueGenericSend_Priv: - pop {r0} b MPU_xQueueGenericSendImpl MPU_xQueueGenericSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGenericSend /*-----------------------------------------------------------*/ @@ -509,12 +463,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueMessagesWaiting_Unpriv MPU_uxQueueMessagesWaiting_Priv: - pop {r0} b MPU_uxQueueMessagesWaitingImpl MPU_uxQueueMessagesWaiting_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueMessagesWaiting /*-----------------------------------------------------------*/ @@ -523,12 +476,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueSpacesAvailable_Unpriv MPU_uxQueueSpacesAvailable_Priv: - pop {r0} b MPU_uxQueueSpacesAvailableImpl MPU_uxQueueSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueSpacesAvailable /*-----------------------------------------------------------*/ @@ -537,12 +489,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueReceive_Unpriv MPU_xQueueReceive_Priv: - pop {r0} b MPU_xQueueReceiveImpl MPU_xQueueReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueReceive /*-----------------------------------------------------------*/ @@ -551,12 +502,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueuePeek_Unpriv MPU_xQueuePeek_Priv: - pop {r0} b MPU_xQueuePeekImpl MPU_xQueuePeek_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueuePeek /*-----------------------------------------------------------*/ @@ -565,12 +515,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSemaphoreTake_Unpriv MPU_xQueueSemaphoreTake_Priv: - pop {r0} b MPU_xQueueSemaphoreTakeImpl MPU_xQueueSemaphoreTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSemaphoreTake /*-----------------------------------------------------------*/ @@ -579,12 +528,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGetMutexHolder_Unpriv MPU_xQueueGetMutexHolder_Priv: - pop {r0} b MPU_xQueueGetMutexHolderImpl MPU_xQueueGetMutexHolder_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGetMutexHolder /*-----------------------------------------------------------*/ @@ -593,12 +541,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueTakeMutexRecursive_Unpriv MPU_xQueueTakeMutexRecursive_Priv: - pop {r0} b MPU_xQueueTakeMutexRecursiveImpl MPU_xQueueTakeMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueTakeMutexRecursive /*-----------------------------------------------------------*/ @@ -607,12 +554,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGiveMutexRecursive_Unpriv MPU_xQueueGiveMutexRecursive_Priv: - pop {r0} b MPU_xQueueGiveMutexRecursiveImpl MPU_xQueueGiveMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGiveMutexRecursive /*-----------------------------------------------------------*/ @@ -621,12 +567,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSelectFromSet_Unpriv MPU_xQueueSelectFromSet_Priv: - pop {r0} b MPU_xQueueSelectFromSetImpl MPU_xQueueSelectFromSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSelectFromSet /*-----------------------------------------------------------*/ @@ -635,12 +580,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueAddToSet_Unpriv MPU_xQueueAddToSet_Priv: - pop {r0} b MPU_xQueueAddToSetImpl MPU_xQueueAddToSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueAddToSet /*-----------------------------------------------------------*/ @@ -649,12 +593,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueAddToRegistry_Unpriv MPU_vQueueAddToRegistry_Priv: - pop {r0} b MPU_vQueueAddToRegistryImpl MPU_vQueueAddToRegistry_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueAddToRegistry /*-----------------------------------------------------------*/ @@ -663,12 +606,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueUnregisterQueue_Unpriv MPU_vQueueUnregisterQueue_Priv: - pop {r0} b MPU_vQueueUnregisterQueueImpl MPU_vQueueUnregisterQueue_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueUnregisterQueue /*-----------------------------------------------------------*/ @@ -677,12 +619,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcQueueGetName_Unpriv MPU_pcQueueGetName_Priv: - pop {r0} b MPU_pcQueueGetNameImpl MPU_pcQueueGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcQueueGetName /*-----------------------------------------------------------*/ @@ -691,12 +632,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTimerGetTimerID_Unpriv MPU_pvTimerGetTimerID_Priv: - pop {r0} b MPU_pvTimerGetTimerIDImpl MPU_pvTimerGetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTimerGetTimerID /*-----------------------------------------------------------*/ @@ -705,12 +645,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetTimerID_Unpriv MPU_vTimerSetTimerID_Priv: - pop {r0} b MPU_vTimerSetTimerIDImpl MPU_vTimerSetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetTimerID /*-----------------------------------------------------------*/ @@ -719,12 +658,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerIsTimerActive_Unpriv MPU_xTimerIsTimerActive_Priv: - pop {r0} b MPU_xTimerIsTimerActiveImpl MPU_xTimerIsTimerActive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerIsTimerActive /*-----------------------------------------------------------*/ @@ -733,33 +671,25 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv MPU_xTimerGetTimerDaemonTaskHandle_Priv: - pop {r0} b MPU_xTimerGetTimerDaemonTaskHandleImpl MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: - pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: - pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -767,12 +697,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcTimerGetName_Unpriv MPU_pcTimerGetName_Priv: - pop {r0} b MPU_pcTimerGetNameImpl MPU_pcTimerGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcTimerGetName /*-----------------------------------------------------------*/ @@ -781,12 +710,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetReloadMode_Unpriv MPU_vTimerSetReloadMode_Priv: - pop {r0} b MPU_vTimerSetReloadModeImpl MPU_vTimerSetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetReloadMode /*-----------------------------------------------------------*/ @@ -795,12 +723,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetReloadMode_Unpriv MPU_xTimerGetReloadMode_Priv: - pop {r0} b MPU_xTimerGetReloadModeImpl MPU_xTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -809,12 +736,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTimerGetReloadMode_Unpriv MPU_uxTimerGetReloadMode_Priv: - pop {r0} b MPU_uxTimerGetReloadModeImpl MPU_uxTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -823,12 +749,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetPeriod_Unpriv MPU_xTimerGetPeriod_Priv: - pop {r0} b MPU_xTimerGetPeriodImpl MPU_xTimerGetPeriod_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetPeriod /*-----------------------------------------------------------*/ @@ -837,12 +762,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetExpiryTime_Unpriv MPU_xTimerGetExpiryTime_Priv: - pop {r0} b MPU_xTimerGetExpiryTimeImpl MPU_xTimerGetExpiryTime_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetExpiryTime /*-----------------------------------------------------------*/ @@ -851,12 +775,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupWaitBits_Unpriv MPU_xEventGroupWaitBits_Priv: - pop {r0} b MPU_xEventGroupWaitBitsImpl MPU_xEventGroupWaitBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupWaitBits /*-----------------------------------------------------------*/ @@ -865,12 +788,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupClearBits_Unpriv MPU_xEventGroupClearBits_Priv: - pop {r0} b MPU_xEventGroupClearBitsImpl MPU_xEventGroupClearBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupClearBits /*-----------------------------------------------------------*/ @@ -879,12 +801,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSetBits_Unpriv MPU_xEventGroupSetBits_Priv: - pop {r0} b MPU_xEventGroupSetBitsImpl MPU_xEventGroupSetBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSetBits /*-----------------------------------------------------------*/ @@ -893,12 +814,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSync_Unpriv MPU_xEventGroupSync_Priv: - pop {r0} b MPU_xEventGroupSyncImpl MPU_xEventGroupSync_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSync /*-----------------------------------------------------------*/ @@ -907,12 +827,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxEventGroupGetNumber_Unpriv MPU_uxEventGroupGetNumber_Priv: - pop {r0} b MPU_uxEventGroupGetNumberImpl MPU_uxEventGroupGetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxEventGroupGetNumber /*-----------------------------------------------------------*/ @@ -921,12 +840,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vEventGroupSetNumber_Unpriv MPU_vEventGroupSetNumber_Priv: - pop {r0} b MPU_vEventGroupSetNumberImpl MPU_vEventGroupSetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_vEventGroupSetNumber /*-----------------------------------------------------------*/ @@ -935,12 +853,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSend_Unpriv MPU_xStreamBufferSend_Priv: - pop {r0} b MPU_xStreamBufferSendImpl MPU_xStreamBufferSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSend /*-----------------------------------------------------------*/ @@ -949,12 +866,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferReceive_Unpriv MPU_xStreamBufferReceive_Priv: - pop {r0} b MPU_xStreamBufferReceiveImpl MPU_xStreamBufferReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferReceive /*-----------------------------------------------------------*/ @@ -963,12 +879,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsFull_Unpriv MPU_xStreamBufferIsFull_Priv: - pop {r0} b MPU_xStreamBufferIsFullImpl MPU_xStreamBufferIsFull_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsFull /*-----------------------------------------------------------*/ @@ -977,12 +892,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsEmpty_Unpriv MPU_xStreamBufferIsEmpty_Priv: - pop {r0} b MPU_xStreamBufferIsEmptyImpl MPU_xStreamBufferIsEmpty_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsEmpty /*-----------------------------------------------------------*/ @@ -991,12 +905,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSpacesAvailable_Unpriv MPU_xStreamBufferSpacesAvailable_Priv: - pop {r0} b MPU_xStreamBufferSpacesAvailableImpl MPU_xStreamBufferSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSpacesAvailable /*-----------------------------------------------------------*/ @@ -1005,12 +918,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferBytesAvailable_Unpriv MPU_xStreamBufferBytesAvailable_Priv: - pop {r0} b MPU_xStreamBufferBytesAvailableImpl MPU_xStreamBufferBytesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferBytesAvailable /*-----------------------------------------------------------*/ @@ -1019,12 +931,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSetTriggerLevel_Unpriv MPU_xStreamBufferSetTriggerLevel_Priv: - pop {r0} b MPU_xStreamBufferSetTriggerLevelImpl MPU_xStreamBufferSetTriggerLevel_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel /*-----------------------------------------------------------*/ @@ -1033,12 +944,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv MPU_xStreamBufferNextMessageLengthBytes_Priv: - pop {r0} b MPU_xStreamBufferNextMessageLengthBytesImpl MPU_xStreamBufferNextMessageLengthBytes_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes /*-----------------------------------------------------------*/ @@ -1089,10 +999,6 @@ MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1151,9 @@ MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/port.c b/Source/portable/IAR/ARM_CM33/non_secure/port.c index 9712ac3..f16a343 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM33/non_secure/port.c
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -54,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 @@ -68,6 +70,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,8 +109,17 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) /*-----------------------------------------------------------*/ /** @@ -111,8 +138,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,72 +161,79 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + +/* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ /* Enable privileged access to unmapped region. */ #define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) @@ -343,6 +377,20 @@ * any secure calls. */ #define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ /** @@ -351,7 +399,7 @@ */ static void prvTaskExitError( void ); -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief Extract MPU region's access permissions from the Region Base Address @@ -362,7 +410,7 @@ * @return uint32_t Access permissions. */ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; -#endif /* configENABLE_MPU */ +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ #if ( configENABLE_MPU == 1 ) @@ -380,6 +428,26 @@ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_FPU */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + +/** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + /** * @brief Setup the timer to generate the tick interrupts. * @@ -448,13 +516,13 @@ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,24 +530,24 @@ #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ -#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief This variable is set to pdTRUE when the scheduler is started. */ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; -#endif +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /** * @brief Each task maintains its own interrupt status in the critical nesting @@ -501,13 +569,13 @@ * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -531,6 +599,7 @@ /*-----------------------------------------------------------*/ #if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) { uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; @@ -746,6 +815,7 @@ __asm volatile ( "cpsie i" ::: "memory" ); } } + #endif /* configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ @@ -760,8 +830,15 @@ } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -795,7 +872,8 @@ } /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ { uint32_t ulAccessPermissions = 0; @@ -812,13 +890,16 @@ return ulAccessPermissions; } -#endif /* configENABLE_MPU */ + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -903,10 +984,12 @@ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ #if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ { #if ( configENABLE_TRUSTZONE == 1 ) @@ -928,6 +1011,7 @@ * LSPEN = 1 ==> Enable lazy context save of FP state. */ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); } + #endif /* configENABLE_FPU */ /*-----------------------------------------------------------*/ @@ -972,13 +1056,19 @@ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1078,7 @@ { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1174,24 @@ vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1116,6 +1213,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1154,12 +1252,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1268,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1190,11 +1287,19 @@ /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; @@ -1224,14 +1329,13 @@ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1259,6 +1363,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -1293,12 +1398,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1414,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1436,11 @@ /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1458,13 @@ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1392,6 +1499,7 @@ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ { uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ ulIndex++; @@ -1410,21 +1518,21 @@ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,20 +1543,30 @@ #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ ulIndex++; } else { xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1469,6 +1587,20 @@ } #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + return &( xMPUSettings->ulContext[ ulIndex ] ); } @@ -1483,7 +1615,7 @@ * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1637,7 @@ } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1672,7 @@ pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1551,6 +1683,20 @@ } #endif /* portPRELOAD_REGISTERS */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + return pxTopOfStack; } @@ -1559,22 +1705,52 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) { - volatile uint32_t ulOriginalPriority; + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1769,10 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1810,22 @@ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ #if ( configENABLE_MPU == 1 ) { @@ -1660,11 +1841,11 @@ /* Initialize the critical nesting count ready for the first task. */ ulCriticalNesting = 0; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { xSchedulerRunning = pdTRUE; } - #endif + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /* Start the first task. */ vStartFirstTask(); @@ -1692,15 +1873,17 @@ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, - uint32_t ulStackDepth ) + configSTACK_DEPTH_TYPE uxStackDepth ) { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1719,10 +1902,10 @@ * which case the stack region parameters will be valid. At all other * times the stack parameters will not be valid and it is assumed that * the stack region has already been configured. */ - if( ulStackDepth > 0 ) + if( uxStackDepth > 0 ) { ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; - ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; /* If the stack is within the privileged SRAM, do not protect it * using a separate MPU region. This is needed because privileged @@ -1790,6 +1973,16 @@ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | ( portMPU_RLAR_REGION_ENABLE ); + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + /* Normal memory/ Device memory. */ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) { @@ -1812,10 +2005,12 @@ lIndex++; } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, uint32_t ulBufferLength, uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ @@ -1825,7 +2020,15 @@ BaseType_t xAccessGranted = pdFALSE; const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ - if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) { xAccessGranted = pdTRUE; } @@ -1860,7 +2063,8 @@ return xAccessGranted; } -#endif /* configENABLE_MPU */ + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /*-----------------------------------------------------------*/ BaseType_t xPortIsInsideInterrupt( void ) @@ -1886,7 +2090,7 @@ } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1924,7 +2128,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); } @@ -1944,7 +2148,7 @@ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) @@ -2041,3 +2245,38 @@ #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portasm.h b/Source/portable/IAR/ARM_CM33/non_secure/portasm.h index f64ceb5..53b4b6e 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -52,7 +52,7 @@ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portasm.s b/Source/portable/IAR/ARM_CM33/non_secure/portasm.s index 5309103..b5c91e5 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -150,6 +152,14 @@ ldr r2, [r1] /* r2 = Location of saved context in TCB. */ restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ msr psp, r3 msr psplim, r4 @@ -175,12 +185,22 @@ ldr r3, [r2] /* Read pxCurrentTCB. */ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ ldr r4, =xSecureContext str r1, [r4] /* Set xSecureContext to this task's value for the same. */ msr psplim, r2 /* Set this task's PSPLIM value. */ - movs r1, #2 /* r1 = 2. */ - msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ adds r0, #32 /* Discard everything up to r0. */ msr psp, r0 /* This is now the new top of stack to use in the task. */ isb @@ -213,7 +233,7 @@ ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -268,11 +288,20 @@ mrs r4, psplim /* r4 = PSPLIM. */ mrs r5, control /* r5 = CONTROL. */ stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ - str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_1 + mrs r5, PAC_KEY_P_2 + mrs r6, PAC_KEY_P_3 + stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -326,6 +355,14 @@ ldr r2, [r1] /* r2 = Location of saved context in TCB. */ restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ msr psp, r3 msr psplim, r4 @@ -371,76 +408,86 @@ mrs r2, psp /* Read PSP in r2. */ cbz r0, save_ns_context /* No secure context to save. */ - push {r0-r2, r14} - bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ - pop {r0-r3} /* LR is now in r3. */ - mov lr, r3 /* LR = r3. */ - lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ - bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ - - ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ - ldr r1, [r3] /* Read pxCurrentTCB. */ - subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ - str r2, [r1] /* Save the new top of stack in TCB. */ - mrs r1, psplim /* r1 = PSPLIM. */ - mov r3, lr /* r3 = LR/EXC_RETURN. */ - stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ - b select_next_task + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} save_ns_context: - ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ - ldr r1, [r3] /* Read pxCurrentTCB. */ + mov r3, lr /* r3 = LR. */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + + save_general_regs: #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ it eq vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ #endif /* configENABLE_FPU || configENABLE_MVE */ - subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ - str r2, [r1] /* Save the new top of stack in TCB. */ - adds r2, r2, #12 /* r2 = r2 + 12. */ - stm r2, {r4-r11} /* Store the registers that are not saved automatically. */ - mrs r1, psplim /* r1 = PSPLIM. */ - mov r3, lr /* r3 = LR/EXC_RETURN. */ - subs r2, r2, #12 /* r2 = r2 - 12. */ - stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ + stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_1 + mrs r6, PAC_KEY_P_0 + stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the new top of stack in TCB. */ select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext mov r0, #0 /* r0 = 0. */ msr basepri, r0 /* Enable interrupts. */ + restore_context: ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r3] /* Read pxCurrentTCB. */ ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ - ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ - msr psplim, r1 /* Restore the PSPLIM register value for the task. */ - mov lr, r4 /* LR = r4. */ + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_1, r5 + msr PAC_KEY_P_0, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmia r2!, {r0, r3, lr} /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + msr psplim, r3 /* Restore the PSPLIM register value for the task. */ ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ str r0, [r3] /* Restore the task's xSecureContext. */ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ - ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ - ldr r1, [r3] /* Read pxCurrentTCB. */ - push {r2, r4} + + restore_s_context: + push {r1-r3, lr} bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ - pop {r2, r4} - mov lr, r4 /* LR = r4. */ - lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ - bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ - msr psp, r2 /* Remember the new top of stack for the task. */ - bx lr + pop {r1-r3, lr} restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ it eq vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: msr psp, r2 /* Remember the new top of stack for the task. */ bx lr
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h index 4eb1c72..df7888d 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -48,20 +48,28 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M33" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33. +#endif +/*-----------------------------------------------------------*/ + /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h index 6f666da..2dfac6a 100644 --- a/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM33/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -117,7 +119,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -125,6 +127,18 @@ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; #endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ /*-----------------------------------------------------------*/ /** @@ -137,7 +151,7 @@ #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) @@ -193,8 +207,8 @@ */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -223,7 +237,20 @@ */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +-----------+---------------+----------+-----------------+------------------------------+-----+ @@ -232,11 +259,24 @@ * +-----------+---------------+----------+-----------------+------------------------------+-----+ * * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 + * 16 17 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 54 + #define MAX_CONTEXT_SIZE 55 - #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ /* * +-----------+---------------+----------+-----------------+----------------------+-----+ @@ -245,15 +285,28 @@ * +-----------+---------------+----------+-----------------+----------------------+-----+ * * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 + * 16 17 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 53 + #define MAX_CONTEXT_SIZE 54 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +----------+-----------------+------------------------------+-----+ @@ -264,7 +317,20 @@ * <---------><----------------><------------------------------><----> * 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 22 + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ @@ -277,17 +343,17 @@ * <---------><----------------><----------------------><----> * 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 21 + #define MAX_CONTEXT_SIZE 21 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) -/* Size of an Access Control List (ACL) entry in bits. */ + /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) typedef struct MPU_SETTINGS @@ -312,8 +378,8 @@ * @brief Validate priority of ISRs that are allowed to call FreeRTOS * system calls. */ -#ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +399,29 @@ /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +507,12 @@ extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +523,56 @@ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus }
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context.c b/Source/portable/IAR/ARM_CM33/secure/secure_context.c index e37dd96..62bcfa1 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_context.c +++ b/Source/portable/IAR/ARM_CM33/secure/secure_context.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -207,7 +207,7 @@ * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ @@ -219,16 +219,16 @@ if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } #else /* configENABLE_MPU */ - { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; - } + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex;
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context.h b/Source/portable/IAR/ARM_CM33/secure/secure_context.h index 2220ea6..8b93857 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_context.h +++ b/Source/portable/IAR/ARM_CM33/secure/secure_context.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s index 0da3e0f..5cc070e 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s +++ b/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_heap.c b/Source/portable/IAR/ARM_CM33/secure/secure_heap.c index 19f7c23..b0e83b4 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_heap.c +++ b/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -29,6 +29,9 @@ /* Standard includes. */ #include <stdint.h> +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + /* Secure context heap includes. */ #include "secure_heap.h" @@ -62,6 +65,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +142,6 @@ static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +186,6 @@ /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -229,7 +237,7 @@ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; } - /* If the block being inserted plugged a gab, so was merged with the block + /* If the block being inserted plugged a gap, so was merged with the block * before and the block after, then it's pxNextFreeBlock pointer will have * already been set, and should not be set here as that would make it point * to itself. */ @@ -250,6 +258,8 @@ BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +272,29 @@ mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +303,20 @@ } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +359,8 @@ pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -352,9 +378,11 @@ mtCOVERAGE_TEST_MARKER(); } + xAllocatedBlockSize = pxBlock->xBlockSize; + /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -372,20 +400,23 @@ mtCOVERAGE_TEST_MARKER(); } - traceMALLOC( pvReturn, xWantedSize ); + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +439,16 @@ pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); {
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_heap.h b/Source/portable/IAR/ARM_CM33/secure/secure_heap.h index 75c9cb0..61a96da 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_heap.h +++ b/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_init.c b/Source/portable/IAR/ARM_CM33/secure/secure_init.c index f93bfce..f7f7e67 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_init.c +++ b/Source/portable/IAR/ARM_CM33/secure/secure_init.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -93,7 +93,7 @@ * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_init.h b/Source/portable/IAR/ARM_CM33/secure/secure_init.h index e6c9da0..46ffbd9 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_init.h +++ b/Source/portable/IAR/ARM_CM33/secure/secure_init.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h index d7ac583..34494e1 100644 --- a/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h +++ b/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S index ef180bd..68192e4 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -47,12 +47,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskDelayUntil_Unpriv MPU_xTaskDelayUntil_Priv: - pop {r0} b MPU_xTaskDelayUntilImpl MPU_xTaskDelayUntil_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskDelayUntil /*-----------------------------------------------------------*/ @@ -61,12 +60,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskAbortDelay_Unpriv MPU_xTaskAbortDelay_Priv: - pop {r0} b MPU_xTaskAbortDelayImpl MPU_xTaskAbortDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskAbortDelay /*-----------------------------------------------------------*/ @@ -75,12 +73,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskDelay_Unpriv MPU_vTaskDelay_Priv: - pop {r0} b MPU_vTaskDelayImpl MPU_vTaskDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskDelay /*-----------------------------------------------------------*/ @@ -89,12 +86,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskPriorityGet_Unpriv MPU_uxTaskPriorityGet_Priv: - pop {r0} b MPU_uxTaskPriorityGetImpl MPU_uxTaskPriorityGet_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskPriorityGet /*-----------------------------------------------------------*/ @@ -103,12 +99,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_eTaskGetState_Unpriv MPU_eTaskGetState_Priv: - pop {r0} b MPU_eTaskGetStateImpl MPU_eTaskGetState_Unpriv: - pop {r0} svc #SYSTEM_CALL_eTaskGetState /*-----------------------------------------------------------*/ @@ -117,12 +112,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskGetInfo_Unpriv MPU_vTaskGetInfo_Priv: - pop {r0} b MPU_vTaskGetInfoImpl MPU_vTaskGetInfo_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskGetInfo /*-----------------------------------------------------------*/ @@ -131,12 +125,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetIdleTaskHandle_Unpriv MPU_xTaskGetIdleTaskHandle_Priv: - pop {r0} b MPU_xTaskGetIdleTaskHandleImpl MPU_xTaskGetIdleTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetIdleTaskHandle /*-----------------------------------------------------------*/ @@ -145,12 +138,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSuspend_Unpriv MPU_vTaskSuspend_Priv: - pop {r0} b MPU_vTaskSuspendImpl MPU_vTaskSuspend_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSuspend /*-----------------------------------------------------------*/ @@ -159,12 +151,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskResume_Unpriv MPU_vTaskResume_Priv: - pop {r0} b MPU_vTaskResumeImpl MPU_vTaskResume_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskResume /*-----------------------------------------------------------*/ @@ -173,12 +164,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetTickCount_Unpriv MPU_xTaskGetTickCount_Priv: - pop {r0} b MPU_xTaskGetTickCountImpl MPU_xTaskGetTickCount_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetTickCount /*-----------------------------------------------------------*/ @@ -187,40 +177,24 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetNumberOfTasks_Unpriv MPU_uxTaskGetNumberOfTasks_Priv: - pop {r0} b MPU_uxTaskGetNumberOfTasksImpl MPU_uxTaskGetNumberOfTasks_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimeCounter_Unpriv MPU_ulTaskGetRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimeCounter /*-----------------------------------------------------------*/ @@ -229,12 +203,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimePercent_Unpriv MPU_ulTaskGetRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetRunTimePercentImpl MPU_ulTaskGetRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimePercent /*-----------------------------------------------------------*/ @@ -243,12 +216,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimePercent_Unpriv MPU_ulTaskGetIdleRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimePercentImpl MPU_ulTaskGetIdleRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent /*-----------------------------------------------------------*/ @@ -257,12 +229,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv MPU_ulTaskGetIdleRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimeCounterImpl MPU_ulTaskGetIdleRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter /*-----------------------------------------------------------*/ @@ -271,12 +242,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetApplicationTaskTag_Unpriv MPU_vTaskSetApplicationTaskTag_Priv: - pop {r0} b MPU_vTaskSetApplicationTaskTagImpl MPU_vTaskSetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -285,12 +255,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetApplicationTaskTag_Unpriv MPU_xTaskGetApplicationTaskTag_Priv: - pop {r0} b MPU_xTaskGetApplicationTaskTagImpl MPU_xTaskGetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -299,12 +268,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv MPU_vTaskSetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_vTaskSetThreadLocalStoragePointerImpl MPU_vTaskSetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -313,12 +281,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv MPU_pvTaskGetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_pvTaskGetThreadLocalStoragePointerImpl MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -327,12 +294,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetSystemState_Unpriv MPU_uxTaskGetSystemState_Priv: - pop {r0} b MPU_uxTaskGetSystemStateImpl MPU_uxTaskGetSystemState_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetSystemState /*-----------------------------------------------------------*/ @@ -341,12 +307,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark_Unpriv MPU_uxTaskGetStackHighWaterMark_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMarkImpl MPU_uxTaskGetStackHighWaterMark_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark /*-----------------------------------------------------------*/ @@ -355,12 +320,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark2_Unpriv MPU_uxTaskGetStackHighWaterMark2_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMark2Impl MPU_uxTaskGetStackHighWaterMark2_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 /*-----------------------------------------------------------*/ @@ -369,12 +333,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetCurrentTaskHandle_Unpriv MPU_xTaskGetCurrentTaskHandle_Priv: - pop {r0} b MPU_xTaskGetCurrentTaskHandleImpl MPU_xTaskGetCurrentTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle /*-----------------------------------------------------------*/ @@ -383,12 +346,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetSchedulerState_Unpriv MPU_xTaskGetSchedulerState_Priv: - pop {r0} b MPU_xTaskGetSchedulerStateImpl MPU_xTaskGetSchedulerState_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetSchedulerState /*-----------------------------------------------------------*/ @@ -397,12 +359,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetTimeOutState_Unpriv MPU_vTaskSetTimeOutState_Priv: - pop {r0} b MPU_vTaskSetTimeOutStateImpl MPU_vTaskSetTimeOutState_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetTimeOutState /*-----------------------------------------------------------*/ @@ -411,12 +372,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskCheckForTimeOut_Unpriv MPU_xTaskCheckForTimeOut_Priv: - pop {r0} b MPU_xTaskCheckForTimeOutImpl MPU_xTaskCheckForTimeOut_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskCheckForTimeOut /*-----------------------------------------------------------*/ @@ -425,12 +385,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotify_Unpriv MPU_xTaskGenericNotify_Priv: - pop {r0} b MPU_xTaskGenericNotifyImpl MPU_xTaskGenericNotify_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotify /*-----------------------------------------------------------*/ @@ -439,12 +398,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyWait_Unpriv MPU_xTaskGenericNotifyWait_Priv: - pop {r0} b MPU_xTaskGenericNotifyWaitImpl MPU_xTaskGenericNotifyWait_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyWait /*-----------------------------------------------------------*/ @@ -453,12 +411,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyTake_Unpriv MPU_ulTaskGenericNotifyTake_Priv: - pop {r0} b MPU_ulTaskGenericNotifyTakeImpl MPU_ulTaskGenericNotifyTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyTake /*-----------------------------------------------------------*/ @@ -467,12 +424,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyStateClear_Unpriv MPU_xTaskGenericNotifyStateClear_Priv: - pop {r0} b MPU_xTaskGenericNotifyStateClearImpl MPU_xTaskGenericNotifyStateClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyStateClear /*-----------------------------------------------------------*/ @@ -481,12 +437,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyValueClear_Unpriv MPU_ulTaskGenericNotifyValueClear_Priv: - pop {r0} b MPU_ulTaskGenericNotifyValueClearImpl MPU_ulTaskGenericNotifyValueClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear /*-----------------------------------------------------------*/ @@ -495,12 +450,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGenericSend_Unpriv MPU_xQueueGenericSend_Priv: - pop {r0} b MPU_xQueueGenericSendImpl MPU_xQueueGenericSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGenericSend /*-----------------------------------------------------------*/ @@ -509,12 +463,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueMessagesWaiting_Unpriv MPU_uxQueueMessagesWaiting_Priv: - pop {r0} b MPU_uxQueueMessagesWaitingImpl MPU_uxQueueMessagesWaiting_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueMessagesWaiting /*-----------------------------------------------------------*/ @@ -523,12 +476,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueSpacesAvailable_Unpriv MPU_uxQueueSpacesAvailable_Priv: - pop {r0} b MPU_uxQueueSpacesAvailableImpl MPU_uxQueueSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueSpacesAvailable /*-----------------------------------------------------------*/ @@ -537,12 +489,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueReceive_Unpriv MPU_xQueueReceive_Priv: - pop {r0} b MPU_xQueueReceiveImpl MPU_xQueueReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueReceive /*-----------------------------------------------------------*/ @@ -551,12 +502,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueuePeek_Unpriv MPU_xQueuePeek_Priv: - pop {r0} b MPU_xQueuePeekImpl MPU_xQueuePeek_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueuePeek /*-----------------------------------------------------------*/ @@ -565,12 +515,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSemaphoreTake_Unpriv MPU_xQueueSemaphoreTake_Priv: - pop {r0} b MPU_xQueueSemaphoreTakeImpl MPU_xQueueSemaphoreTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSemaphoreTake /*-----------------------------------------------------------*/ @@ -579,12 +528,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGetMutexHolder_Unpriv MPU_xQueueGetMutexHolder_Priv: - pop {r0} b MPU_xQueueGetMutexHolderImpl MPU_xQueueGetMutexHolder_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGetMutexHolder /*-----------------------------------------------------------*/ @@ -593,12 +541,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueTakeMutexRecursive_Unpriv MPU_xQueueTakeMutexRecursive_Priv: - pop {r0} b MPU_xQueueTakeMutexRecursiveImpl MPU_xQueueTakeMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueTakeMutexRecursive /*-----------------------------------------------------------*/ @@ -607,12 +554,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGiveMutexRecursive_Unpriv MPU_xQueueGiveMutexRecursive_Priv: - pop {r0} b MPU_xQueueGiveMutexRecursiveImpl MPU_xQueueGiveMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGiveMutexRecursive /*-----------------------------------------------------------*/ @@ -621,12 +567,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSelectFromSet_Unpriv MPU_xQueueSelectFromSet_Priv: - pop {r0} b MPU_xQueueSelectFromSetImpl MPU_xQueueSelectFromSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSelectFromSet /*-----------------------------------------------------------*/ @@ -635,12 +580,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueAddToSet_Unpriv MPU_xQueueAddToSet_Priv: - pop {r0} b MPU_xQueueAddToSetImpl MPU_xQueueAddToSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueAddToSet /*-----------------------------------------------------------*/ @@ -649,12 +593,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueAddToRegistry_Unpriv MPU_vQueueAddToRegistry_Priv: - pop {r0} b MPU_vQueueAddToRegistryImpl MPU_vQueueAddToRegistry_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueAddToRegistry /*-----------------------------------------------------------*/ @@ -663,12 +606,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueUnregisterQueue_Unpriv MPU_vQueueUnregisterQueue_Priv: - pop {r0} b MPU_vQueueUnregisterQueueImpl MPU_vQueueUnregisterQueue_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueUnregisterQueue /*-----------------------------------------------------------*/ @@ -677,12 +619,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcQueueGetName_Unpriv MPU_pcQueueGetName_Priv: - pop {r0} b MPU_pcQueueGetNameImpl MPU_pcQueueGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcQueueGetName /*-----------------------------------------------------------*/ @@ -691,12 +632,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTimerGetTimerID_Unpriv MPU_pvTimerGetTimerID_Priv: - pop {r0} b MPU_pvTimerGetTimerIDImpl MPU_pvTimerGetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTimerGetTimerID /*-----------------------------------------------------------*/ @@ -705,12 +645,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetTimerID_Unpriv MPU_vTimerSetTimerID_Priv: - pop {r0} b MPU_vTimerSetTimerIDImpl MPU_vTimerSetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetTimerID /*-----------------------------------------------------------*/ @@ -719,12 +658,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerIsTimerActive_Unpriv MPU_xTimerIsTimerActive_Priv: - pop {r0} b MPU_xTimerIsTimerActiveImpl MPU_xTimerIsTimerActive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerIsTimerActive /*-----------------------------------------------------------*/ @@ -733,33 +671,25 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv MPU_xTimerGetTimerDaemonTaskHandle_Priv: - pop {r0} b MPU_xTimerGetTimerDaemonTaskHandleImpl MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: - pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: - pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -767,12 +697,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcTimerGetName_Unpriv MPU_pcTimerGetName_Priv: - pop {r0} b MPU_pcTimerGetNameImpl MPU_pcTimerGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcTimerGetName /*-----------------------------------------------------------*/ @@ -781,12 +710,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetReloadMode_Unpriv MPU_vTimerSetReloadMode_Priv: - pop {r0} b MPU_vTimerSetReloadModeImpl MPU_vTimerSetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetReloadMode /*-----------------------------------------------------------*/ @@ -795,12 +723,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetReloadMode_Unpriv MPU_xTimerGetReloadMode_Priv: - pop {r0} b MPU_xTimerGetReloadModeImpl MPU_xTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -809,12 +736,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTimerGetReloadMode_Unpriv MPU_uxTimerGetReloadMode_Priv: - pop {r0} b MPU_uxTimerGetReloadModeImpl MPU_uxTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -823,12 +749,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetPeriod_Unpriv MPU_xTimerGetPeriod_Priv: - pop {r0} b MPU_xTimerGetPeriodImpl MPU_xTimerGetPeriod_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetPeriod /*-----------------------------------------------------------*/ @@ -837,12 +762,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetExpiryTime_Unpriv MPU_xTimerGetExpiryTime_Priv: - pop {r0} b MPU_xTimerGetExpiryTimeImpl MPU_xTimerGetExpiryTime_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetExpiryTime /*-----------------------------------------------------------*/ @@ -851,12 +775,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupWaitBits_Unpriv MPU_xEventGroupWaitBits_Priv: - pop {r0} b MPU_xEventGroupWaitBitsImpl MPU_xEventGroupWaitBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupWaitBits /*-----------------------------------------------------------*/ @@ -865,12 +788,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupClearBits_Unpriv MPU_xEventGroupClearBits_Priv: - pop {r0} b MPU_xEventGroupClearBitsImpl MPU_xEventGroupClearBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupClearBits /*-----------------------------------------------------------*/ @@ -879,12 +801,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSetBits_Unpriv MPU_xEventGroupSetBits_Priv: - pop {r0} b MPU_xEventGroupSetBitsImpl MPU_xEventGroupSetBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSetBits /*-----------------------------------------------------------*/ @@ -893,12 +814,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSync_Unpriv MPU_xEventGroupSync_Priv: - pop {r0} b MPU_xEventGroupSyncImpl MPU_xEventGroupSync_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSync /*-----------------------------------------------------------*/ @@ -907,12 +827,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxEventGroupGetNumber_Unpriv MPU_uxEventGroupGetNumber_Priv: - pop {r0} b MPU_uxEventGroupGetNumberImpl MPU_uxEventGroupGetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxEventGroupGetNumber /*-----------------------------------------------------------*/ @@ -921,12 +840,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vEventGroupSetNumber_Unpriv MPU_vEventGroupSetNumber_Priv: - pop {r0} b MPU_vEventGroupSetNumberImpl MPU_vEventGroupSetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_vEventGroupSetNumber /*-----------------------------------------------------------*/ @@ -935,12 +853,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSend_Unpriv MPU_xStreamBufferSend_Priv: - pop {r0} b MPU_xStreamBufferSendImpl MPU_xStreamBufferSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSend /*-----------------------------------------------------------*/ @@ -949,12 +866,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferReceive_Unpriv MPU_xStreamBufferReceive_Priv: - pop {r0} b MPU_xStreamBufferReceiveImpl MPU_xStreamBufferReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferReceive /*-----------------------------------------------------------*/ @@ -963,12 +879,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsFull_Unpriv MPU_xStreamBufferIsFull_Priv: - pop {r0} b MPU_xStreamBufferIsFullImpl MPU_xStreamBufferIsFull_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsFull /*-----------------------------------------------------------*/ @@ -977,12 +892,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsEmpty_Unpriv MPU_xStreamBufferIsEmpty_Priv: - pop {r0} b MPU_xStreamBufferIsEmptyImpl MPU_xStreamBufferIsEmpty_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsEmpty /*-----------------------------------------------------------*/ @@ -991,12 +905,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSpacesAvailable_Unpriv MPU_xStreamBufferSpacesAvailable_Priv: - pop {r0} b MPU_xStreamBufferSpacesAvailableImpl MPU_xStreamBufferSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSpacesAvailable /*-----------------------------------------------------------*/ @@ -1005,12 +918,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferBytesAvailable_Unpriv MPU_xStreamBufferBytesAvailable_Priv: - pop {r0} b MPU_xStreamBufferBytesAvailableImpl MPU_xStreamBufferBytesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferBytesAvailable /*-----------------------------------------------------------*/ @@ -1019,12 +931,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSetTriggerLevel_Unpriv MPU_xStreamBufferSetTriggerLevel_Priv: - pop {r0} b MPU_xStreamBufferSetTriggerLevelImpl MPU_xStreamBufferSetTriggerLevel_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel /*-----------------------------------------------------------*/ @@ -1033,12 +944,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv MPU_xStreamBufferNextMessageLengthBytes_Priv: - pop {r0} b MPU_xStreamBufferNextMessageLengthBytesImpl MPU_xStreamBufferNextMessageLengthBytes_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes /*-----------------------------------------------------------*/ @@ -1089,10 +999,6 @@ MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1151,9 @@ MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c index 9712ac3..f16a343 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -54,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 @@ -68,6 +70,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,8 +109,17 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) /*-----------------------------------------------------------*/ /** @@ -111,8 +138,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,72 +161,79 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + +/* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ /* Enable privileged access to unmapped region. */ #define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) @@ -343,6 +377,20 @@ * any secure calls. */ #define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ /** @@ -351,7 +399,7 @@ */ static void prvTaskExitError( void ); -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief Extract MPU region's access permissions from the Region Base Address @@ -362,7 +410,7 @@ * @return uint32_t Access permissions. */ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; -#endif /* configENABLE_MPU */ +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ #if ( configENABLE_MPU == 1 ) @@ -380,6 +428,26 @@ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_FPU */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + +/** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + /** * @brief Setup the timer to generate the tick interrupts. * @@ -448,13 +516,13 @@ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,24 +530,24 @@ #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ -#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief This variable is set to pdTRUE when the scheduler is started. */ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; -#endif +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /** * @brief Each task maintains its own interrupt status in the critical nesting @@ -501,13 +569,13 @@ * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -531,6 +599,7 @@ /*-----------------------------------------------------------*/ #if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) { uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; @@ -746,6 +815,7 @@ __asm volatile ( "cpsie i" ::: "memory" ); } } + #endif /* configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ @@ -760,8 +830,15 @@ } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -795,7 +872,8 @@ } /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ { uint32_t ulAccessPermissions = 0; @@ -812,13 +890,16 @@ return ulAccessPermissions; } -#endif /* configENABLE_MPU */ + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -903,10 +984,12 @@ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ #if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ { #if ( configENABLE_TRUSTZONE == 1 ) @@ -928,6 +1011,7 @@ * LSPEN = 1 ==> Enable lazy context save of FP state. */ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); } + #endif /* configENABLE_FPU */ /*-----------------------------------------------------------*/ @@ -972,13 +1056,19 @@ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1078,7 @@ { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1174,24 @@ vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1116,6 +1213,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1154,12 +1252,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1268,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1190,11 +1287,19 @@ /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; @@ -1224,14 +1329,13 @@ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1259,6 +1363,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -1293,12 +1398,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1414,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1436,11 @@ /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1458,13 @@ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1392,6 +1499,7 @@ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ { uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ ulIndex++; @@ -1410,21 +1518,21 @@ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,20 +1543,30 @@ #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ ulIndex++; } else { xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1469,6 +1587,20 @@ } #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + return &( xMPUSettings->ulContext[ ulIndex ] ); } @@ -1483,7 +1615,7 @@ * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1637,7 @@ } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1672,7 @@ pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1551,6 +1683,20 @@ } #endif /* portPRELOAD_REGISTERS */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + return pxTopOfStack; } @@ -1559,22 +1705,52 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) { - volatile uint32_t ulOriginalPriority; + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1769,10 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1810,22 @@ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ #if ( configENABLE_MPU == 1 ) { @@ -1660,11 +1841,11 @@ /* Initialize the critical nesting count ready for the first task. */ ulCriticalNesting = 0; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { xSchedulerRunning = pdTRUE; } - #endif + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /* Start the first task. */ vStartFirstTask(); @@ -1692,15 +1873,17 @@ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, - uint32_t ulStackDepth ) + configSTACK_DEPTH_TYPE uxStackDepth ) { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1719,10 +1902,10 @@ * which case the stack region parameters will be valid. At all other * times the stack parameters will not be valid and it is assumed that * the stack region has already been configured. */ - if( ulStackDepth > 0 ) + if( uxStackDepth > 0 ) { ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; - ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; /* If the stack is within the privileged SRAM, do not protect it * using a separate MPU region. This is needed because privileged @@ -1790,6 +1973,16 @@ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | ( portMPU_RLAR_REGION_ENABLE ); + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + /* Normal memory/ Device memory. */ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) { @@ -1812,10 +2005,12 @@ lIndex++; } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, uint32_t ulBufferLength, uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ @@ -1825,7 +2020,15 @@ BaseType_t xAccessGranted = pdFALSE; const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ - if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) { xAccessGranted = pdTRUE; } @@ -1860,7 +2063,8 @@ return xAccessGranted; } -#endif /* configENABLE_MPU */ + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /*-----------------------------------------------------------*/ BaseType_t xPortIsInsideInterrupt( void ) @@ -1886,7 +2090,7 @@ } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1924,7 +2128,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); } @@ -1944,7 +2148,7 @@ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) @@ -2041,3 +2245,38 @@ #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h index f64ceb5..53b4b6e 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -52,7 +52,7 @@ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s index 00ee5a5..8092255 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -140,6 +142,14 @@ ldr r1, [r0] /* r1 = Location of saved context in TCB. */ restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ msr psp, r2 msr psplim, r3 @@ -163,10 +173,20 @@ ldr r1, [r2] /* Read pxCurrentTCB. */ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ msr psplim, r1 /* Set this task's PSPLIM value. */ - movs r1, #2 /* r1 = 2. */ - msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ adds r0, #32 /* Discard everything up to r0. */ msr psp, r0 /* This is now the new top of stack to use in the task. */ isb @@ -199,7 +219,7 @@ ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -230,7 +250,6 @@ vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */ #endif /* configENABLE_FPU || configENABLE_MVE */ - stmia r1!, {r4-r11} /* Store r4-r11. */ ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */ stmia r1!, {r4-r11} /* Store the hardware saved context. */ @@ -239,11 +258,20 @@ mrs r3, psplim /* r3 = PSPLIM. */ mrs r4, control /* r4 = CONTROL. */ stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_3 + stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -297,6 +325,14 @@ ldr r1, [r0] /* r1 = Location of saved context in TCB. */ restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ msr psp, r2 msr psplim, r3 @@ -332,12 +368,21 @@ mov r3, lr /* r3 = LR/EXC_RETURN. */ stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ +#if ( configENABLE_PAC == 1 ) + mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r2, PAC_KEY_P_2 + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_0 + stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */ + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -348,6 +393,15 @@ ldr r1, [r2] /* Read pxCurrentTCB. */ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r3 + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_0, r5 + clrm {r2-r5} /* Clear r2-r5. */ +#endif /* configENABLE_PAC */ + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h index 4eb1c72..df7888d 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -48,20 +48,28 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M33" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M33" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 0 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ #include "portmacrocommon.h" /*-----------------------------------------------------------*/ +#ifndef configENABLE_MVE + #define configENABLE_MVE 0 +#elif ( configENABLE_MVE != 0 ) + #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33. +#endif +/*-----------------------------------------------------------*/ + /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h index 6f666da..2dfac6a 100644 --- a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -117,7 +119,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -125,6 +127,18 @@ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; #endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ /*-----------------------------------------------------------*/ /** @@ -137,7 +151,7 @@ #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) @@ -193,8 +207,8 @@ */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -223,7 +237,20 @@ */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +-----------+---------------+----------+-----------------+------------------------------+-----+ @@ -232,11 +259,24 @@ * +-----------+---------------+----------+-----------------+------------------------------+-----+ * * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 + * 16 17 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 54 + #define MAX_CONTEXT_SIZE 55 - #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ /* * +-----------+---------------+----------+-----------------+----------------------+-----+ @@ -245,15 +285,28 @@ * +-----------+---------------+----------+-----------------+----------------------+-----+ * * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 + * 16 17 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 53 + #define MAX_CONTEXT_SIZE 54 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +----------+-----------------+------------------------------+-----+ @@ -264,7 +317,20 @@ * <---------><----------------><------------------------------><----> * 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 22 + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ @@ -277,17 +343,17 @@ * <---------><----------------><----------------------><----> * 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 21 + #define MAX_CONTEXT_SIZE 21 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) -/* Size of an Access Control List (ACL) entry in bits. */ + /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) typedef struct MPU_SETTINGS @@ -312,8 +378,8 @@ * @brief Validate priority of ISRs that are allowed to call FreeRTOS * system calls. */ -#ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +399,29 @@ /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +507,12 @@ extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +523,56 @@ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus }
diff --git a/Source/portable/IAR/ARM_CM4F/port.c b/Source/portable/IAR/ARM_CM4F/port.c index 692400b..a863cac 100644 --- a/Source/portable/IAR/ARM_CM4F/port.c +++ b/Source/portable/IAR/ARM_CM4F/port.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -45,10 +45,14 @@ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) /* ...then bits in the registers. */ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) @@ -69,6 +73,11 @@ #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -141,6 +150,11 @@ */ static void prvTaskExitError( void ); +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ); +extern void xPortPendSVHandler( void ); /*-----------------------------------------------------------*/ /* Each task maintains its own interrupt status in the critical nesting @@ -246,6 +260,40 @@ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -281,7 +329,7 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -295,22 +343,22 @@ if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -330,9 +378,11 @@ } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the lowest priority interrupts. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Start the timer that generates the tick ISR. Interrupts are disabled * here already. */ @@ -399,14 +449,21 @@ * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } @@ -696,7 +753,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); }
diff --git a/Source/portable/IAR/ARM_CM4F/portasm.s b/Source/portable/IAR/ARM_CM4F/portasm.s index 89b72b2..627b1bf 100644 --- a/Source/portable/IAR/ARM_CM4F/portasm.s +++ b/Source/portable/IAR/ARM_CM4F/portasm.s
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM4F/portmacro.h b/Source/portable/IAR/ARM_CM4F/portmacro.h index 92cb7c7..2bc2281 100644 --- a/Source/portable/IAR/ARM_CM4F/portmacro.h +++ b/Source/portable/IAR/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -27,7 +27,7 @@ */ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -46,50 +46,50 @@ */ /* IAR includes. */ - #include <intrinsics.h> +#include <intrinsics.h> /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Compiler directives. */ - #define portWEAK_SYMBOL __attribute__( ( weak ) ) +#define portWEAK_SYMBOL __attribute__( ( weak ) ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -97,112 +97,124 @@ __ISB(); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); - #define portDISABLE_INTERRUPTS() \ +#define portDISABLE_INTERRUPTS() \ { \ __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ __DSB(); \ __ISB(); \ } - #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() - #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif /*-----------------------------------------------------------*/ - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdFALSE; } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in * the source code because to do so would cause other compilers to generate * warnings. */ - #pragma diag_suppress=Pe191 - #pragma diag_suppress=Pa082 +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 /* *INDENT-OFF* */ #ifdef __cplusplus
diff --git a/Source/portable/IAR/ARM_CM4_MPU/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM4_MPU/mpu_wrappers_v2_asm.S index 276a1cf..310636b 100644 --- a/Source/portable/IAR/ARM_CM4_MPU/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM4_MPU/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -51,12 +51,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskDelayUntil_Unpriv MPU_xTaskDelayUntil_Priv: - pop {r0} b MPU_xTaskDelayUntilImpl MPU_xTaskDelayUntil_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskDelayUntil /*-----------------------------------------------------------*/ @@ -65,12 +64,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskAbortDelay_Unpriv MPU_xTaskAbortDelay_Priv: - pop {r0} b MPU_xTaskAbortDelayImpl MPU_xTaskAbortDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskAbortDelay /*-----------------------------------------------------------*/ @@ -79,12 +77,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskDelay_Unpriv MPU_vTaskDelay_Priv: - pop {r0} b MPU_vTaskDelayImpl MPU_vTaskDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskDelay /*-----------------------------------------------------------*/ @@ -93,12 +90,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskPriorityGet_Unpriv MPU_uxTaskPriorityGet_Priv: - pop {r0} b MPU_uxTaskPriorityGetImpl MPU_uxTaskPriorityGet_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskPriorityGet /*-----------------------------------------------------------*/ @@ -107,12 +103,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_eTaskGetState_Unpriv MPU_eTaskGetState_Priv: - pop {r0} b MPU_eTaskGetStateImpl MPU_eTaskGetState_Unpriv: - pop {r0} svc #SYSTEM_CALL_eTaskGetState /*-----------------------------------------------------------*/ @@ -121,12 +116,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskGetInfo_Unpriv MPU_vTaskGetInfo_Priv: - pop {r0} b MPU_vTaskGetInfoImpl MPU_vTaskGetInfo_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskGetInfo /*-----------------------------------------------------------*/ @@ -135,12 +129,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetIdleTaskHandle_Unpriv MPU_xTaskGetIdleTaskHandle_Priv: - pop {r0} b MPU_xTaskGetIdleTaskHandleImpl MPU_xTaskGetIdleTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetIdleTaskHandle /*-----------------------------------------------------------*/ @@ -149,12 +142,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSuspend_Unpriv MPU_vTaskSuspend_Priv: - pop {r0} b MPU_vTaskSuspendImpl MPU_vTaskSuspend_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSuspend /*-----------------------------------------------------------*/ @@ -163,12 +155,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskResume_Unpriv MPU_vTaskResume_Priv: - pop {r0} b MPU_vTaskResumeImpl MPU_vTaskResume_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskResume /*-----------------------------------------------------------*/ @@ -177,12 +168,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetTickCount_Unpriv MPU_xTaskGetTickCount_Priv: - pop {r0} b MPU_xTaskGetTickCountImpl MPU_xTaskGetTickCount_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetTickCount /*-----------------------------------------------------------*/ @@ -191,40 +181,24 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetNumberOfTasks_Unpriv MPU_uxTaskGetNumberOfTasks_Priv: - pop {r0} b MPU_uxTaskGetNumberOfTasksImpl MPU_uxTaskGetNumberOfTasks_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimeCounter_Unpriv MPU_ulTaskGetRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimeCounter /*-----------------------------------------------------------*/ @@ -233,12 +207,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimePercent_Unpriv MPU_ulTaskGetRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetRunTimePercentImpl MPU_ulTaskGetRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimePercent /*-----------------------------------------------------------*/ @@ -247,12 +220,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimePercent_Unpriv MPU_ulTaskGetIdleRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimePercentImpl MPU_ulTaskGetIdleRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent /*-----------------------------------------------------------*/ @@ -261,12 +233,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv MPU_ulTaskGetIdleRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimeCounterImpl MPU_ulTaskGetIdleRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter /*-----------------------------------------------------------*/ @@ -275,12 +246,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetApplicationTaskTag_Unpriv MPU_vTaskSetApplicationTaskTag_Priv: - pop {r0} b MPU_vTaskSetApplicationTaskTagImpl MPU_vTaskSetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -289,12 +259,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetApplicationTaskTag_Unpriv MPU_xTaskGetApplicationTaskTag_Priv: - pop {r0} b MPU_xTaskGetApplicationTaskTagImpl MPU_xTaskGetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -303,12 +272,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv MPU_vTaskSetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_vTaskSetThreadLocalStoragePointerImpl MPU_vTaskSetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -317,12 +285,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv MPU_pvTaskGetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_pvTaskGetThreadLocalStoragePointerImpl MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -331,12 +298,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetSystemState_Unpriv MPU_uxTaskGetSystemState_Priv: - pop {r0} b MPU_uxTaskGetSystemStateImpl MPU_uxTaskGetSystemState_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetSystemState /*-----------------------------------------------------------*/ @@ -345,12 +311,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark_Unpriv MPU_uxTaskGetStackHighWaterMark_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMarkImpl MPU_uxTaskGetStackHighWaterMark_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark /*-----------------------------------------------------------*/ @@ -359,12 +324,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark2_Unpriv MPU_uxTaskGetStackHighWaterMark2_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMark2Impl MPU_uxTaskGetStackHighWaterMark2_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 /*-----------------------------------------------------------*/ @@ -373,12 +337,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetCurrentTaskHandle_Unpriv MPU_xTaskGetCurrentTaskHandle_Priv: - pop {r0} b MPU_xTaskGetCurrentTaskHandleImpl MPU_xTaskGetCurrentTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle /*-----------------------------------------------------------*/ @@ -387,12 +350,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetSchedulerState_Unpriv MPU_xTaskGetSchedulerState_Priv: - pop {r0} b MPU_xTaskGetSchedulerStateImpl MPU_xTaskGetSchedulerState_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetSchedulerState /*-----------------------------------------------------------*/ @@ -401,12 +363,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetTimeOutState_Unpriv MPU_vTaskSetTimeOutState_Priv: - pop {r0} b MPU_vTaskSetTimeOutStateImpl MPU_vTaskSetTimeOutState_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetTimeOutState /*-----------------------------------------------------------*/ @@ -415,12 +376,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskCheckForTimeOut_Unpriv MPU_xTaskCheckForTimeOut_Priv: - pop {r0} b MPU_xTaskCheckForTimeOutImpl MPU_xTaskCheckForTimeOut_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskCheckForTimeOut /*-----------------------------------------------------------*/ @@ -429,12 +389,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotify_Unpriv MPU_xTaskGenericNotify_Priv: - pop {r0} b MPU_xTaskGenericNotifyImpl MPU_xTaskGenericNotify_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotify /*-----------------------------------------------------------*/ @@ -443,12 +402,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyWait_Unpriv MPU_xTaskGenericNotifyWait_Priv: - pop {r0} b MPU_xTaskGenericNotifyWaitImpl MPU_xTaskGenericNotifyWait_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyWait /*-----------------------------------------------------------*/ @@ -457,12 +415,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyTake_Unpriv MPU_ulTaskGenericNotifyTake_Priv: - pop {r0} b MPU_ulTaskGenericNotifyTakeImpl MPU_ulTaskGenericNotifyTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyTake /*-----------------------------------------------------------*/ @@ -471,12 +428,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyStateClear_Unpriv MPU_xTaskGenericNotifyStateClear_Priv: - pop {r0} b MPU_xTaskGenericNotifyStateClearImpl MPU_xTaskGenericNotifyStateClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyStateClear /*-----------------------------------------------------------*/ @@ -485,12 +441,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyValueClear_Unpriv MPU_ulTaskGenericNotifyValueClear_Priv: - pop {r0} b MPU_ulTaskGenericNotifyValueClearImpl MPU_ulTaskGenericNotifyValueClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear /*-----------------------------------------------------------*/ @@ -499,12 +454,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGenericSend_Unpriv MPU_xQueueGenericSend_Priv: - pop {r0} b MPU_xQueueGenericSendImpl MPU_xQueueGenericSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGenericSend /*-----------------------------------------------------------*/ @@ -513,12 +467,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueMessagesWaiting_Unpriv MPU_uxQueueMessagesWaiting_Priv: - pop {r0} b MPU_uxQueueMessagesWaitingImpl MPU_uxQueueMessagesWaiting_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueMessagesWaiting /*-----------------------------------------------------------*/ @@ -527,12 +480,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueSpacesAvailable_Unpriv MPU_uxQueueSpacesAvailable_Priv: - pop {r0} b MPU_uxQueueSpacesAvailableImpl MPU_uxQueueSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueSpacesAvailable /*-----------------------------------------------------------*/ @@ -541,12 +493,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueReceive_Unpriv MPU_xQueueReceive_Priv: - pop {r0} b MPU_xQueueReceiveImpl MPU_xQueueReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueReceive /*-----------------------------------------------------------*/ @@ -555,12 +506,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueuePeek_Unpriv MPU_xQueuePeek_Priv: - pop {r0} b MPU_xQueuePeekImpl MPU_xQueuePeek_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueuePeek /*-----------------------------------------------------------*/ @@ -569,12 +519,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSemaphoreTake_Unpriv MPU_xQueueSemaphoreTake_Priv: - pop {r0} b MPU_xQueueSemaphoreTakeImpl MPU_xQueueSemaphoreTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSemaphoreTake /*-----------------------------------------------------------*/ @@ -583,12 +532,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGetMutexHolder_Unpriv MPU_xQueueGetMutexHolder_Priv: - pop {r0} b MPU_xQueueGetMutexHolderImpl MPU_xQueueGetMutexHolder_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGetMutexHolder /*-----------------------------------------------------------*/ @@ -597,12 +545,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueTakeMutexRecursive_Unpriv MPU_xQueueTakeMutexRecursive_Priv: - pop {r0} b MPU_xQueueTakeMutexRecursiveImpl MPU_xQueueTakeMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueTakeMutexRecursive /*-----------------------------------------------------------*/ @@ -611,12 +558,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGiveMutexRecursive_Unpriv MPU_xQueueGiveMutexRecursive_Priv: - pop {r0} b MPU_xQueueGiveMutexRecursiveImpl MPU_xQueueGiveMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGiveMutexRecursive /*-----------------------------------------------------------*/ @@ -625,12 +571,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSelectFromSet_Unpriv MPU_xQueueSelectFromSet_Priv: - pop {r0} b MPU_xQueueSelectFromSetImpl MPU_xQueueSelectFromSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSelectFromSet /*-----------------------------------------------------------*/ @@ -639,12 +584,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueAddToSet_Unpriv MPU_xQueueAddToSet_Priv: - pop {r0} b MPU_xQueueAddToSetImpl MPU_xQueueAddToSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueAddToSet /*-----------------------------------------------------------*/ @@ -653,12 +597,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueAddToRegistry_Unpriv MPU_vQueueAddToRegistry_Priv: - pop {r0} b MPU_vQueueAddToRegistryImpl MPU_vQueueAddToRegistry_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueAddToRegistry /*-----------------------------------------------------------*/ @@ -667,12 +610,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueUnregisterQueue_Unpriv MPU_vQueueUnregisterQueue_Priv: - pop {r0} b MPU_vQueueUnregisterQueueImpl MPU_vQueueUnregisterQueue_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueUnregisterQueue /*-----------------------------------------------------------*/ @@ -681,12 +623,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcQueueGetName_Unpriv MPU_pcQueueGetName_Priv: - pop {r0} b MPU_pcQueueGetNameImpl MPU_pcQueueGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcQueueGetName /*-----------------------------------------------------------*/ @@ -695,12 +636,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTimerGetTimerID_Unpriv MPU_pvTimerGetTimerID_Priv: - pop {r0} b MPU_pvTimerGetTimerIDImpl MPU_pvTimerGetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTimerGetTimerID /*-----------------------------------------------------------*/ @@ -709,12 +649,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetTimerID_Unpriv MPU_vTimerSetTimerID_Priv: - pop {r0} b MPU_vTimerSetTimerIDImpl MPU_vTimerSetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetTimerID /*-----------------------------------------------------------*/ @@ -723,12 +662,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerIsTimerActive_Unpriv MPU_xTimerIsTimerActive_Priv: - pop {r0} b MPU_xTimerIsTimerActiveImpl MPU_xTimerIsTimerActive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerIsTimerActive /*-----------------------------------------------------------*/ @@ -737,33 +675,25 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv MPU_xTimerGetTimerDaemonTaskHandle_Priv: - pop {r0} b MPU_xTimerGetTimerDaemonTaskHandleImpl MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: - pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: - pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -771,12 +701,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcTimerGetName_Unpriv MPU_pcTimerGetName_Priv: - pop {r0} b MPU_pcTimerGetNameImpl MPU_pcTimerGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcTimerGetName /*-----------------------------------------------------------*/ @@ -785,12 +714,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetReloadMode_Unpriv MPU_vTimerSetReloadMode_Priv: - pop {r0} b MPU_vTimerSetReloadModeImpl MPU_vTimerSetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetReloadMode /*-----------------------------------------------------------*/ @@ -799,12 +727,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetReloadMode_Unpriv MPU_xTimerGetReloadMode_Priv: - pop {r0} b MPU_xTimerGetReloadModeImpl MPU_xTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -813,12 +740,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTimerGetReloadMode_Unpriv MPU_uxTimerGetReloadMode_Priv: - pop {r0} b MPU_uxTimerGetReloadModeImpl MPU_uxTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -827,12 +753,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetPeriod_Unpriv MPU_xTimerGetPeriod_Priv: - pop {r0} b MPU_xTimerGetPeriodImpl MPU_xTimerGetPeriod_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetPeriod /*-----------------------------------------------------------*/ @@ -841,12 +766,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetExpiryTime_Unpriv MPU_xTimerGetExpiryTime_Priv: - pop {r0} b MPU_xTimerGetExpiryTimeImpl MPU_xTimerGetExpiryTime_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetExpiryTime /*-----------------------------------------------------------*/ @@ -855,12 +779,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupWaitBits_Unpriv MPU_xEventGroupWaitBits_Priv: - pop {r0} b MPU_xEventGroupWaitBitsImpl MPU_xEventGroupWaitBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupWaitBits /*-----------------------------------------------------------*/ @@ -869,12 +792,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupClearBits_Unpriv MPU_xEventGroupClearBits_Priv: - pop {r0} b MPU_xEventGroupClearBitsImpl MPU_xEventGroupClearBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupClearBits /*-----------------------------------------------------------*/ @@ -883,12 +805,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSetBits_Unpriv MPU_xEventGroupSetBits_Priv: - pop {r0} b MPU_xEventGroupSetBitsImpl MPU_xEventGroupSetBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSetBits /*-----------------------------------------------------------*/ @@ -897,12 +818,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSync_Unpriv MPU_xEventGroupSync_Priv: - pop {r0} b MPU_xEventGroupSyncImpl MPU_xEventGroupSync_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSync /*-----------------------------------------------------------*/ @@ -911,12 +831,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxEventGroupGetNumber_Unpriv MPU_uxEventGroupGetNumber_Priv: - pop {r0} b MPU_uxEventGroupGetNumberImpl MPU_uxEventGroupGetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxEventGroupGetNumber /*-----------------------------------------------------------*/ @@ -925,12 +844,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vEventGroupSetNumber_Unpriv MPU_vEventGroupSetNumber_Priv: - pop {r0} b MPU_vEventGroupSetNumberImpl MPU_vEventGroupSetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_vEventGroupSetNumber /*-----------------------------------------------------------*/ @@ -939,12 +857,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSend_Unpriv MPU_xStreamBufferSend_Priv: - pop {r0} b MPU_xStreamBufferSendImpl MPU_xStreamBufferSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSend /*-----------------------------------------------------------*/ @@ -953,12 +870,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferReceive_Unpriv MPU_xStreamBufferReceive_Priv: - pop {r0} b MPU_xStreamBufferReceiveImpl MPU_xStreamBufferReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferReceive /*-----------------------------------------------------------*/ @@ -967,12 +883,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsFull_Unpriv MPU_xStreamBufferIsFull_Priv: - pop {r0} b MPU_xStreamBufferIsFullImpl MPU_xStreamBufferIsFull_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsFull /*-----------------------------------------------------------*/ @@ -981,12 +896,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsEmpty_Unpriv MPU_xStreamBufferIsEmpty_Priv: - pop {r0} b MPU_xStreamBufferIsEmptyImpl MPU_xStreamBufferIsEmpty_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsEmpty /*-----------------------------------------------------------*/ @@ -995,12 +909,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSpacesAvailable_Unpriv MPU_xStreamBufferSpacesAvailable_Priv: - pop {r0} b MPU_xStreamBufferSpacesAvailableImpl MPU_xStreamBufferSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSpacesAvailable /*-----------------------------------------------------------*/ @@ -1009,12 +922,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferBytesAvailable_Unpriv MPU_xStreamBufferBytesAvailable_Priv: - pop {r0} b MPU_xStreamBufferBytesAvailableImpl MPU_xStreamBufferBytesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferBytesAvailable /*-----------------------------------------------------------*/ @@ -1023,12 +935,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSetTriggerLevel_Unpriv MPU_xStreamBufferSetTriggerLevel_Priv: - pop {r0} b MPU_xStreamBufferSetTriggerLevelImpl MPU_xStreamBufferSetTriggerLevel_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel /*-----------------------------------------------------------*/ @@ -1037,12 +948,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv MPU_xStreamBufferNextMessageLengthBytes_Priv: - pop {r0} b MPU_xStreamBufferNextMessageLengthBytesImpl MPU_xStreamBufferNextMessageLengthBytes_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes /*-----------------------------------------------------------*/ @@ -1093,10 +1003,6 @@ MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1249,9 +1155,9 @@ MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM4_MPU/port.c b/Source/portable/IAR/ARM_CM4_MPU/port.c index 518dfbc..08125a2 100644 --- a/Source/portable/IAR/ARM_CM4_MPU/port.c +++ b/Source/portable/IAR/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -69,6 +69,9 @@ #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 1 #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) @@ -108,7 +111,11 @@ #define portMIN_INTERRUPT_PRIORITY ( 255UL ) #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) -#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL ) + +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) @@ -258,13 +265,13 @@ #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -277,20 +284,30 @@ */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; +/** + * @brief Make a task unprivileged. + */ +void vPortSwitchToUserMode( void ); + +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ) PRIVILEGED_FUNCTION; +extern void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ /* Each task maintains its own interrupt status in the critical nesting * variable. */ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; -#if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) /* * This variable is set to pdTRUE when the scheduler is started. */ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; -#endif +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /* * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure @@ -321,28 +338,29 @@ } else { - xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); + xMPUSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); xMPUSettings->ulContext[ 0 ] = portINITIAL_CONTROL_IF_UNPRIVILEGED; } - xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ - xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ - xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ - xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ - xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ - xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ - xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ - xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ - xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ - xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ - xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ - xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ - xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ - xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ - xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ - xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ + xMPUSettings->ulContext[ 1 ] = 0x04040404; /* r4. */ + xMPUSettings->ulContext[ 2 ] = 0x05050505; /* r5. */ + xMPUSettings->ulContext[ 3 ] = 0x06060606; /* r6. */ + xMPUSettings->ulContext[ 4 ] = 0x07070707; /* r7. */ + xMPUSettings->ulContext[ 5 ] = 0x08080808; /* r8. */ + xMPUSettings->ulContext[ 6 ] = 0x09090909; /* r9. */ + xMPUSettings->ulContext[ 7 ] = 0x10101010; /* r10. */ + xMPUSettings->ulContext[ 8 ] = 0x11111111; /* r11. */ + xMPUSettings->ulContext[ 9 ] = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ + + xMPUSettings->ulContext[ 10 ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ + xMPUSettings->ulContext[ 11 ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ 12 ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ 13 ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ 14 ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ 15 ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ 16 ] = 0; /* LR. */ xMPUSettings->ulContext[ 17 ] = ( ( uint32_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC. */ - xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ 18 ] = portINITIAL_XPSR; /* xPSR. */ #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) { @@ -378,7 +396,6 @@ switch( ucSVCNumber ) { case portSVC_START_SCHEDULER: - portNVIC_SHPR2_REG |= portNVIC_SVC_PRI; vPortRestoreContextOfFirstTask(); break; @@ -481,12 +498,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -507,13 +523,12 @@ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r1, control \n" /* Obtain current control value. */ " bic r1, #1 \n" /* Clear nPRIV bit. */ " msr control, r1 \n" /* Write back new control value. */ ::: "r1", "memory" - ); + ); /* Remember the location where we should copy the stack frame when we exit from * the system call. */ @@ -528,7 +543,6 @@ /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; - /* Raise a request to exit from the system call upon finishing the * system call. */ pulSystemCallStack[ portOFFSET_TO_LR ] = ( uint32_t ) vRequestSystemCallExit; @@ -607,12 +621,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -633,13 +646,12 @@ __asm volatile ( "msr psp, %0" : : "r" ( pulTaskStack ) ); /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r1, control \n" /* Obtain current control value. */ " orr r1, #1 \n" /* Set nPRIV bit. */ " msr control, r1 \n" /* Write back new control value. */ ::: "r1", "memory" - ); + ); /* Return to the caller of the System Call entry point (i.e. the * caller of the MPU_<API>). */ @@ -681,6 +693,19 @@ } /*-----------------------------------------------------------*/ +void vPortSwitchToUserMode( void ) +{ + /* Load the current task's MPU settings from its TCB. */ + xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); + + /* Mark the task as unprivileged. */ + xTaskMpuSettings->ulTaskFlags &= ( ~( portTASK_IS_PRIVILEGED_FLAG ) ); + + /* Lower the processor's privilege level. */ + vResetPrivilege(); +} +/*-----------------------------------------------------------*/ + /* * See header file for description. */ @@ -691,6 +716,7 @@ #if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) configASSERT( ( portCPUID == portCORTEX_M7_r0p1_ID ) || ( portCPUID == portCORTEX_M7_r0p0_ID ) ); #else + /* When using this port on a Cortex-M7 r0p0 or r0p1 core, define * configENABLE_ERRATA_837070_WORKAROUND to 1 in your * FreeRTOSConfig.h. */ @@ -698,6 +724,40 @@ configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); #endif + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -733,7 +793,7 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -782,9 +842,11 @@ } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the lowest priority interrupts. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Configure the regions in the MPU that are common to all tasks. */ prvSetupMPU(); @@ -796,11 +858,11 @@ /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; - #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) { xSchedulerRunning = pdTRUE; } - #endif + #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); @@ -932,14 +994,21 @@ * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } @@ -1058,7 +1127,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, - uint32_t ulStackDepth ) + configSTACK_DEPTH_TYPE uxStackDepth ) { extern uint32_t __SRAM_segment_start__[]; extern uint32_t __SRAM_segment_end__[]; @@ -1103,7 +1172,7 @@ * which case the stack region parameters will be valid. At all other * times the stack parameters will not be valid and it is assumed that the * stack region has already been configured. */ - if( ulStackDepth > 0 ) + if( uxStackDepth > 0 ) { /* Define the region that allows access to the stack. */ xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = @@ -1114,13 +1183,13 @@ xMPUSettings->xRegion[ 0 ].ulRegionAttribute = ( portMPU_REGION_READ_WRITE ) | ( portMPU_REGION_EXECUTE_NEVER ) | - ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) | + ( prvGetMPURegionSizeSetting( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) ) | ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) | ( portMPU_REGION_ENABLE ); xMPUSettings->xRegionSettings[ 0 ].ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; xMPUSettings->xRegionSettings[ 0 ].ulRegionEndAddress = ( uint32_t ) ( ( uint32_t ) ( pxBottomOfStack ) + - ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1UL ); + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1UL ); xMPUSettings->xRegionSettings[ 0 ].ulRegionPermissions = ( tskMPU_READ_PERMISSION | tskMPU_WRITE_PERMISSION ); } @@ -1175,45 +1244,57 @@ } /*-----------------------------------------------------------*/ -BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, - uint32_t ulBufferLength, - uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ +#if ( configUSE_MPU_WRAPPERS_V1 == 0 ) -{ - uint32_t i, ulBufferStartAddress, ulBufferEndAddress; - BaseType_t xAccessGranted = pdFALSE; - const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, + uint32_t ulBufferLength, + uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ - if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) { - xAccessGranted = pdTRUE; - } - else - { - if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) + uint32_t i, ulBufferStartAddress, ulBufferEndAddress; + BaseType_t xAccessGranted = pdFALSE; + const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ + + if( xSchedulerRunning == pdFALSE ) { - ulBufferStartAddress = ( uint32_t ) pvBuffer; - ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); - - for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ ) + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + { + xAccessGranted = pdTRUE; + } + else + { + if( portADD_UINT32_WILL_OVERFLOW( ( ( uint32_t ) pvBuffer ), ( ulBufferLength - 1UL ) ) == pdFALSE ) { - if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, - xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, - xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && - portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, - xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, - xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && - portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) ) + ulBufferStartAddress = ( uint32_t ) pvBuffer; + ulBufferEndAddress = ( ( ( uint32_t ) pvBuffer ) + ulBufferLength - 1UL ); + + for( i = 0; i < portTOTAL_NUM_REGIONS_IN_TCB; i++ ) { - xAccessGranted = pdTRUE; - break; + if( portIS_ADDRESS_WITHIN_RANGE( ulBufferStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && + portIS_ADDRESS_WITHIN_RANGE( ulBufferEndAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionStartAddress, + xTaskMpuSettings->xRegionSettings[ i ].ulRegionEndAddress ) && + portIS_AUTHORIZED( ulAccessRequested, xTaskMpuSettings->xRegionSettings[ i ].ulRegionPermissions ) ) + { + xAccessGranted = pdTRUE; + break; + } } } } + + return xAccessGranted; } - return xAccessGranted; -} +#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /*-----------------------------------------------------------*/ @@ -1255,7 +1336,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); }
diff --git a/Source/portable/IAR/ARM_CM4_MPU/portasm.s b/Source/portable/IAR/ARM_CM4_MPU/portasm.s index 0da9a4f..523422a 100644 --- a/Source/portable/IAR/ARM_CM4_MPU/portasm.s +++ b/Source/portable/IAR/ARM_CM4_MPU/portasm.s
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -57,6 +57,12 @@ #define configUSE_MPU_WRAPPERS_V1 0 #endif +/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ +#ifndef configENABLE_ERRATA_837070_WORKAROUND + #define configENABLE_ERRATA_837070_WORKAROUND 0 +#endif + /* These must be in sync with portmacro.h. */ #define portSVC_START_SCHEDULER 100 #define portSVC_SYSTEM_CALL_EXIT 103 @@ -113,15 +119,15 @@ str r3, [r0] /* Disable MPU. */ ldr r0, =0xe000ed9c /* Region Base Address register. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ #ifdef configTOTAL_MPU_REGIONS #if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ #endif /* configTOTAL_MPU_REGIONS == 16. */ #endif @@ -233,15 +239,15 @@ str r3, [r0] /* Disable MPU. */ ldr r0, =0xe000ed9c /* Region Base Address register. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */ + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */ #ifdef configTOTAL_MPU_REGIONS #if ( configTOTAL_MPU_REGIONS == 16 ) + ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */ + stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */ ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */ stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */ - ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */ - stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */ #endif /* configTOTAL_MPU_REGIONS == 16. */ #endif
diff --git a/Source/portable/IAR/ARM_CM4_MPU/portmacro.h b/Source/portable/IAR/ARM_CM4_MPU/portmacro.h index cae9bcc..12e35b6 100644 --- a/Source/portable/IAR/ARM_CM4_MPU/portmacro.h +++ b/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -65,7 +65,7 @@ #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) typedef uint16_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffff -#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) typedef uint32_t TickType_t; #define portMAX_DELAY ( TickType_t ) 0xffffffffUL @@ -73,9 +73,14 @@ * not need to be guarded with a critical section. */ #define portTICK_TYPE_IS_ATOMIC 1 #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. + #error "configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width." #endif +/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0 + * and r0p1 cores. */ +#ifndef configENABLE_ERRATA_837070_WORKAROUND + #define configENABLE_ERRATA_837070_WORKAROUND 0 +#endif /*-----------------------------------------------------------*/ /* MPU specific constants. */ @@ -95,7 +100,7 @@ #define portMPU_RASR_TEX_S_C_B_LOCATION ( 16UL ) #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) @@ -177,8 +182,8 @@ #define configTEX_S_C_B_SRAM ( 0x07UL ) #endif -#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL ) -#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL ) +#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 5UL ) +#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 4UL ) #define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL ) #define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL ) #define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL ) @@ -187,8 +192,6 @@ #define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL ) #define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */ -#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" ) - typedef struct MPU_REGION_REGISTERS { uint32_t ulRegionBaseAddress; @@ -205,7 +208,7 @@ #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) #ifndef configSYSTEM_CALL_STACK_SIZE - #error configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2. + #error "configSYSTEM_CALL_STACK_SIZE must be defined to the desired size of the system call stack in words for using MPU wrappers v2." #endif typedef struct SYSTEM_CALL_STACK_INFO @@ -218,14 +221,23 @@ #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ -#define MAX_CONTEXT_SIZE ( 52 ) +/* + * +---------+---------------+-----------------+-----------------+-----+ + * | s16-s31 | s0-s15, FPSCR | CONTROL, r4-r11 | PSP, r0-r3, r12 | | + * | | | EXC_RETURN | LR, PC, xPSR | | + * +---------+---------------+-----------------+-----------------+-----+ + * + * <--------><---------------><----------------><----------------><----> + * 16 17 10 9 1 + */ +#define MAX_CONTEXT_SIZE ( 53 ) /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ -#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) -#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) +#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) +#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) typedef struct MPU_SETTINGS { @@ -256,7 +268,7 @@ /* Scheduler utilities. */ -#define portYIELD() __asm volatile ( " SVC %0 \n"::"i" ( portSVC_YIELD ) : "memory" ) +#define portYIELD() __asm volatile ( " SVC %0 \n" ::"i" ( portSVC_YIELD ) : "memory" ) #define portYIELD_WITHIN_API() \ { \ /* Set a PendSV to request a context switch. */ \ @@ -267,8 +279,20 @@ #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API(); } while( 0 ) -#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD_WITHIN_API(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ @@ -280,7 +304,7 @@ /* Check the configuration. */ #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice." #endif /* Store/clear the ready priorities in a bit map. */ @@ -298,23 +322,23 @@ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); -#if( configENABLE_ERRATA_837070_WORKAROUND == 1 ) - #define portDISABLE_INTERRUPTS() \ - { \ - __disable_interrupt(); \ - __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ - __DSB(); \ - __ISB(); \ - __enable_interrupt(); \ - } +#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) + #define portDISABLE_INTERRUPTS() \ + { \ + __disable_interrupt(); \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + __enable_interrupt(); \ + } #else - #define portDISABLE_INTERRUPTS() \ - { \ - __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ - __DSB(); \ - __ISB(); \ - } -#endif + #define portDISABLE_INTERRUPTS() \ + { \ + __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \ + __DSB(); \ + __ISB(); \ + } +#endif /* if ( configENABLE_ERRATA_837070_WORKAROUND == 1 ) */ #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) #define portENTER_CRITICAL() vPortEnterCritical() @@ -330,7 +354,7 @@ #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ -#ifdef configASSERT +#if ( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -371,24 +395,33 @@ extern BaseType_t xIsPrivileged( void ); extern void vResetPrivilege( void ); +extern void vPortSwitchToUserMode( void ); /** * @brief Checks whether or not the processor is privileged. * * @return 1 if the processor is already privileged, 0 otherwise. */ -#define portIS_PRIVILEGED() xIsPrivileged() +#define portIS_PRIVILEGED() xIsPrivileged() /** * @brief Raise an SVC request to raise privilege. */ -#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); +#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" ); /** * @brief Lowers the privilege level by setting the bit 0 of the CONTROL * register. */ -#define portRESET_PRIVILEGE() vResetPrivilege() +#define portRESET_PRIVILEGE() vResetPrivilege() + +/** + * @brief Make a task unprivileged. + * + * It must be called from privileged tasks only. Calling it from unprivileged + * task will result in a memory protection fault. + */ +#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() /*-----------------------------------------------------------*/ extern BaseType_t xPortIsTaskPrivileged( void ); @@ -398,11 +431,11 @@ * * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. */ -#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() /*-----------------------------------------------------------*/ #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY - #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html" + #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. www.FreeRTOS.org/FreeRTOS-V10.3.x.html" #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY 0 #endif /*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S index ef180bd..68192e4 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -47,12 +47,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskDelayUntil_Unpriv MPU_xTaskDelayUntil_Priv: - pop {r0} b MPU_xTaskDelayUntilImpl MPU_xTaskDelayUntil_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskDelayUntil /*-----------------------------------------------------------*/ @@ -61,12 +60,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskAbortDelay_Unpriv MPU_xTaskAbortDelay_Priv: - pop {r0} b MPU_xTaskAbortDelayImpl MPU_xTaskAbortDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskAbortDelay /*-----------------------------------------------------------*/ @@ -75,12 +73,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskDelay_Unpriv MPU_vTaskDelay_Priv: - pop {r0} b MPU_vTaskDelayImpl MPU_vTaskDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskDelay /*-----------------------------------------------------------*/ @@ -89,12 +86,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskPriorityGet_Unpriv MPU_uxTaskPriorityGet_Priv: - pop {r0} b MPU_uxTaskPriorityGetImpl MPU_uxTaskPriorityGet_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskPriorityGet /*-----------------------------------------------------------*/ @@ -103,12 +99,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_eTaskGetState_Unpriv MPU_eTaskGetState_Priv: - pop {r0} b MPU_eTaskGetStateImpl MPU_eTaskGetState_Unpriv: - pop {r0} svc #SYSTEM_CALL_eTaskGetState /*-----------------------------------------------------------*/ @@ -117,12 +112,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskGetInfo_Unpriv MPU_vTaskGetInfo_Priv: - pop {r0} b MPU_vTaskGetInfoImpl MPU_vTaskGetInfo_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskGetInfo /*-----------------------------------------------------------*/ @@ -131,12 +125,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetIdleTaskHandle_Unpriv MPU_xTaskGetIdleTaskHandle_Priv: - pop {r0} b MPU_xTaskGetIdleTaskHandleImpl MPU_xTaskGetIdleTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetIdleTaskHandle /*-----------------------------------------------------------*/ @@ -145,12 +138,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSuspend_Unpriv MPU_vTaskSuspend_Priv: - pop {r0} b MPU_vTaskSuspendImpl MPU_vTaskSuspend_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSuspend /*-----------------------------------------------------------*/ @@ -159,12 +151,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskResume_Unpriv MPU_vTaskResume_Priv: - pop {r0} b MPU_vTaskResumeImpl MPU_vTaskResume_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskResume /*-----------------------------------------------------------*/ @@ -173,12 +164,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetTickCount_Unpriv MPU_xTaskGetTickCount_Priv: - pop {r0} b MPU_xTaskGetTickCountImpl MPU_xTaskGetTickCount_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetTickCount /*-----------------------------------------------------------*/ @@ -187,40 +177,24 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetNumberOfTasks_Unpriv MPU_uxTaskGetNumberOfTasks_Priv: - pop {r0} b MPU_uxTaskGetNumberOfTasksImpl MPU_uxTaskGetNumberOfTasks_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimeCounter_Unpriv MPU_ulTaskGetRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimeCounter /*-----------------------------------------------------------*/ @@ -229,12 +203,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimePercent_Unpriv MPU_ulTaskGetRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetRunTimePercentImpl MPU_ulTaskGetRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimePercent /*-----------------------------------------------------------*/ @@ -243,12 +216,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimePercent_Unpriv MPU_ulTaskGetIdleRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimePercentImpl MPU_ulTaskGetIdleRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent /*-----------------------------------------------------------*/ @@ -257,12 +229,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv MPU_ulTaskGetIdleRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimeCounterImpl MPU_ulTaskGetIdleRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter /*-----------------------------------------------------------*/ @@ -271,12 +242,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetApplicationTaskTag_Unpriv MPU_vTaskSetApplicationTaskTag_Priv: - pop {r0} b MPU_vTaskSetApplicationTaskTagImpl MPU_vTaskSetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -285,12 +255,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetApplicationTaskTag_Unpriv MPU_xTaskGetApplicationTaskTag_Priv: - pop {r0} b MPU_xTaskGetApplicationTaskTagImpl MPU_xTaskGetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -299,12 +268,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv MPU_vTaskSetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_vTaskSetThreadLocalStoragePointerImpl MPU_vTaskSetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -313,12 +281,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv MPU_pvTaskGetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_pvTaskGetThreadLocalStoragePointerImpl MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -327,12 +294,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetSystemState_Unpriv MPU_uxTaskGetSystemState_Priv: - pop {r0} b MPU_uxTaskGetSystemStateImpl MPU_uxTaskGetSystemState_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetSystemState /*-----------------------------------------------------------*/ @@ -341,12 +307,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark_Unpriv MPU_uxTaskGetStackHighWaterMark_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMarkImpl MPU_uxTaskGetStackHighWaterMark_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark /*-----------------------------------------------------------*/ @@ -355,12 +320,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark2_Unpriv MPU_uxTaskGetStackHighWaterMark2_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMark2Impl MPU_uxTaskGetStackHighWaterMark2_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 /*-----------------------------------------------------------*/ @@ -369,12 +333,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetCurrentTaskHandle_Unpriv MPU_xTaskGetCurrentTaskHandle_Priv: - pop {r0} b MPU_xTaskGetCurrentTaskHandleImpl MPU_xTaskGetCurrentTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle /*-----------------------------------------------------------*/ @@ -383,12 +346,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetSchedulerState_Unpriv MPU_xTaskGetSchedulerState_Priv: - pop {r0} b MPU_xTaskGetSchedulerStateImpl MPU_xTaskGetSchedulerState_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetSchedulerState /*-----------------------------------------------------------*/ @@ -397,12 +359,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetTimeOutState_Unpriv MPU_vTaskSetTimeOutState_Priv: - pop {r0} b MPU_vTaskSetTimeOutStateImpl MPU_vTaskSetTimeOutState_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetTimeOutState /*-----------------------------------------------------------*/ @@ -411,12 +372,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskCheckForTimeOut_Unpriv MPU_xTaskCheckForTimeOut_Priv: - pop {r0} b MPU_xTaskCheckForTimeOutImpl MPU_xTaskCheckForTimeOut_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskCheckForTimeOut /*-----------------------------------------------------------*/ @@ -425,12 +385,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotify_Unpriv MPU_xTaskGenericNotify_Priv: - pop {r0} b MPU_xTaskGenericNotifyImpl MPU_xTaskGenericNotify_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotify /*-----------------------------------------------------------*/ @@ -439,12 +398,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyWait_Unpriv MPU_xTaskGenericNotifyWait_Priv: - pop {r0} b MPU_xTaskGenericNotifyWaitImpl MPU_xTaskGenericNotifyWait_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyWait /*-----------------------------------------------------------*/ @@ -453,12 +411,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyTake_Unpriv MPU_ulTaskGenericNotifyTake_Priv: - pop {r0} b MPU_ulTaskGenericNotifyTakeImpl MPU_ulTaskGenericNotifyTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyTake /*-----------------------------------------------------------*/ @@ -467,12 +424,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyStateClear_Unpriv MPU_xTaskGenericNotifyStateClear_Priv: - pop {r0} b MPU_xTaskGenericNotifyStateClearImpl MPU_xTaskGenericNotifyStateClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyStateClear /*-----------------------------------------------------------*/ @@ -481,12 +437,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyValueClear_Unpriv MPU_ulTaskGenericNotifyValueClear_Priv: - pop {r0} b MPU_ulTaskGenericNotifyValueClearImpl MPU_ulTaskGenericNotifyValueClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear /*-----------------------------------------------------------*/ @@ -495,12 +450,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGenericSend_Unpriv MPU_xQueueGenericSend_Priv: - pop {r0} b MPU_xQueueGenericSendImpl MPU_xQueueGenericSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGenericSend /*-----------------------------------------------------------*/ @@ -509,12 +463,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueMessagesWaiting_Unpriv MPU_uxQueueMessagesWaiting_Priv: - pop {r0} b MPU_uxQueueMessagesWaitingImpl MPU_uxQueueMessagesWaiting_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueMessagesWaiting /*-----------------------------------------------------------*/ @@ -523,12 +476,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueSpacesAvailable_Unpriv MPU_uxQueueSpacesAvailable_Priv: - pop {r0} b MPU_uxQueueSpacesAvailableImpl MPU_uxQueueSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueSpacesAvailable /*-----------------------------------------------------------*/ @@ -537,12 +489,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueReceive_Unpriv MPU_xQueueReceive_Priv: - pop {r0} b MPU_xQueueReceiveImpl MPU_xQueueReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueReceive /*-----------------------------------------------------------*/ @@ -551,12 +502,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueuePeek_Unpriv MPU_xQueuePeek_Priv: - pop {r0} b MPU_xQueuePeekImpl MPU_xQueuePeek_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueuePeek /*-----------------------------------------------------------*/ @@ -565,12 +515,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSemaphoreTake_Unpriv MPU_xQueueSemaphoreTake_Priv: - pop {r0} b MPU_xQueueSemaphoreTakeImpl MPU_xQueueSemaphoreTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSemaphoreTake /*-----------------------------------------------------------*/ @@ -579,12 +528,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGetMutexHolder_Unpriv MPU_xQueueGetMutexHolder_Priv: - pop {r0} b MPU_xQueueGetMutexHolderImpl MPU_xQueueGetMutexHolder_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGetMutexHolder /*-----------------------------------------------------------*/ @@ -593,12 +541,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueTakeMutexRecursive_Unpriv MPU_xQueueTakeMutexRecursive_Priv: - pop {r0} b MPU_xQueueTakeMutexRecursiveImpl MPU_xQueueTakeMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueTakeMutexRecursive /*-----------------------------------------------------------*/ @@ -607,12 +554,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGiveMutexRecursive_Unpriv MPU_xQueueGiveMutexRecursive_Priv: - pop {r0} b MPU_xQueueGiveMutexRecursiveImpl MPU_xQueueGiveMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGiveMutexRecursive /*-----------------------------------------------------------*/ @@ -621,12 +567,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSelectFromSet_Unpriv MPU_xQueueSelectFromSet_Priv: - pop {r0} b MPU_xQueueSelectFromSetImpl MPU_xQueueSelectFromSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSelectFromSet /*-----------------------------------------------------------*/ @@ -635,12 +580,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueAddToSet_Unpriv MPU_xQueueAddToSet_Priv: - pop {r0} b MPU_xQueueAddToSetImpl MPU_xQueueAddToSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueAddToSet /*-----------------------------------------------------------*/ @@ -649,12 +593,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueAddToRegistry_Unpriv MPU_vQueueAddToRegistry_Priv: - pop {r0} b MPU_vQueueAddToRegistryImpl MPU_vQueueAddToRegistry_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueAddToRegistry /*-----------------------------------------------------------*/ @@ -663,12 +606,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueUnregisterQueue_Unpriv MPU_vQueueUnregisterQueue_Priv: - pop {r0} b MPU_vQueueUnregisterQueueImpl MPU_vQueueUnregisterQueue_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueUnregisterQueue /*-----------------------------------------------------------*/ @@ -677,12 +619,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcQueueGetName_Unpriv MPU_pcQueueGetName_Priv: - pop {r0} b MPU_pcQueueGetNameImpl MPU_pcQueueGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcQueueGetName /*-----------------------------------------------------------*/ @@ -691,12 +632,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTimerGetTimerID_Unpriv MPU_pvTimerGetTimerID_Priv: - pop {r0} b MPU_pvTimerGetTimerIDImpl MPU_pvTimerGetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTimerGetTimerID /*-----------------------------------------------------------*/ @@ -705,12 +645,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetTimerID_Unpriv MPU_vTimerSetTimerID_Priv: - pop {r0} b MPU_vTimerSetTimerIDImpl MPU_vTimerSetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetTimerID /*-----------------------------------------------------------*/ @@ -719,12 +658,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerIsTimerActive_Unpriv MPU_xTimerIsTimerActive_Priv: - pop {r0} b MPU_xTimerIsTimerActiveImpl MPU_xTimerIsTimerActive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerIsTimerActive /*-----------------------------------------------------------*/ @@ -733,33 +671,25 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv MPU_xTimerGetTimerDaemonTaskHandle_Priv: - pop {r0} b MPU_xTimerGetTimerDaemonTaskHandleImpl MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: - pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: - pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -767,12 +697,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcTimerGetName_Unpriv MPU_pcTimerGetName_Priv: - pop {r0} b MPU_pcTimerGetNameImpl MPU_pcTimerGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcTimerGetName /*-----------------------------------------------------------*/ @@ -781,12 +710,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetReloadMode_Unpriv MPU_vTimerSetReloadMode_Priv: - pop {r0} b MPU_vTimerSetReloadModeImpl MPU_vTimerSetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetReloadMode /*-----------------------------------------------------------*/ @@ -795,12 +723,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetReloadMode_Unpriv MPU_xTimerGetReloadMode_Priv: - pop {r0} b MPU_xTimerGetReloadModeImpl MPU_xTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -809,12 +736,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTimerGetReloadMode_Unpriv MPU_uxTimerGetReloadMode_Priv: - pop {r0} b MPU_uxTimerGetReloadModeImpl MPU_uxTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -823,12 +749,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetPeriod_Unpriv MPU_xTimerGetPeriod_Priv: - pop {r0} b MPU_xTimerGetPeriodImpl MPU_xTimerGetPeriod_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetPeriod /*-----------------------------------------------------------*/ @@ -837,12 +762,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetExpiryTime_Unpriv MPU_xTimerGetExpiryTime_Priv: - pop {r0} b MPU_xTimerGetExpiryTimeImpl MPU_xTimerGetExpiryTime_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetExpiryTime /*-----------------------------------------------------------*/ @@ -851,12 +775,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupWaitBits_Unpriv MPU_xEventGroupWaitBits_Priv: - pop {r0} b MPU_xEventGroupWaitBitsImpl MPU_xEventGroupWaitBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupWaitBits /*-----------------------------------------------------------*/ @@ -865,12 +788,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupClearBits_Unpriv MPU_xEventGroupClearBits_Priv: - pop {r0} b MPU_xEventGroupClearBitsImpl MPU_xEventGroupClearBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupClearBits /*-----------------------------------------------------------*/ @@ -879,12 +801,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSetBits_Unpriv MPU_xEventGroupSetBits_Priv: - pop {r0} b MPU_xEventGroupSetBitsImpl MPU_xEventGroupSetBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSetBits /*-----------------------------------------------------------*/ @@ -893,12 +814,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSync_Unpriv MPU_xEventGroupSync_Priv: - pop {r0} b MPU_xEventGroupSyncImpl MPU_xEventGroupSync_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSync /*-----------------------------------------------------------*/ @@ -907,12 +827,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxEventGroupGetNumber_Unpriv MPU_uxEventGroupGetNumber_Priv: - pop {r0} b MPU_uxEventGroupGetNumberImpl MPU_uxEventGroupGetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxEventGroupGetNumber /*-----------------------------------------------------------*/ @@ -921,12 +840,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vEventGroupSetNumber_Unpriv MPU_vEventGroupSetNumber_Priv: - pop {r0} b MPU_vEventGroupSetNumberImpl MPU_vEventGroupSetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_vEventGroupSetNumber /*-----------------------------------------------------------*/ @@ -935,12 +853,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSend_Unpriv MPU_xStreamBufferSend_Priv: - pop {r0} b MPU_xStreamBufferSendImpl MPU_xStreamBufferSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSend /*-----------------------------------------------------------*/ @@ -949,12 +866,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferReceive_Unpriv MPU_xStreamBufferReceive_Priv: - pop {r0} b MPU_xStreamBufferReceiveImpl MPU_xStreamBufferReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferReceive /*-----------------------------------------------------------*/ @@ -963,12 +879,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsFull_Unpriv MPU_xStreamBufferIsFull_Priv: - pop {r0} b MPU_xStreamBufferIsFullImpl MPU_xStreamBufferIsFull_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsFull /*-----------------------------------------------------------*/ @@ -977,12 +892,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsEmpty_Unpriv MPU_xStreamBufferIsEmpty_Priv: - pop {r0} b MPU_xStreamBufferIsEmptyImpl MPU_xStreamBufferIsEmpty_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsEmpty /*-----------------------------------------------------------*/ @@ -991,12 +905,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSpacesAvailable_Unpriv MPU_xStreamBufferSpacesAvailable_Priv: - pop {r0} b MPU_xStreamBufferSpacesAvailableImpl MPU_xStreamBufferSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSpacesAvailable /*-----------------------------------------------------------*/ @@ -1005,12 +918,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferBytesAvailable_Unpriv MPU_xStreamBufferBytesAvailable_Priv: - pop {r0} b MPU_xStreamBufferBytesAvailableImpl MPU_xStreamBufferBytesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferBytesAvailable /*-----------------------------------------------------------*/ @@ -1019,12 +931,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSetTriggerLevel_Unpriv MPU_xStreamBufferSetTriggerLevel_Priv: - pop {r0} b MPU_xStreamBufferSetTriggerLevelImpl MPU_xStreamBufferSetTriggerLevel_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel /*-----------------------------------------------------------*/ @@ -1033,12 +944,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv MPU_xStreamBufferNextMessageLengthBytes_Priv: - pop {r0} b MPU_xStreamBufferNextMessageLengthBytesImpl MPU_xStreamBufferNextMessageLengthBytes_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes /*-----------------------------------------------------------*/ @@ -1089,10 +999,6 @@ MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1151,9 @@ MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/port.c b/Source/portable/IAR/ARM_CM55/non_secure/port.c index 9712ac3..f16a343 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM55/non_secure/port.c
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -54,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 @@ -68,6 +70,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,8 +109,17 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) /*-----------------------------------------------------------*/ /** @@ -111,8 +138,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,72 +161,79 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + +/* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ /* Enable privileged access to unmapped region. */ #define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) @@ -343,6 +377,20 @@ * any secure calls. */ #define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ /** @@ -351,7 +399,7 @@ */ static void prvTaskExitError( void ); -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief Extract MPU region's access permissions from the Region Base Address @@ -362,7 +410,7 @@ * @return uint32_t Access permissions. */ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; -#endif /* configENABLE_MPU */ +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ #if ( configENABLE_MPU == 1 ) @@ -380,6 +428,26 @@ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_FPU */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + +/** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + /** * @brief Setup the timer to generate the tick interrupts. * @@ -448,13 +516,13 @@ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,24 +530,24 @@ #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ -#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief This variable is set to pdTRUE when the scheduler is started. */ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; -#endif +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /** * @brief Each task maintains its own interrupt status in the critical nesting @@ -501,13 +569,13 @@ * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -531,6 +599,7 @@ /*-----------------------------------------------------------*/ #if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) { uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; @@ -746,6 +815,7 @@ __asm volatile ( "cpsie i" ::: "memory" ); } } + #endif /* configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ @@ -760,8 +830,15 @@ } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -795,7 +872,8 @@ } /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ { uint32_t ulAccessPermissions = 0; @@ -812,13 +890,16 @@ return ulAccessPermissions; } -#endif /* configENABLE_MPU */ + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -903,10 +984,12 @@ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ #if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ { #if ( configENABLE_TRUSTZONE == 1 ) @@ -928,6 +1011,7 @@ * LSPEN = 1 ==> Enable lazy context save of FP state. */ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); } + #endif /* configENABLE_FPU */ /*-----------------------------------------------------------*/ @@ -972,13 +1056,19 @@ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1078,7 @@ { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1174,24 @@ vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1116,6 +1213,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1154,12 +1252,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1268,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1190,11 +1287,19 @@ /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; @@ -1224,14 +1329,13 @@ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1259,6 +1363,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -1293,12 +1398,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1414,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1436,11 @@ /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1458,13 @@ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1392,6 +1499,7 @@ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ { uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ ulIndex++; @@ -1410,21 +1518,21 @@ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,20 +1543,30 @@ #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ ulIndex++; } else { xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1469,6 +1587,20 @@ } #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + return &( xMPUSettings->ulContext[ ulIndex ] ); } @@ -1483,7 +1615,7 @@ * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1637,7 @@ } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1672,7 @@ pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1551,6 +1683,20 @@ } #endif /* portPRELOAD_REGISTERS */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + return pxTopOfStack; } @@ -1559,22 +1705,52 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) { - volatile uint32_t ulOriginalPriority; + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1769,10 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1810,22 @@ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ #if ( configENABLE_MPU == 1 ) { @@ -1660,11 +1841,11 @@ /* Initialize the critical nesting count ready for the first task. */ ulCriticalNesting = 0; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { xSchedulerRunning = pdTRUE; } - #endif + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /* Start the first task. */ vStartFirstTask(); @@ -1692,15 +1873,17 @@ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, - uint32_t ulStackDepth ) + configSTACK_DEPTH_TYPE uxStackDepth ) { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1719,10 +1902,10 @@ * which case the stack region parameters will be valid. At all other * times the stack parameters will not be valid and it is assumed that * the stack region has already been configured. */ - if( ulStackDepth > 0 ) + if( uxStackDepth > 0 ) { ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; - ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; /* If the stack is within the privileged SRAM, do not protect it * using a separate MPU region. This is needed because privileged @@ -1790,6 +1973,16 @@ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | ( portMPU_RLAR_REGION_ENABLE ); + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + /* Normal memory/ Device memory. */ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) { @@ -1812,10 +2005,12 @@ lIndex++; } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, uint32_t ulBufferLength, uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ @@ -1825,7 +2020,15 @@ BaseType_t xAccessGranted = pdFALSE; const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ - if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) { xAccessGranted = pdTRUE; } @@ -1860,7 +2063,8 @@ return xAccessGranted; } -#endif /* configENABLE_MPU */ + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /*-----------------------------------------------------------*/ BaseType_t xPortIsInsideInterrupt( void ) @@ -1886,7 +2090,7 @@ } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1924,7 +2128,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); } @@ -1944,7 +2148,7 @@ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) @@ -2041,3 +2245,38 @@ #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portasm.h b/Source/portable/IAR/ARM_CM55/non_secure/portasm.h index f64ceb5..53b4b6e 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM55/non_secure/portasm.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -52,7 +52,7 @@ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portasm.s b/Source/portable/IAR/ARM_CM55/non_secure/portasm.s index 5309103..b5c91e5 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM55/non_secure/portasm.s
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -150,6 +152,14 @@ ldr r2, [r1] /* r2 = Location of saved context in TCB. */ restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ msr psp, r3 msr psplim, r4 @@ -175,12 +185,22 @@ ldr r3, [r2] /* Read pxCurrentTCB. */ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ ldr r4, =xSecureContext str r1, [r4] /* Set xSecureContext to this task's value for the same. */ msr psplim, r2 /* Set this task's PSPLIM value. */ - movs r1, #2 /* r1 = 2. */ - msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ adds r0, #32 /* Discard everything up to r0. */ msr psp, r0 /* This is now the new top of stack to use in the task. */ isb @@ -213,7 +233,7 @@ ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -268,11 +288,20 @@ mrs r4, psplim /* r4 = PSPLIM. */ mrs r5, control /* r5 = CONTROL. */ stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ - str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_1 + mrs r5, PAC_KEY_P_2 + mrs r6, PAC_KEY_P_3 + stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -326,6 +355,14 @@ ldr r2, [r1] /* r2 = Location of saved context in TCB. */ restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ msr psp, r3 msr psplim, r4 @@ -371,76 +408,86 @@ mrs r2, psp /* Read PSP in r2. */ cbz r0, save_ns_context /* No secure context to save. */ - push {r0-r2, r14} - bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ - pop {r0-r3} /* LR is now in r3. */ - mov lr, r3 /* LR = r3. */ - lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ - bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ - - ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ - ldr r1, [r3] /* Read pxCurrentTCB. */ - subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ - str r2, [r1] /* Save the new top of stack in TCB. */ - mrs r1, psplim /* r1 = PSPLIM. */ - mov r3, lr /* r3 = LR/EXC_RETURN. */ - stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ - b select_next_task + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} save_ns_context: - ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ - ldr r1, [r3] /* Read pxCurrentTCB. */ + mov r3, lr /* r3 = LR. */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + + save_general_regs: #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ it eq vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ #endif /* configENABLE_FPU || configENABLE_MVE */ - subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ - str r2, [r1] /* Save the new top of stack in TCB. */ - adds r2, r2, #12 /* r2 = r2 + 12. */ - stm r2, {r4-r11} /* Store the registers that are not saved automatically. */ - mrs r1, psplim /* r1 = PSPLIM. */ - mov r3, lr /* r3 = LR/EXC_RETURN. */ - subs r2, r2, #12 /* r2 = r2 - 12. */ - stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ + stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_1 + mrs r6, PAC_KEY_P_0 + stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the new top of stack in TCB. */ select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext mov r0, #0 /* r0 = 0. */ msr basepri, r0 /* Enable interrupts. */ + restore_context: ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r3] /* Read pxCurrentTCB. */ ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ - ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ - msr psplim, r1 /* Restore the PSPLIM register value for the task. */ - mov lr, r4 /* LR = r4. */ + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_1, r5 + msr PAC_KEY_P_0, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmia r2!, {r0, r3, lr} /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + msr psplim, r3 /* Restore the PSPLIM register value for the task. */ ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ str r0, [r3] /* Restore the task's xSecureContext. */ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ - ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ - ldr r1, [r3] /* Read pxCurrentTCB. */ - push {r2, r4} + + restore_s_context: + push {r1-r3, lr} bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ - pop {r2, r4} - mov lr, r4 /* LR = r4. */ - lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ - bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ - msr psp, r2 /* Remember the new top of stack for the task. */ - bx lr + pop {r1-r3, lr} restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ it eq vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: msr psp, r2 /* Remember the new top of stack for the task. */ bx lr
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h index 15cb65e..0526455 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM55/non_secure/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -53,9 +53,10 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M55" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -65,8 +66,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h index 6f666da..2dfac6a 100644 --- a/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM55/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -117,7 +119,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -125,6 +127,18 @@ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; #endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ /*-----------------------------------------------------------*/ /** @@ -137,7 +151,7 @@ #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) @@ -193,8 +207,8 @@ */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -223,7 +237,20 @@ */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +-----------+---------------+----------+-----------------+------------------------------+-----+ @@ -232,11 +259,24 @@ * +-----------+---------------+----------+-----------------+------------------------------+-----+ * * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 + * 16 17 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 54 + #define MAX_CONTEXT_SIZE 55 - #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ /* * +-----------+---------------+----------+-----------------+----------------------+-----+ @@ -245,15 +285,28 @@ * +-----------+---------------+----------+-----------------+----------------------+-----+ * * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 + * 16 17 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 53 + #define MAX_CONTEXT_SIZE 54 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +----------+-----------------+------------------------------+-----+ @@ -264,7 +317,20 @@ * <---------><----------------><------------------------------><----> * 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 22 + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ @@ -277,17 +343,17 @@ * <---------><----------------><----------------------><----> * 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 21 + #define MAX_CONTEXT_SIZE 21 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) -/* Size of an Access Control List (ACL) entry in bits. */ + /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) typedef struct MPU_SETTINGS @@ -312,8 +378,8 @@ * @brief Validate priority of ISRs that are allowed to call FreeRTOS * system calls. */ -#ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +399,29 @@ /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +507,12 @@ extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +523,56 @@ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus }
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_context.c b/Source/portable/IAR/ARM_CM55/secure/secure_context.c index e37dd96..62bcfa1 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_context.c +++ b/Source/portable/IAR/ARM_CM55/secure/secure_context.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -207,7 +207,7 @@ * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ @@ -219,16 +219,16 @@ if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } #else /* configENABLE_MPU */ - { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; - } + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex;
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_context.h b/Source/portable/IAR/ARM_CM55/secure/secure_context.h index 2220ea6..8b93857 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_context.h +++ b/Source/portable/IAR/ARM_CM55/secure/secure_context.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s index 0da3e0f..5cc070e 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s +++ b/Source/portable/IAR/ARM_CM55/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_heap.c b/Source/portable/IAR/ARM_CM55/secure/secure_heap.c index 19f7c23..b0e83b4 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_heap.c +++ b/Source/portable/IAR/ARM_CM55/secure/secure_heap.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -29,6 +29,9 @@ /* Standard includes. */ #include <stdint.h> +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + /* Secure context heap includes. */ #include "secure_heap.h" @@ -62,6 +65,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +142,6 @@ static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +186,6 @@ /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -229,7 +237,7 @@ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; } - /* If the block being inserted plugged a gab, so was merged with the block + /* If the block being inserted plugged a gap, so was merged with the block * before and the block after, then it's pxNextFreeBlock pointer will have * already been set, and should not be set here as that would make it point * to itself. */ @@ -250,6 +258,8 @@ BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +272,29 @@ mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +303,20 @@ } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +359,8 @@ pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -352,9 +378,11 @@ mtCOVERAGE_TEST_MARKER(); } + xAllocatedBlockSize = pxBlock->xBlockSize; + /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -372,20 +400,23 @@ mtCOVERAGE_TEST_MARKER(); } - traceMALLOC( pvReturn, xWantedSize ); + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +439,16 @@ pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); {
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_heap.h b/Source/portable/IAR/ARM_CM55/secure/secure_heap.h index 75c9cb0..61a96da 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_heap.h +++ b/Source/portable/IAR/ARM_CM55/secure/secure_heap.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_init.c b/Source/portable/IAR/ARM_CM55/secure/secure_init.c index f93bfce..f7f7e67 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_init.c +++ b/Source/portable/IAR/ARM_CM55/secure/secure_init.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -93,7 +93,7 @@ * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_init.h b/Source/portable/IAR/ARM_CM55/secure/secure_init.h index e6c9da0..46ffbd9 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_init.h +++ b/Source/portable/IAR/ARM_CM55/secure/secure_init.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h index d7ac583..34494e1 100644 --- a/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h +++ b/Source/portable/IAR/ARM_CM55/secure/secure_port_macros.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S index ef180bd..68192e4 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -47,12 +47,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskDelayUntil_Unpriv MPU_xTaskDelayUntil_Priv: - pop {r0} b MPU_xTaskDelayUntilImpl MPU_xTaskDelayUntil_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskDelayUntil /*-----------------------------------------------------------*/ @@ -61,12 +60,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskAbortDelay_Unpriv MPU_xTaskAbortDelay_Priv: - pop {r0} b MPU_xTaskAbortDelayImpl MPU_xTaskAbortDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskAbortDelay /*-----------------------------------------------------------*/ @@ -75,12 +73,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskDelay_Unpriv MPU_vTaskDelay_Priv: - pop {r0} b MPU_vTaskDelayImpl MPU_vTaskDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskDelay /*-----------------------------------------------------------*/ @@ -89,12 +86,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskPriorityGet_Unpriv MPU_uxTaskPriorityGet_Priv: - pop {r0} b MPU_uxTaskPriorityGetImpl MPU_uxTaskPriorityGet_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskPriorityGet /*-----------------------------------------------------------*/ @@ -103,12 +99,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_eTaskGetState_Unpriv MPU_eTaskGetState_Priv: - pop {r0} b MPU_eTaskGetStateImpl MPU_eTaskGetState_Unpriv: - pop {r0} svc #SYSTEM_CALL_eTaskGetState /*-----------------------------------------------------------*/ @@ -117,12 +112,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskGetInfo_Unpriv MPU_vTaskGetInfo_Priv: - pop {r0} b MPU_vTaskGetInfoImpl MPU_vTaskGetInfo_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskGetInfo /*-----------------------------------------------------------*/ @@ -131,12 +125,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetIdleTaskHandle_Unpriv MPU_xTaskGetIdleTaskHandle_Priv: - pop {r0} b MPU_xTaskGetIdleTaskHandleImpl MPU_xTaskGetIdleTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetIdleTaskHandle /*-----------------------------------------------------------*/ @@ -145,12 +138,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSuspend_Unpriv MPU_vTaskSuspend_Priv: - pop {r0} b MPU_vTaskSuspendImpl MPU_vTaskSuspend_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSuspend /*-----------------------------------------------------------*/ @@ -159,12 +151,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskResume_Unpriv MPU_vTaskResume_Priv: - pop {r0} b MPU_vTaskResumeImpl MPU_vTaskResume_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskResume /*-----------------------------------------------------------*/ @@ -173,12 +164,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetTickCount_Unpriv MPU_xTaskGetTickCount_Priv: - pop {r0} b MPU_xTaskGetTickCountImpl MPU_xTaskGetTickCount_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetTickCount /*-----------------------------------------------------------*/ @@ -187,40 +177,24 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetNumberOfTasks_Unpriv MPU_uxTaskGetNumberOfTasks_Priv: - pop {r0} b MPU_uxTaskGetNumberOfTasksImpl MPU_uxTaskGetNumberOfTasks_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimeCounter_Unpriv MPU_ulTaskGetRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimeCounter /*-----------------------------------------------------------*/ @@ -229,12 +203,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimePercent_Unpriv MPU_ulTaskGetRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetRunTimePercentImpl MPU_ulTaskGetRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimePercent /*-----------------------------------------------------------*/ @@ -243,12 +216,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimePercent_Unpriv MPU_ulTaskGetIdleRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimePercentImpl MPU_ulTaskGetIdleRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent /*-----------------------------------------------------------*/ @@ -257,12 +229,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv MPU_ulTaskGetIdleRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimeCounterImpl MPU_ulTaskGetIdleRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter /*-----------------------------------------------------------*/ @@ -271,12 +242,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetApplicationTaskTag_Unpriv MPU_vTaskSetApplicationTaskTag_Priv: - pop {r0} b MPU_vTaskSetApplicationTaskTagImpl MPU_vTaskSetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -285,12 +255,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetApplicationTaskTag_Unpriv MPU_xTaskGetApplicationTaskTag_Priv: - pop {r0} b MPU_xTaskGetApplicationTaskTagImpl MPU_xTaskGetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -299,12 +268,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv MPU_vTaskSetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_vTaskSetThreadLocalStoragePointerImpl MPU_vTaskSetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -313,12 +281,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv MPU_pvTaskGetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_pvTaskGetThreadLocalStoragePointerImpl MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -327,12 +294,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetSystemState_Unpriv MPU_uxTaskGetSystemState_Priv: - pop {r0} b MPU_uxTaskGetSystemStateImpl MPU_uxTaskGetSystemState_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetSystemState /*-----------------------------------------------------------*/ @@ -341,12 +307,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark_Unpriv MPU_uxTaskGetStackHighWaterMark_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMarkImpl MPU_uxTaskGetStackHighWaterMark_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark /*-----------------------------------------------------------*/ @@ -355,12 +320,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark2_Unpriv MPU_uxTaskGetStackHighWaterMark2_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMark2Impl MPU_uxTaskGetStackHighWaterMark2_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 /*-----------------------------------------------------------*/ @@ -369,12 +333,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetCurrentTaskHandle_Unpriv MPU_xTaskGetCurrentTaskHandle_Priv: - pop {r0} b MPU_xTaskGetCurrentTaskHandleImpl MPU_xTaskGetCurrentTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle /*-----------------------------------------------------------*/ @@ -383,12 +346,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetSchedulerState_Unpriv MPU_xTaskGetSchedulerState_Priv: - pop {r0} b MPU_xTaskGetSchedulerStateImpl MPU_xTaskGetSchedulerState_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetSchedulerState /*-----------------------------------------------------------*/ @@ -397,12 +359,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetTimeOutState_Unpriv MPU_vTaskSetTimeOutState_Priv: - pop {r0} b MPU_vTaskSetTimeOutStateImpl MPU_vTaskSetTimeOutState_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetTimeOutState /*-----------------------------------------------------------*/ @@ -411,12 +372,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskCheckForTimeOut_Unpriv MPU_xTaskCheckForTimeOut_Priv: - pop {r0} b MPU_xTaskCheckForTimeOutImpl MPU_xTaskCheckForTimeOut_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskCheckForTimeOut /*-----------------------------------------------------------*/ @@ -425,12 +385,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotify_Unpriv MPU_xTaskGenericNotify_Priv: - pop {r0} b MPU_xTaskGenericNotifyImpl MPU_xTaskGenericNotify_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotify /*-----------------------------------------------------------*/ @@ -439,12 +398,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyWait_Unpriv MPU_xTaskGenericNotifyWait_Priv: - pop {r0} b MPU_xTaskGenericNotifyWaitImpl MPU_xTaskGenericNotifyWait_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyWait /*-----------------------------------------------------------*/ @@ -453,12 +411,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyTake_Unpriv MPU_ulTaskGenericNotifyTake_Priv: - pop {r0} b MPU_ulTaskGenericNotifyTakeImpl MPU_ulTaskGenericNotifyTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyTake /*-----------------------------------------------------------*/ @@ -467,12 +424,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyStateClear_Unpriv MPU_xTaskGenericNotifyStateClear_Priv: - pop {r0} b MPU_xTaskGenericNotifyStateClearImpl MPU_xTaskGenericNotifyStateClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyStateClear /*-----------------------------------------------------------*/ @@ -481,12 +437,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyValueClear_Unpriv MPU_ulTaskGenericNotifyValueClear_Priv: - pop {r0} b MPU_ulTaskGenericNotifyValueClearImpl MPU_ulTaskGenericNotifyValueClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear /*-----------------------------------------------------------*/ @@ -495,12 +450,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGenericSend_Unpriv MPU_xQueueGenericSend_Priv: - pop {r0} b MPU_xQueueGenericSendImpl MPU_xQueueGenericSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGenericSend /*-----------------------------------------------------------*/ @@ -509,12 +463,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueMessagesWaiting_Unpriv MPU_uxQueueMessagesWaiting_Priv: - pop {r0} b MPU_uxQueueMessagesWaitingImpl MPU_uxQueueMessagesWaiting_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueMessagesWaiting /*-----------------------------------------------------------*/ @@ -523,12 +476,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueSpacesAvailable_Unpriv MPU_uxQueueSpacesAvailable_Priv: - pop {r0} b MPU_uxQueueSpacesAvailableImpl MPU_uxQueueSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueSpacesAvailable /*-----------------------------------------------------------*/ @@ -537,12 +489,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueReceive_Unpriv MPU_xQueueReceive_Priv: - pop {r0} b MPU_xQueueReceiveImpl MPU_xQueueReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueReceive /*-----------------------------------------------------------*/ @@ -551,12 +502,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueuePeek_Unpriv MPU_xQueuePeek_Priv: - pop {r0} b MPU_xQueuePeekImpl MPU_xQueuePeek_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueuePeek /*-----------------------------------------------------------*/ @@ -565,12 +515,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSemaphoreTake_Unpriv MPU_xQueueSemaphoreTake_Priv: - pop {r0} b MPU_xQueueSemaphoreTakeImpl MPU_xQueueSemaphoreTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSemaphoreTake /*-----------------------------------------------------------*/ @@ -579,12 +528,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGetMutexHolder_Unpriv MPU_xQueueGetMutexHolder_Priv: - pop {r0} b MPU_xQueueGetMutexHolderImpl MPU_xQueueGetMutexHolder_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGetMutexHolder /*-----------------------------------------------------------*/ @@ -593,12 +541,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueTakeMutexRecursive_Unpriv MPU_xQueueTakeMutexRecursive_Priv: - pop {r0} b MPU_xQueueTakeMutexRecursiveImpl MPU_xQueueTakeMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueTakeMutexRecursive /*-----------------------------------------------------------*/ @@ -607,12 +554,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGiveMutexRecursive_Unpriv MPU_xQueueGiveMutexRecursive_Priv: - pop {r0} b MPU_xQueueGiveMutexRecursiveImpl MPU_xQueueGiveMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGiveMutexRecursive /*-----------------------------------------------------------*/ @@ -621,12 +567,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSelectFromSet_Unpriv MPU_xQueueSelectFromSet_Priv: - pop {r0} b MPU_xQueueSelectFromSetImpl MPU_xQueueSelectFromSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSelectFromSet /*-----------------------------------------------------------*/ @@ -635,12 +580,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueAddToSet_Unpriv MPU_xQueueAddToSet_Priv: - pop {r0} b MPU_xQueueAddToSetImpl MPU_xQueueAddToSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueAddToSet /*-----------------------------------------------------------*/ @@ -649,12 +593,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueAddToRegistry_Unpriv MPU_vQueueAddToRegistry_Priv: - pop {r0} b MPU_vQueueAddToRegistryImpl MPU_vQueueAddToRegistry_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueAddToRegistry /*-----------------------------------------------------------*/ @@ -663,12 +606,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueUnregisterQueue_Unpriv MPU_vQueueUnregisterQueue_Priv: - pop {r0} b MPU_vQueueUnregisterQueueImpl MPU_vQueueUnregisterQueue_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueUnregisterQueue /*-----------------------------------------------------------*/ @@ -677,12 +619,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcQueueGetName_Unpriv MPU_pcQueueGetName_Priv: - pop {r0} b MPU_pcQueueGetNameImpl MPU_pcQueueGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcQueueGetName /*-----------------------------------------------------------*/ @@ -691,12 +632,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTimerGetTimerID_Unpriv MPU_pvTimerGetTimerID_Priv: - pop {r0} b MPU_pvTimerGetTimerIDImpl MPU_pvTimerGetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTimerGetTimerID /*-----------------------------------------------------------*/ @@ -705,12 +645,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetTimerID_Unpriv MPU_vTimerSetTimerID_Priv: - pop {r0} b MPU_vTimerSetTimerIDImpl MPU_vTimerSetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetTimerID /*-----------------------------------------------------------*/ @@ -719,12 +658,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerIsTimerActive_Unpriv MPU_xTimerIsTimerActive_Priv: - pop {r0} b MPU_xTimerIsTimerActiveImpl MPU_xTimerIsTimerActive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerIsTimerActive /*-----------------------------------------------------------*/ @@ -733,33 +671,25 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv MPU_xTimerGetTimerDaemonTaskHandle_Priv: - pop {r0} b MPU_xTimerGetTimerDaemonTaskHandleImpl MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: - pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: - pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -767,12 +697,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcTimerGetName_Unpriv MPU_pcTimerGetName_Priv: - pop {r0} b MPU_pcTimerGetNameImpl MPU_pcTimerGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcTimerGetName /*-----------------------------------------------------------*/ @@ -781,12 +710,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetReloadMode_Unpriv MPU_vTimerSetReloadMode_Priv: - pop {r0} b MPU_vTimerSetReloadModeImpl MPU_vTimerSetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetReloadMode /*-----------------------------------------------------------*/ @@ -795,12 +723,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetReloadMode_Unpriv MPU_xTimerGetReloadMode_Priv: - pop {r0} b MPU_xTimerGetReloadModeImpl MPU_xTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -809,12 +736,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTimerGetReloadMode_Unpriv MPU_uxTimerGetReloadMode_Priv: - pop {r0} b MPU_uxTimerGetReloadModeImpl MPU_uxTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -823,12 +749,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetPeriod_Unpriv MPU_xTimerGetPeriod_Priv: - pop {r0} b MPU_xTimerGetPeriodImpl MPU_xTimerGetPeriod_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetPeriod /*-----------------------------------------------------------*/ @@ -837,12 +762,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetExpiryTime_Unpriv MPU_xTimerGetExpiryTime_Priv: - pop {r0} b MPU_xTimerGetExpiryTimeImpl MPU_xTimerGetExpiryTime_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetExpiryTime /*-----------------------------------------------------------*/ @@ -851,12 +775,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupWaitBits_Unpriv MPU_xEventGroupWaitBits_Priv: - pop {r0} b MPU_xEventGroupWaitBitsImpl MPU_xEventGroupWaitBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupWaitBits /*-----------------------------------------------------------*/ @@ -865,12 +788,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupClearBits_Unpriv MPU_xEventGroupClearBits_Priv: - pop {r0} b MPU_xEventGroupClearBitsImpl MPU_xEventGroupClearBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupClearBits /*-----------------------------------------------------------*/ @@ -879,12 +801,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSetBits_Unpriv MPU_xEventGroupSetBits_Priv: - pop {r0} b MPU_xEventGroupSetBitsImpl MPU_xEventGroupSetBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSetBits /*-----------------------------------------------------------*/ @@ -893,12 +814,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSync_Unpriv MPU_xEventGroupSync_Priv: - pop {r0} b MPU_xEventGroupSyncImpl MPU_xEventGroupSync_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSync /*-----------------------------------------------------------*/ @@ -907,12 +827,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxEventGroupGetNumber_Unpriv MPU_uxEventGroupGetNumber_Priv: - pop {r0} b MPU_uxEventGroupGetNumberImpl MPU_uxEventGroupGetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxEventGroupGetNumber /*-----------------------------------------------------------*/ @@ -921,12 +840,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vEventGroupSetNumber_Unpriv MPU_vEventGroupSetNumber_Priv: - pop {r0} b MPU_vEventGroupSetNumberImpl MPU_vEventGroupSetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_vEventGroupSetNumber /*-----------------------------------------------------------*/ @@ -935,12 +853,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSend_Unpriv MPU_xStreamBufferSend_Priv: - pop {r0} b MPU_xStreamBufferSendImpl MPU_xStreamBufferSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSend /*-----------------------------------------------------------*/ @@ -949,12 +866,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferReceive_Unpriv MPU_xStreamBufferReceive_Priv: - pop {r0} b MPU_xStreamBufferReceiveImpl MPU_xStreamBufferReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferReceive /*-----------------------------------------------------------*/ @@ -963,12 +879,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsFull_Unpriv MPU_xStreamBufferIsFull_Priv: - pop {r0} b MPU_xStreamBufferIsFullImpl MPU_xStreamBufferIsFull_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsFull /*-----------------------------------------------------------*/ @@ -977,12 +892,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsEmpty_Unpriv MPU_xStreamBufferIsEmpty_Priv: - pop {r0} b MPU_xStreamBufferIsEmptyImpl MPU_xStreamBufferIsEmpty_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsEmpty /*-----------------------------------------------------------*/ @@ -991,12 +905,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSpacesAvailable_Unpriv MPU_xStreamBufferSpacesAvailable_Priv: - pop {r0} b MPU_xStreamBufferSpacesAvailableImpl MPU_xStreamBufferSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSpacesAvailable /*-----------------------------------------------------------*/ @@ -1005,12 +918,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferBytesAvailable_Unpriv MPU_xStreamBufferBytesAvailable_Priv: - pop {r0} b MPU_xStreamBufferBytesAvailableImpl MPU_xStreamBufferBytesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferBytesAvailable /*-----------------------------------------------------------*/ @@ -1019,12 +931,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSetTriggerLevel_Unpriv MPU_xStreamBufferSetTriggerLevel_Priv: - pop {r0} b MPU_xStreamBufferSetTriggerLevelImpl MPU_xStreamBufferSetTriggerLevel_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel /*-----------------------------------------------------------*/ @@ -1033,12 +944,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv MPU_xStreamBufferNextMessageLengthBytes_Priv: - pop {r0} b MPU_xStreamBufferNextMessageLengthBytesImpl MPU_xStreamBufferNextMessageLengthBytes_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes /*-----------------------------------------------------------*/ @@ -1089,10 +999,6 @@ MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1151,9 @@ MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c index 9712ac3..f16a343 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -54,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 @@ -68,6 +70,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,8 +109,17 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) /*-----------------------------------------------------------*/ /** @@ -111,8 +138,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,72 +161,79 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + +/* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ /* Enable privileged access to unmapped region. */ #define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) @@ -343,6 +377,20 @@ * any secure calls. */ #define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ /** @@ -351,7 +399,7 @@ */ static void prvTaskExitError( void ); -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief Extract MPU region's access permissions from the Region Base Address @@ -362,7 +410,7 @@ * @return uint32_t Access permissions. */ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; -#endif /* configENABLE_MPU */ +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ #if ( configENABLE_MPU == 1 ) @@ -380,6 +428,26 @@ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_FPU */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + +/** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + /** * @brief Setup the timer to generate the tick interrupts. * @@ -448,13 +516,13 @@ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,24 +530,24 @@ #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ -#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief This variable is set to pdTRUE when the scheduler is started. */ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; -#endif +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /** * @brief Each task maintains its own interrupt status in the critical nesting @@ -501,13 +569,13 @@ * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -531,6 +599,7 @@ /*-----------------------------------------------------------*/ #if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) { uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; @@ -746,6 +815,7 @@ __asm volatile ( "cpsie i" ::: "memory" ); } } + #endif /* configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ @@ -760,8 +830,15 @@ } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -795,7 +872,8 @@ } /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ { uint32_t ulAccessPermissions = 0; @@ -812,13 +890,16 @@ return ulAccessPermissions; } -#endif /* configENABLE_MPU */ + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -903,10 +984,12 @@ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ #if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ { #if ( configENABLE_TRUSTZONE == 1 ) @@ -928,6 +1011,7 @@ * LSPEN = 1 ==> Enable lazy context save of FP state. */ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); } + #endif /* configENABLE_FPU */ /*-----------------------------------------------------------*/ @@ -972,13 +1056,19 @@ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1078,7 @@ { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1174,24 @@ vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1116,6 +1213,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1154,12 +1252,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1268,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1190,11 +1287,19 @@ /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; @@ -1224,14 +1329,13 @@ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1259,6 +1363,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -1293,12 +1398,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1414,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1436,11 @@ /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1458,13 @@ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1392,6 +1499,7 @@ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ { uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ ulIndex++; @@ -1410,21 +1518,21 @@ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,20 +1543,30 @@ #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ ulIndex++; } else { xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1469,6 +1587,20 @@ } #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + return &( xMPUSettings->ulContext[ ulIndex ] ); } @@ -1483,7 +1615,7 @@ * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1637,7 @@ } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1672,7 @@ pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1551,6 +1683,20 @@ } #endif /* portPRELOAD_REGISTERS */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + return pxTopOfStack; } @@ -1559,22 +1705,52 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) { - volatile uint32_t ulOriginalPriority; + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1769,10 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1810,22 @@ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ #if ( configENABLE_MPU == 1 ) { @@ -1660,11 +1841,11 @@ /* Initialize the critical nesting count ready for the first task. */ ulCriticalNesting = 0; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { xSchedulerRunning = pdTRUE; } - #endif + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /* Start the first task. */ vStartFirstTask(); @@ -1692,15 +1873,17 @@ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, - uint32_t ulStackDepth ) + configSTACK_DEPTH_TYPE uxStackDepth ) { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1719,10 +1902,10 @@ * which case the stack region parameters will be valid. At all other * times the stack parameters will not be valid and it is assumed that * the stack region has already been configured. */ - if( ulStackDepth > 0 ) + if( uxStackDepth > 0 ) { ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; - ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; /* If the stack is within the privileged SRAM, do not protect it * using a separate MPU region. This is needed because privileged @@ -1790,6 +1973,16 @@ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | ( portMPU_RLAR_REGION_ENABLE ); + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + /* Normal memory/ Device memory. */ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) { @@ -1812,10 +2005,12 @@ lIndex++; } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, uint32_t ulBufferLength, uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ @@ -1825,7 +2020,15 @@ BaseType_t xAccessGranted = pdFALSE; const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ - if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) { xAccessGranted = pdTRUE; } @@ -1860,7 +2063,8 @@ return xAccessGranted; } -#endif /* configENABLE_MPU */ + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /*-----------------------------------------------------------*/ BaseType_t xPortIsInsideInterrupt( void ) @@ -1886,7 +2090,7 @@ } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1924,7 +2128,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); } @@ -1944,7 +2148,7 @@ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) @@ -2041,3 +2245,38 @@ #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h index f64ceb5..53b4b6e 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -52,7 +52,7 @@ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s index 00ee5a5..8092255 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -140,6 +142,14 @@ ldr r1, [r0] /* r1 = Location of saved context in TCB. */ restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ msr psp, r2 msr psplim, r3 @@ -163,10 +173,20 @@ ldr r1, [r2] /* Read pxCurrentTCB. */ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ msr psplim, r1 /* Set this task's PSPLIM value. */ - movs r1, #2 /* r1 = 2. */ - msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ adds r0, #32 /* Discard everything up to r0. */ msr psp, r0 /* This is now the new top of stack to use in the task. */ isb @@ -199,7 +219,7 @@ ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -230,7 +250,6 @@ vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */ #endif /* configENABLE_FPU || configENABLE_MVE */ - stmia r1!, {r4-r11} /* Store r4-r11. */ ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */ stmia r1!, {r4-r11} /* Store the hardware saved context. */ @@ -239,11 +258,20 @@ mrs r3, psplim /* r3 = PSPLIM. */ mrs r4, control /* r4 = CONTROL. */ stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_3 + stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -297,6 +325,14 @@ ldr r1, [r0] /* r1 = Location of saved context in TCB. */ restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ msr psp, r2 msr psplim, r3 @@ -332,12 +368,21 @@ mov r3, lr /* r3 = LR/EXC_RETURN. */ stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ +#if ( configENABLE_PAC == 1 ) + mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r2, PAC_KEY_P_2 + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_0 + stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */ + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -348,6 +393,15 @@ ldr r1, [r2] /* Read pxCurrentTCB. */ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r3 + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_0, r5 + clrm {r2-r5} /* Clear r2-r5. */ +#endif /* configENABLE_PAC */ + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h index 15cb65e..0526455 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -53,9 +53,10 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M55" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M55" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -65,8 +66,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h index 6f666da..2dfac6a 100644 --- a/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM55_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -117,7 +119,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -125,6 +127,18 @@ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; #endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ /*-----------------------------------------------------------*/ /** @@ -137,7 +151,7 @@ #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) @@ -193,8 +207,8 @@ */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -223,7 +237,20 @@ */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +-----------+---------------+----------+-----------------+------------------------------+-----+ @@ -232,11 +259,24 @@ * +-----------+---------------+----------+-----------------+------------------------------+-----+ * * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 + * 16 17 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 54 + #define MAX_CONTEXT_SIZE 55 - #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ /* * +-----------+---------------+----------+-----------------+----------------------+-----+ @@ -245,15 +285,28 @@ * +-----------+---------------+----------+-----------------+----------------------+-----+ * * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 + * 16 17 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 53 + #define MAX_CONTEXT_SIZE 54 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +----------+-----------------+------------------------------+-----+ @@ -264,7 +317,20 @@ * <---------><----------------><------------------------------><----> * 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 22 + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ @@ -277,17 +343,17 @@ * <---------><----------------><----------------------><----> * 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 21 + #define MAX_CONTEXT_SIZE 21 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) -/* Size of an Access Control List (ACL) entry in bits. */ + /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) typedef struct MPU_SETTINGS @@ -312,8 +378,8 @@ * @brief Validate priority of ISRs that are allowed to call FreeRTOS * system calls. */ -#ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +399,29 @@ /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +507,12 @@ extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +523,56 @@ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus }
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/port.c b/Source/portable/IAR/ARM_CM7/r0p1/port.c index a04532b..924e27e 100644 --- a/Source/portable/IAR/ARM_CM7/r0p1/port.c +++ b/Source/portable/IAR/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -45,10 +45,14 @@ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ #endif +/* Prototype of all Interrupt Service Routines (ISRs). */ +typedef void ( * portISR_t )( void ); + /* Constants required to manipulate the core. Registers first... */ #define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) #define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) ) #define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) /* ...then bits in the registers. */ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) @@ -63,6 +67,11 @@ #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 16UL ) #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) portMIN_INTERRUPT_PRIORITY ) << 24UL ) +/* Constants used to check the installation of the FreeRTOS interrupt handlers. */ +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xE000ED08 ) ) +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) + /* Constants required to check the validity of an interrupt priority. */ #define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) @@ -135,6 +144,11 @@ */ static void prvTaskExitError( void ); +/* + * FreeRTOS handlers implemented in assembly. + */ +extern void vPortSVCHandler( void ); +extern void xPortPendSVHandler( void ); /*-----------------------------------------------------------*/ /* Each task maintains its own interrupt status in the critical nesting @@ -234,6 +248,40 @@ */ BaseType_t xPortStartScheduler( void ) { + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions vPortSVCHandler and + * xPortPendSVHandler for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * vPortSVCHandler and xPortPendSVHandler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) + { + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == vPortSVCHandler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == xPortPendSVHandler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + #if ( configASSERT_DEFINED == 1 ) { volatile uint8_t ucOriginalPriority; @@ -269,7 +317,7 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -283,22 +331,22 @@ if( ulImplementedPrioBits == 8 ) { /* When the hardware implements 8 priority bits, there is no way for - * the software to configure PRIGROUP to not have sub-priorities. As - * a result, the least significant bit is always used for sub-priority - * and there are 128 preemption priorities and 2 sub-priorities. - * - * This may cause some confusion in some cases - for example, if - * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 - * priority interrupts will be masked in Critical Sections as those - * are at the same preemption priority. This may appear confusing as - * 4 is higher (numerically lower) priority than - * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not - * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY - * to 4, this confusion does not happen and the behaviour remains the same. - * - * The following assert ensures that the sub-priority bit in the - * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned - * confusion. */ + * the software to configure PRIGROUP to not have sub-priorities. As + * a result, the least significant bit is always used for sub-priority + * and there are 128 preemption priorities and 2 sub-priorities. + * + * This may cause some confusion in some cases - for example, if + * configMAX_SYSCALL_INTERRUPT_PRIORITY is set to 5, both 5 and 4 + * priority interrupts will be masked in Critical Sections as those + * are at the same preemption priority. This may appear confusing as + * 4 is higher (numerically lower) priority than + * configMAX_SYSCALL_INTERRUPT_PRIORITY and therefore, should not + * have been masked. Instead, if we set configMAX_SYSCALL_INTERRUPT_PRIORITY + * to 4, this confusion does not happen and the behaviour remains the same. + * + * The following assert ensures that the sub-priority bit in the + * configMAX_SYSCALL_INTERRUPT_PRIORITY is clear to avoid the above mentioned + * confusion. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & 0x1U ) == 0U ); ulMaxPRIGROUPValue = 0; } @@ -318,9 +366,11 @@ } #endif /* configASSERT_DEFINED */ - /* Make PendSV and SysTick the lowest priority interrupts. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; /* Start the timer that generates the tick ISR. Interrupts are disabled * here already. */ @@ -387,14 +437,21 @@ * save and then restore the interrupt mask value as its value is already * known. */ portDISABLE_INTERRUPTS(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); + /* A context switch is required. Context switching is performed in * the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portENABLE_INTERRUPTS(); } @@ -684,7 +741,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); }
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/portasm.s b/Source/portable/IAR/ARM_CM7/r0p1/portasm.s index 19cc6cd..4d4ffaf 100644 --- a/Source/portable/IAR/ARM_CM7/r0p1/portasm.s +++ b/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h b/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h index f93146e..4fa219e 100644 --- a/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h +++ b/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -27,7 +27,7 @@ */ #ifndef PORTMACRO_H - #define PORTMACRO_H +#define PORTMACRO_H /* *INDENT-OFF* */ #ifdef __cplusplus @@ -46,50 +46,50 @@ */ /* IAR includes. */ - #include <intrinsics.h> +#include <intrinsics.h> /* Type definitions. */ - #define portCHAR char - #define portFLOAT float - #define portDOUBLE double - #define portLONG long - #define portSHORT short - #define portSTACK_TYPE uint32_t - #define portBASE_TYPE long +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long - typedef portSTACK_TYPE StackType_t; - typedef long BaseType_t; - typedef unsigned long UBaseType_t; +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; - #if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) - typedef uint16_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffff - #elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) - typedef uint32_t TickType_t; - #define portMAX_DELAY ( TickType_t ) 0xffffffffUL +#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS ) + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do * not need to be guarded with a critical section. */ - #define portTICK_TYPE_IS_ATOMIC 1 - #else - #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. - #endif + #define portTICK_TYPE_IS_ATOMIC 1 +#else + #error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width. +#endif /*-----------------------------------------------------------*/ /* Architecture specifics. */ - #define portSTACK_GROWTH ( -1 ) - #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) - #define portBYTE_ALIGNMENT 8 +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 /*-----------------------------------------------------------*/ /* Compiler directives. */ - #define portWEAK_SYMBOL __attribute__( ( weak ) ) +#define portWEAK_SYMBOL __attribute__( ( weak ) ) /*-----------------------------------------------------------*/ /* Scheduler utilities. */ - #define portYIELD() \ +#define portYIELD() \ { \ /* Set a PendSV to request a context switch. */ \ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ @@ -97,41 +97,53 @@ __ISB(); \ } - #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) - #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) - #define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 ) - #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired != pdFALSE ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portYIELD(); \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ /* Architecture specific optimisations. */ - #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 - #endif +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif - #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) /* Check the configuration. */ - #if ( configMAX_PRIORITIES > 32 ) - #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. - #endif + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. + #endif /* Store/clear the ready priorities in a bit map. */ - #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) - #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) /*-----------------------------------------------------------*/ - #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) ) - #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ /*-----------------------------------------------------------*/ /* Critical section management. */ - extern void vPortEnterCritical( void ); - extern void vPortExitCritical( void ); +extern void vPortEnterCritical( void ); +extern void vPortExitCritical( void ); - #define portDISABLE_INTERRUPTS() \ +#define portDISABLE_INTERRUPTS() \ { \ /* Errata work around. */ \ __disable_interrupt(); \ @@ -141,71 +153,71 @@ __enable_interrupt(); \ } - #define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) - #define portENTER_CRITICAL() vPortEnterCritical() - #define portEXIT_CRITICAL() vPortExitCritical() - #define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) +#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_BASEPRI(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) __set_BASEPRI( x ) /*-----------------------------------------------------------*/ /* Tickless idle/low power functionality. */ - #ifndef portSUPPRESS_TICKS_AND_SLEEP - extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) - #endif +#ifndef portSUPPRESS_TICKS_AND_SLEEP + extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif /*-----------------------------------------------------------*/ /* Task function macros as described on the FreeRTOS.org WEB site. These are * not necessary for to use this port. They are defined so the common demo files * (which build with all the ports) will build. */ - #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) - #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) /*-----------------------------------------------------------*/ - #ifdef configASSERT - void vPortValidateInterruptPriority( void ); - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() - #endif +#if ( configASSERT_DEFINED == 1 ) + void vPortValidateInterruptPriority( void ); + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif /* portNOP() is not required by this port. */ - #define portNOP() +#define portNOP() - #define portINLINE __inline +#define portINLINE __inline - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) - #endif +#ifndef portFORCE_INLINE + #define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif /*-----------------------------------------------------------*/ - portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); + + if( ulCurrentInterrupt == 0 ) { - uint32_t ulCurrentInterrupt; - BaseType_t xReturn; - - /* Obtain the number of the currently executing interrupt. */ - __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" ); - - if( ulCurrentInterrupt == 0 ) - { - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; + xReturn = pdFALSE; } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in * the source code because to do so would cause other compilers to generate * warnings. */ - #pragma diag_suppress=Pe191 - #pragma diag_suppress=Pa082 +#pragma diag_suppress=Pe191 +#pragma diag_suppress=Pa082 /* *INDENT-OFF* */ #ifdef __cplusplus
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S index ef180bd..68192e4 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -47,12 +47,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskDelayUntil_Unpriv MPU_xTaskDelayUntil_Priv: - pop {r0} b MPU_xTaskDelayUntilImpl MPU_xTaskDelayUntil_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskDelayUntil /*-----------------------------------------------------------*/ @@ -61,12 +60,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskAbortDelay_Unpriv MPU_xTaskAbortDelay_Priv: - pop {r0} b MPU_xTaskAbortDelayImpl MPU_xTaskAbortDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskAbortDelay /*-----------------------------------------------------------*/ @@ -75,12 +73,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskDelay_Unpriv MPU_vTaskDelay_Priv: - pop {r0} b MPU_vTaskDelayImpl MPU_vTaskDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskDelay /*-----------------------------------------------------------*/ @@ -89,12 +86,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskPriorityGet_Unpriv MPU_uxTaskPriorityGet_Priv: - pop {r0} b MPU_uxTaskPriorityGetImpl MPU_uxTaskPriorityGet_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskPriorityGet /*-----------------------------------------------------------*/ @@ -103,12 +99,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_eTaskGetState_Unpriv MPU_eTaskGetState_Priv: - pop {r0} b MPU_eTaskGetStateImpl MPU_eTaskGetState_Unpriv: - pop {r0} svc #SYSTEM_CALL_eTaskGetState /*-----------------------------------------------------------*/ @@ -117,12 +112,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskGetInfo_Unpriv MPU_vTaskGetInfo_Priv: - pop {r0} b MPU_vTaskGetInfoImpl MPU_vTaskGetInfo_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskGetInfo /*-----------------------------------------------------------*/ @@ -131,12 +125,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetIdleTaskHandle_Unpriv MPU_xTaskGetIdleTaskHandle_Priv: - pop {r0} b MPU_xTaskGetIdleTaskHandleImpl MPU_xTaskGetIdleTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetIdleTaskHandle /*-----------------------------------------------------------*/ @@ -145,12 +138,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSuspend_Unpriv MPU_vTaskSuspend_Priv: - pop {r0} b MPU_vTaskSuspendImpl MPU_vTaskSuspend_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSuspend /*-----------------------------------------------------------*/ @@ -159,12 +151,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskResume_Unpriv MPU_vTaskResume_Priv: - pop {r0} b MPU_vTaskResumeImpl MPU_vTaskResume_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskResume /*-----------------------------------------------------------*/ @@ -173,12 +164,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetTickCount_Unpriv MPU_xTaskGetTickCount_Priv: - pop {r0} b MPU_xTaskGetTickCountImpl MPU_xTaskGetTickCount_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetTickCount /*-----------------------------------------------------------*/ @@ -187,40 +177,24 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetNumberOfTasks_Unpriv MPU_uxTaskGetNumberOfTasks_Priv: - pop {r0} b MPU_uxTaskGetNumberOfTasksImpl MPU_uxTaskGetNumberOfTasks_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimeCounter_Unpriv MPU_ulTaskGetRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimeCounter /*-----------------------------------------------------------*/ @@ -229,12 +203,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimePercent_Unpriv MPU_ulTaskGetRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetRunTimePercentImpl MPU_ulTaskGetRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimePercent /*-----------------------------------------------------------*/ @@ -243,12 +216,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimePercent_Unpriv MPU_ulTaskGetIdleRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimePercentImpl MPU_ulTaskGetIdleRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent /*-----------------------------------------------------------*/ @@ -257,12 +229,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv MPU_ulTaskGetIdleRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimeCounterImpl MPU_ulTaskGetIdleRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter /*-----------------------------------------------------------*/ @@ -271,12 +242,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetApplicationTaskTag_Unpriv MPU_vTaskSetApplicationTaskTag_Priv: - pop {r0} b MPU_vTaskSetApplicationTaskTagImpl MPU_vTaskSetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -285,12 +255,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetApplicationTaskTag_Unpriv MPU_xTaskGetApplicationTaskTag_Priv: - pop {r0} b MPU_xTaskGetApplicationTaskTagImpl MPU_xTaskGetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -299,12 +268,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv MPU_vTaskSetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_vTaskSetThreadLocalStoragePointerImpl MPU_vTaskSetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -313,12 +281,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv MPU_pvTaskGetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_pvTaskGetThreadLocalStoragePointerImpl MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -327,12 +294,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetSystemState_Unpriv MPU_uxTaskGetSystemState_Priv: - pop {r0} b MPU_uxTaskGetSystemStateImpl MPU_uxTaskGetSystemState_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetSystemState /*-----------------------------------------------------------*/ @@ -341,12 +307,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark_Unpriv MPU_uxTaskGetStackHighWaterMark_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMarkImpl MPU_uxTaskGetStackHighWaterMark_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark /*-----------------------------------------------------------*/ @@ -355,12 +320,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark2_Unpriv MPU_uxTaskGetStackHighWaterMark2_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMark2Impl MPU_uxTaskGetStackHighWaterMark2_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 /*-----------------------------------------------------------*/ @@ -369,12 +333,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetCurrentTaskHandle_Unpriv MPU_xTaskGetCurrentTaskHandle_Priv: - pop {r0} b MPU_xTaskGetCurrentTaskHandleImpl MPU_xTaskGetCurrentTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle /*-----------------------------------------------------------*/ @@ -383,12 +346,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetSchedulerState_Unpriv MPU_xTaskGetSchedulerState_Priv: - pop {r0} b MPU_xTaskGetSchedulerStateImpl MPU_xTaskGetSchedulerState_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetSchedulerState /*-----------------------------------------------------------*/ @@ -397,12 +359,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetTimeOutState_Unpriv MPU_vTaskSetTimeOutState_Priv: - pop {r0} b MPU_vTaskSetTimeOutStateImpl MPU_vTaskSetTimeOutState_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetTimeOutState /*-----------------------------------------------------------*/ @@ -411,12 +372,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskCheckForTimeOut_Unpriv MPU_xTaskCheckForTimeOut_Priv: - pop {r0} b MPU_xTaskCheckForTimeOutImpl MPU_xTaskCheckForTimeOut_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskCheckForTimeOut /*-----------------------------------------------------------*/ @@ -425,12 +385,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotify_Unpriv MPU_xTaskGenericNotify_Priv: - pop {r0} b MPU_xTaskGenericNotifyImpl MPU_xTaskGenericNotify_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotify /*-----------------------------------------------------------*/ @@ -439,12 +398,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyWait_Unpriv MPU_xTaskGenericNotifyWait_Priv: - pop {r0} b MPU_xTaskGenericNotifyWaitImpl MPU_xTaskGenericNotifyWait_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyWait /*-----------------------------------------------------------*/ @@ -453,12 +411,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyTake_Unpriv MPU_ulTaskGenericNotifyTake_Priv: - pop {r0} b MPU_ulTaskGenericNotifyTakeImpl MPU_ulTaskGenericNotifyTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyTake /*-----------------------------------------------------------*/ @@ -467,12 +424,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyStateClear_Unpriv MPU_xTaskGenericNotifyStateClear_Priv: - pop {r0} b MPU_xTaskGenericNotifyStateClearImpl MPU_xTaskGenericNotifyStateClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyStateClear /*-----------------------------------------------------------*/ @@ -481,12 +437,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyValueClear_Unpriv MPU_ulTaskGenericNotifyValueClear_Priv: - pop {r0} b MPU_ulTaskGenericNotifyValueClearImpl MPU_ulTaskGenericNotifyValueClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear /*-----------------------------------------------------------*/ @@ -495,12 +450,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGenericSend_Unpriv MPU_xQueueGenericSend_Priv: - pop {r0} b MPU_xQueueGenericSendImpl MPU_xQueueGenericSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGenericSend /*-----------------------------------------------------------*/ @@ -509,12 +463,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueMessagesWaiting_Unpriv MPU_uxQueueMessagesWaiting_Priv: - pop {r0} b MPU_uxQueueMessagesWaitingImpl MPU_uxQueueMessagesWaiting_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueMessagesWaiting /*-----------------------------------------------------------*/ @@ -523,12 +476,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueSpacesAvailable_Unpriv MPU_uxQueueSpacesAvailable_Priv: - pop {r0} b MPU_uxQueueSpacesAvailableImpl MPU_uxQueueSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueSpacesAvailable /*-----------------------------------------------------------*/ @@ -537,12 +489,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueReceive_Unpriv MPU_xQueueReceive_Priv: - pop {r0} b MPU_xQueueReceiveImpl MPU_xQueueReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueReceive /*-----------------------------------------------------------*/ @@ -551,12 +502,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueuePeek_Unpriv MPU_xQueuePeek_Priv: - pop {r0} b MPU_xQueuePeekImpl MPU_xQueuePeek_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueuePeek /*-----------------------------------------------------------*/ @@ -565,12 +515,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSemaphoreTake_Unpriv MPU_xQueueSemaphoreTake_Priv: - pop {r0} b MPU_xQueueSemaphoreTakeImpl MPU_xQueueSemaphoreTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSemaphoreTake /*-----------------------------------------------------------*/ @@ -579,12 +528,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGetMutexHolder_Unpriv MPU_xQueueGetMutexHolder_Priv: - pop {r0} b MPU_xQueueGetMutexHolderImpl MPU_xQueueGetMutexHolder_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGetMutexHolder /*-----------------------------------------------------------*/ @@ -593,12 +541,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueTakeMutexRecursive_Unpriv MPU_xQueueTakeMutexRecursive_Priv: - pop {r0} b MPU_xQueueTakeMutexRecursiveImpl MPU_xQueueTakeMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueTakeMutexRecursive /*-----------------------------------------------------------*/ @@ -607,12 +554,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGiveMutexRecursive_Unpriv MPU_xQueueGiveMutexRecursive_Priv: - pop {r0} b MPU_xQueueGiveMutexRecursiveImpl MPU_xQueueGiveMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGiveMutexRecursive /*-----------------------------------------------------------*/ @@ -621,12 +567,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSelectFromSet_Unpriv MPU_xQueueSelectFromSet_Priv: - pop {r0} b MPU_xQueueSelectFromSetImpl MPU_xQueueSelectFromSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSelectFromSet /*-----------------------------------------------------------*/ @@ -635,12 +580,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueAddToSet_Unpriv MPU_xQueueAddToSet_Priv: - pop {r0} b MPU_xQueueAddToSetImpl MPU_xQueueAddToSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueAddToSet /*-----------------------------------------------------------*/ @@ -649,12 +593,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueAddToRegistry_Unpriv MPU_vQueueAddToRegistry_Priv: - pop {r0} b MPU_vQueueAddToRegistryImpl MPU_vQueueAddToRegistry_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueAddToRegistry /*-----------------------------------------------------------*/ @@ -663,12 +606,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueUnregisterQueue_Unpriv MPU_vQueueUnregisterQueue_Priv: - pop {r0} b MPU_vQueueUnregisterQueueImpl MPU_vQueueUnregisterQueue_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueUnregisterQueue /*-----------------------------------------------------------*/ @@ -677,12 +619,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcQueueGetName_Unpriv MPU_pcQueueGetName_Priv: - pop {r0} b MPU_pcQueueGetNameImpl MPU_pcQueueGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcQueueGetName /*-----------------------------------------------------------*/ @@ -691,12 +632,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTimerGetTimerID_Unpriv MPU_pvTimerGetTimerID_Priv: - pop {r0} b MPU_pvTimerGetTimerIDImpl MPU_pvTimerGetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTimerGetTimerID /*-----------------------------------------------------------*/ @@ -705,12 +645,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetTimerID_Unpriv MPU_vTimerSetTimerID_Priv: - pop {r0} b MPU_vTimerSetTimerIDImpl MPU_vTimerSetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetTimerID /*-----------------------------------------------------------*/ @@ -719,12 +658,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerIsTimerActive_Unpriv MPU_xTimerIsTimerActive_Priv: - pop {r0} b MPU_xTimerIsTimerActiveImpl MPU_xTimerIsTimerActive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerIsTimerActive /*-----------------------------------------------------------*/ @@ -733,33 +671,25 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv MPU_xTimerGetTimerDaemonTaskHandle_Priv: - pop {r0} b MPU_xTimerGetTimerDaemonTaskHandleImpl MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: - pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: - pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -767,12 +697,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcTimerGetName_Unpriv MPU_pcTimerGetName_Priv: - pop {r0} b MPU_pcTimerGetNameImpl MPU_pcTimerGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcTimerGetName /*-----------------------------------------------------------*/ @@ -781,12 +710,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetReloadMode_Unpriv MPU_vTimerSetReloadMode_Priv: - pop {r0} b MPU_vTimerSetReloadModeImpl MPU_vTimerSetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetReloadMode /*-----------------------------------------------------------*/ @@ -795,12 +723,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetReloadMode_Unpriv MPU_xTimerGetReloadMode_Priv: - pop {r0} b MPU_xTimerGetReloadModeImpl MPU_xTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -809,12 +736,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTimerGetReloadMode_Unpriv MPU_uxTimerGetReloadMode_Priv: - pop {r0} b MPU_uxTimerGetReloadModeImpl MPU_uxTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -823,12 +749,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetPeriod_Unpriv MPU_xTimerGetPeriod_Priv: - pop {r0} b MPU_xTimerGetPeriodImpl MPU_xTimerGetPeriod_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetPeriod /*-----------------------------------------------------------*/ @@ -837,12 +762,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetExpiryTime_Unpriv MPU_xTimerGetExpiryTime_Priv: - pop {r0} b MPU_xTimerGetExpiryTimeImpl MPU_xTimerGetExpiryTime_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetExpiryTime /*-----------------------------------------------------------*/ @@ -851,12 +775,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupWaitBits_Unpriv MPU_xEventGroupWaitBits_Priv: - pop {r0} b MPU_xEventGroupWaitBitsImpl MPU_xEventGroupWaitBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupWaitBits /*-----------------------------------------------------------*/ @@ -865,12 +788,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupClearBits_Unpriv MPU_xEventGroupClearBits_Priv: - pop {r0} b MPU_xEventGroupClearBitsImpl MPU_xEventGroupClearBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupClearBits /*-----------------------------------------------------------*/ @@ -879,12 +801,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSetBits_Unpriv MPU_xEventGroupSetBits_Priv: - pop {r0} b MPU_xEventGroupSetBitsImpl MPU_xEventGroupSetBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSetBits /*-----------------------------------------------------------*/ @@ -893,12 +814,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSync_Unpriv MPU_xEventGroupSync_Priv: - pop {r0} b MPU_xEventGroupSyncImpl MPU_xEventGroupSync_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSync /*-----------------------------------------------------------*/ @@ -907,12 +827,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxEventGroupGetNumber_Unpriv MPU_uxEventGroupGetNumber_Priv: - pop {r0} b MPU_uxEventGroupGetNumberImpl MPU_uxEventGroupGetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxEventGroupGetNumber /*-----------------------------------------------------------*/ @@ -921,12 +840,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vEventGroupSetNumber_Unpriv MPU_vEventGroupSetNumber_Priv: - pop {r0} b MPU_vEventGroupSetNumberImpl MPU_vEventGroupSetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_vEventGroupSetNumber /*-----------------------------------------------------------*/ @@ -935,12 +853,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSend_Unpriv MPU_xStreamBufferSend_Priv: - pop {r0} b MPU_xStreamBufferSendImpl MPU_xStreamBufferSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSend /*-----------------------------------------------------------*/ @@ -949,12 +866,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferReceive_Unpriv MPU_xStreamBufferReceive_Priv: - pop {r0} b MPU_xStreamBufferReceiveImpl MPU_xStreamBufferReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferReceive /*-----------------------------------------------------------*/ @@ -963,12 +879,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsFull_Unpriv MPU_xStreamBufferIsFull_Priv: - pop {r0} b MPU_xStreamBufferIsFullImpl MPU_xStreamBufferIsFull_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsFull /*-----------------------------------------------------------*/ @@ -977,12 +892,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsEmpty_Unpriv MPU_xStreamBufferIsEmpty_Priv: - pop {r0} b MPU_xStreamBufferIsEmptyImpl MPU_xStreamBufferIsEmpty_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsEmpty /*-----------------------------------------------------------*/ @@ -991,12 +905,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSpacesAvailable_Unpriv MPU_xStreamBufferSpacesAvailable_Priv: - pop {r0} b MPU_xStreamBufferSpacesAvailableImpl MPU_xStreamBufferSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSpacesAvailable /*-----------------------------------------------------------*/ @@ -1005,12 +918,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferBytesAvailable_Unpriv MPU_xStreamBufferBytesAvailable_Priv: - pop {r0} b MPU_xStreamBufferBytesAvailableImpl MPU_xStreamBufferBytesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferBytesAvailable /*-----------------------------------------------------------*/ @@ -1019,12 +931,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSetTriggerLevel_Unpriv MPU_xStreamBufferSetTriggerLevel_Priv: - pop {r0} b MPU_xStreamBufferSetTriggerLevelImpl MPU_xStreamBufferSetTriggerLevel_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel /*-----------------------------------------------------------*/ @@ -1033,12 +944,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv MPU_xStreamBufferNextMessageLengthBytes_Priv: - pop {r0} b MPU_xStreamBufferNextMessageLengthBytesImpl MPU_xStreamBufferNextMessageLengthBytes_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes /*-----------------------------------------------------------*/ @@ -1089,10 +999,6 @@ MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1151,9 @@ MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/port.c b/Source/portable/IAR/ARM_CM85/non_secure/port.c index 9712ac3..f16a343 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM85/non_secure/port.c
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -54,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 @@ -68,6 +70,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,8 +109,17 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) /*-----------------------------------------------------------*/ /** @@ -111,8 +138,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,72 +161,79 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + +/* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ /* Enable privileged access to unmapped region. */ #define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) @@ -343,6 +377,20 @@ * any secure calls. */ #define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ /** @@ -351,7 +399,7 @@ */ static void prvTaskExitError( void ); -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief Extract MPU region's access permissions from the Region Base Address @@ -362,7 +410,7 @@ * @return uint32_t Access permissions. */ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; -#endif /* configENABLE_MPU */ +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ #if ( configENABLE_MPU == 1 ) @@ -380,6 +428,26 @@ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_FPU */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + +/** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + /** * @brief Setup the timer to generate the tick interrupts. * @@ -448,13 +516,13 @@ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,24 +530,24 @@ #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ -#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief This variable is set to pdTRUE when the scheduler is started. */ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; -#endif +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /** * @brief Each task maintains its own interrupt status in the critical nesting @@ -501,13 +569,13 @@ * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -531,6 +599,7 @@ /*-----------------------------------------------------------*/ #if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) { uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; @@ -746,6 +815,7 @@ __asm volatile ( "cpsie i" ::: "memory" ); } } + #endif /* configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ @@ -760,8 +830,15 @@ } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -795,7 +872,8 @@ } /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ { uint32_t ulAccessPermissions = 0; @@ -812,13 +890,16 @@ return ulAccessPermissions; } -#endif /* configENABLE_MPU */ + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -903,10 +984,12 @@ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ #if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ { #if ( configENABLE_TRUSTZONE == 1 ) @@ -928,6 +1011,7 @@ * LSPEN = 1 ==> Enable lazy context save of FP state. */ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); } + #endif /* configENABLE_FPU */ /*-----------------------------------------------------------*/ @@ -972,13 +1056,19 @@ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1078,7 @@ { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1174,24 @@ vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1116,6 +1213,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1154,12 +1252,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1268,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1190,11 +1287,19 @@ /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; @@ -1224,14 +1329,13 @@ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1259,6 +1363,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -1293,12 +1398,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1414,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1436,11 @@ /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1458,13 @@ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1392,6 +1499,7 @@ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ { uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ ulIndex++; @@ -1410,21 +1518,21 @@ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,20 +1543,30 @@ #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ ulIndex++; } else { xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1469,6 +1587,20 @@ } #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + return &( xMPUSettings->ulContext[ ulIndex ] ); } @@ -1483,7 +1615,7 @@ * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1637,7 @@ } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1672,7 @@ pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1551,6 +1683,20 @@ } #endif /* portPRELOAD_REGISTERS */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + return pxTopOfStack; } @@ -1559,22 +1705,52 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) { - volatile uint32_t ulOriginalPriority; + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1769,10 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1810,22 @@ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ #if ( configENABLE_MPU == 1 ) { @@ -1660,11 +1841,11 @@ /* Initialize the critical nesting count ready for the first task. */ ulCriticalNesting = 0; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { xSchedulerRunning = pdTRUE; } - #endif + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /* Start the first task. */ vStartFirstTask(); @@ -1692,15 +1873,17 @@ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, - uint32_t ulStackDepth ) + configSTACK_DEPTH_TYPE uxStackDepth ) { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1719,10 +1902,10 @@ * which case the stack region parameters will be valid. At all other * times the stack parameters will not be valid and it is assumed that * the stack region has already been configured. */ - if( ulStackDepth > 0 ) + if( uxStackDepth > 0 ) { ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; - ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; /* If the stack is within the privileged SRAM, do not protect it * using a separate MPU region. This is needed because privileged @@ -1790,6 +1973,16 @@ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | ( portMPU_RLAR_REGION_ENABLE ); + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + /* Normal memory/ Device memory. */ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) { @@ -1812,10 +2005,12 @@ lIndex++; } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, uint32_t ulBufferLength, uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ @@ -1825,7 +2020,15 @@ BaseType_t xAccessGranted = pdFALSE; const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ - if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) { xAccessGranted = pdTRUE; } @@ -1860,7 +2063,8 @@ return xAccessGranted; } -#endif /* configENABLE_MPU */ + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /*-----------------------------------------------------------*/ BaseType_t xPortIsInsideInterrupt( void ) @@ -1886,7 +2090,7 @@ } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1924,7 +2128,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); } @@ -1944,7 +2148,7 @@ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) @@ -2041,3 +2245,38 @@ #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portasm.h b/Source/portable/IAR/ARM_CM85/non_secure/portasm.h index f64ceb5..53b4b6e 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM85/non_secure/portasm.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -52,7 +52,7 @@ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portasm.s b/Source/portable/IAR/ARM_CM85/non_secure/portasm.s index 5309103..b5c91e5 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM85/non_secure/portasm.s
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -150,6 +152,14 @@ ldr r2, [r1] /* r2 = Location of saved context in TCB. */ restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ msr psp, r3 msr psplim, r4 @@ -175,12 +185,22 @@ ldr r3, [r2] /* Read pxCurrentTCB. */ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */ ldr r4, =xSecureContext str r1, [r4] /* Set xSecureContext to this task's value for the same. */ msr psplim, r2 /* Set this task's PSPLIM value. */ - movs r1, #2 /* r1 = 2. */ - msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ adds r0, #32 /* Discard everything up to r0. */ msr psp, r0 /* This is now the new top of stack to use in the task. */ isb @@ -213,7 +233,7 @@ ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -268,11 +288,20 @@ mrs r4, psplim /* r4 = PSPLIM. */ mrs r5, control /* r5 = CONTROL. */ stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ - str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_1 + mrs r5, PAC_KEY_P_2 + mrs r6, PAC_KEY_P_3 + stmia r2!, {r3-r6} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */ select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -326,6 +355,14 @@ ldr r2, [r1] /* r2 = Location of saved context in TCB. */ restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r2!, {r3-r6} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_2, r5 + msr PAC_KEY_P_3, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */ msr psp, r3 msr psplim, r4 @@ -371,76 +408,86 @@ mrs r2, psp /* Read PSP in r2. */ cbz r0, save_ns_context /* No secure context to save. */ - push {r0-r2, r14} - bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ - pop {r0-r3} /* LR is now in r3. */ - mov lr, r3 /* LR = r3. */ - lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ - bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ - - ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ - ldr r1, [r3] /* Read pxCurrentTCB. */ - subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */ - str r2, [r1] /* Save the new top of stack in TCB. */ - mrs r1, psplim /* r1 = PSPLIM. */ - mov r3, lr /* r3 = LR/EXC_RETURN. */ - stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ - b select_next_task + save_s_context: + push {r0-r2, lr} + bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ + pop {r0-r2, lr} save_ns_context: - ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ - ldr r1, [r3] /* Read pxCurrentTCB. */ + mov r3, lr /* r3 = LR. */ + lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi save_special_regs /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */ + + save_general_regs: #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ it eq vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */ #endif /* configENABLE_FPU || configENABLE_MVE */ - subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */ - str r2, [r1] /* Save the new top of stack in TCB. */ - adds r2, r2, #12 /* r2 = r2 + 12. */ - stm r2, {r4-r11} /* Store the registers that are not saved automatically. */ - mrs r1, psplim /* r1 = PSPLIM. */ - mov r3, lr /* r3 = LR/EXC_RETURN. */ - subs r2, r2, #12 /* r2 = r2 - 12. */ - stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */ + stmdb r2!, {r4-r11} /* Store the registers that are not saved automatically. */ + + save_special_regs: + mrs r3, psplim /* r3 = PSPLIM. */ + stmdb r2!, {r0, r3, lr} /* Store xSecureContext, PSPLIM and LR on the stack. */ + #if ( configENABLE_PAC == 1 ) + mrs r3, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_1 + mrs r6, PAC_KEY_P_0 + stmdb r2!, {r3-r6} /* Store the task's dedicated PAC key on the stack. */ + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + + str r2, [r1] /* Save the new top of stack in TCB. */ select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext mov r0, #0 /* r0 = 0. */ msr basepri, r0 /* Enable interrupts. */ + restore_context: ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r3] /* Read pxCurrentTCB. */ ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */ - ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */ - msr psplim, r1 /* Restore the PSPLIM register value for the task. */ - mov lr, r4 /* LR = r4. */ + restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmia r2!, {r3-r6} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r3 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_1, r5 + msr PAC_KEY_P_0, r6 + clrm {r3-r6} /* Clear r3-r6. */ + #endif /* configENABLE_PAC */ + ldmia r2!, {r0, r3, lr} /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */ + msr psplim, r3 /* Restore the PSPLIM register value for the task. */ ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */ str r0, [r3] /* Restore the task's xSecureContext. */ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */ - ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ - ldr r1, [r3] /* Read pxCurrentTCB. */ - push {r2, r4} + + restore_s_context: + push {r1-r3, lr} bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */ - pop {r2, r4} - mov lr, r4 /* LR = r4. */ - lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ - bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */ - msr psp, r2 /* Remember the new top of stack for the task. */ - bx lr + pop {r1-r3, lr} restore_ns_context: + mov r0, lr /* r0 = LR (EXC_RETURN). */ + lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */ + bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */ + + restore_general_regs: ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */ it eq vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */ #endif /* configENABLE_FPU || configENABLE_MVE */ + + restore_context_done: msr psp, r2 /* Remember the new top of stack for the task. */ bx lr
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h index ee5baf1..2f1676c 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM85/non_secure/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -53,9 +53,10 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M85" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -65,8 +66,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h index 6f666da..2dfac6a 100644 --- a/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM85/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -117,7 +119,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -125,6 +127,18 @@ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; #endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ /*-----------------------------------------------------------*/ /** @@ -137,7 +151,7 @@ #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) @@ -193,8 +207,8 @@ */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -223,7 +237,20 @@ */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +-----------+---------------+----------+-----------------+------------------------------+-----+ @@ -232,11 +259,24 @@ * +-----------+---------------+----------+-----------------+------------------------------+-----+ * * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 + * 16 17 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 54 + #define MAX_CONTEXT_SIZE 55 - #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ /* * +-----------+---------------+----------+-----------------+----------------------+-----+ @@ -245,15 +285,28 @@ * +-----------+---------------+----------+-----------------+----------------------+-----+ * * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 + * 16 17 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 53 + #define MAX_CONTEXT_SIZE 54 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +----------+-----------------+------------------------------+-----+ @@ -264,7 +317,20 @@ * <---------><----------------><------------------------------><----> * 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 22 + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ @@ -277,17 +343,17 @@ * <---------><----------------><----------------------><----> * 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 21 + #define MAX_CONTEXT_SIZE 21 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) -/* Size of an Access Control List (ACL) entry in bits. */ + /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) typedef struct MPU_SETTINGS @@ -312,8 +378,8 @@ * @brief Validate priority of ISRs that are allowed to call FreeRTOS * system calls. */ -#ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +399,29 @@ /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +507,12 @@ extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +523,56 @@ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus }
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_context.c b/Source/portable/IAR/ARM_CM85/secure/secure_context.c index e37dd96..62bcfa1 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_context.c +++ b/Source/portable/IAR/ARM_CM85/secure/secure_context.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -65,7 +65,7 @@ * @brief Maximum number of secure contexts. */ #ifndef secureconfigMAX_SECURE_CONTEXTS - #define secureconfigMAX_SECURE_CONTEXTS 8UL + #define secureconfigMAX_SECURE_CONTEXTS 8UL #endif /*-----------------------------------------------------------*/ @@ -164,15 +164,15 @@ } #if ( configENABLE_MPU == 1 ) - { - /* Configure thread mode to use PSP and to be unprivileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be unprivileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED ); + } #else /* configENABLE_MPU */ - { - /* Configure thread mode to use PSP and to be privileged. */ - secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); - } + { + /* Configure thread mode to use PSP and to be privileged. */ + secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED ); + } #endif /* configENABLE_MPU */ } } @@ -207,7 +207,7 @@ * securecontextNO_STACK when no secure context is loaded. */ if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) ) { - /* Ontain a free secure context. */ + /* Obtain a free secure context. */ ulSecureContextIndex = ulGetSecureContext( pvTaskHandle ); /* Were we able to get a free context? */ @@ -219,16 +219,16 @@ if( pucStackMemory != NULL ) { /* Since stack grows down, the starting point will be the last - * location. Note that this location is next to the last - * allocated byte for stack (excluding the space for seal values) - * because the hardware decrements the stack pointer before - * writing i.e. if stack pointer is 0x2, a push operation will - * decrement the stack pointer to 0x1 and then write at 0x1. */ + * location. Note that this location is next to the last + * allocated byte for stack (excluding the space for seal values) + * because the hardware decrements the stack pointer before + * writing i.e. if stack pointer is 0x2, a push operation will + * decrement the stack pointer to 0x1 and then write at 0x1. */ xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize; /* Seal the created secure process stack. */ - *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; - *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE; + *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE; /* The stack cannot go beyond this location. This value is * programmed in the PSPLIM register on context switch.*/ @@ -237,32 +237,32 @@ xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle; #if ( configENABLE_MPU == 1 ) + { + /* Store the correct CONTROL value for the task on the stack. + * This value is programmed in the CONTROL register on + * context switch. */ + pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; + pulCurrentStackPointer--; + + if( ulIsTaskPrivileged ) { - /* Store the correct CONTROL value for the task on the stack. - * This value is programmed in the CONTROL register on - * context switch. */ - pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart; - pulCurrentStackPointer--; - - if( ulIsTaskPrivileged ) - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; - } - else - { - *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; - } - - /* Store the current stack pointer. This value is programmed in - * the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED; } + else + { + *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED; + } + + /* Store the current stack pointer. This value is programmed in + * the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer; + } #else /* configENABLE_MPU */ - { - /* Current SP is set to the starting of the stack. This - * value programmed in the PSP register on context switch. */ - xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; - } + { + /* Current SP is set to the starting of the stack. This + * value programmed in the PSP register on context switch. */ + xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart; + } #endif /* configENABLE_MPU */ /* Ensure to never return 0 as a valid context handle. */ @@ -275,7 +275,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint32_t ulIPSR, ulSecureContextIndex; @@ -306,7 +307,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex; @@ -328,7 +330,8 @@ } /*-----------------------------------------------------------*/ -secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ) +secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ) { uint8_t * pucStackLimit; uint32_t ulSecureContextIndex;
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_context.h b/Source/portable/IAR/ARM_CM85/secure/secure_context.h index 2220ea6..8b93857 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_context.h +++ b/Source/portable/IAR/ARM_CM85/secure/secure_context.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -38,12 +38,12 @@ /** * @brief PSP value when no secure context is loaded. */ -#define securecontextNO_STACK 0x0 +#define securecontextNO_STACK 0x0 /** * @brief Invalid context ID. */ -#define securecontextINVALID_CONTEXT_ID 0UL +#define securecontextINVALID_CONTEXT_ID 0UL /*-----------------------------------------------------------*/ /** @@ -108,7 +108,8 @@ * @param[in] xSecureContextHandle Context handle corresponding to the * context to be freed. */ -void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Loads the given context. @@ -119,7 +120,8 @@ * @param[in] xSecureContextHandle Context handle corresponding to the context * to be loaded. */ -void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); /** * @brief Saves the given context. @@ -130,6 +132,7 @@ * @param[in] xSecureContextHandle Context handle corresponding to the context * to be saved. */ -void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle ); +void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, + void * pvTaskHandle ); #endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s index 0da3e0f..5cc070e 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s +++ b/Source/portable/IAR/ARM_CM85/secure/secure_context_port_asm.s
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_heap.c b/Source/portable/IAR/ARM_CM85/secure/secure_heap.c index 19f7c23..b0e83b4 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_heap.c +++ b/Source/portable/IAR/ARM_CM85/secure/secure_heap.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -29,6 +29,9 @@ /* Standard includes. */ #include <stdint.h> +/* Configuration includes. */ +#include "FreeRTOSConfig.h" + /* Secure context heap includes. */ #include "secure_heap.h" @@ -62,6 +65,22 @@ /* Assumes 8bit bytes! */ #define secureheapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Max value that fits in a size_t type. */ +#define secureheapSIZE_MAX ( ~( ( size_t ) 0 ) ) + +/* Check if adding a and b will result in overflow. */ +#define secureheapADD_WILL_OVERFLOW( a, b ) ( ( a ) > ( secureheapSIZE_MAX - ( b ) ) ) + +/* MSB of the xBlockSize member of an BlockLink_t structure is used to track + * the allocation status of a block. When MSB of the xBlockSize member of + * an BlockLink_t structure is set then the block belongs to the application. + * When the bit is free the block is still part of the free heap space. */ +#define secureheapBLOCK_ALLOCATED_BITMASK ( ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ) ) +#define secureheapBLOCK_SIZE_IS_VALID( xBlockSize ) ( ( ( xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) == 0 ) +#define secureheapBLOCK_IS_ALLOCATED( pxBlock ) ( ( ( pxBlock->xBlockSize ) & secureheapBLOCK_ALLOCATED_BITMASK ) != 0 ) +#define secureheapALLOCATE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) |= secureheapBLOCK_ALLOCATED_BITMASK ) +#define secureheapFREE_BLOCK( pxBlock ) ( ( pxBlock->xBlockSize ) &= ~secureheapBLOCK_ALLOCATED_BITMASK ) /*-----------------------------------------------------------*/ /* Allocate the memory for the heap. */ @@ -123,14 +142,6 @@ static size_t xFreeBytesRemaining = 0U; static size_t xMinimumEverFreeBytesRemaining = 0U; -/** - * @brief Gets set to the top bit of an size_t type. - * - * When this bit in the xBlockSize member of an BlockLink_t structure is set - * then the block belongs to the application. When the bit is free the block is - * still part of the free heap space. - */ -static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ static void prvHeapInit( void ) @@ -175,9 +186,6 @@ /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - - /* Work out the position of the top bit in a size_t variable. */ - xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 ); } /*-----------------------------------------------------------*/ @@ -229,7 +237,7 @@ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; } - /* If the block being inserted plugged a gab, so was merged with the block + /* If the block being inserted plugged a gap, so was merged with the block * before and the block after, then it's pxNextFreeBlock pointer will have * already been set, and should not be set here as that would make it point * to itself. */ @@ -250,6 +258,8 @@ BlockLink_t * pxPreviousBlock; BlockLink_t * pxNewBlockLink; void * pvReturn = NULL; + size_t xAdditionalRequiredSize; + size_t xAllocatedBlockSize = 0; /* If this is the first call to malloc then the heap will require * initialisation to setup the list of free blocks. */ @@ -262,25 +272,29 @@ mtCOVERAGE_TEST_MARKER(); } - /* Check the requested block size is not so large that the top bit is set. - * The top bit of the block size member of the BlockLink_t structure is used - * to determine who owns the block - the application or the kernel, so it - * must be free. */ - if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + if( xWantedSize > 0 ) { - /* The wanted size is increased so it can contain a BlockLink_t + /* The wanted size must be increased so it can contain a BlockLink_t * structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xHeapStructSize ) == 0 ) { xWantedSize += xHeapStructSize; - /* Ensure that blocks are always aligned to the required number of - * bytes. */ + /* Ensure that blocks are always aligned to the required number + * of bytes. */ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 ) { /* Byte alignment required. */ - xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) ); - secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 ); + xAdditionalRequiredSize = secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ); + + if( secureheapADD_WILL_OVERFLOW( xWantedSize, xAdditionalRequiredSize ) == 0 ) + { + xWantedSize += xAdditionalRequiredSize; + } + else + { + xWantedSize = 0; + } } else { @@ -289,9 +303,20 @@ } else { - mtCOVERAGE_TEST_MARKER(); + xWantedSize = 0; } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + /* Check the requested block size is not so large that the top bit is set. + * The top bit of the block size member of the BlockLink_t structure is used + * to determine who owns the block - the application or the kernel, so it + * must be free. */ + if( secureheapBLOCK_SIZE_IS_VALID( xWantedSize ) != 0 ) + { if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) { /* Traverse the list from the start (lowest address) block until @@ -334,7 +359,8 @@ pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( pxNewBlockLink ); + pxNewBlockLink->pxNextFreeBlock = pxPreviousBlock->pxNextFreeBlock; + pxPreviousBlock->pxNextFreeBlock = pxNewBlockLink; } else { @@ -352,9 +378,11 @@ mtCOVERAGE_TEST_MARKER(); } + xAllocatedBlockSize = pxBlock->xBlockSize; + /* The block is being returned - it is allocated and owned by * the application and has no "next" block. */ - pxBlock->xBlockSize |= xBlockAllocatedBit; + secureheapALLOCATE_BLOCK( pxBlock ); pxBlock->pxNextFreeBlock = NULL; } else @@ -372,20 +400,23 @@ mtCOVERAGE_TEST_MARKER(); } - traceMALLOC( pvReturn, xWantedSize ); + traceMALLOC( pvReturn, xAllocatedBlockSize ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xAllocatedBlockSize; #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 ); @@ -408,16 +439,16 @@ pxLink = ( void * ) puc; /* Check the block is actually allocated. */ - secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + secureportASSERT( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ); secureportASSERT( pxLink->pxNextFreeBlock == NULL ); - if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + if( secureheapBLOCK_IS_ALLOCATED( pxLink ) != 0 ) { if( pxLink->pxNextFreeBlock == NULL ) { /* The block is being returned to the heap - it is no longer * allocated. */ - pxLink->xBlockSize &= ~xBlockAllocatedBit; + secureheapFREE_BLOCK( pxLink ); secureportDISABLE_NON_SECURE_INTERRUPTS(); {
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_heap.h b/Source/portable/IAR/ARM_CM85/secure/secure_heap.h index 75c9cb0..61a96da 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_heap.h +++ b/Source/portable/IAR/ARM_CM85/secure/secure_heap.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_init.c b/Source/portable/IAR/ARM_CM85/secure/secure_init.c index f93bfce..f7f7e67 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_init.c +++ b/Source/portable/IAR/ARM_CM85/secure/secure_init.c
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -93,7 +93,7 @@ * permitted. CP11 should be programmed to the same value as CP10. */ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK ); - /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures + /* LSPENS = 0 ==> LSPEN is writable from non-secure state. This ensures * that we can enable/disable lazy stacking in port.c file. */ *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_init.h b/Source/portable/IAR/ARM_CM85/secure/secure_init.h index e6c9da0..46ffbd9 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_init.h +++ b/Source/portable/IAR/ARM_CM85/secure/secure_init.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h index d7ac583..34494e1 100644 --- a/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h +++ b/Source/portable/IAR/ARM_CM85/secure/secure_port_macros.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT *
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S index ef180bd..68192e4 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -47,12 +47,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskDelayUntil_Unpriv MPU_xTaskDelayUntil_Priv: - pop {r0} b MPU_xTaskDelayUntilImpl MPU_xTaskDelayUntil_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskDelayUntil /*-----------------------------------------------------------*/ @@ -61,12 +60,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskAbortDelay_Unpriv MPU_xTaskAbortDelay_Priv: - pop {r0} b MPU_xTaskAbortDelayImpl MPU_xTaskAbortDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskAbortDelay /*-----------------------------------------------------------*/ @@ -75,12 +73,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskDelay_Unpriv MPU_vTaskDelay_Priv: - pop {r0} b MPU_vTaskDelayImpl MPU_vTaskDelay_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskDelay /*-----------------------------------------------------------*/ @@ -89,12 +86,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskPriorityGet_Unpriv MPU_uxTaskPriorityGet_Priv: - pop {r0} b MPU_uxTaskPriorityGetImpl MPU_uxTaskPriorityGet_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskPriorityGet /*-----------------------------------------------------------*/ @@ -103,12 +99,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_eTaskGetState_Unpriv MPU_eTaskGetState_Priv: - pop {r0} b MPU_eTaskGetStateImpl MPU_eTaskGetState_Unpriv: - pop {r0} svc #SYSTEM_CALL_eTaskGetState /*-----------------------------------------------------------*/ @@ -117,12 +112,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskGetInfo_Unpriv MPU_vTaskGetInfo_Priv: - pop {r0} b MPU_vTaskGetInfoImpl MPU_vTaskGetInfo_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskGetInfo /*-----------------------------------------------------------*/ @@ -131,12 +125,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetIdleTaskHandle_Unpriv MPU_xTaskGetIdleTaskHandle_Priv: - pop {r0} b MPU_xTaskGetIdleTaskHandleImpl MPU_xTaskGetIdleTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetIdleTaskHandle /*-----------------------------------------------------------*/ @@ -145,12 +138,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSuspend_Unpriv MPU_vTaskSuspend_Priv: - pop {r0} b MPU_vTaskSuspendImpl MPU_vTaskSuspend_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSuspend /*-----------------------------------------------------------*/ @@ -159,12 +151,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskResume_Unpriv MPU_vTaskResume_Priv: - pop {r0} b MPU_vTaskResumeImpl MPU_vTaskResume_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskResume /*-----------------------------------------------------------*/ @@ -173,12 +164,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetTickCount_Unpriv MPU_xTaskGetTickCount_Priv: - pop {r0} b MPU_xTaskGetTickCountImpl MPU_xTaskGetTickCount_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetTickCount /*-----------------------------------------------------------*/ @@ -187,40 +177,24 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetNumberOfTasks_Unpriv MPU_uxTaskGetNumberOfTasks_Priv: - pop {r0} b MPU_uxTaskGetNumberOfTasksImpl MPU_uxTaskGetNumberOfTasks_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetNumberOfTasks /*-----------------------------------------------------------*/ - PUBLIC MPU_pcTaskGetName -MPU_pcTaskGetName: - push {r0} - mrs r0, control - tst r0, #1 - bne MPU_pcTaskGetName_Unpriv - MPU_pcTaskGetName_Priv: - pop {r0} - b MPU_pcTaskGetNameImpl - MPU_pcTaskGetName_Unpriv: - pop {r0} - svc #SYSTEM_CALL_pcTaskGetName -/*-----------------------------------------------------------*/ - PUBLIC MPU_ulTaskGetRunTimeCounter MPU_ulTaskGetRunTimeCounter: push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimeCounter_Unpriv MPU_ulTaskGetRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimeCounter /*-----------------------------------------------------------*/ @@ -229,12 +203,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetRunTimePercent_Unpriv MPU_ulTaskGetRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetRunTimePercentImpl MPU_ulTaskGetRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetRunTimePercent /*-----------------------------------------------------------*/ @@ -243,12 +216,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimePercent_Unpriv MPU_ulTaskGetIdleRunTimePercent_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimePercentImpl MPU_ulTaskGetIdleRunTimePercent_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent /*-----------------------------------------------------------*/ @@ -257,12 +229,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv MPU_ulTaskGetIdleRunTimeCounter_Priv: - pop {r0} b MPU_ulTaskGetIdleRunTimeCounterImpl MPU_ulTaskGetIdleRunTimeCounter_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter /*-----------------------------------------------------------*/ @@ -271,12 +242,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetApplicationTaskTag_Unpriv MPU_vTaskSetApplicationTaskTag_Priv: - pop {r0} b MPU_vTaskSetApplicationTaskTagImpl MPU_vTaskSetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -285,12 +255,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetApplicationTaskTag_Unpriv MPU_xTaskGetApplicationTaskTag_Priv: - pop {r0} b MPU_xTaskGetApplicationTaskTagImpl MPU_xTaskGetApplicationTaskTag_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetApplicationTaskTag /*-----------------------------------------------------------*/ @@ -299,12 +268,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv MPU_vTaskSetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_vTaskSetThreadLocalStoragePointerImpl MPU_vTaskSetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -313,12 +281,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv MPU_pvTaskGetThreadLocalStoragePointer_Priv: - pop {r0} b MPU_pvTaskGetThreadLocalStoragePointerImpl MPU_pvTaskGetThreadLocalStoragePointer_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer /*-----------------------------------------------------------*/ @@ -327,12 +294,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetSystemState_Unpriv MPU_uxTaskGetSystemState_Priv: - pop {r0} b MPU_uxTaskGetSystemStateImpl MPU_uxTaskGetSystemState_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetSystemState /*-----------------------------------------------------------*/ @@ -341,12 +307,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark_Unpriv MPU_uxTaskGetStackHighWaterMark_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMarkImpl MPU_uxTaskGetStackHighWaterMark_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark /*-----------------------------------------------------------*/ @@ -355,12 +320,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTaskGetStackHighWaterMark2_Unpriv MPU_uxTaskGetStackHighWaterMark2_Priv: - pop {r0} b MPU_uxTaskGetStackHighWaterMark2Impl MPU_uxTaskGetStackHighWaterMark2_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2 /*-----------------------------------------------------------*/ @@ -369,12 +333,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetCurrentTaskHandle_Unpriv MPU_xTaskGetCurrentTaskHandle_Priv: - pop {r0} b MPU_xTaskGetCurrentTaskHandleImpl MPU_xTaskGetCurrentTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle /*-----------------------------------------------------------*/ @@ -383,12 +346,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGetSchedulerState_Unpriv MPU_xTaskGetSchedulerState_Priv: - pop {r0} b MPU_xTaskGetSchedulerStateImpl MPU_xTaskGetSchedulerState_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGetSchedulerState /*-----------------------------------------------------------*/ @@ -397,12 +359,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTaskSetTimeOutState_Unpriv MPU_vTaskSetTimeOutState_Priv: - pop {r0} b MPU_vTaskSetTimeOutStateImpl MPU_vTaskSetTimeOutState_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTaskSetTimeOutState /*-----------------------------------------------------------*/ @@ -411,12 +372,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskCheckForTimeOut_Unpriv MPU_xTaskCheckForTimeOut_Priv: - pop {r0} b MPU_xTaskCheckForTimeOutImpl MPU_xTaskCheckForTimeOut_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskCheckForTimeOut /*-----------------------------------------------------------*/ @@ -425,12 +385,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotify_Unpriv MPU_xTaskGenericNotify_Priv: - pop {r0} b MPU_xTaskGenericNotifyImpl MPU_xTaskGenericNotify_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotify /*-----------------------------------------------------------*/ @@ -439,12 +398,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyWait_Unpriv MPU_xTaskGenericNotifyWait_Priv: - pop {r0} b MPU_xTaskGenericNotifyWaitImpl MPU_xTaskGenericNotifyWait_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyWait /*-----------------------------------------------------------*/ @@ -453,12 +411,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyTake_Unpriv MPU_ulTaskGenericNotifyTake_Priv: - pop {r0} b MPU_ulTaskGenericNotifyTakeImpl MPU_ulTaskGenericNotifyTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyTake /*-----------------------------------------------------------*/ @@ -467,12 +424,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTaskGenericNotifyStateClear_Unpriv MPU_xTaskGenericNotifyStateClear_Priv: - pop {r0} b MPU_xTaskGenericNotifyStateClearImpl MPU_xTaskGenericNotifyStateClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTaskGenericNotifyStateClear /*-----------------------------------------------------------*/ @@ -481,12 +437,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_ulTaskGenericNotifyValueClear_Unpriv MPU_ulTaskGenericNotifyValueClear_Priv: - pop {r0} b MPU_ulTaskGenericNotifyValueClearImpl MPU_ulTaskGenericNotifyValueClear_Unpriv: - pop {r0} svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear /*-----------------------------------------------------------*/ @@ -495,12 +450,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGenericSend_Unpriv MPU_xQueueGenericSend_Priv: - pop {r0} b MPU_xQueueGenericSendImpl MPU_xQueueGenericSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGenericSend /*-----------------------------------------------------------*/ @@ -509,12 +463,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueMessagesWaiting_Unpriv MPU_uxQueueMessagesWaiting_Priv: - pop {r0} b MPU_uxQueueMessagesWaitingImpl MPU_uxQueueMessagesWaiting_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueMessagesWaiting /*-----------------------------------------------------------*/ @@ -523,12 +476,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxQueueSpacesAvailable_Unpriv MPU_uxQueueSpacesAvailable_Priv: - pop {r0} b MPU_uxQueueSpacesAvailableImpl MPU_uxQueueSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxQueueSpacesAvailable /*-----------------------------------------------------------*/ @@ -537,12 +489,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueReceive_Unpriv MPU_xQueueReceive_Priv: - pop {r0} b MPU_xQueueReceiveImpl MPU_xQueueReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueReceive /*-----------------------------------------------------------*/ @@ -551,12 +502,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueuePeek_Unpriv MPU_xQueuePeek_Priv: - pop {r0} b MPU_xQueuePeekImpl MPU_xQueuePeek_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueuePeek /*-----------------------------------------------------------*/ @@ -565,12 +515,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSemaphoreTake_Unpriv MPU_xQueueSemaphoreTake_Priv: - pop {r0} b MPU_xQueueSemaphoreTakeImpl MPU_xQueueSemaphoreTake_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSemaphoreTake /*-----------------------------------------------------------*/ @@ -579,12 +528,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGetMutexHolder_Unpriv MPU_xQueueGetMutexHolder_Priv: - pop {r0} b MPU_xQueueGetMutexHolderImpl MPU_xQueueGetMutexHolder_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGetMutexHolder /*-----------------------------------------------------------*/ @@ -593,12 +541,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueTakeMutexRecursive_Unpriv MPU_xQueueTakeMutexRecursive_Priv: - pop {r0} b MPU_xQueueTakeMutexRecursiveImpl MPU_xQueueTakeMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueTakeMutexRecursive /*-----------------------------------------------------------*/ @@ -607,12 +554,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueGiveMutexRecursive_Unpriv MPU_xQueueGiveMutexRecursive_Priv: - pop {r0} b MPU_xQueueGiveMutexRecursiveImpl MPU_xQueueGiveMutexRecursive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueGiveMutexRecursive /*-----------------------------------------------------------*/ @@ -621,12 +567,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueSelectFromSet_Unpriv MPU_xQueueSelectFromSet_Priv: - pop {r0} b MPU_xQueueSelectFromSetImpl MPU_xQueueSelectFromSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueSelectFromSet /*-----------------------------------------------------------*/ @@ -635,12 +580,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xQueueAddToSet_Unpriv MPU_xQueueAddToSet_Priv: - pop {r0} b MPU_xQueueAddToSetImpl MPU_xQueueAddToSet_Unpriv: - pop {r0} svc #SYSTEM_CALL_xQueueAddToSet /*-----------------------------------------------------------*/ @@ -649,12 +593,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueAddToRegistry_Unpriv MPU_vQueueAddToRegistry_Priv: - pop {r0} b MPU_vQueueAddToRegistryImpl MPU_vQueueAddToRegistry_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueAddToRegistry /*-----------------------------------------------------------*/ @@ -663,12 +606,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vQueueUnregisterQueue_Unpriv MPU_vQueueUnregisterQueue_Priv: - pop {r0} b MPU_vQueueUnregisterQueueImpl MPU_vQueueUnregisterQueue_Unpriv: - pop {r0} svc #SYSTEM_CALL_vQueueUnregisterQueue /*-----------------------------------------------------------*/ @@ -677,12 +619,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcQueueGetName_Unpriv MPU_pcQueueGetName_Priv: - pop {r0} b MPU_pcQueueGetNameImpl MPU_pcQueueGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcQueueGetName /*-----------------------------------------------------------*/ @@ -691,12 +632,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pvTimerGetTimerID_Unpriv MPU_pvTimerGetTimerID_Priv: - pop {r0} b MPU_pvTimerGetTimerIDImpl MPU_pvTimerGetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_pvTimerGetTimerID /*-----------------------------------------------------------*/ @@ -705,12 +645,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetTimerID_Unpriv MPU_vTimerSetTimerID_Priv: - pop {r0} b MPU_vTimerSetTimerIDImpl MPU_vTimerSetTimerID_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetTimerID /*-----------------------------------------------------------*/ @@ -719,12 +658,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerIsTimerActive_Unpriv MPU_xTimerIsTimerActive_Priv: - pop {r0} b MPU_xTimerIsTimerActiveImpl MPU_xTimerIsTimerActive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerIsTimerActive /*-----------------------------------------------------------*/ @@ -733,33 +671,25 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv MPU_xTimerGetTimerDaemonTaskHandle_Priv: - pop {r0} b MPU_xTimerGetTimerDaemonTaskHandleImpl MPU_xTimerGetTimerDaemonTaskHandle_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle /*-----------------------------------------------------------*/ - PUBLIC MPU_xTimerGenericCommandEntry -MPU_xTimerGenericCommandEntry: + PUBLIC MPU_xTimerGenericCommandFromTaskEntry +MPU_xTimerGenericCommandFromTaskEntry: push {r0} - /* This function can be called from ISR also and therefore, we need a check - * to take privileged path, if called from ISR. */ - mrs r0, ipsr - cmp r0, #0 - bne MPU_xTimerGenericCommand_Priv mrs r0, control tst r0, #1 - beq MPU_xTimerGenericCommand_Priv - MPU_xTimerGenericCommand_Unpriv: - pop {r0} - svc #SYSTEM_CALL_xTimerGenericCommand - MPU_xTimerGenericCommand_Priv: - pop {r0} - b MPU_xTimerGenericCommandPrivImpl - + pop {r0} + bne MPU_xTimerGenericCommandFromTask_Unpriv + MPU_xTimerGenericCommandFromTask_Priv: + b MPU_xTimerGenericCommandFromTaskImpl + MPU_xTimerGenericCommandFromTask_Unpriv: + svc #SYSTEM_CALL_xTimerGenericCommandFromTask /*-----------------------------------------------------------*/ PUBLIC MPU_pcTimerGetName @@ -767,12 +697,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_pcTimerGetName_Unpriv MPU_pcTimerGetName_Priv: - pop {r0} b MPU_pcTimerGetNameImpl MPU_pcTimerGetName_Unpriv: - pop {r0} svc #SYSTEM_CALL_pcTimerGetName /*-----------------------------------------------------------*/ @@ -781,12 +710,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vTimerSetReloadMode_Unpriv MPU_vTimerSetReloadMode_Priv: - pop {r0} b MPU_vTimerSetReloadModeImpl MPU_vTimerSetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_vTimerSetReloadMode /*-----------------------------------------------------------*/ @@ -795,12 +723,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetReloadMode_Unpriv MPU_xTimerGetReloadMode_Priv: - pop {r0} b MPU_xTimerGetReloadModeImpl MPU_xTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -809,12 +736,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxTimerGetReloadMode_Unpriv MPU_uxTimerGetReloadMode_Priv: - pop {r0} b MPU_uxTimerGetReloadModeImpl MPU_uxTimerGetReloadMode_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxTimerGetReloadMode /*-----------------------------------------------------------*/ @@ -823,12 +749,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetPeriod_Unpriv MPU_xTimerGetPeriod_Priv: - pop {r0} b MPU_xTimerGetPeriodImpl MPU_xTimerGetPeriod_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetPeriod /*-----------------------------------------------------------*/ @@ -837,12 +762,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xTimerGetExpiryTime_Unpriv MPU_xTimerGetExpiryTime_Priv: - pop {r0} b MPU_xTimerGetExpiryTimeImpl MPU_xTimerGetExpiryTime_Unpriv: - pop {r0} svc #SYSTEM_CALL_xTimerGetExpiryTime /*-----------------------------------------------------------*/ @@ -851,12 +775,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupWaitBits_Unpriv MPU_xEventGroupWaitBits_Priv: - pop {r0} b MPU_xEventGroupWaitBitsImpl MPU_xEventGroupWaitBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupWaitBits /*-----------------------------------------------------------*/ @@ -865,12 +788,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupClearBits_Unpriv MPU_xEventGroupClearBits_Priv: - pop {r0} b MPU_xEventGroupClearBitsImpl MPU_xEventGroupClearBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupClearBits /*-----------------------------------------------------------*/ @@ -879,12 +801,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSetBits_Unpriv MPU_xEventGroupSetBits_Priv: - pop {r0} b MPU_xEventGroupSetBitsImpl MPU_xEventGroupSetBits_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSetBits /*-----------------------------------------------------------*/ @@ -893,12 +814,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xEventGroupSync_Unpriv MPU_xEventGroupSync_Priv: - pop {r0} b MPU_xEventGroupSyncImpl MPU_xEventGroupSync_Unpriv: - pop {r0} svc #SYSTEM_CALL_xEventGroupSync /*-----------------------------------------------------------*/ @@ -907,12 +827,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_uxEventGroupGetNumber_Unpriv MPU_uxEventGroupGetNumber_Priv: - pop {r0} b MPU_uxEventGroupGetNumberImpl MPU_uxEventGroupGetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_uxEventGroupGetNumber /*-----------------------------------------------------------*/ @@ -921,12 +840,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_vEventGroupSetNumber_Unpriv MPU_vEventGroupSetNumber_Priv: - pop {r0} b MPU_vEventGroupSetNumberImpl MPU_vEventGroupSetNumber_Unpriv: - pop {r0} svc #SYSTEM_CALL_vEventGroupSetNumber /*-----------------------------------------------------------*/ @@ -935,12 +853,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSend_Unpriv MPU_xStreamBufferSend_Priv: - pop {r0} b MPU_xStreamBufferSendImpl MPU_xStreamBufferSend_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSend /*-----------------------------------------------------------*/ @@ -949,12 +866,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferReceive_Unpriv MPU_xStreamBufferReceive_Priv: - pop {r0} b MPU_xStreamBufferReceiveImpl MPU_xStreamBufferReceive_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferReceive /*-----------------------------------------------------------*/ @@ -963,12 +879,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsFull_Unpriv MPU_xStreamBufferIsFull_Priv: - pop {r0} b MPU_xStreamBufferIsFullImpl MPU_xStreamBufferIsFull_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsFull /*-----------------------------------------------------------*/ @@ -977,12 +892,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferIsEmpty_Unpriv MPU_xStreamBufferIsEmpty_Priv: - pop {r0} b MPU_xStreamBufferIsEmptyImpl MPU_xStreamBufferIsEmpty_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferIsEmpty /*-----------------------------------------------------------*/ @@ -991,12 +905,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSpacesAvailable_Unpriv MPU_xStreamBufferSpacesAvailable_Priv: - pop {r0} b MPU_xStreamBufferSpacesAvailableImpl MPU_xStreamBufferSpacesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSpacesAvailable /*-----------------------------------------------------------*/ @@ -1005,12 +918,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferBytesAvailable_Unpriv MPU_xStreamBufferBytesAvailable_Priv: - pop {r0} b MPU_xStreamBufferBytesAvailableImpl MPU_xStreamBufferBytesAvailable_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferBytesAvailable /*-----------------------------------------------------------*/ @@ -1019,12 +931,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferSetTriggerLevel_Unpriv MPU_xStreamBufferSetTriggerLevel_Priv: - pop {r0} b MPU_xStreamBufferSetTriggerLevelImpl MPU_xStreamBufferSetTriggerLevel_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel /*-----------------------------------------------------------*/ @@ -1033,12 +944,11 @@ push {r0} mrs r0, control tst r0, #1 + pop {r0} bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv MPU_xStreamBufferNextMessageLengthBytes_Priv: - pop {r0} b MPU_xStreamBufferNextMessageLengthBytesImpl MPU_xStreamBufferNextMessageLengthBytes_Unpriv: - pop {r0} svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes /*-----------------------------------------------------------*/ @@ -1089,10 +999,6 @@ MPU_uxTaskGetNumberOfTasksImpl: b MPU_uxTaskGetNumberOfTasksImpl - PUBWEAK MPU_pcTaskGetNameImpl -MPU_pcTaskGetNameImpl: - b MPU_pcTaskGetNameImpl - PUBWEAK MPU_ulTaskGetRunTimeCounterImpl MPU_ulTaskGetRunTimeCounterImpl: b MPU_ulTaskGetRunTimeCounterImpl @@ -1245,9 +1151,9 @@ MPU_xTimerGetTimerDaemonTaskHandleImpl: b MPU_xTimerGetTimerDaemonTaskHandleImpl - PUBWEAK MPU_xTimerGenericCommandPrivImpl -MPU_xTimerGenericCommandPrivImpl: - b MPU_xTimerGenericCommandPrivImpl + PUBWEAK MPU_xTimerGenericCommandFromTaskImpl +MPU_xTimerGenericCommandFromTaskImpl: + b MPU_xTimerGenericCommandFromTaskImpl PUBWEAK MPU_pcTimerGetNameImpl MPU_pcTimerGetNameImpl:
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c index 9712ac3..f16a343 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -54,7 +56,7 @@ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only * i.e. the processor boots as secure and never jumps to the non-secure side. * The Trust Zone support in the port must be disabled in order to run FreeRTOS - * on the secure side. The following are the valid configuration seetings: + * on the secure side. The following are the valid configuration settings: * * 1. Run FreeRTOS on the Secure Side: * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0 @@ -68,6 +70,22 @@ #if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) ) #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side. #endif + +/** + * Cortex-M23 does not have non-secure PSPLIM. We should use PSPLIM on Cortex-M23 + * only when FreeRTOS runs on secure side. + */ +#if ( ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) && ( configRUN_FREERTOS_SECURE_ONLY == 0 ) ) + #define portUSE_PSPLIM_REGISTER 0 +#else + #define portUSE_PSPLIM_REGISTER 1 +#endif +/*-----------------------------------------------------------*/ + +/** + * @brief Prototype of all Interrupt Service Routines (ISRs). + */ +typedef void ( * portISR_t )( void ); /*-----------------------------------------------------------*/ /** @@ -91,8 +109,17 @@ /** * @brief Constants required to manipulate the SCB. */ -#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( volatile uint32_t * ) 0xe000ed24 ) +#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) ) +#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) ) #define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL ) +#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL ) +/*-----------------------------------------------------------*/ + +/** + * @brief Constants used to check the installation of the FreeRTOS interrupt handlers. + */ +#define portVECTOR_INDEX_SVC ( 11 ) +#define portVECTOR_INDEX_PENDSV ( 14 ) /*-----------------------------------------------------------*/ /** @@ -111,8 +138,8 @@ /** * @brief Constants used during system call enter and exit. */ -#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) -#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) +#define portPSR_STACK_PADDING_MASK ( 1UL << 9UL ) +#define portEXC_RETURN_STACK_FRAME_TYPE_MASK ( 1UL << 4UL ) /*-----------------------------------------------------------*/ /** @@ -134,72 +161,79 @@ /** * @brief Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_LR ( 5 ) -#define portOFFSET_TO_PC ( 6 ) -#define portOFFSET_TO_PSR ( 7 ) +#define portOFFSET_TO_LR ( 5 ) +#define portOFFSET_TO_PC ( 6 ) +#define portOFFSET_TO_PSR ( 7 ) /*-----------------------------------------------------------*/ /** * @brief Constants required to manipulate the MPU. */ -#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) -#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) -#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) +#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) ) +#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) +#define portMPU_RNR_REG ( *( ( volatile uint32_t * ) 0xe000ed98 ) ) -#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) -#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) +#define portMPU_RBAR_REG ( *( ( volatile uint32_t * ) 0xe000ed9c ) ) +#define portMPU_RLAR_REG ( *( ( volatile uint32_t * ) 0xe000eda0 ) ) -#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) -#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) +#define portMPU_RBAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda4 ) ) +#define portMPU_RLAR_A1_REG ( *( ( volatile uint32_t * ) 0xe000eda8 ) ) -#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) -#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) +#define portMPU_RBAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edac ) ) +#define portMPU_RLAR_A2_REG ( *( ( volatile uint32_t * ) 0xe000edb0 ) ) -#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) -#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) +#define portMPU_RBAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb4 ) ) +#define portMPU_RLAR_A3_REG ( *( ( volatile uint32_t * ) 0xe000edb8 ) ) -#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) -#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) +#define portMPU_MAIR0_REG ( *( ( volatile uint32_t * ) 0xe000edc0 ) ) +#define portMPU_MAIR1_REG ( *( ( volatile uint32_t * ) 0xe000edc4 ) ) -#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ +#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */ -#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) +#define portMPU_RBAR_ACCESS_PERMISSIONS_MASK ( 3UL << 1UL ) -#define portMPU_MAIR_ATTR0_POS ( 0UL ) -#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR0_POS ( 0UL ) +#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR1_POS ( 8UL ) -#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR1_POS ( 8UL ) +#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR2_POS ( 16UL ) -#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR2_POS ( 16UL ) +#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR3_POS ( 24UL ) -#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR3_POS ( 24UL ) +#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 ) -#define portMPU_MAIR_ATTR4_POS ( 0UL ) -#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) +#define portMPU_MAIR_ATTR4_POS ( 0UL ) +#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff ) -#define portMPU_MAIR_ATTR5_POS ( 8UL ) -#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) +#define portMPU_MAIR_ATTR5_POS ( 8UL ) +#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 ) -#define portMPU_MAIR_ATTR6_POS ( 16UL ) -#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) +#define portMPU_MAIR_ATTR6_POS ( 16UL ) +#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 ) -#define portMPU_MAIR_ATTR7_POS ( 24UL ) -#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) +#define portMPU_MAIR_ATTR7_POS ( 24UL ) +#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 ) -#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) -#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL ) +#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL ) -#define portMPU_RLAR_REGION_ENABLE ( 1UL ) +#define portMPU_RLAR_REGION_ENABLE ( 1UL ) + +#if ( portARMV8M_MINOR_VERSION >= 1 ) + +/* Enable Privileged eXecute Never MPU attribute for the selected memory + * region. */ + #define portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ( 1UL << 4UL ) +#endif /* portARMV8M_MINOR_VERSION >= 1 */ /* Enable privileged access to unmapped region. */ #define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1UL << 2UL ) @@ -343,6 +377,20 @@ * any secure calls. */ #define portNO_SECURE_CONTEXT 0 + +/** + * @brief Constants required to check and configure PACBTI security feature implementation. + */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + #define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) ) + + #define portCONTROL_UPAC_EN ( 1UL << 7UL ) + #define portCONTROL_PAC_EN ( 1UL << 6UL ) + #define portCONTROL_UBTI_EN ( 1UL << 5UL ) + #define portCONTROL_BTI_EN ( 1UL << 4UL ) + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ /*-----------------------------------------------------------*/ /** @@ -351,7 +399,7 @@ */ static void prvTaskExitError( void ); -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief Extract MPU region's access permissions from the Region Base Address @@ -362,7 +410,7 @@ * @return uint32_t Access permissions. */ static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) PRIVILEGED_FUNCTION; -#endif /* configENABLE_MPU */ +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ #if ( configENABLE_MPU == 1 ) @@ -380,6 +428,26 @@ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_FPU */ +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + +/** + * @brief Configures PACBTI features. + * + * This function configures the Pointer Authentication, and Branch Target + * Identification security features as per the user configuration. It returns + * the value of the special purpose CONTROL register accordingly, and optionally + * updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M + * architecture based) target supports PACBTI security feature. + * + * @param xWriteControlRegister Used to control whether the special purpose + * CONTROL register should be updated or not. + * + * @return CONTROL register value according to the configured PACBTI option. + */ + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ); + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + /** * @brief Setup the timer to generate the tick interrupts. * @@ -448,13 +516,13 @@ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) - /** - * @brief Sets up the task stack so that upon returning from - * SVC, the task stack is used again. - * - * @param pulSystemCallStack The current SP when the SVC was raised. - * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. - */ +/** + * @brief Sets up the task stack so that upon returning from + * SVC, the task stack is used again. + * + * @param pulSystemCallStack The current SP when the SVC was raised. + * @param ulLR The value of Link Register (EXC_RETURN) in the SVC handler. + */ void vSystemCallExit( uint32_t * pulSystemCallStack, uint32_t ulLR ) PRIVILEGED_FUNCTION; @@ -462,24 +530,24 @@ #if ( configENABLE_MPU == 1 ) - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ BaseType_t xPortIsTaskPrivileged( void ) PRIVILEGED_FUNCTION; #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ -#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) /** * @brief This variable is set to pdTRUE when the scheduler is started. */ PRIVILEGED_DATA static BaseType_t xSchedulerRunning = pdFALSE; -#endif +#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /** * @brief Each task maintains its own interrupt status in the critical nesting @@ -501,13 +569,13 @@ * FreeRTOS API functions are not called from interrupts that have been assigned * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. */ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) static uint8_t ucMaxSysCallPriority = 0; static uint32_t ulMaxPRIGROUPValue = 0; static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16; -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ #if ( configUSE_TICKLESS_IDLE == 1 ) @@ -531,6 +599,7 @@ /*-----------------------------------------------------------*/ #if ( configUSE_TICKLESS_IDLE == 1 ) + __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ) { uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickDecrementsLeft; @@ -746,6 +815,7 @@ __asm volatile ( "cpsie i" ::: "memory" ); } } + #endif /* configUSE_TICKLESS_IDLE */ /*-----------------------------------------------------------*/ @@ -760,8 +830,15 @@ } #endif /* configUSE_TICKLESS_IDLE */ - /* Stop and reset the SysTick. */ - portNVIC_SYSTICK_CTRL_REG = 0UL; + /* Stop and reset SysTick. + * + * QEMU versions older than 7.0.0 contain a bug which causes an error if we + * enable SysTick without first selecting a valid clock source. We trigger + * the bug if we change clock sources from a clock with a zero clock period + * to one with a nonzero clock period and enable Systick at the same time. + * So we configure the CLKSOURCE bit here, prior to setting the ENABLE bit. + * This workaround avoids the bug in QEMU versions older than 7.0.0. */ + portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT_CONFIG; portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; /* Configure SysTick to interrupt at the requested rate. */ @@ -795,7 +872,8 @@ } /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + static uint32_t prvGetRegionAccessPermissions( uint32_t ulRBARValue ) /* PRIVILEGED_FUNCTION */ { uint32_t ulAccessPermissions = 0; @@ -812,13 +890,16 @@ return ulAccessPermissions; } -#endif /* configENABLE_MPU */ + +#endif /* configENABLE_MPU == 1 && configUSE_MPU_WRAPPERS_V1 == 0 */ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */ { #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -903,10 +984,12 @@ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT ); } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ #if ( configENABLE_FPU == 1 ) + static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */ { #if ( configENABLE_TRUSTZONE == 1 ) @@ -928,6 +1011,7 @@ * LSPEN = 1 ==> Enable lazy context save of FP state. */ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK ); } + #endif /* configENABLE_FPU */ /*-----------------------------------------------------------*/ @@ -972,13 +1056,19 @@ uint32_t ulPreviousMask; ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR(); + traceISR_ENTER(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) { + traceISR_EXIT_TO_SCHEDULER(); /* Pend a context switch. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } + else + { + traceISR_EXIT(); + } } portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask ); } @@ -988,6 +1078,7 @@ { #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1083,18 +1174,24 @@ vRestoreContextOfFirstTask(); break; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) - case portSVC_RAISE_PRIVILEGE: + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) ) + case portSVC_RAISE_PRIVILEGE: - /* Only raise the privilege, if the svc was raised from any of - * the system calls. */ - if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && - ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) - { - vRaisePrivilege(); - } - break; - #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + /* Only raise the privilege, if the svc was raised from any of + * the system calls. */ + if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) && + ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) ) + { + vRaisePrivilege(); + } + break; + #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 1 ) */ + + #if ( configENABLE_MPU == 1 ) + case portSVC_YIELD: + vPortYield(); + break; + #endif /* configENABLE_MPU == 1 */ default: /* Incorrect SVC call. */ @@ -1116,6 +1213,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __syscalls_flash_start__; @@ -1154,12 +1252,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1171,7 +1268,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the system call stack for the stack frame. */ pulSystemCallStack = pulSystemCallStack - ulStackFrameSize; @@ -1190,11 +1287,19 @@ /* Store the value of the PSPLIM register before the SVC was raised. * We need to restore it when we exit from the system call. */ - __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "mrs %0, psplim" : "=r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* Use the pulSystemCallStack in thread mode. */ __asm volatile ( "msr psp, %0" : : "r" ( pulSystemCallStack ) ); - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.pulSystemCallStackLimit ) ); + } + #endif /* Start executing the system call upon returning from this handler. */ pulSystemCallStack[ portOFFSET_TO_PC ] = uxSystemCallImplementations[ ucSystemCallNumber ]; @@ -1224,14 +1329,13 @@ pulSystemCallStack[ portOFFSET_TO_PSR ] &= ( ~portPSR_STACK_PADDING_MASK ); /* Raise the privilege for the duration of the system call. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " bics r0, r1 \n" /* Clear nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1259,6 +1363,7 @@ uint32_t ulStackFrameSize, ulSystemCallLocation, i; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_functions_start__; @@ -1293,12 +1398,11 @@ { /* Extended frame i.e. FPU in use. */ ulStackFrameSize = 26; - __asm volatile - ( + __asm volatile ( " vpush {s0} \n" /* Trigger lazy stacking. */ " vpop {s0} \n" /* Nullify the affect of the above instruction. */ ::: "memory" - ); + ); } else { @@ -1310,7 +1414,7 @@ { ulStackFrameSize = 8; } - #endif /* if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ + #endif /* configENABLE_FPU || configENABLE_MVE */ /* Make space on the task stack for the stack frame. */ pulTaskStack = pulTaskStack - ulStackFrameSize; @@ -1332,7 +1436,11 @@ /* Restore the PSPLIM register to what it was at the time of * system call entry. */ - __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + #if ( portUSE_PSPLIM_REGISTER == 1 ) + { + __asm volatile ( "msr psplim, %0" : : "r" ( pxMpuSettings->xSystemCallStackInfo.ulStackLimitRegisterAtSystemCallEntry ) ); + } + #endif /* If the hardware used padding to force the stack pointer * to be double word aligned, set the stacked xPSR bit[9], @@ -1350,14 +1458,13 @@ pxMpuSettings->xSystemCallStackInfo.pulTaskStack = NULL; /* Drop the privilege before returning to the thread mode. */ - __asm volatile - ( + __asm volatile ( " mrs r0, control \n" /* Obtain current control value. */ " movs r1, #1 \n" /* r1 = 1. */ " orrs r0, r1 \n" /* Set nPRIV bit. */ " msr control, r0 \n" /* Write back new control value. */ ::: "r0", "r1", "memory" - ); + ); } } @@ -1392,6 +1499,7 @@ xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */ { uint32_t ulIndex = 0; + uint32_t ulControl = 0x0; xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */ ulIndex++; @@ -1410,21 +1518,21 @@ xMPUSettings->ulContext[ ulIndex ] = 0x11111111; /* r11. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pvParameters; /* r0. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ + xMPUSettings->ulContext[ ulIndex ] = 0x01010101; /* r1. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ + xMPUSettings->ulContext[ ulIndex ] = 0x02020202; /* r2. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ + xMPUSettings->ulContext[ ulIndex ] = 0x03030303; /* r3. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ + xMPUSettings->ulContext[ ulIndex ] = 0x12121212; /* r12. */ ulIndex++; xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portTASK_RETURN_ADDRESS; /* LR. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxCode; /* PC. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_XPSR; /* xPSR. */ ulIndex++; #if ( configENABLE_TRUSTZONE == 1 ) @@ -1435,20 +1543,30 @@ #endif /* configENABLE_TRUSTZONE */ xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) ( pxTopOfStack - 8 ); /* PSP with the hardware saved stack. */ ulIndex++; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ + xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */ ulIndex++; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Check PACBTI security feature configuration before pushing the + * CONTROL register's value on task's TCB. */ + ulControl = prvConfigurePACBTI( pdFALSE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ + if( xRunPrivileged == pdTRUE ) { xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG; - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */ ulIndex++; } else { xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG ); - xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */ + xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */ ulIndex++; } + xMPUSettings->ulContext[ ulIndex ] = portINITIAL_EXC_RETURN; /* LR (EXC_RETURN). */ ulIndex++; @@ -1469,6 +1587,20 @@ } #endif /* configUSE_MPU_WRAPPERS_V1 == 0 */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + xMPUSettings->ulContext[ ulIndex ] = ulTaskPacKey[ i ]; + ulIndex++; + } + } + #endif /* configENABLE_PAC */ + return &( xMPUSettings->ulContext[ ulIndex ] ); } @@ -1483,7 +1615,7 @@ * interrupt. */ #if ( portPRELOAD_REGISTERS == 0 ) { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1505,7 +1637,7 @@ } #else /* portPRELOAD_REGISTERS */ { - pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ + pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */ *pxTopOfStack = portINITIAL_XPSR; /* xPSR. */ pxTopOfStack--; *pxTopOfStack = ( StackType_t ) pxCode; /* PC. */ @@ -1540,7 +1672,7 @@ pxTopOfStack--; *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN. */ pxTopOfStack--; - *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ + *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */ #if ( configENABLE_TRUSTZONE == 1 ) { @@ -1551,6 +1683,20 @@ } #endif /* portPRELOAD_REGISTERS */ + #if ( configENABLE_PAC == 1 ) + { + uint32_t ulTaskPacKey[ 4 ], i; + + vApplicationGenerateTaskRandomPacKey( &( ulTaskPacKey[ 0 ] ) ); + + for( i = 0; i < 4; i++ ) + { + pxTopOfStack--; + *pxTopOfStack = ulTaskPacKey[ i ]; + } + } + #endif /* configENABLE_PAC */ + return pxTopOfStack; } @@ -1559,22 +1705,52 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ { - #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) + /* An application can install FreeRTOS interrupt handlers in one of the + * following ways: + * 1. Direct Routing - Install the functions SVC_Handler and PendSV_Handler + * for SVCall and PendSV interrupts respectively. + * 2. Indirect Routing - Install separate handlers for SVCall and PendSV + * interrupts and route program control from those handlers to + * SVC_Handler and PendSV_Handler functions. + * + * Applications that use Indirect Routing must set + * configCHECK_HANDLER_INSTALLATION to 0 in their FreeRTOSConfig.h. Direct + * routing, which is validated here when configCHECK_HANDLER_INSTALLATION + * is 1, should be preferred when possible. */ + #if ( configCHECK_HANDLER_INSTALLATION == 1 ) { - volatile uint32_t ulOriginalPriority; + const portISR_t * const pxVectorTable = portSCB_VTOR_REG; + + /* Validate that the application has correctly installed the FreeRTOS + * handlers for SVCall and PendSV interrupts. We do not check the + * installation of the SysTick handler because the application may + * choose to drive the RTOS tick using a timer other than the SysTick + * timer by overriding the weak function vPortSetupTimerInterrupt(). + * + * Assertion failures here indicate incorrect installation of the + * FreeRTOS handlers. For help installing the FreeRTOS handlers, see + * https://www.freertos.org/Why-FreeRTOS/FAQs. + * + * Systems with a configurable address for the interrupt vector table + * can also encounter assertion failures or even system faults here if + * VTOR is not set correctly to point to the application's vector table. */ + configASSERT( pxVectorTable[ portVECTOR_INDEX_SVC ] == SVC_Handler ); + configASSERT( pxVectorTable[ portVECTOR_INDEX_PENDSV ] == PendSV_Handler ); + } + #endif /* configCHECK_HANDLER_INSTALLATION */ + + #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) + { volatile uint32_t ulImplementedPrioBits = 0; volatile uint8_t ucMaxPriorityValue; /* Determine the maximum priority from which ISR safe FreeRTOS API - * functions can be called. ISR safe functions are those that end in - * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to * ensure interrupt entry is as fast and simple as possible. * - * Save the interrupt priority value that is about to be clobbered. */ - ulOriginalPriority = portNVIC_SHPR2_REG; - - /* Determine the number of priority bits available. First write to all - * possible bits. */ + * First, determine the number of priority bits available. Write to all + * possible bits in the priority setting for SVCall. */ portNVIC_SHPR2_REG = 0xFF000000; /* Read the value back to see how many bits stuck. */ @@ -1593,11 +1769,10 @@ /* Check that the bits not implemented in hardware are zero in * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ - configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( uint8_t ) ( ~( uint32_t ) ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ - while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) { ulImplementedPrioBits++; @@ -1635,16 +1810,22 @@ * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - - /* Restore the clobbered interrupt priority register to its original - * value. */ - portNVIC_SHPR2_REG = ulOriginalPriority; } - #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ + #endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ - /* Make PendSV, CallSV and SysTick the same priority as the kernel. */ + /* Make PendSV and SysTick the lowest priority interrupts, and make SVCall + * the highest priority. */ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + portNVIC_SHPR2_REG = 0; + + #if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + { + /* Set the CONTROL register value based on PACBTI security feature + * configuration before starting the first task. */ + ( void ) prvConfigurePACBTI( pdTRUE ); + } + #endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ #if ( configENABLE_MPU == 1 ) { @@ -1660,11 +1841,11 @@ /* Initialize the critical nesting count ready for the first task. */ ulCriticalNesting = 0; - #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) + #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) { xSchedulerRunning = pdTRUE; } - #endif + #endif /* ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /* Start the first task. */ vStartFirstTask(); @@ -1692,15 +1873,17 @@ /*-----------------------------------------------------------*/ #if ( configENABLE_MPU == 1 ) + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t * pxBottomOfStack, - uint32_t ulStackDepth ) + configSTACK_DEPTH_TYPE uxStackDepth ) { uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber; int32_t lIndex = 0; #if defined( __ARMCC_VERSION ) + /* Declaration when these variable are defined in code instead of being * exported from linker scripts. */ extern uint32_t * __privileged_sram_start__; @@ -1719,10 +1902,10 @@ * which case the stack region parameters will be valid. At all other * times the stack parameters will not be valid and it is assumed that * the stack region has already been configured. */ - if( ulStackDepth > 0 ) + if( uxStackDepth > 0 ) { ulRegionStartAddress = ( uint32_t ) pxBottomOfStack; - ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1; + ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( uxStackDepth * ( configSTACK_DEPTH_TYPE ) sizeof( StackType_t ) ) - 1; /* If the stack is within the privileged SRAM, do not protect it * using a separate MPU region. This is needed because privileged @@ -1790,6 +1973,16 @@ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) | ( portMPU_RLAR_REGION_ENABLE ); + /* PXN. */ + #if ( portARMV8M_MINOR_VERSION >= 1 ) + { + if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ) != 0 ) + { + xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= ( portMPU_RLAR_PRIVILEGED_EXECUTE_NEVER ); + } + } + #endif /* portARMV8M_MINOR_VERSION >= 1 */ + /* Normal memory/ Device memory. */ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 ) { @@ -1812,10 +2005,12 @@ lIndex++; } } + #endif /* configENABLE_MPU */ /*-----------------------------------------------------------*/ -#if ( configENABLE_MPU == 1 ) +#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) + BaseType_t xPortIsAuthorizedToAccessBuffer( const void * pvBuffer, uint32_t ulBufferLength, uint32_t ulAccessRequested ) /* PRIVILEGED_FUNCTION */ @@ -1825,7 +2020,15 @@ BaseType_t xAccessGranted = pdFALSE; const xMPU_SETTINGS * xTaskMpuSettings = xTaskGetMPUSettings( NULL ); /* Calling task's MPU settings. */ - if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) + if( xSchedulerRunning == pdFALSE ) + { + /* Grant access to all the kernel objects before the scheduler + * is started. It is necessary because there is no task running + * yet and therefore, we cannot use the permissions of any + * task. */ + xAccessGranted = pdTRUE; + } + else if( ( xTaskMpuSettings->ulTaskFlags & portTASK_IS_PRIVILEGED_FLAG ) == portTASK_IS_PRIVILEGED_FLAG ) { xAccessGranted = pdTRUE; } @@ -1860,7 +2063,8 @@ return xAccessGranted; } -#endif /* configENABLE_MPU */ + +#endif /* #if ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */ /*-----------------------------------------------------------*/ BaseType_t xPortIsInsideInterrupt( void ) @@ -1886,7 +2090,7 @@ } /*-----------------------------------------------------------*/ -#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) +#if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) void vPortValidateInterruptPriority( void ) { @@ -1924,7 +2128,7 @@ * * The following links provide detailed information: * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html - * https://www.FreeRTOS.org/FAQHelp.html */ + * https://www.freertos.org/Why-FreeRTOS/FAQs */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); } @@ -1944,7 +2148,7 @@ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); } -#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_BASEPRI == 1 ) ) */ +#endif /* #if ( ( configASSERT_DEFINED == 1 ) && ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) ) */ /*-----------------------------------------------------------*/ #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) @@ -2041,3 +2245,38 @@ #endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */ /*-----------------------------------------------------------*/ + +#if ( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) ) + + static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister ) + { + uint32_t ulControl = 0x0; + + /* Ensure that PACBTI is implemented. */ + configASSERT( portID_ISAR5_REG != 0x0 ); + + /* Enable UsageFault exception. */ + portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT; + + #if ( configENABLE_PAC == 1 ) + { + ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN ); + } + #endif + + #if ( configENABLE_BTI == 1 ) + { + ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN ); + } + #endif + + if( xWriteControlRegister == pdTRUE ) + { + __asm volatile ( "msr control, %0" : : "r" ( ulControl ) ); + } + + return ulControl; + } + +#endif /* configENABLE_PAC == 1 || configENABLE_BTI == 1 */ +/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h index f64ceb5..53b4b6e 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -52,7 +52,7 @@ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL * register. * - * @note This is a privileged function and should only be called from the kenrel + * @note This is a privileged function and should only be called from the kernel * code. * * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s index 00ee5a5..8092255 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -140,6 +142,14 @@ ldr r1, [r0] /* r1 = Location of saved context in TCB. */ restore_special_regs_first_task: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ msr psp, r2 msr psplim, r3 @@ -163,10 +173,20 @@ ldr r1, [r2] /* Read pxCurrentTCB. */ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */ +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r1-r4} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r1 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r2 + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_0, r4 + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */ msr psplim, r1 /* Set this task's PSPLIM value. */ - movs r1, #2 /* r1 = 2. */ - msr CONTROL, r1 /* Switch to use PSP in the thread mode. */ + mrs r1, control /* Obtain current control register value. */ + orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */ + msr control, r1 /* Write back the new control register value. */ adds r0, #32 /* Discard everything up to r0. */ msr psp, r0 /* This is now the new top of stack to use in the task. */ isb @@ -199,7 +219,7 @@ ulSetInterruptMask: mrs r0, basepri /* r0 = basepri. Return original basepri value. */ mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r1 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bx lr /* Return. */ @@ -230,7 +250,6 @@ vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */ sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */ #endif /* configENABLE_FPU || configENABLE_MVE */ - stmia r1!, {r4-r11} /* Store r4-r11. */ ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */ stmia r1!, {r4-r11} /* Store the hardware saved context. */ @@ -239,11 +258,20 @@ mrs r3, psplim /* r3 = PSPLIM. */ mrs r4, control /* r4 = CONTROL. */ stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */ + #if ( configENABLE_PAC == 1 ) + mrs r2, PAC_KEY_P_0 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_2 + mrs r5, PAC_KEY_P_3 + stmia r1!, {r2-r5} /* Store the task's dedicated PAC key on the task's context. */ + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ + str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */ select_next_task: mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -297,6 +325,14 @@ ldr r1, [r0] /* r1 = Location of saved context in TCB. */ restore_special_regs: + #if ( configENABLE_PAC == 1 ) + ldmdb r1!, {r2-r5} /* Read task's dedicated PAC key from the task's context. */ + msr PAC_KEY_P_0, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_1, r3 + msr PAC_KEY_P_2, r4 + msr PAC_KEY_P_3, r5 + clrm {r2-r5} /* Clear r2-r5. */ + #endif /* configENABLE_PAC */ ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */ msr psp, r2 msr psplim, r3 @@ -332,12 +368,21 @@ mov r3, lr /* r3 = LR/EXC_RETURN. */ stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */ +#if ( configENABLE_PAC == 1 ) + mrs r1, PAC_KEY_P_3 /* Read task's dedicated PAC key from the PAC key registers. */ + mrs r2, PAC_KEY_P_2 + mrs r3, PAC_KEY_P_1 + mrs r4, PAC_KEY_P_0 + stmdb r0!, {r1-r4} /* Store the task's dedicated PAC key on the stack. */ + clrm {r1-r4} /* Clear r1-r4. */ +#endif /* configENABLE_PAC */ + ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */ ldr r1, [r2] /* Read pxCurrentTCB. */ str r0, [r1] /* Save the new top of stack in TCB. */ mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */ + msr basepri, r0 /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */ dsb isb bl vTaskSwitchContext @@ -348,6 +393,15 @@ ldr r1, [r2] /* Read pxCurrentTCB. */ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */ +#if ( configENABLE_PAC == 1 ) + ldmia r0!, {r2-r5} /* Read task's dedicated PAC key from stack. */ + msr PAC_KEY_P_3, r2 /* Write the task's dedicated PAC key to the PAC key registers. */ + msr PAC_KEY_P_2, r3 + msr PAC_KEY_P_1, r4 + msr PAC_KEY_P_0, r5 + clrm {r2-r5} /* Clear r2-r5. */ +#endif /* configENABLE_PAC */ + ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h index ee5baf1..2f1676c 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacro.h
@@ -1,6 +1,6 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. * * SPDX-License-Identifier: MIT * @@ -53,9 +53,10 @@ /** * Architecture specifics. */ -#define portARCH_NAME "Cortex-M85" -#define portHAS_BASEPRI 1 -#define portDONT_DISCARD __root +#define portARCH_NAME "Cortex-M85" +#define portHAS_ARMV8M_MAIN_EXTENSION 1 +#define portARMV8M_MINOR_VERSION 1 +#define portDONT_DISCARD __root /*-----------------------------------------------------------*/ /* ARMv8-M common port configurations. */ @@ -65,8 +66,8 @@ /** * @brief Critical section management. */ -#define portDISABLE_INTERRUPTS() ulSetInterruptMask() -#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) +#define portDISABLE_INTERRUPTS() ulSetInterruptMask() +#define portENABLE_INTERRUPTS() vClearInterruptMask( 0 ) /*-----------------------------------------------------------*/ /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h index 6f666da..2dfac6a 100644 --- a/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h +++ b/Source/portable/IAR/ARM_CM85_NTZ/non_secure/portmacrocommon.h
@@ -1,6 +1,8 @@ /* - * FreeRTOS Kernel V10.6.2 - * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * FreeRTOS Kernel V11.2.0 + * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Copyright 2024 Arm Limited and/or its affiliates + * <open-source-office@arm.com> * * SPDX-License-Identifier: MIT * @@ -117,7 +119,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */; #if ( configENABLE_TRUSTZONE == 1 ) - extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ + extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */ extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */; #endif /* configENABLE_TRUSTZONE */ @@ -125,6 +127,18 @@ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */; extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */; #endif /* configENABLE_MPU */ + +#if ( configENABLE_PAC == 1 ) + + /** + * @brief Generates 128-bit task's random PAC key. + * + * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be + * filled with a 128-bit random number. + */ + void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey ); + +#endif /* configENABLE_PAC */ /*-----------------------------------------------------------*/ /** @@ -137,7 +151,7 @@ #define portPRIVILEGE_BIT ( 0x0UL ) #endif /* configENABLE_MPU */ -/* MPU settings that can be overriden in FreeRTOSConfig.h. */ +/* MPU settings that can be overridden in FreeRTOSConfig.h. */ #ifndef configTOTAL_MPU_REGIONS /* Define to 8 for backward compatibility. */ #define configTOTAL_MPU_REGIONS ( 8UL ) @@ -193,8 +207,8 @@ */ typedef struct MPURegionSettings { - uint32_t ulRBAR; /**< RBAR for the region. */ - uint32_t ulRLAR; /**< RLAR for the region. */ + uint32_t ulRBAR; /**< RBAR for the region. */ + uint32_t ulRLAR; /**< RLAR for the region. */ } MPURegionSettings_t; #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) @@ -223,7 +237,20 @@ */ #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><-----------------------------><-----------><----> + * 16 17 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 71 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +-----------+---------------+----------+-----------------+------------------------------+-----+ @@ -232,11 +259,24 @@ * +-----------+---------------+----------+-----------------+------------------------------+-----+ * * <-----------><--------------><---------><----------------><-----------------------------><----> - * 16 16 8 8 5 1 + * 16 17 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 54 + #define MAX_CONTEXT_SIZE 55 - #else /* #if( configENABLE_TRUSTZONE == 1 ) */ + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * | s16-s31 | s0-s15, FPSCR | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | | | PC, xPSR | EXC_RETURN | | | + * +-----------+---------------+----------+-----------------+----------------------+------------+-----+ + * + * <-----------><--------------><---------><----------------><---------------------><-----------><----> + * 16 17 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 70 + + #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ /* * +-----------+---------------+----------+-----------------+----------------------+-----+ @@ -245,15 +285,28 @@ * +-----------+---------------+----------+-----------------+----------------------+-----+ * * <-----------><--------------><---------><----------------><---------------------><----> - * 16 16 8 8 4 1 + * 16 17 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 53 + #define MAX_CONTEXT_SIZE 54 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ - #if( configENABLE_TRUSTZONE == 1 ) + #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+------------------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey | | + * | | PC, xPSR | CONTROL, EXC_RETURN | | | + * +----------+-----------------+------------------------------+------------+-----+ + * + * <---------><----------------><------------------------------><-----------><----> + * 8 8 5 16 1 + */ + #define MAX_CONTEXT_SIZE 38 + + #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) ) /* * +----------+-----------------+------------------------------+-----+ @@ -264,7 +317,20 @@ * <---------><----------------><------------------------------><----> * 8 8 5 1 */ - #define MAX_CONTEXT_SIZE 22 + #define MAX_CONTEXT_SIZE 22 + + #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) ) + + /* + * +----------+-----------------+----------------------+------------+-----+ + * | r4-r11 | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey | | + * | | PC, xPSR | EXC_RETURN | | | + * +----------+-----------------+----------------------+------------+-----+ + * + * <---------><----------------><----------------------><-----------><----> + * 8 8 4 16 1 + */ + #define MAX_CONTEXT_SIZE 37 #else /* #if( configENABLE_TRUSTZONE == 1 ) */ @@ -277,17 +343,17 @@ * <---------><----------------><----------------------><----> * 8 8 4 1 */ - #define MAX_CONTEXT_SIZE 21 + #define MAX_CONTEXT_SIZE 21 - #endif /* #if( configENABLE_TRUSTZONE == 1 ) */ + #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */ #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */ /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */ - #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) - #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) + #define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL ) + #define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL ) -/* Size of an Access Control List (ACL) entry in bits. */ + /* Size of an Access Control List (ACL) entry in bits. */ #define portACL_ENTRY_SIZE_BITS ( 32U ) typedef struct MPU_SETTINGS @@ -312,8 +378,8 @@ * @brief Validate priority of ISRs that are allowed to call FreeRTOS * system calls. */ -#ifdef configASSERT - #if ( portHAS_BASEPRI == 1 ) +#if ( configASSERT_DEFINED == 1 ) + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) void vPortValidateInterruptPriority( void ); #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() #endif @@ -333,12 +399,29 @@ /** * @brief Scheduler utilities. */ -#define portYIELD() vPortYield() +#if ( configENABLE_MPU == 1 ) + #define portYIELD() __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" ) + #define portYIELD_WITHIN_API() vPortYield() +#else + #define portYIELD() vPortYield() + #define portYIELD_WITHIN_API() vPortYield() +#endif + #define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) #define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) -#define portEND_SWITCHING_ISR( xSwitchRequired ) \ - do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \ - while( 0 ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) \ + do \ + { \ + if( xSwitchRequired ) \ + { \ + traceISR_EXIT_TO_SCHEDULER(); \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + } \ + else \ + { \ + traceISR_EXIT(); \ + } \ + } while( 0 ) #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) /*-----------------------------------------------------------*/ @@ -424,12 +507,12 @@ extern BaseType_t xPortIsTaskPrivileged( void ); - /** - * @brief Checks whether or not the calling task is privileged. - * - * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. - */ - #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() +/** + * @brief Checks whether or not the calling task is privileged. + * + * @return pdTRUE if the calling task is privileged, pdFALSE otherwise. + */ + #define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged() #endif /* configENABLE_MPU == 1 */ /*-----------------------------------------------------------*/ @@ -440,6 +523,56 @@ #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) /*-----------------------------------------------------------*/ +/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION + * based on whether or not Mainline extension is implemented. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 ) + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 + #else + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 + #endif +#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/** + * @brief Port-optimised task selection. + */ +#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 ) + +/** + * @brief Count the number of leading zeros in a 32-bit value. + */ + static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap ) + { + uint32_t ulReturn; + + __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" ); + + return ulReturn; + } + +/* Check the configuration. */ + #if ( configMAX_PRIORITIES > 32 ) + #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice. + #endif + + #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 ) + #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection. Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined. + #endif + +/** + * @brief Store/clear the ready priorities in a bit map. + */ + #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) + #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/** + * @brief Get the priority of the highest-priority task that is ready to execute. + */ + #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ +/*-----------------------------------------------------------*/ + /* *INDENT-OFF* */ #ifdef __cplusplus }