Release v10.2.1_20200117
diff --git a/License/license.txt b/License/license.txt
index 0072310..2977d52 100644
--- a/License/license.txt
+++ b/License/license.txt
@@ -17,7 +17,7 @@
License text:
-------------
-Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
diff --git a/README.md b/README.md
index 4e80f18..991bdb4 100644
--- a/README.md
+++ b/README.md
@@ -40,6 +40,7 @@
FreeRTOS | CMSIS Core |
-------- | ---------- |
Tag v10.0.1 | Tag v5.4.0
+Tag v10.2.1 | Tag v5.4.0
## Troubleshooting
diff --git a/Source/CMSIS_RTOS/cmsis_os.c b/Source/CMSIS_RTOS/cmsis_os.c
index 72f23ad..89c3633 100644
--- a/Source/CMSIS_RTOS/cmsis_os.c
+++ b/Source/CMSIS_RTOS/cmsis_os.c
@@ -364,7 +364,7 @@
1, // period should be filled when starting the Timer using osTimerStart
(type == osTimerPeriodic) ? pdTRUE : pdFALSE,
(void *) argument,
- (TaskFunction_t)timer_def->ptimer,
+ (TimerCallbackFunction_t)timer_def->ptimer,
(StaticTimer_t *)timer_def->controlblock);
}
else {
@@ -372,21 +372,21 @@
1, // period should be filled when starting the Timer using osTimerStart
(type == osTimerPeriodic) ? pdTRUE : pdFALSE,
(void *) argument,
- (TaskFunction_t)timer_def->ptimer);
+ (TimerCallbackFunction_t)timer_def->ptimer);
}
#elif( configSUPPORT_STATIC_ALLOCATION == 1 )
return xTimerCreateStatic((const char *)"",
1, // period should be filled when starting the Timer using osTimerStart
(type == osTimerPeriodic) ? pdTRUE : pdFALSE,
(void *) argument,
- (TaskFunction_t)timer_def->ptimer,
+ (TimerCallbackFunction_t)timer_def->ptimer,
(StaticTimer_t *)timer_def->controlblock);
#else
return xTimerCreate((const char *)"",
1, // period should be filled when starting the Timer using osTimerStart
(type == osTimerPeriodic) ? pdTRUE : pdFALSE,
(void *) argument,
- (TaskFunction_t)timer_def->ptimer);
+ (TimerCallbackFunction_t)timer_def->ptimer);
#endif
#else
diff --git a/Source/CMSIS_RTOS_V2/cmsis_os.h b/Source/CMSIS_RTOS_V2/cmsis_os.h
index 3b885bb..711408a 100644
--- a/Source/CMSIS_RTOS_V2/cmsis_os.h
+++ b/Source/CMSIS_RTOS_V2/cmsis_os.h
@@ -1,7 +1,5 @@
-/* --------------------------------------------------------------------------
- * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved.
- * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved.
- * --------------------------------------------------------------------------
+/*
+ * Copyright (c) 2013-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -17,8 +15,13 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*
+ * ----------------------------------------------------------------------
+ *
+ * $Date: 10. January 2017
+ * $Revision: V2.1.0
+ *
* Project: CMSIS-RTOS API
- * Title: cmsis_os.h header file
+ * Title: cmsis_os.h FreeRTOS header file
*
* Version 0.02
* Initial Proposal Phase
@@ -36,7 +39,7 @@
* Version 1.02
* Control functions for short timeouts in microsecond resolution:
* Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
- * Removed: osSignalGet
+ * Removed: osSignalGet
* Version 2.0.0
* OS objects creation without macros (dynamic creation and resource allocation):
* - added: osXxxxNew functions which replace osXxxxCreate
@@ -64,7 +67,7 @@
* - added: osThreadSuspend, osThreadResume
* - added: osThreadJoin, osThreadDetach, osThreadExit
* - added: osThreadGetCount, osThreadEnumerate
- * - added: Thread Flags (moved from Signals)
+ * - added: Thread Flags (moved from Signals)
* Signals:
* - renamed osSignals to osThreadFlags (moved to Thread Flags)
* - changed return value of Set/Clear/Wait functions
@@ -107,7 +110,7 @@
* - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize
* - added: osMessageQueueGetCount, osMessageQueueGetSpace
* - added: osMessageQueueReset, osMessageQueueDelete
- * Mail Queue:
+ * Mail Queue:
* - deprecated (superseded by extended Message Queue functionality)
* Version 2.1.0
* Support for critical and uncritical sections (nesting safe):
@@ -116,16 +119,22 @@
* Updated Thread and Event Flags:
* - changed flags parameter and return type from int32_t to uint32_t
*---------------------------------------------------------------------------*/
-
+
#ifndef CMSIS_OS_H_
#define CMSIS_OS_H_
-#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0])
+#include "FreeRTOS.h"
+#include "task.h"
-#define osCMSIS_FreeRTOS 0xA0001U ///< RTOS identification and version (main[31:16].sub[15:0])
+#define RTOS_ID_n ((tskKERNEL_VERSION_MAJOR << 16) | (tskKERNEL_VERSION_MINOR))
+#define RTOS_ID_s ("FreeRTOS " tskKERNEL_VERSION_NUMBER)
-#define osKernelSystemId "FreeRTOS V10.0.1" ///< RTOS identification string
+#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0])
+#define osCMSIS_FreeRTOS RTOS_ID_n ///< RTOS identification and version (main[31:16].sub[15:0])
+
+#define osKernelSystemId RTOS_ID_s ///< RTOS identification string
+
#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available
#define osFeature_Signals 24U ///< maximum number of Signal Flags available per thread
#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function
@@ -134,7 +143,7 @@
#define osFeature_Pool 0 ///< Memory Pools: 1=available, 0=not available
#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
#define osFeature_MailQ 0 ///< Mail Queues: 1=available, 0=not available
-
+
#if defined(__CC_ARM)
#define os_InRegs __value_in_regs
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -142,18 +151,17 @@
#else
#define os_InRegs
#endif
-
+
#include "cmsis_os2.h"
-#include "FreeRTOS.h"
-
+
#ifdef __cplusplus
extern "C"
{
#endif
-
-
+
+
// ==== Enumerations, structures, defines ====
-
+
/// Priority values.
#if (osCMSIS < 0x20000U)
typedef enum {
@@ -173,10 +181,10 @@
/// Entry point of a thread.
typedef void (*os_pthread) (void const *argument);
-
+
/// Entry point of a timer call back function.
typedef void (*os_ptimer) (void const *argument);
-
+
/// Timer type.
#if (osCMSIS < 0x20000U)
typedef enum {
@@ -186,10 +194,10 @@
#else
#define os_timer_type osTimerType_t
#endif
-
+
/// Timeout value.
#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value.
-
+
/// Status code values returned by CMSIS-RTOS functions.
#if (osCMSIS < 0x20000U)
typedef enum {
@@ -221,48 +229,48 @@
#define osErrorValue (-127)
#define osErrorPriority (-128)
#endif
-
-
+
+
// >>> the following data type definitions may be adapted towards a specific RTOS
-
+
/// Thread ID identifies the thread.
#if (osCMSIS < 0x20000U)
typedef void *osThreadId;
#else
#define osThreadId osThreadId_t
#endif
-
+
/// Timer ID identifies the timer.
#if (osCMSIS < 0x20000U)
typedef void *osTimerId;
#else
#define osTimerId osTimerId_t
#endif
-
+
/// Mutex ID identifies the mutex.
#if (osCMSIS < 0x20000U)
typedef void *osMutexId;
#else
#define osMutexId osMutexId_t
#endif
-
+
/// Semaphore ID identifies the semaphore.
#if (osCMSIS < 0x20000U)
typedef void *osSemaphoreId;
#else
#define osSemaphoreId osSemaphoreId_t
#endif
-
+
/// Pool ID identifies the memory pool.
typedef void *osPoolId;
-
+
/// Message ID identifies the message queue.
typedef void *osMessageQId;
-
+
/// Mail ID identifies the mail queue.
typedef void *osMailQId;
-
-
+
+
/// Thread Definition structure contains startup information of a thread.
#if (osCMSIS < 0x20000U)
typedef struct os_thread_def {
@@ -277,7 +285,7 @@
osThreadAttr_t attr; ///< thread attributes
} osThreadDef_t;
#endif
-
+
/// Timer Definition structure contains timer parameters.
#if (osCMSIS < 0x20000U)
typedef struct os_timer_def {
@@ -289,7 +297,7 @@
osTimerAttr_t attr; ///< timer attributes
} osTimerDef_t;
#endif
-
+
/// Mutex Definition structure contains setup information for a mutex.
#if (osCMSIS < 0x20000U)
typedef struct os_mutex_def {
@@ -298,7 +306,7 @@
#else
#define osMutexDef_t osMutexAttr_t
#endif
-
+
/// Semaphore Definition structure contains setup information for a semaphore.
#if (osCMSIS < 0x20000U)
typedef struct os_semaphore_def {
@@ -307,7 +315,7 @@
#else
#define osSemaphoreDef_t osSemaphoreAttr_t
#endif
-
+
/// Definition structure for memory block allocation.
#if (osCMSIS < 0x20000U)
typedef struct os_pool_def {
@@ -322,7 +330,7 @@
osMemoryPoolAttr_t attr; ///< memory pool attributes
} osPoolDef_t;
#endif
-
+
/// Definition structure for message queue.
#if (osCMSIS < 0x20000U)
typedef struct os_messageQ_def {
@@ -335,7 +343,7 @@
osMessageQueueAttr_t attr; ///< message queue attributes
} osMessageQDef_t;
#endif
-
+
/// Definition structure for mail queue.
#if (osCMSIS < 0x20000U)
typedef struct os_mailQ_def {
@@ -352,8 +360,8 @@
osMessageQueueAttr_t mq_attr; ///< message queue attributes
} osMailQDef_t;
#endif
-
-
+
+
/// Event structure contains detailed information about an event.
typedef struct {
osStatus status; ///< status code: event or error information
@@ -367,44 +375,44 @@
osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
} def; ///< event definition
} osEvent;
-
-
+
+
// ==== Kernel Management Functions ====
-
+
/// Initialize the RTOS Kernel for creating objects.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osKernelInitialize (void);
#endif
-
+
/// Start the RTOS Kernel scheduler.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osKernelStart (void);
#endif
-
+
/// Check if the RTOS kernel is already started.
/// \return 0 RTOS is not started, 1 RTOS is started.
#if (osCMSIS < 0x20000U)
int32_t osKernelRunning(void);
#endif
-
+
#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
-
+
/// Get the RTOS kernel system timer counter.
-/// \return RTOS kernel system timer as 32-bit value
+/// \return RTOS kernel system timer as 32-bit value
#if (osCMSIS < 0x20000U)
uint32_t osKernelSysTick (void);
#else
#define osKernelSysTick osKernelGetSysTimerCount
#endif
-
+
/// The RTOS kernel system timer frequency in Hz.
/// \note Reflects the system timer setting and is typically defined in a configuration file.
#if (osCMSIS < 0x20000U)
#define osKernelSysTickFrequency 100000000
#endif
-
+
/// Convert a microseconds value to a RTOS kernel system timer value.
/// \param microsec time value in microseconds.
/// \return time value normalized to the \ref osKernelSysTickFrequency
@@ -413,23 +421,23 @@
#else
#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000)
#endif
-
+
#endif // System Timer available
-
-
+
+
// ==== Thread Management Functions ====
-
+
/// Create a Thread Definition with function, priority, and stack requirements.
/// \param name name of the thread function.
/// \param priority initial priority of the thread function.
-/// \param instances number of possible thread instances (used to statically allocate memory).
+/// \param instances number of possible thread instances.
/// \param stacksz stack size (in bytes) requirements for the thread function.
#if defined (osObjectsExternal) // object is external
#define osThreadDef(name, priority, instances, stacksz) \
extern const osThreadDef_t os_thread_def_##name
#else // define the object
#define osThreadDef(name, priority, instances, stacksz) \
-static uint32_t os_thread_stack##name[(stacksz)?(((stacksz+3)/4)):1]; \
+static uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1]; \
static StaticTask_t os_thread_cb_##name; \
const osThreadDef_t os_thread_def_##name = \
{ (name), \
@@ -437,27 +445,27 @@
(instances == 1) ? (&os_thread_cb_##name) : NULL,\
(instances == 1) ? sizeof(StaticTask_t) : 0U, \
((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \
- 4*((stacksz+3)/4), \
+ 8*((stacksz+7)/8), \
(priority), 0U, 0U } }
#endif
-
+
/// Access a Thread definition.
/// \param name name of the thread definition object.
#define osThread(name) \
&os_thread_def_##name
-
+
/// Create a thread and add it to Active Threads and set it to state READY.
/// \param[in] thread_def thread definition referenced with \ref osThread.
/// \param[in] argument pointer that is passed to the thread function as start argument.
/// \return thread ID for reference by other functions or NULL in case of error.
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
-
+
/// Return the thread ID of the current running thread.
/// \return thread ID for reference by other functions or NULL in case of error.
#if (osCMSIS < 0x20000U)
osThreadId osThreadGetId (void);
#endif
-
+
/// Change priority of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] priority new priority value for the thread function.
@@ -465,70 +473,70 @@
#if (osCMSIS < 0x20000U)
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
#endif
-
+
/// Get current priority of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return current priority value of the specified thread.
#if (osCMSIS < 0x20000U)
osPriority osThreadGetPriority (osThreadId thread_id);
#endif
-
+
/// Pass control to next thread that is in state \b READY.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osThreadYield (void);
#endif
-
+
/// Terminate execution of a thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osThreadTerminate (osThreadId thread_id);
#endif
-
-
+
+
// ==== Signal Management ====
-
+
/// Set the specified Signal Flags of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] signals specifies the signal flags of the thread that should be set.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
int32_t osSignalSet (osThreadId thread_id, int32_t signals);
-
+
/// Clear the specified Signal Flags of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
int32_t osSignalClear (osThreadId thread_id, int32_t signals);
-
+
/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event flag information or error code.
os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
-
-
+
+
// ==== Generic Wait Functions ====
-
+
/// Wait for Timeout (Time Delay).
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osDelay (uint32_t millisec);
#endif
-
+
#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
-
+
/// Wait for Signal, Message, Mail, or Timeout.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return event that contains signal, message, or mail information or error code.
os_InRegs osEvent osWait (uint32_t millisec);
-
+
#endif // Generic Wait available
-
-
+
+
// ==== Timer Management Functions ====
-
+
/// Define a Timer object.
/// \param name name of the timer object.
/// \param function name of the timer call back function.
@@ -541,19 +549,19 @@
const osTimerDef_t os_timer_def_##name = \
{ (function), { NULL, 0U, (&os_timer_cb_##name), sizeof(StaticTimer_t) } }
#endif
-
+
/// Access a Timer definition.
/// \param name name of the timer object.
#define osTimer(name) \
&os_timer_def_##name
-
+
/// Create and Initialize a timer.
/// \param[in] timer_def timer object referenced with \ref osTimer.
/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
/// \param[in] argument argument to the timer call back function.
/// \return timer ID for reference by other functions or NULL in case of error.
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
-
+
/// Start or restart a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
@@ -561,24 +569,24 @@
#if (osCMSIS < 0x20000U)
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
#endif
-
+
/// Stop a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osTimerStop (osTimerId timer_id);
#endif
-
+
/// Delete a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osTimerDelete (osTimerId timer_id);
#endif
-
-
+
+
// ==== Mutex Management Functions ====
-
+
/// Define a Mutex.
/// \param name name of the mutex object.
#if defined (osObjectsExternal) // object is external
@@ -590,17 +598,17 @@
const osMutexDef_t os_mutex_def_##name = \
{ NULL, osMutexRecursive | osMutexPrioInherit, (&os_mutex_cb_##name), sizeof(StaticSemaphore_t) }
#endif
-
+
/// Access a Mutex definition.
/// \param name name of the mutex object.
#define osMutex(name) \
&os_mutex_def_##name
-
+
/// Create and Initialize a Mutex object.
/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
/// \return mutex ID for reference by other functions or NULL in case of error.
osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
-
+
/// Wait until a Mutex becomes available.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
@@ -610,26 +618,26 @@
#else
#define osMutexWait osMutexAcquire
#endif
-
+
/// Release a Mutex that was obtained by \ref osMutexWait.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osMutexRelease (osMutexId mutex_id);
#endif
-
+
/// Delete a Mutex object.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osMutexDelete (osMutexId mutex_id);
#endif
-
-
+
+
// ==== Semaphore Management Functions ====
-
+
#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available
-
+
/// Define a Semaphore object.
/// \param name name of the semaphore object.
#if defined (osObjectsExternal) // object is external
@@ -641,45 +649,45 @@
const osSemaphoreDef_t os_semaphore_def_##name = \
{ NULL, 0U, (&os_semaphore_cb_##name), sizeof(StaticSemaphore_t) }
#endif
-
+
/// Access a Semaphore definition.
/// \param name name of the semaphore object.
#define osSemaphore(name) \
&os_semaphore_def_##name
-
+
/// Create and Initialize a Semaphore object.
/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
/// \param[in] count maximum and initial number of available tokens.
/// \return semaphore ID for reference by other functions or NULL in case of error.
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
-
+
/// Wait until a Semaphore token becomes available.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return number of available tokens, or -1 in case of incorrect parameters.
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
-
+
/// Release a Semaphore token.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
#endif
-
+
/// Delete a Semaphore object.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
#if (osCMSIS < 0x20000U)
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
#endif
-
+
#endif // Semaphore available
-
-
+
+
// ==== Memory Pool Management Functions ====
#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available
-
+
/// \brief Define a Memory Pool.
/// \param name name of the memory pool.
/// \param no maximum number of blocks (objects) in the memory pool.
@@ -690,42 +698,42 @@
#else // define the object
#define osPoolDef(name, no, type) \
const osPoolDef_t os_pool_def_##name = \
-{ (no), sizeof(type), NULL }
+{ (no), sizeof(type), {NULL} }
#endif
-
+
/// \brief Access a Memory Pool definition.
/// \param name name of the memory pool
#define osPool(name) \
&os_pool_def_##name
-
+
/// Create and Initialize a Memory Pool object.
/// \param[in] pool_def memory pool definition referenced with \ref osPool.
/// \return memory pool ID for reference by other functions or NULL in case of error.
osPoolId osPoolCreate (const osPoolDef_t *pool_def);
-
+
/// Allocate a memory block from a Memory Pool.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
void *osPoolAlloc (osPoolId pool_id);
-
+
/// Allocate a memory block from a Memory Pool and set memory block to zero.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
void *osPoolCAlloc (osPoolId pool_id);
-
+
/// Return an allocated memory block back to a Memory Pool.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \param[in] block address of the allocated memory block to be returned to the memory pool.
/// \return status code that indicates the execution status of the function.
osStatus osPoolFree (osPoolId pool_id, void *block);
-
+
#endif // Memory Pool available
-
-
+
+
// ==== Message Queue Management Functions ====
-
+
#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available
-
+
/// \brief Create a Message Queue Definition.
/// \param name name of the queue.
/// \param queue_sz maximum number of messages in the queue.
@@ -742,38 +750,38 @@
{ NULL, 0U, (&os_mq_cb_##name), sizeof(StaticQueue_t), \
(&os_mq_data_##name), sizeof(os_mq_data_##name) } }
#endif
-
+
/// \brief Access a Message Queue Definition.
/// \param name name of the queue
#define osMessageQ(name) \
&os_messageQ_def_##name
-
+
/// Create and Initialize a Message Queue object.
/// \param[in] queue_def message queue definition referenced with \ref osMessageQ.
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return message queue ID for reference by other functions or NULL in case of error.
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
-
+
/// Put a Message to a Queue.
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
/// \param[in] info message information.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
-
+
/// Get a Message from a Queue or timeout if Queue is empty.
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event information that includes status code.
os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
-
+
#endif // Message Queue available
-
-
+
+
// ==== Mail Queue Management Functions ====
-
+
#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available
-
+
/// \brief Create a Mail Queue Definition.
/// \param name name of the queue.
/// \param queue_sz maximum number of mails in the queue.
@@ -786,52 +794,53 @@
const osMailQDef_t os_mailQ_def_##name = \
{ (queue_sz), sizeof(type), NULL }
#endif
-
+
/// \brief Access a Mail Queue Definition.
/// \param name name of the queue
#define osMailQ(name) \
&os_mailQ_def_##name
-
+
/// Create and Initialize a Mail Queue object.
/// \param[in] queue_def mail queue definition referenced with \ref osMailQ.
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return mail queue ID for reference by other functions or NULL in case of error.
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
-
+
/// Allocate a memory block for mail from a mail memory pool.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
-
+
/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
-
+
/// Put a Mail into a Queue.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] mail pointer to memory with mail to put into a queue.
/// \return status code that indicates the execution status of the function.
osStatus osMailPut (osMailQId queue_id, const void *mail);
-
+
/// Get a Mail from a Queue or timeout if Queue is empty.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
/// \return event information that includes status code.
os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
-
+
/// Free a memory block by returning it to a mail memory pool.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet.
/// \return status code that indicates the execution status of the function.
osStatus osMailFree (osMailQId queue_id, void *mail);
-
+
#endif // Mail Queue available
-
+
+
#ifdef __cplusplus
}
#endif
-
+
#endif // CMSIS_OS_H_
diff --git a/Source/CMSIS_RTOS_V2/cmsis_os1.c b/Source/CMSIS_RTOS_V2/cmsis_os1.c
deleted file mode 100644
index 05ffe36..0000000
--- a/Source/CMSIS_RTOS_V2/cmsis_os1.c
+++ /dev/null
@@ -1,368 +0,0 @@
-/*---------------------------------------------------------------------------
- * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved.
- * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * Project: CMSIS-RTOS API V1
- * Title: cmsis_os1.c V1 module file
- *
- *----------------------------------------------------------------------------*/
-
-#include <string.h>
-#include "cmsis_os.h"
-
-#if (osCMSIS >= 0x20000U) && !defined(os1_Disable)
-
-
-// Thread
-#if !defined(os1_Disable_Thread)
-osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) {
-
- if (thread_def == NULL) {
- return NULL;
- }
- return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr);
-}
-#endif
-
-
-// Signals
-
-#if !defined(os1_Disable_Signal)
-
-#define SignalMask ((1U<<osFeature_Signals)-1U)
-
-int32_t osSignalSet (osThreadId thread_id, int32_t signals) {
- uint32_t flags;
-
- flags = osThreadFlagsSet(thread_id, (uint32_t)signals);
- if ((flags & 0x80000000U) != 0U) {
- return ((int32_t)0x80000000U);
- }
- return ((int32_t)(flags & ~((uint32_t)signals)));
-}
-
-int32_t osSignalClear (osThreadId thread_id, int32_t signals) {
- uint32_t flags;
-
- if (thread_id != osThreadGetId()) {
- return ((int32_t)0x80000000U);
- }
- flags = osThreadFlagsClear((uint32_t)signals);
- if ((flags & 0x80000000U) != 0U) {
- return ((int32_t)0x80000000U);
- }
- return ((int32_t)flags);
-}
-
-os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec) {
- osEvent event;
- uint32_t flags;
-
- if (signals != 0) {
- flags = osThreadFlagsWait((uint32_t)signals, osFlagsWaitAll, millisec);
- } else {
- flags = osThreadFlagsWait(SignalMask, osFlagsWaitAny, millisec);
- }
- if ((flags > 0U) && (flags < 0x80000000U)) {
- event.status = osEventSignal;
- event.value.signals = (int32_t)flags;
- } else {
- switch ((int32_t)flags) {
- case osErrorResource:
- event.status = osOK;
- break;
- case osErrorTimeout:
- event.status = osEventTimeout;
- break;
- case osErrorParameter:
- event.status = osErrorValue;
- break;
- default:
- event.status = (osStatus)flags;
- break;
- }
- }
- return event;
-}
-
-#endif // Signal
-
-
-// Timer
-#if !defined(os1_Disable_Timer)
-osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
-
- if (timer_def == NULL) {
- return NULL;
- }
- return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr);
-}
-#endif
-
-
-// Mutex
-#if !defined(os1_Disable_Mutex)
-osMutexId osMutexCreate (const osMutexDef_t *mutex_def) {
-
- if (mutex_def == NULL) {
- return NULL;
- }
- return osMutexNew(mutex_def);
-}
-#endif
-
-
-// Semaphore
-
-#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) && !defined(os1_Disable_Semaphore)
-
-osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
-
- if (semaphore_def == NULL) {
- return NULL;
- }
- return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def);
-}
-
-int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
- osStatus_t status;
- uint32_t count;
-
- status = osSemaphoreAcquire(semaphore_id, millisec);
- switch (status) {
- case osOK:
- count = osSemaphoreGetCount(semaphore_id);
- return ((int32_t)count + 1);
- case osErrorResource:
- case osErrorTimeout:
- return 0;
- default:
- break;
- }
- return -1;
-}
-
-#endif // Semaphore
-
-
-// Memory Pool
-
-#if (defined(osFeature_Pool) && (osFeature_Pool != 0))&& !defined(os1_Disable_Pool)
-
-osPoolId osPoolCreate (const osPoolDef_t *pool_def) {
-
- if (pool_def == NULL) {
- return NULL;
- }
- return osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr);
-}
-
-void *osPoolAlloc (osPoolId pool_id) {
- return osMemoryPoolAlloc(pool_id, 0U);
-}
-
-void *osPoolCAlloc (osPoolId pool_id) {
- void *block;
- uint32_t block_size;
-
- block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id);
- if (block_size == 0U) {
- return NULL;
- }
- block = osMemoryPoolAlloc(pool_id, 0U);
- if (block != NULL) {
- memset(block, 0, block_size);
- }
- return block;
-}
-
-osStatus osPoolFree (osPoolId pool_id, void *block) {
- return osMemoryPoolFree(pool_id, block);
-}
-
-#endif // Memory Pool
-
-
-// Message Queue
-
-#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) && !defined(os1_Disable_MessageQ)
-
-osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
- (void)thread_id;
-
- if (queue_def == NULL) {
- return NULL;
- }
- return osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr);
-}
-
-osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
- return osMessageQueuePut(queue_id, &info, 0U, millisec);
-}
-
-os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {
- osStatus_t status;
- osEvent event;
- uint32_t message;
-
- status = osMessageQueueGet(queue_id, &message, NULL, millisec);
- switch (status) {
- case osOK:
- event.status = osEventMessage;
- event.value.v = message;
- break;
- case osErrorResource:
- event.status = osOK;
- break;
- case osErrorTimeout:
- event.status = osEventTimeout;
- break;
- default:
- event.status = status;
- break;
- }
- return event;
-}
-
-#endif // Message Queue
-
-
-// Mail Queue
-
-#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) && !defined(os1_Disable_MailQ)
-
-typedef struct os_mail_queue_s {
- osMemoryPoolId_t mp_id;
- osMessageQueueId_t mq_id;
-} os_mail_queue_t;
-
-osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
- os_mail_queue_t *ptr;
- (void)thread_id;
-
- if (queue_def == NULL) {
- return NULL;
- }
-
- ptr = queue_def->mail;
- if (ptr == NULL) {
- return NULL;
- }
-
- ptr->mp_id = osMemoryPoolNew (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr);
- ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr);
- if ((ptr->mp_id == NULL) || (ptr->mq_id == NULL)) {
- if (ptr->mp_id != NULL) {
- osMemoryPoolDelete(ptr->mp_id);
- }
- if (ptr->mq_id != NULL) {
- osMessageQueueDelete(ptr->mq_id);
- }
- return NULL;
- }
-
- return ptr;
-}
-
-void *osMailAlloc (osMailQId queue_id, uint32_t millisec) {
- os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
-
- if (ptr == NULL) {
- return NULL;
- }
- return osMemoryPoolAlloc(ptr->mp_id, millisec);
-}
-
-void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {
- os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
- void *block;
- uint32_t block_size;
-
- if (ptr == NULL) {
- return NULL;
- }
- block_size = osMemoryPoolGetBlockSize(ptr->mp_id);
- if (block_size == 0U) {
- return NULL;
- }
- block = osMemoryPoolAlloc(ptr->mp_id, millisec);
- if (block != NULL) {
- memset(block, 0, block_size);
- }
-
- return block;
-
-}
-
-osStatus osMailPut (osMailQId queue_id, const void *mail) {
- os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
-
- if (ptr == NULL) {
- return osErrorParameter;
- }
- if (mail == NULL) {
- return osErrorValue;
- }
- return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U);
-}
-
-os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) {
- os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
- osStatus_t status;
- osEvent event;
- void *mail;
-
- if (ptr == NULL) {
- event.status = osErrorParameter;
- return event;
- }
-
- status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec);
- switch (status) {
- case osOK:
- event.status = osEventMail;
- event.value.p = mail;
- break;
- case osErrorResource:
- event.status = osOK;
- break;
- case osErrorTimeout:
- event.status = osEventTimeout;
- break;
- default:
- event.status = status;
- break;
- }
- return event;
-}
-
-osStatus osMailFree (osMailQId queue_id, void *mail) {
- os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;
-
- if (ptr == NULL) {
- return osErrorParameter;
- }
- if (mail == NULL) {
- return osErrorValue;
- }
- return osMemoryPoolFree(ptr->mp_id, mail);
-}
-
-#endif // Mail Queue
-
-
-#endif // osCMSIS
diff --git a/Source/CMSIS_RTOS_V2/cmsis_os2.c b/Source/CMSIS_RTOS_V2/cmsis_os2.c
index b65b3a0..91fca30 100644
--- a/Source/CMSIS_RTOS_V2/cmsis_os2.c
+++ b/Source/CMSIS_RTOS_V2/cmsis_os2.c
@@ -1,7 +1,6 @@
/* --------------------------------------------------------------------------
- * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved.
- * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved.
- * --------------------------------------------------------------------------
+ * Portions Copyright © 2019 STMicroelectronics International N.V. All rights reserved.
+ * Copyright (c) 2013-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -52,11 +51,14 @@
#if ((__ARM_ARCH_7M__ == 1U) || \
(__ARM_ARCH_7EM__ == 1U) || \
(__ARM_ARCH_8M_MAIN__ == 1U))
-#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || ((KernelState == osKernelRunning) && (__get_BASEPRI() != 0U)))
+#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U))
#elif (__ARM_ARCH_6M__ == 1U)
-#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) && (KernelState == osKernelRunning))
-#elif (__ARM_ARCH_7A__ == 1)
-#define IS_IRQ_MASKED() (0U)
+#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U)
+#elif (__ARM_ARCH_7A__ == 1U)
+/* CPSR mask bits */
+#define CPSR_MASKBIT_I 0x80U
+
+#define IS_IRQ_MASKED() ((__get_CPSR() & CPSR_MASKBIT_I) != 0U)
#else
#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U)
#endif
@@ -71,7 +73,7 @@
#define IS_IRQ_MODE() (__get_IPSR() != 0U)
#endif
-#define IS_IRQ() (IS_IRQ_MODE() || IS_IRQ_MASKED())
+#define IS_IRQ() (IS_IRQ_MODE() || (IS_IRQ_MASKED() && (KernelState == osKernelRunning)))
/* Limits */
#define MAX_BITS_TASK_NOTIFY 31U
@@ -80,12 +82,12 @@
#define THREAD_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_TASK_NOTIFY) - 1U))
#define EVENT_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_EVENT_GROUPS) - 1U))
-/* Kernel version and identification string definition */
+/* Kernel version and identification string definition (major.minor.rev: mmnnnrrrr dec) */
#define KERNEL_VERSION (((uint32_t)tskKERNEL_VERSION_MAJOR * 10000000UL) | \
((uint32_t)tskKERNEL_VERSION_MINOR * 10000UL) | \
((uint32_t)tskKERNEL_VERSION_BUILD * 1UL))
-#define KERNEL_ID "FreeRTOS V10.0.1"
+#define KERNEL_ID ("FreeRTOS " tskKERNEL_VERSION_NUMBER)
/* Timer callback information structure definition */
typedef struct {
@@ -94,27 +96,55 @@
} TimerCallback_t;
/* Kernel initialization state */
-static osKernelState_t KernelState;
+static osKernelState_t KernelState = osKernelInactive;
-/* Heap region definition used by heap_5 variant */
-#if defined(USE_FreeRTOS_HEAP_5)
-#if (configAPPLICATION_ALLOCATED_HEAP == 1)
/*
- The application writer has already defined the array used for the RTOS
- heap - probably so it can be placed in a special segment or address.
-*/
- extern uint8_t ucHeap[configTOTAL_HEAP_SIZE];
-#else
- static uint8_t ucHeap[configTOTAL_HEAP_SIZE];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
+ Heap region definition used by heap_5 variant
-static HeapRegion_t xHeapRegions[] = {
- { ucHeap, configTOTAL_HEAP_SIZE },
- { NULL, 0 }
-};
-#endif /* USE_FreeRTOS_HEAP_5 */
+ Define configAPPLICATION_ALLOCATED_HEAP as nonzero value in FreeRTOSConfig.h if
+ heap regions are already defined and vPortDefineHeapRegions is called in application.
+
+ Otherwise vPortDefineHeapRegions will be called by osKernelInitialize using
+ definition configHEAP_5_REGIONS as parameter. Overriding configHEAP_5_REGIONS
+ is possible by defining it globally or in FreeRTOSConfig.h.
+*/
+#if defined(USE_FREERTOS_HEAP_5)
+#if (configAPPLICATION_ALLOCATED_HEAP == 0)
+ /*
+ FreeRTOS heap is not defined by the application.
+ Single region of size configTOTAL_HEAP_SIZE (defined in FreeRTOSConfig.h)
+ is provided by default. Define configHEAP_5_REGIONS to provide custom
+ HeapRegion_t array.
+ */
+ #define HEAP_5_REGION_SETUP 1
+
+ #ifndef configHEAP_5_REGIONS
+ #define configHEAP_5_REGIONS xHeapRegions
+
+ static uint8_t ucHeap[configTOTAL_HEAP_SIZE];
+
+ static HeapRegion_t xHeapRegions[] = {
+ { ucHeap, configTOTAL_HEAP_SIZE },
+ { NULL, 0 }
+ };
+ #else
+ /* Global definition is provided to override default heap array */
+ extern HeapRegion_t configHEAP_5_REGIONS[];
+ #endif
+#else
+ /*
+ The application already defined the array used for the FreeRTOS heap and
+ called vPortDefineHeapRegions to initialize heap.
+ */
+ #define HEAP_5_REGION_SETUP 0
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+#endif /* USE_FREERTOS_HEAP_5 */
#if defined(SysTick)
+#undef SysTick_Handler
+
+/* CMSIS SysTick interrupt handler prototype */
+extern void SysTick_Handler (void);
/* FreeRTOS tick timer interrupt handler prototype */
extern void xPortSysTickHandler (void);
@@ -125,11 +155,31 @@
/* Clear overflow flag */
SysTick->CTRL;
- /* Call tick handler */
- xPortSysTickHandler();
+ if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
+ /* Call tick handler */
+ xPortSysTickHandler();
+ }
}
#endif /* SysTick */
+/*
+ Setup SVC to reset value.
+*/
+__STATIC_INLINE void SVC_Setup (void) {
+#if (__ARM_ARCH_7A__ == 0U)
+ /* Service Call interrupt might be configured before kernel start */
+ /* and when its priority is lower or equal to BASEPRI, svc intruction */
+ /* causes a Hard Fault. */
+
+ /*
+ * the call below has introduced a regression compared to revious release
+ * The issue was logged under:https://github.com/ARM-software/CMSIS-FreeRTOS/issues/35
+ * until it is correctly fixed, the code below is commented
+ */
+/* NVIC_SetPriority (SVCall_IRQn, 0U); */
+#endif
+}
+
/*---------------------------------------------------------------------------*/
osStatus_t osKernelInitialize (void) {
@@ -140,8 +190,8 @@
}
else {
if (KernelState == osKernelInactive) {
- #if defined(USE_FreeRTOS_HEAP_5)
- vPortDefineHeapRegions (xHeapRegions);
+ #if defined(USE_FREERTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
+ vPortDefineHeapRegions (configHEAP_5_REGIONS);
#endif
KernelState = osKernelReady;
stat = osOK;
@@ -156,6 +206,7 @@
osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {
if (version != NULL) {
+ /* Version encoding is major.minor.rev: mmnnnrrrr dec */
version->api = KERNEL_VERSION;
version->kernel = KERNEL_VERSION;
}
@@ -203,7 +254,11 @@
}
else {
if (KernelState == osKernelReady) {
+ /* Ensure SVC priority is at the reset value */
+ SVC_Setup();
+ /* Change state to enable IRQ masking check */
KernelState = osKernelRunning;
+ /* Start the kernel scheduler */
vTaskStartScheduler();
stat = osOK;
} else {
@@ -326,15 +381,18 @@
}
uint32_t osKernelGetSysTimerCount (void) {
+ uint32_t irqmask = IS_IRQ_MASKED();
TickType_t ticks;
uint32_t val;
- portDISABLE_INTERRUPTS();
+ __disable_irq();
ticks = xTaskGetTickCount();
val = ticks * ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
- portENABLE_INTERRUPTS();
+ if (irqmask == 0U) {
+ __enable_irq();
+ }
return (val);
}
@@ -346,7 +404,6 @@
/*---------------------------------------------------------------------------*/
osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
- char empty;
const char *name;
uint32_t stack;
TaskHandle_t hTask;
@@ -359,9 +416,8 @@
stack = configMINIMAL_STACK_SIZE;
prio = (UBaseType_t)osPriorityNormal;
- empty = '\0';
- name = ∅
- mem = -1;
+ name = NULL;
+ mem = -1;
if (attr != NULL) {
if (attr->name != NULL) {
@@ -427,11 +483,7 @@
osThreadId_t osThreadGetId (void) {
osThreadId_t id;
- if (IS_IRQ()) {
- id = NULL;
- } else {
- id = (osThreadId_t)xTaskGetCurrentTaskHandle();
- }
+ id = (osThreadId_t)xTaskGetCurrentTaskHandle();
return (id);
}
@@ -471,16 +523,6 @@
return (sz);
}
-uint32_t osThreadGetStackSize (osThreadId_t thread_id) {
- /*
- * this implmentation is not correct.
- * this function is implmented to avoid link errors (undefined reference)
- * Bug reported : https://github.com/ARM-software/CMSIS-FreeRTOS/issues/14
- */
- (void) thread_id;
- return 0;
-}
-
osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {
TaskHandle_t hTask = (TaskHandle_t)thread_id;
osStatus_t stat;
@@ -806,7 +848,7 @@
}
osStatus_t osDelayUntil (uint32_t ticks) {
- TickType_t tcnt;
+ TickType_t tcnt, delay;
osStatus_t stat;
if (IS_IRQ()) {
@@ -816,7 +858,18 @@
stat = osOK;
tcnt = xTaskGetTickCount();
- vTaskDelayUntil (&tcnt, (TickType_t)(ticks - tcnt));
+ /* Determine remaining number of ticks to delay */
+ delay = (TickType_t)ticks - tcnt;
+
+ /* Check if target tick has not expired */
+ if((delay != 0U) && (0 == (delay >> (8 * sizeof(TickType_t) - 1)))) {
+ vTaskDelayUntil (&tcnt, delay);
+ }
+ else
+ {
+ /* No delay or already expired */
+ stat = osErrorParameter;
+ }
}
return (stat);
@@ -1043,7 +1096,7 @@
else if (IS_IRQ()) {
yield = pdFALSE;
- if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) != pdFAIL) {
+ if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) == pdFAIL) {
rflags = (uint32_t)osErrorResource;
} else {
rflags = flags;
@@ -1416,7 +1469,7 @@
hSemaphore = xSemaphoreCreateCounting (max_count, initial_count);
}
}
-
+
#if (configQUEUE_REGISTRY_SIZE > 0)
if (hSemaphore != NULL) {
if (attr != NULL) {
diff --git a/Source/croutine.c b/Source/croutine.c
index b715884..56c8ac2 100644
--- a/Source/croutine.c
+++ b/Source/croutine.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -260,7 +260,7 @@
( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
/* Is the co-routine waiting on an event also? */
- if( pxCRCB->xEventListItem.pvContainer )
+ if( pxCRCB->xEventListItem.pxContainer )
{
( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
}
diff --git a/Source/event_groups.c b/Source/event_groups.c
index 14d7b02..65a5ff2 100644
--- a/Source/event_groups.c
+++ b/Source/event_groups.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -39,11 +39,11 @@
#include "timers.h"
#include "event_groups.h"
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */
/* The following bit fields convey control information in a task's event list
item value. It is important they don't clash with the
@@ -60,7 +60,7 @@
#define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL
#endif
-typedef struct xEventGroupDefinition
+typedef struct EventGroupDef_t
{
EventBits_t uxEventBits;
List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */
@@ -104,11 +104,11 @@
event group structure. */
volatile size_t xSize = sizeof( StaticEventGroup_t );
configASSERT( xSize == sizeof( EventGroup_t ) );
- }
+ } /*lint !e529 xSize is referenced if configASSERT() is defined. */
#endif /* configASSERT_DEFINED */
/* The user has provided a statically allocated event group - use it. */
- pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 EventGroup_t and StaticEventGroup_t are guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
+ pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
if( pxEventBits != NULL )
{
@@ -128,10 +128,13 @@
}
else
{
+ /* xEventGroupCreateStatic should only ever be called with
+ pxEventGroupBuffer pointing to a pre-allocated (compile time
+ allocated) StaticEventGroup_t variable. */
traceEVENT_GROUP_CREATE_FAILED();
}
- return ( EventGroupHandle_t ) pxEventBits;
+ return pxEventBits;
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
@@ -143,8 +146,20 @@
{
EventGroup_t *pxEventBits;
- /* Allocate the event group. */
- pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );
+ /* Allocate the event group. Justification for MISRA deviation as
+ follows: pvPortMalloc() always ensures returned memory blocks are
+ aligned per the requirements of the MCU stack. In this case
+ pvPortMalloc() must return a pointer that is guaranteed to meet the
+ alignment requirements of the EventGroup_t structure - which (if you
+ follow it through) is the alignment requirements of the TickType_t type
+ (EventBits_t being of TickType_t itself). Therefore, whenever the
+ stack alignment requirements are greater than or equal to the
+ TickType_t alignment requirements the cast is safe. In other cases,
+ where the natural word size of the architecture is less than
+ sizeof( TickType_t ), the TickType_t variables will be accessed in two
+ or more reads operations, and the alignment requirements is only that
+ of each individual read. */
+ pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */
if( pxEventBits != NULL )
{
@@ -164,10 +179,10 @@
}
else
{
- traceEVENT_GROUP_CREATE_FAILED();
+ traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */
}
- return ( EventGroupHandle_t ) pxEventBits;
+ return pxEventBits;
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
@@ -176,7 +191,7 @@
EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )
{
EventBits_t uxOriginalBitValue, uxReturn;
-EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventGroup_t *pxEventBits = xEventGroup;
BaseType_t xAlreadyYielded;
BaseType_t xTimeoutOccurred = pdFALSE;
@@ -295,7 +310,7 @@
EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )
{
-EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventGroup_t *pxEventBits = xEventGroup;
EventBits_t uxReturn, uxControlBits = 0;
BaseType_t xWaitConditionMet, xAlreadyYielded;
BaseType_t xTimeoutOccurred = pdFALSE;
@@ -445,7 +460,7 @@
EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
{
-EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventGroup_t *pxEventBits = xEventGroup;
EventBits_t uxReturn;
/* Check the user is not attempting to clear the bits used by the kernel
@@ -477,7 +492,7 @@
BaseType_t xReturn;
traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
- xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
+ xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
return xReturn;
}
@@ -488,7 +503,7 @@
EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
{
UBaseType_t uxSavedInterruptStatus;
-EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventGroup_t const * const pxEventBits = xEventGroup;
EventBits_t uxReturn;
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
@@ -498,16 +513,16 @@
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return uxReturn;
-}
+} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
/*-----------------------------------------------------------*/
EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )
{
ListItem_t *pxListItem, *pxNext;
ListItem_t const *pxListEnd;
-List_t *pxList;
+List_t const * pxList;
EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
-EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventGroup_t *pxEventBits = xEventGroup;
BaseType_t xMatchFound = pdFALSE;
/* Check the user is not attempting to set the bits used by the kernel
@@ -516,7 +531,7 @@
configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
pxList = &( pxEventBits->xTasksWaitingForBits );
- pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
vTaskSuspendAll();
{
traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
@@ -597,7 +612,7 @@
void vEventGroupDelete( EventGroupHandle_t xEventGroup )
{
-EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventGroup_t *pxEventBits = xEventGroup;
const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
vTaskSuspendAll();
@@ -641,7 +656,7 @@
an interrupt. */
void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )
{
- ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );
+ ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
}
/*-----------------------------------------------------------*/
@@ -649,7 +664,7 @@
an interrupt. */
void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )
{
- ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );
+ ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
}
/*-----------------------------------------------------------*/
@@ -695,7 +710,7 @@
BaseType_t xReturn;
traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
- xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
+ xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
return xReturn;
}
@@ -708,7 +723,7 @@
UBaseType_t uxEventGroupGetNumber( void* xEventGroup )
{
UBaseType_t xReturn;
- EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+ EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
if( xEventGroup == NULL )
{
@@ -729,7 +744,7 @@
void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber )
{
- ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber;
+ ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
}
#endif /* configUSE_TRACE_FACILITY */
diff --git a/Source/include/FreeRTOS.h b/Source/include/FreeRTOS.h
index 78d176a..9d09d91 100644
--- a/Source/include/FreeRTOS.h
+++ b/Source/include/FreeRTOS.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -156,6 +156,10 @@
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#endif
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark2
+ #define INCLUDE_uxTaskGetStackHighWaterMark2 0
+#endif
+
#ifndef INCLUDE_eTaskGetState
#define INCLUDE_eTaskGetState 0
#endif
@@ -237,6 +241,10 @@
#define configASSERT_DEFINED 1
#endif
+#ifndef portMEMORY_BARRIER
+ #define portMEMORY_BARRIER()
+#endif
+
/* The timers module relies on xTaskGetSchedulerState(). */
#if configUSE_TIMERS == 1
@@ -758,8 +766,12 @@
#define portTASK_USES_FLOATING_POINT()
#endif
-#ifndef portTASK_CALLS_SECURE_FUNCTIONS
- #define portTASK_CALLS_SECURE_FUNCTIONS()
+#ifndef portALLOCATE_SECURE_CONTEXT
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+#endif
+
+#ifndef portDONT_DISCARD
+ #define portDONT_DISCARD
#endif
#ifndef configUSE_TIME_SLICING
@@ -806,6 +818,10 @@
#define configUSE_TASK_NOTIFICATIONS 1
#endif
+#ifndef configUSE_POSIX_ERRNO
+ #define configUSE_POSIX_ERRNO 0
+#endif
+
#ifndef portTICK_TYPE_IS_ATOMIC
#define portTICK_TYPE_IS_ATOMIC 0
#endif
@@ -826,6 +842,13 @@
#define configSTACK_DEPTH_TYPE uint16_t
#endif
+#ifndef configMESSAGE_BUFFER_LENGTH_TYPE
+ /* Defaults to size_t for backward compatibility, but can be overridden
+ in FreeRTOSConfig.h if lengths will always be less than the number of bytes
+ in a size_t. */
+ #define configMESSAGE_BUFFER_LENGTH_TYPE size_t
+#endif
+
/* Sanity check the configuration. */
#if( configUSE_TICKLESS_IDLE != 0 )
#if( INCLUDE_vTaskSuspend != 1 )
@@ -921,6 +944,10 @@
#define pdTASK_CODE TaskFunction_t
#define xListItem ListItem_t
#define xList List_t
+
+ /* For libraries that break the list data hiding, and access list structure
+ members directly (which is not supposed to be done). */
+ #define pxContainer pvContainer
#endif /* configENABLE_BACKWARD_COMPATIBILITY */
#if( configUSE_ALTERNATIVE_API != 0 )
@@ -935,6 +962,75 @@
#define configUSE_TASK_FPU_SUPPORT 1
#endif
+/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_MPU
+ #define configENABLE_MPU 0
+#endif
+
+/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_FPU
+ #define configENABLE_FPU 1
+#endif
+
+/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.
+This is currently used in ARMv8M ports. */
+#ifndef configENABLE_TRUSTZONE
+ #define configENABLE_TRUSTZONE 1
+#endif
+
+/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on
+the Secure Side only. */
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+ #define configRUN_FREERTOS_SECURE_ONLY 0
+#endif
+
+/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
+ * dynamically allocated RAM, in which case when any task is deleted it is known
+ * that both the task's stack and TCB need to be freed. Sometimes the
+ * FreeRTOSConfig.h settings only allow a task to be created using statically
+ * allocated RAM, in which case when any task is deleted it is known that neither
+ * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h
+ * settings allow a task to be created using either statically or dynamically
+ * allocated RAM, in which case a member of the TCB is used to record whether the
+ * stack and/or TCB were allocated statically or dynamically, so when a task is
+ * deleted the RAM that was allocated dynamically is freed again and no attempt is
+ * made to free the RAM that was allocated statically.
+ * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
+ * task to be created using either statically or dynamically allocated RAM. Note
+ * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
+ * a statically allocated stack and a dynamically allocated TCB.
+ *
+ * The following table lists various combinations of portUSING_MPU_WRAPPERS,
+ * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and
+ * when it is possible to have both static and dynamic allocation:
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free |
+ * | | | | | | Static Possible | |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes |
+ * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No |
+ * | | | | xTaskCreateRestrictedStatic | | | |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes |
+ * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes |
+ * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | |
+ * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | |
+ * | | | | xTaskCreateRestrictedStatic | | | |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \
+ ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )
+
/*
* In line with software engineering best practice, FreeRTOS implements a strict
* data hiding policy, so the real structures used by FreeRTOS to maintain the
@@ -947,25 +1043,40 @@
*/
struct xSTATIC_LIST_ITEM
{
- TickType_t xDummy1;
- void *pvDummy2[ 4 ];
+ #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+ TickType_t xDummy1;
+ #endif
+ TickType_t xDummy2;
+ void *pvDummy3[ 4 ];
+ #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+ TickType_t xDummy4;
+ #endif
};
typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
struct xSTATIC_MINI_LIST_ITEM
{
- TickType_t xDummy1;
- void *pvDummy2[ 2 ];
+ #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+ TickType_t xDummy1;
+ #endif
+ TickType_t xDummy2;
+ void *pvDummy3[ 2 ];
};
typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
typedef struct xSTATIC_LIST
{
- UBaseType_t uxDummy1;
- void *pvDummy2;
- StaticMiniListItem_t xDummy3;
+ #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+ TickType_t xDummy1;
+ #endif
+ UBaseType_t uxDummy2;
+ void *pvDummy3;
+ StaticMiniListItem_t xDummy4;
+ #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+ TickType_t xDummy5;
+ #endif
} StaticList_t;
/*
@@ -1019,14 +1130,16 @@
uint32_t ulDummy18;
uint8_t ucDummy19;
#endif
- #if( ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) || ( portUSING_MPU_WRAPPERS == 1 ) )
+ #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
uint8_t uxDummy20;
#endif
#if( INCLUDE_xTaskAbortDelay == 1 )
uint8_t ucDummy21;
#endif
-
+ #if ( configUSE_POSIX_ERRNO == 1 )
+ int iDummy22;
+ #endif
} StaticTask_t;
/*
@@ -1121,15 +1234,12 @@
void *pvDummy1;
StaticListItem_t xDummy2;
TickType_t xDummy3;
- UBaseType_t uxDummy4;
- void *pvDummy5[ 2 ];
+ void *pvDummy5;
+ TaskFunction_t pvDummy6;
#if( configUSE_TRACE_FACILITY == 1 )
- UBaseType_t uxDummy6;
+ UBaseType_t uxDummy7;
#endif
-
- #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- uint8_t ucDummy7;
- #endif
+ uint8_t ucDummy8;
} StaticTimer_t;
diff --git a/Source/include/FreeRTOSConfig_template.h b/Source/include/FreeRTOSConfig_template.h
index 0bef5a4..e0dff5c 100644
--- a/Source/include/FreeRTOSConfig_template.h
+++ b/Source/include/FreeRTOSConfig_template.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/include/StackMacros.h b/Source/include/StackMacros.h
index 534f004..3ed8b22 100644
--- a/Source/include/StackMacros.h
+++ b/Source/include/StackMacros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/include/croutine.h b/Source/include/croutine.h
index f4c54d2..8b3b41b 100644
--- a/Source/include/croutine.h
+++ b/Source/include/croutine.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/include/deprecated_definitions.h b/Source/include/deprecated_definitions.h
index 1125673..9cece98 100644
--- a/Source/include/deprecated_definitions.h
+++ b/Source/include/deprecated_definitions.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/include/event_groups.h b/Source/include/event_groups.h
index 69ec2e6..1f38bdb 100644
--- a/Source/include/event_groups.h
+++ b/Source/include/event_groups.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -78,7 +78,8 @@
* \defgroup EventGroupHandle_t EventGroupHandle_t
* \ingroup EventGroup
*/
-typedef void * EventGroupHandle_t;
+struct EventGroupDef_t;
+typedef struct EventGroupDef_t * EventGroupHandle_t;
/*
* The type that holds event bits always matches TickType_t - therefore the
@@ -404,7 +405,7 @@
* \ingroup EventGroup
*/
#if( configUSE_TRACE_FACILITY == 1 )
- BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+ BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
#else
#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
#endif
diff --git a/Source/include/list.h b/Source/include/list.h
index 4a3afa1..2fb6775 100644
--- a/Source/include/list.h
+++ b/Source/include/list.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -136,6 +136,7 @@
/*
* Definition of the only type of object that a list can contain.
*/
+struct xLIST;
struct xLIST_ITEM
{
listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
@@ -143,7 +144,7 @@
struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */
struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */
void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */
- void * configLIST_VOLATILE pvContainer; /*< Pointer to the list in which this list item is placed (if any). */
+ struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */
listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
};
typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */
@@ -246,7 +247,7 @@
* \page listLIST_IS_EMPTY listLIST_IS_EMPTY
* \ingroup LinkedList
*/
-#define listLIST_IS_EMPTY( pxList ) ( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) )
+#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )
/*
* Access macro to return the number of items in the list.
@@ -314,7 +315,7 @@
* @param pxListItem The list item we want to know if is in the list.
* @return pdTRUE if the list item is in the list, otherwise pdFALSE.
*/
-#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) )
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )
/*
* Return the list a list item is contained within (referenced from).
@@ -322,7 +323,7 @@
* @param pxListItem The list item being queried.
* @return A pointer to the List_t object that references the pxListItem
*/
-#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer )
+#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer )
/*
* This provides a crude means of knowing if a list has been initialised, as
diff --git a/Source/include/message_buffer.h b/Source/include/message_buffer.h
index 91e34fa..cfa08cb 100644
--- a/Source/include/message_buffer.h
+++ b/Source/include/message_buffer.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -692,6 +692,26 @@
* \ingroup MessageBufferManagement
*/
#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ <pre>
+ size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ </pre>
+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
/**
* message_buffer.h
diff --git a/Source/include/mpu_prototypes.h b/Source/include/mpu_prototypes.h
index e2c89ab..5d74907 100644
--- a/Source/include/mpu_prototypes.h
+++ b/Source/include/mpu_prototypes.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -38,116 +38,118 @@
#define MPU_PROTOTYPES_H
/* MPU versions of tasks.h API functions. */
-BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask );
-TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer );
-BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
-BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
-void MPU_vTaskDelete( TaskHandle_t xTaskToDelete );
-void MPU_vTaskDelay( const TickType_t xTicksToDelay );
-void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement );
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask );
-UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t xTask );
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask );
-void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
-void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend );
-void MPU_vTaskResume( TaskHandle_t xTaskToResume );
-void MPU_vTaskStartScheduler( void );
-void MPU_vTaskSuspendAll( void );
-BaseType_t MPU_xTaskResumeAll( void );
-TickType_t MPU_xTaskGetTickCount( void );
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void );
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery );
-TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery );
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask );
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue );
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex );
-BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void );
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );
-void MPU_vTaskList( char * pcWriteBuffer );
-void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue );
-BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
-uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
-BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask );
-BaseType_t MPU_xTaskIncrementTick( void );
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void );
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
-void MPU_vTaskMissedYield( void );
-BaseType_t MPU_xTaskGetSchedulerState( void );
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
/* MPU versions of queue.h API functions. */
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition );
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait );
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue );
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue );
-void MPU_vQueueDelete( QueueHandle_t xQueue );
-QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType );
-QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue );
-QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount );
-QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue );
-void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait );
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex );
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName );
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue );
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue );
-QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType );
-QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType );
-QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength );
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
-BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait );
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue );
-void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber );
-UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue );
-uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue );
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
/* MPU versions of timers.h API functions. */
-TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction );
-TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer );
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer );
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer );
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void );
-BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer );
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer );
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer );
-BaseType_t MPU_xTimerCreateTimerTask( void );
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait );
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
/* MPU versions of event_group.h API functions. */
-EventGroupHandle_t MPU_xEventGroupCreate( void );
-EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer );
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait );
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait );
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup );
-UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup );
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
/* MPU versions of message/stream_buffer.h API functions. */
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait );
-size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait );
-size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
-StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer );
-StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer );
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
diff --git a/Source/include/mpu_wrappers.h b/Source/include/mpu_wrappers.h
index eb326e7..711393f 100644
--- a/Source/include/mpu_wrappers.h
+++ b/Source/include/mpu_wrappers.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -67,6 +67,7 @@
#define pcTaskGetName MPU_pcTaskGetName
#define xTaskGetHandle MPU_xTaskGetHandle
#define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark
+ #define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2
#define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag
#define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag
#define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer
@@ -76,6 +77,7 @@
#define uxTaskGetSystemState MPU_uxTaskGetSystemState
#define vTaskList MPU_vTaskList
#define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats
+ #define xTaskGetIdleRunTimeCounter MPU_xTaskGetIdleRunTimeCounter
#define xTaskGenericNotify MPU_xTaskGenericNotify
#define xTaskNotifyWait MPU_xTaskNotifyWait
#define ulTaskNotifyTake MPU_ulTaskNotifyTake
@@ -124,6 +126,7 @@
#define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle
#define xTimerPendFunctionCall MPU_xTimerPendFunctionCall
#define pcTimerGetName MPU_pcTimerGetName
+ #define vTimerSetReloadMode MPU_vTimerSetReloadMode
#define xTimerGetPeriod MPU_xTimerGetPeriod
#define xTimerGetExpiryTime MPU_xTimerGetExpiryTime
#define xTimerGenericCommand MPU_xTimerGenericCommand
@@ -140,9 +143,8 @@
/* Map standard message/stream_buffer.h API functions to the MPU
equivalents. */
#define xStreamBufferSend MPU_xStreamBufferSend
- #define xStreamBufferSendFromISR MPU_xStreamBufferSendFromISR
#define xStreamBufferReceive MPU_xStreamBufferReceive
- #define xStreamBufferReceiveFromISR MPU_xStreamBufferReceiveFromISR
+ #define xStreamBufferNextMessageLengthBytes MPU_xStreamBufferNextMessageLengthBytes
#define vStreamBufferDelete MPU_vStreamBufferDelete
#define xStreamBufferIsFull MPU_xStreamBufferIsFull
#define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty
@@ -159,12 +161,14 @@
(useful when using statically allocated objects). */
#define PRIVILEGED_FUNCTION
#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+ #define FREERTOS_SYSTEM_CALL
#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
/* Ensure API functions go in the privileged execution section. */
#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+ #define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
@@ -172,6 +176,7 @@
#define PRIVILEGED_FUNCTION
#define PRIVILEGED_DATA
+ #define FREERTOS_SYSTEM_CALL
#define portUSING_MPU_WRAPPERS 0
#endif /* portUSING_MPU_WRAPPERS */
diff --git a/Source/include/portable.h b/Source/include/portable.h
index 3d0ef0a..59e8169 100644
--- a/Source/include/portable.h
+++ b/Source/include/portable.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -84,6 +84,14 @@
#define portNUM_CONFIGURABLE_REGIONS 1
#endif
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+ #define portHAS_STACK_OVERFLOW_CHECKING 0
+#endif
+
+#ifndef portARCH_NAME
+ #define portARCH_NAME NULL
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -97,9 +105,17 @@
*
*/
#if( portUSING_MPU_WRAPPERS == 1 )
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+ #else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+ #endif
#else
- StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+ #else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+ #endif
#endif
/* Used by heap_5.c. */
diff --git a/Source/include/projdefs.h b/Source/include/projdefs.h
index 27337a8..e045861 100644
--- a/Source/include/projdefs.h
+++ b/Source/include/projdefs.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/include/queue.h b/Source/include/queue.h
index a23fa1e..3b9da93 100644
--- a/Source/include/queue.h
+++ b/Source/include/queue.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -37,27 +37,29 @@
extern "C" {
#endif
+#include "task.h"
/**
* Type by which queues are referenced. For example, a call to xQueueCreate()
* returns an QueueHandle_t variable that can then be used as a parameter to
* xQueueSend(), xQueueReceive(), etc.
*/
-typedef void * QueueHandle_t;
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition * QueueHandle_t;
/**
* Type by which queue sets are referenced. For example, a call to
* xQueueCreateSet() returns an xQueueSet variable that can then be used as a
* parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
*/
-typedef void * QueueSetHandle_t;
+typedef struct QueueDefinition * QueueSetHandle_t;
/**
* Queue sets can contain both queues and semaphores, so the
* QueueSetMemberHandle_t is defined as a type to be used where a parameter or
* return value can be either an QueueHandle_t or an SemaphoreHandle_t.
*/
-typedef void * QueueSetMemberHandle_t;
+typedef struct QueueDefinition * QueueSetMemberHandle_t;
/* For internal use only. */
#define queueSEND_TO_BACK ( ( BaseType_t ) 0 )
@@ -1414,15 +1416,15 @@
QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
-void* xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
/*
* For internal use only. Use xSemaphoreTakeMutexRecursive() or
* xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
*/
BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
/*
* Reset a queue back to its original empty state. The return value is now
@@ -1453,7 +1455,7 @@
* preferably in ROM/Flash), not on the stack.
*/
#if( configQUEUE_REGISTRY_SIZE > 0 )
- void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
#endif
/*
diff --git a/Source/include/semphr.h b/Source/include/semphr.h
index e603b4a..2c106ea 100644
--- a/Source/include/semphr.h
+++ b/Source/include/semphr.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/include/stack_macros.h b/Source/include/stack_macros.h
index 79a83ea..18406bb 100644
--- a/Source/include/stack_macros.h
+++ b/Source/include/stack_macros.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -82,10 +82,10 @@
const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \
const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \
\
- if( ( pulStack[ 0 ] != ulCheckValue ) || \
- ( pulStack[ 1 ] != ulCheckValue ) || \
- ( pulStack[ 2 ] != ulCheckValue ) || \
- ( pulStack[ 3 ] != ulCheckValue ) ) \
+ if( ( pulStack[ 0 ] != ulCheckValue ) || \
+ ( pulStack[ 1 ] != ulCheckValue ) || \
+ ( pulStack[ 2 ] != ulCheckValue ) || \
+ ( pulStack[ 3 ] != ulCheckValue ) ) \
{ \
vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
} \
diff --git a/Source/include/stream_buffer.h b/Source/include/stream_buffer.h
index 5418e05..0f00119 100644
--- a/Source/include/stream_buffer.h
+++ b/Source/include/stream_buffer.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -61,7 +61,8 @@
* then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
* etc.
*/
-typedef void * StreamBufferHandle_t;
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
/**
@@ -220,7 +221,7 @@
const void *pvTxData,
size_t xDataLengthBytes,
TickType_t xTicksToWait );
-<pre>
+</pre>
*
* Sends bytes to a stream buffer. The bytes are copied into the stream buffer.
*
@@ -317,7 +318,7 @@
const void *pvTxData,
size_t xDataLengthBytes,
BaseType_t *pxHigherPriorityTaskWoken );
-<pre>
+</pre>
*
* Interrupt safe version of the API function that sends a stream of bytes to
* the stream buffer.
@@ -839,6 +840,8 @@
uint8_t * const pucStreamBufferStorageArea,
StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
#if( configUSE_TRACE_FACILITY == 1 )
void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
diff --git a/Source/include/task.h b/Source/include/task.h
index d0ee068..f3cf118 100644
--- a/Source/include/task.h
+++ b/Source/include/task.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -43,10 +43,18 @@
* MACROS AND DEFINITIONS
*----------------------------------------------------------*/
-#define tskKERNEL_VERSION_NUMBER "V10.0.1"
+#define tskKERNEL_VERSION_NUMBER "V10.2.0"
#define tskKERNEL_VERSION_MAJOR 10
-#define tskKERNEL_VERSION_MINOR 0
-#define tskKERNEL_VERSION_BUILD 1
+#define tskKERNEL_VERSION_MINOR 2
+#define tskKERNEL_VERSION_BUILD 0
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY ( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL )
/**
* task. h
@@ -58,7 +66,8 @@
* \defgroup TaskHandle_t TaskHandle_t
* \ingroup Tasks
*/
-typedef void * TaskHandle_t;
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock* TaskHandle_t;
/*
* Defines the prototype to which the application task hook function must
@@ -74,7 +83,7 @@
eBlocked, /* The task being queried is in the Blocked state. */
eSuspended, /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
eDeleted, /* The task being queried has been deleted, but its TCB has not yet been freed. */
- eInvalid /* Used as an 'invalid state' value. */
+ eInvalid /* Used as an 'invalid state' value. */
} eTaskState;
/* Actions that can be performed when vTaskNotify() is called. */
@@ -113,7 +122,7 @@
{
TaskFunction_t pvTaskCode;
const char * const pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
- uint16_t usStackDepth;
+ configSTACK_DEPTH_TYPE usStackDepth;
void *pvParameters;
UBaseType_t uxPriority;
StackType_t *puxStackBuffer;
@@ -135,7 +144,7 @@
UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
uint32_t ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See http://www.freertos.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
StackType_t *pxStackBase; /* Points to the lowest address of the task's stack area. */
- uint16_t usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */
+ configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */
} TaskStatus_t;
/* Possible return values for eTaskConfirmSleepModeStatus(). */
@@ -375,9 +384,9 @@
* memory to be allocated dynamically.
*
* @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
- * be created and pdPASS is returned. If either pxStackBuffer or pxTaskBuffer
- * are NULL then the task will not be created and
- * errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY is returned.
+ * be created and a handle to the created task is returned. If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
*
* Example usage:
<pre>
@@ -834,7 +843,7 @@
/**
* task. h
- * <pre>UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask );</pre>
+ * <pre>UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );</pre>
*
* INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
* See the configuration section for more information.
@@ -877,15 +886,15 @@
* \defgroup uxTaskPriorityGet uxTaskPriorityGet
* \ingroup TaskCtrl
*/
-UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
/**
* task. h
- * <pre>UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask );</pre>
+ * <pre>UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );</pre>
*
* A version of uxTaskPriorityGet() that can be used from an ISR.
*/
-UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
/**
* task. h
@@ -1412,6 +1421,12 @@
* a value of 1 means 4 bytes) since the task started. The smaller the returned
* number the closer the task has come to overflowing its stack.
*
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type. Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type. It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
* @param xTask Handle of the task associated with the stack to be checked.
* Set xTask to NULL to check the stack of the calling task.
*
@@ -1421,6 +1436,33 @@
*/
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+/**
+ * task.h
+ * <PRE>configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );</PRE>
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask. That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started. The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type. Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type. It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
/* When using trace macros it is sometimes necessary to include task.h before
FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined,
so the following two prototypes will cause a compilation error. This can be
@@ -1443,9 +1485,20 @@
* task.h
* <pre>void xTaskGetApplicationTaskTag( TaskHandle_t xTask );</pre>
*
- * Returns the pxHookFunction value assigned to the task xTask.
+ * Returns the pxHookFunction value assigned to the task xTask. Do not
+ * call from an interrupt service routine - call
+ * xTaskGetApplicationTaskTagFromISR() instead.
*/
TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+ /**
+ * task.h
+ * <pre>void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );</pre>
+ *
+ * Returns the pxHookFunction value assigned to the task xTask. Can
+ * be called from an interrupt service routine.
+ */
+ TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
@@ -1684,6 +1737,36 @@
void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
/**
+* task. h
+* <PRE>TickType_t xTaskGetIdleRunTimeCounter( void );</PRE>
+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available. The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively. The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task. The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, xTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task. This is the amount of time the
+* idle task has actually been executing. The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup xTaskGetIdleRunTimeCounter xTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+TickType_t xTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
+/**
* task. h
* <PRE>BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );</PRE>
*
@@ -2221,7 +2304,7 @@
* Sets the pointer to the current TCB to the TCB of the highest priority task
* that is ready to run.
*/
-void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
/*
* THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY
@@ -2301,7 +2384,7 @@
void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
/*
- * Only avilable when configUSE_TICKLESS_IDLE is set to 1.
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
* Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
* specific sleep function to determine if it is ok to proceed with the sleep,
* and if it is ok to proceed, if it is ok to sleep indefinitely.
@@ -2320,7 +2403,7 @@
* For internal use only. Increment the mutex held count when a mutex is
* taken and return the handle of the task that has taken the mutex.
*/
-void *pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
/*
* For internal use only. Same as vTaskSetTimeOutState(), but without a critial
diff --git a/Source/include/timers.h b/Source/include/timers.h
index 05eb90f..cb72179 100644
--- a/Source/include/timers.h
+++ b/Source/include/timers.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -73,7 +73,8 @@
* reference the subject timer in calls to other software timer API functions
* (for example, xTimerStart(), xTimerReset(), etc.).
*/
-typedef void * TimerHandle_t;
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
/*
* Defines the prototype to which timer callback functions must conform.
@@ -1231,6 +1232,23 @@
const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an autoreload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function). If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
* TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
*
* Returns the period of a timer.
diff --git a/Source/list.c b/Source/list.c
index 758523a..21dabde 100644
--- a/Source/list.c
+++ b/Source/list.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -39,7 +39,7 @@
/* The list structure contains a list item which is used to mark the
end of the list. To initialise the list the list end is inserted
as the only list entry. */
- pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
/* The list end value is the highest possible value in the list to
ensure it remains at the end of the list. */
@@ -47,8 +47,8 @@
/* The list end next and previous pointers point to itself so we know
when the list is empty. */
- pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
- pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
@@ -62,7 +62,7 @@
void vListInitialiseItem( ListItem_t * const pxItem )
{
/* Make sure the list item is not recorded as being on a list. */
- pxItem->pvContainer = NULL;
+ pxItem->pxContainer = NULL;
/* Write known values into the list item if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
@@ -94,7 +94,7 @@
pxIndex->pxPrevious = pxNewListItem;
/* Remember which list the item is in. */
- pxNewListItem->pvContainer = ( void * ) pxList;
+ pxNewListItem->pxContainer = pxList;
( pxList->uxNumberOfItems )++;
}
@@ -114,7 +114,7 @@
/* Insert the new list item into the list, sorted in xItemValue order.
If the list already contains a list item with the same item value then the
- new list item should be placed after it. This ensures that TCB's which are
+ new list item should be placed after it. This ensures that TCBs which are
stored in ready lists (all of which have the same xItemValue value) get a
share of the CPU. However, if the xItemValue is the same as the back marker
the iteration loop below will not end. Therefore the value is checked
@@ -127,18 +127,18 @@
{
/* *** NOTE ***********************************************************
If you find your application is crashing here then likely causes are
- listed below. In addition see http://www.freertos.org/FAQHelp.html for
+ listed below. In addition see https://www.freertos.org/FAQHelp.html for
more tips, and ensure configASSERT() is defined!
- http://www.freertos.org/a00110.html#configASSERT
+ https://www.freertos.org/a00110.html#configASSERT
1) Stack overflow -
- see http://www.freertos.org/Stacks-and-stack-overflow-checking.html
+ see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
2) Incorrect interrupt priority assignment, especially on Cortex-M
parts where numerically high priority values denote low actual
interrupt priorities, which can seem counter intuitive. See
- http://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+ https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
of configMAX_SYSCALL_INTERRUPT_PRIORITY on
- http://www.freertos.org/a00110.html
+ https://www.freertos.org/a00110.html
3) Calling an API function from within a critical section or when
the scheduler is suspended, or calling an API function that does
not end in "FromISR" from an interrupt.
@@ -147,7 +147,7 @@
before vTaskStartScheduler() has been called?).
**********************************************************************/
- for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
{
/* There is nothing to do here, just iterating to the wanted
insertion position. */
@@ -161,7 +161,7 @@
/* Remember which list the item is in. This allows fast removal of the
item later. */
- pxNewListItem->pvContainer = ( void * ) pxList;
+ pxNewListItem->pxContainer = pxList;
( pxList->uxNumberOfItems )++;
}
@@ -171,7 +171,7 @@
{
/* The list item knows which list it is in. Obtain the list from the list
item. */
-List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;
+List_t * const pxList = pxItemToRemove->pxContainer;
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
@@ -189,7 +189,7 @@
mtCOVERAGE_TEST_MARKER();
}
- pxItemToRemove->pvContainer = NULL;
+ pxItemToRemove->pxContainer = NULL;
( pxList->uxNumberOfItems )--;
return pxList->uxNumberOfItems;
diff --git a/Source/portable/Common/mpu_wrappers.c b/Source/portable/Common/mpu_wrappers.c
index 6872b74..8b3ff27 100644
--- a/Source/portable/Common/mpu_wrappers.c
+++ b/Source/portable/Common/mpu_wrappers.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -46,17 +46,48 @@
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
*/
-extern BaseType_t xPortRaisePrivilege( void );
+BaseType_t xPortRaisePrivilege( void ) FREERTOS_SYSTEM_CALL;
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortRaisePrivilege( void ) /* FREERTOS_SYSTEM_CALL */
+{
+BaseType_t xRunningPrivileged;
+
+ /* Check whether the processor is already privileged. */
+ xRunningPrivileged = portIS_PRIVILEGED();
+
+ /* If the processor is not already privileged, raise privilege. */
+ if( xRunningPrivileged != pdTRUE )
+ {
+ portRAISE_PRIVILEGE();
+ }
+
+ return xRunningPrivileged;
+}
+/*-----------------------------------------------------------*/
+
+void vPortResetPrivilege( BaseType_t xRunningPrivileged )
+{
+ if( xRunningPrivileged != pdTRUE )
+ {
+ portRESET_PRIVILEGE();
+ }
+}
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+ BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -69,7 +100,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
- BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+ BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -82,7 +113,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask )
+ BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -95,7 +126,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
- TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer )
+ TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */
{
TaskHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -107,7 +138,7 @@
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions )
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -117,7 +148,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
- void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete )
+ void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -128,7 +159,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelayUntil == 1 )
- void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement )
+ void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -139,7 +170,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_xTaskAbortDelay == 1 )
- BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask )
+ BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -152,7 +183,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelay == 1 )
- void MPU_vTaskDelay( TickType_t xTicksToDelay )
+ void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -163,7 +194,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_uxTaskPriorityGet == 1 )
- UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t pxTask )
+ UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
{
UBaseType_t uxReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -176,7 +207,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskPrioritySet == 1 )
- void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority )
+ void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -187,7 +218,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_eTaskGetState == 1 )
- eTaskState MPU_eTaskGetState( TaskHandle_t pxTask )
+ eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
eTaskState eReturn;
@@ -200,7 +231,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TRACE_FACILITY == 1 )
- void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+ void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -211,7 +242,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
- TaskHandle_t MPU_xTaskGetIdleTaskHandle( void )
+ TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
{
TaskHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -224,7 +255,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskSuspend == 1 )
- void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend )
+ void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -235,7 +266,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskSuspend == 1 )
- void MPU_vTaskResume( TaskHandle_t pxTaskToResume )
+ void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -245,7 +276,7 @@
#endif
/*-----------------------------------------------------------*/
-void MPU_vTaskSuspendAll( void )
+void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -254,7 +285,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t MPU_xTaskResumeAll( void )
+BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -265,7 +296,7 @@
}
/*-----------------------------------------------------------*/
-TickType_t MPU_xTaskGetTickCount( void )
+TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
{
TickType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -276,7 +307,7 @@
}
/*-----------------------------------------------------------*/
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void )
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
{
UBaseType_t uxReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -287,7 +318,7 @@
}
/*-----------------------------------------------------------*/
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery )
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
{
char *pcReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -299,7 +330,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_xTaskGetHandle == 1 )
- TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery )
+ TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */
{
TaskHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -312,7 +343,7 @@
/*-----------------------------------------------------------*/
#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- void MPU_vTaskList( char *pcWriteBuffer )
+ void MPU_vTaskList( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -323,7 +354,7 @@
/*-----------------------------------------------------------*/
#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer )
+ void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -333,8 +364,21 @@
#endif
/*-----------------------------------------------------------*/
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+ TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
+ {
+ TickType_t xReturn;
+ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+ xReturn = xTaskGetIdleRunTimeCounter();
+ vPortResetPrivilege( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
- void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue )
+ void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -345,7 +389,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
- TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+ TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
{
TaskHookFunction_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -358,7 +402,7 @@
/*-----------------------------------------------------------*/
#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
- void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+ void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -369,7 +413,7 @@
/*-----------------------------------------------------------*/
#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
- void *MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+ void *MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
{
void *pvReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -382,7 +426,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
- BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+ BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -395,7 +439,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_TRACE_FACILITY == 1 )
- UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime )
+ UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
{
UBaseType_t uxReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -408,7 +452,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
- UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+ UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
{
UBaseType_t uxReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -420,8 +464,21 @@
#endif
/*-----------------------------------------------------------*/
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+ configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+ {
+ configSTACK_DEPTH_TYPE uxReturn;
+ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+ uxReturn = uxTaskGetStackHighWaterMark2( xTask );
+ vPortResetPrivilege( xRunningPrivileged );
+ return uxReturn;
+ }
+#endif
+/*-----------------------------------------------------------*/
+
#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )
- TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void )
+ TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
{
TaskHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -434,7 +491,7 @@
/*-----------------------------------------------------------*/
#if ( INCLUDE_xTaskGetSchedulerState == 1 )
- BaseType_t MPU_xTaskGetSchedulerState( void )
+ BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -446,7 +503,7 @@
#endif
/*-----------------------------------------------------------*/
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -455,7 +512,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -467,7 +524,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TASK_NOTIFICATIONS == 1 )
- BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+ BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -480,7 +537,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TASK_NOTIFICATIONS == 1 )
- BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+ BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -493,7 +550,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TASK_NOTIFICATIONS == 1 )
- uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+ uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
uint32_t ulReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -506,7 +563,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TASK_NOTIFICATIONS == 1 )
- BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask )
+ BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -519,7 +576,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType )
+ QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
{
QueueHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -532,7 +589,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
- QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+ QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
{
QueueHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -544,7 +601,7 @@
#endif
/*-----------------------------------------------------------*/
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue )
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -555,7 +612,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -566,7 +623,7 @@
}
/*-----------------------------------------------------------*/
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue )
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
UBaseType_t uxReturn;
@@ -577,7 +634,7 @@
}
/*-----------------------------------------------------------*/
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
UBaseType_t uxReturn;
@@ -588,7 +645,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait )
+BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
BaseType_t xReturn;
@@ -599,7 +656,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
BaseType_t xReturn;
@@ -610,7 +667,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
BaseType_t xReturn;
@@ -621,30 +678,21 @@
}
/*-----------------------------------------------------------*/
-BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t pxQueue, void * const pvBuffer )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-BaseType_t xReturn;
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+ TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+ void * xReturn;
- xReturn = xQueuePeekFromISR( pxQueue, pvBuffer );
- vPortResetPrivilege( xRunningPrivileged );
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-void * xReturn;
-
- xReturn = ( void * ) xQueueGetMutexHolder( xSemaphore );
- vPortResetPrivilege( xRunningPrivileged );
- return xReturn;
-}
+ xReturn = xQueueGetMutexHolder( xSemaphore );
+ vPortResetPrivilege( xRunningPrivileged );
+ return xReturn;
+ }
+#endif
/*-----------------------------------------------------------*/
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType )
+ QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
{
QueueHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -657,7 +705,7 @@
/*-----------------------------------------------------------*/
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
- QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+ QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
{
QueueHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -670,7 +718,7 @@
/*-----------------------------------------------------------*/
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount )
+ QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */
{
QueueHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -684,7 +732,7 @@
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
- QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+ QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
{
QueueHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -697,7 +745,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_RECURSIVE_MUTEXES == 1 )
- BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime )
+ BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -710,7 +758,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_RECURSIVE_MUTEXES == 1 )
- BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+ BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -723,7 +771,7 @@
/*-----------------------------------------------------------*/
#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength )
+ QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */
{
QueueSetHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -736,7 +784,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_QUEUE_SETS == 1 )
- QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks )
+ QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */
{
QueueSetMemberHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -749,7 +797,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_QUEUE_SETS == 1 )
- BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+ BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -762,7 +810,7 @@
/*-----------------------------------------------------------*/
#if ( configUSE_QUEUE_SETS == 1 )
- BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+ BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -775,7 +823,7 @@
/*-----------------------------------------------------------*/
#if configQUEUE_REGISTRY_SIZE > 0
- void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName )
+ void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -787,7 +835,7 @@
/*-----------------------------------------------------------*/
#if configQUEUE_REGISTRY_SIZE > 0
- void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue )
+ void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -799,7 +847,7 @@
/*-----------------------------------------------------------*/
#if configQUEUE_REGISTRY_SIZE > 0
- const char *MPU_pcQueueGetName( QueueHandle_t xQueue )
+ const char *MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
const char *pcReturn;
@@ -812,7 +860,7 @@
#endif
/*-----------------------------------------------------------*/
-void MPU_vQueueDelete( QueueHandle_t xQueue )
+void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -823,7 +871,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- void *MPU_pvPortMalloc( size_t xSize )
+ void *MPU_pvPortMalloc( size_t xSize ) /* FREERTOS_SYSTEM_CALL */
{
void *pvReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -838,7 +886,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- void MPU_vPortFree( void *pv )
+ void MPU_vPortFree( void *pv ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -850,7 +898,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- void MPU_vPortInitialiseBlocks( void )
+ void MPU_vPortInitialiseBlocks( void ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -862,7 +910,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- size_t MPU_xPortGetFreeHeapSize( void )
+ size_t MPU_xPortGetFreeHeapSize( void ) /* FREERTOS_SYSTEM_CALL */
{
size_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -877,7 +925,7 @@
/*-----------------------------------------------------------*/
#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
- TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction )
+ TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */
{
TimerHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -891,7 +939,7 @@
/*-----------------------------------------------------------*/
#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
- TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer )
+ TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */
{
TimerHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -905,7 +953,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TIMERS == 1 )
- void *MPU_pvTimerGetTimerID( const TimerHandle_t xTimer )
+ void *MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
{
void * pvReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -919,7 +967,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TIMERS == 1 )
- void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+ void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -930,7 +978,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer )
+ BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -944,7 +992,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TIMERS == 1 )
- TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void )
+ TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
{
TaskHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -958,7 +1006,7 @@
/*-----------------------------------------------------------*/
#if( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
- BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+ BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -972,7 +1020,18 @@
/*-----------------------------------------------------------*/
#if( configUSE_TIMERS == 1 )
- const char * MPU_pcTimerGetName( TimerHandle_t xTimer )
+ void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+ {
+ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+ vTimerSetReloadMode( xTimer, uxAutoReload );
+ vPortResetPrivilege( xRunningPrivileged );
+ }
+#endif
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+ const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
{
const char * pcReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -986,7 +1045,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TIMERS == 1 )
- TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer )
+ TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
{
TickType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1000,7 +1059,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TIMERS == 1 )
- TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer )
+ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
{
TickType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1014,7 +1073,7 @@
/*-----------------------------------------------------------*/
#if( configUSE_TIMERS == 1 )
- BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+ BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1028,7 +1087,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- EventGroupHandle_t MPU_xEventGroupCreate( void )
+ EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */
{
EventGroupHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1042,7 +1101,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
- EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )
+ EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */
{
EventGroupHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1055,7 +1114,7 @@
#endif
/*-----------------------------------------------------------*/
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
EventBits_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1067,7 +1126,7 @@
}
/*-----------------------------------------------------------*/
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
{
EventBits_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1079,7 +1138,7 @@
}
/*-----------------------------------------------------------*/
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
{
EventBits_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1091,7 +1150,7 @@
}
/*-----------------------------------------------------------*/
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
EventBits_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1103,7 +1162,7 @@
}
/*-----------------------------------------------------------*/
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup )
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1112,7 +1171,7 @@
}
/*-----------------------------------------------------------*/
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait )
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
size_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1124,19 +1183,19 @@
}
/*-----------------------------------------------------------*/
-size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken )
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
size_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
- xReturn = xStreamBufferSendFromISR( xStreamBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken );
+ xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
vPortResetPrivilege( xRunningPrivileged );
return xReturn;
}
/*-----------------------------------------------------------*/
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait )
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
{
size_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1148,19 +1207,7 @@
}
/*-----------------------------------------------------------*/
-size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken )
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
- xReturn = xStreamBufferReceiveFromISR( xStreamBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken );
- vPortResetPrivilege( xRunningPrivileged );
-
- return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1169,7 +1216,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1181,7 +1228,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1193,7 +1240,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1205,7 +1252,7 @@
}
/*-----------------------------------------------------------*/
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
size_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1217,7 +1264,7 @@
}
/*-----------------------------------------------------------*/
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
size_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1229,7 +1276,7 @@
}
/*-----------------------------------------------------------*/
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
{
BaseType_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1242,7 +1289,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+ StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */
{
StreamBufferHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
@@ -1256,7 +1303,7 @@
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
- StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer )
+ StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
{
StreamBufferHandle_t xReturn;
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
diff --git a/Source/portable/GCC/ARM_CM0/port.c b/Source/portable/GCC/ARM_CM0/port.c
index dc2c5c6..a5fb4cc 100644
--- a/Source/portable/GCC/ARM_CM0/port.c
+++ b/Source/portable/GCC/ARM_CM0/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -213,7 +213,7 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
diff --git a/Source/portable/GCC/ARM_CM0/portmacro.h b/Source/portable/GCC/ARM_CM0/portmacro.h
index 2ca4cb9..e1aa450 100644
--- a/Source/portable/GCC/ARM_CM0/portmacro.h
+++ b/Source/portable/GCC/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -115,6 +115,8 @@
#define portNOP()
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
#ifdef __cplusplus
}
#endif
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/port.c b/Source/portable/GCC/ARM_CM23/non_secure/port.c
new file mode 100644
index 0000000..bd85a6f
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )
+#define portNVIC_SYSTICK_INT ( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )
+#define portNVIC_PENDSVSET ( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Stop and reset the SysTick. */
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Check that the MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0;
+ #if( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ 6 ];
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+ {
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != NULL );
+ SecureContext_LoadContext( xSecureContext );
+ }
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+ {
+ /* R0 contains the secure context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+ }
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ }
+ break;
+
+ #if( configENABLE_MPU == 1 )
+ case portSVC_RAISE_PRIVILEGE:
+ {
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+ {
+ vRaisePrivilege();
+ }
+ }
+ break;
+ #endif /* configENABLE_MPU */
+
+ default:
+ {
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ prvSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( ulStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr1 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portasm.c b/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
new file mode 100644
index 0000000..c8345c7
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -0,0 +1,468 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configENABLE_FPU == 1 )
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */
+ " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " movs r5, #1 \n" /* r5 = 1. */
+ " bics r4, r5 \n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n" /* Disable MPU. */
+ " \n"
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n" /* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ " movs r5, #4 \n" /* r5 = 4. */
+ " str r5, [r2] \n" /* Program RNR = 4. */
+ " ldmia r3!, {r6,r7} \n" /* Read first set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n" /* Write first set of RBAR/RLAR registers. */
+ " movs r5, #5 \n" /* r5 = 5. */
+ " str r5, [r2] \n" /* Program RNR = 5. */
+ " ldmia r3!, {r6,r7} \n" /* Read second set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n" /* Write second set of RBAR/RLAR registers. */
+ " movs r5, #6 \n" /* r5 = 6. */
+ " str r5, [r2] \n" /* Program RNR = 6. */
+ " ldmia r3!, {r6,r7} \n" /* Read third set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n" /* Write third set of RBAR/RLAR registers. */
+ " movs r5, #7 \n" /* r5 = 7. */
+ " str r5, [r2] \n" /* Program RNR = 7. */
+ " ldmia r3!, {r6,r7} \n" /* Read fourth set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n" /* Write fourth set of RBAR/RLAR registers. */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " movs r5, #1 \n" /* r5 = 1. */
+ " orrs r4, r5 \n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+ " ldr r5, xSecureContextConst2 \n"
+ " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */
+ " msr control, r3 \n" /* Set this task's CONTROL value. */
+ " adds r0, #32 \n" /* Discard everything up to r0. */
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r4 \n" /* Finally, branch to EXC_RETURN. */
+ #else /* configENABLE_MPU */
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+ " ldr r4, xSecureContextConst2 \n"
+ " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */
+ " movs r1, #2 \n" /* r1 = 2. */
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n" /* Discard everything up to r0. */
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ "xSecureContextConst2: .word xSecureContext \n"
+ #if( configENABLE_MPU == 1 )
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+ " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */
+ " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " bx lr \n" /* Return. */
+ " running_privileged: \n"
+ " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n" /* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* Read the CONTROL register. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " bics r0, r1 \n" /* Clear the bit 0. */
+ " msr control, r0 \n" /* Write back the new CONTROL value. */
+ " bx lr \n" /* Return to the caller. */
+ ::: "r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " orrs r0, r1 \n" /* r0 = r0 | r1. */
+ " msr control, r0 \n" /* CONTROL = r0. */
+ " bx lr \n" /* Return to the caller. */
+ :::"r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
+ " cpsie i \n" /* Globally enable interrupts. */
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n" /* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " mrs r0, PRIMASK \n"
+ " cpsid i \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ /* To avoid compiler warnings. The return statement will never be reached,
+ * but some compilers warn if it is not included, while others won't compile
+ * if it is. */
+ return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " msr PRIMASK, r0 \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ /* Just to avoid compiler warning. ulMask is used from the asm code but
+ * the compiler can't see that. Some compilers generate warnings without
+ * the following line, while others generate warnings if the line is
+ * included. */
+ ( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern SecureContext_SaveContext \n"
+ " .extern SecureContext_LoadContext \n"
+ " \n"
+ " mrs r1, psp \n" /* Read PSP in r1. */
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ " \n"
+ " cbz r0, save_ns_context \n" /* No secure context to save. */
+ " push {r0-r2, r14} \n"
+ " bl SecureContext_SaveContext \n"
+ " pop {r0-r3} \n" /* LR is now in r3. */
+ " mov lr, r3 \n" /* LR = r3. */
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */
+ #if( configENABLE_MPU == 1 )
+ " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ " mrs r3, control \n" /* r3 = CONTROL. */
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #endif /* configENABLE_MPU */
+ " b select_next_task \n"
+ " \n"
+ " save_ns_context: \n"
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */
+ #if( configENABLE_MPU == 1 )
+ " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */
+ " adds r1, r1, #16 \n" /* r1 = r1 + 16. */
+ " stmia r1!, {r4-r7} \n" /* Store the low registers that are not saved automatically. */
+ " mov r4, r8 \n" /* r4 = r8. */
+ " mov r5, r9 \n" /* r5 = r9. */
+ " mov r6, r10 \n" /* r6 = r10. */
+ " mov r7, r11 \n" /* r7 = r11. */
+ " stmia r1!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ " mrs r3, control \n" /* r3 = CONTROL. */
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */
+ " subs r1, r1, #48 \n" /* r1 = r1 - 48. */
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
+ " stmia r1!, {r0, r2-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+ " mov r4, r8 \n" /* r4 = r8. */
+ " mov r5, r9 \n" /* r5 = r9. */
+ " mov r6, r10 \n" /* r6 = r10. */
+ " mov r7, r11 \n" /* r7 = r11. */
+ " stmia r1!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " select_next_task: \n"
+ " cpsid i \n"
+ " bl vTaskSwitchContext \n"
+ " cpsie i \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " movs r5, #1 \n" /* r5 = 1. */
+ " bics r4, r5 \n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n" /* Disable MPU. */
+ " \n"
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n" /* Program MAIR0. */
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ " movs r5, #4 \n" /* r5 = 4. */
+ " str r5, [r2] \n" /* Program RNR = 4. */
+ " ldmia r3!, {r6,r7} \n" /* Read first set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n" /* Write first set of RBAR/RLAR registers. */
+ " movs r5, #5 \n" /* r5 = 5. */
+ " str r5, [r2] \n" /* Program RNR = 5. */
+ " ldmia r3!, {r6,r7} \n" /* Read second set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n" /* Write second set of RBAR/RLAR registers. */
+ " movs r5, #6 \n" /* r5 = 6. */
+ " str r5, [r2] \n" /* Program RNR = 6. */
+ " ldmia r3!, {r6,r7} \n" /* Read third set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n" /* Write third set of RBAR/RLAR registers. */
+ " movs r5, #7 \n" /* r5 = 7. */
+ " str r5, [r2] \n" /* Program RNR = 7. */
+ " ldmia r3!, {r6,r7} \n" /* Read fourth set of RBAR/RLAR from TCB. */
+ " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r4!, {r6,r7} \n" /* Write fourth set of RBAR/RLAR registers. */
+ " \n"
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " movs r5, #1 \n" /* r5 = 1. */
+ " orrs r4, r5 \n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
+ " msr control, r3 \n" /* Restore the CONTROL register value for the task. */
+ " mov lr, r4 \n" /* LR = r4. */
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
+ " push {r1,r4} \n"
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */
+ " pop {r1,r4} \n"
+ " mov lr, r4 \n" /* LR = r4. */
+ " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */
+ " bx lr \n"
+ #else /* configENABLE_MPU */
+ " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
+ " mov lr, r3 \n" /* LR = r3. */
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
+ " push {r1,r3} \n"
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */
+ " pop {r1,r3} \n"
+ " mov lr, r3 \n" /* LR = r3. */
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */
+ " bx lr \n"
+ #endif /* configENABLE_MPU */
+ " \n"
+ " restore_ns_context: \n"
+ " adds r1, r1, #16 \n" /* Move to the high registers. */
+ " ldmia r1!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */
+ " mov r8, r4 \n" /* r8 = r4. */
+ " mov r9, r5 \n" /* r9 = r5. */
+ " mov r10, r6 \n" /* r10 = r6. */
+ " mov r11, r7 \n" /* r11 = r7. */
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */
+ " subs r1, r1, #32 \n" /* Go back to the low registers. */
+ " ldmia r1!, {r4-r7} \n" /* Restore the low registers that are not automatically restored. */
+ " bx lr \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ "xSecureContextConst: .word xSecureContext \n"
+ #if( configENABLE_MPU == 1 )
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " movs r0, #4 \n"
+ " mov r1, lr \n"
+ " tst r0, r1 \n"
+ " beq stacking_used_msp \n"
+ " mrs r0, psp \n"
+ " ldr r2, svchandler_address_const \n"
+ " bx r2 \n"
+ " stacking_used_msp: \n"
+ " mrs r0, msp \n"
+ " ldr r2, svchandler_address_const \n"
+ " bx r2 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " svc %0 \n" /* Secure context is allocated in the supervisor call. */
+ " bx lr \n" /* Return. */
+ :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */
+ " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */
+ " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */
+ " beq free_secure_context \n"
+ " bx lr \n" /* There is no secure context (xSecureContext is NULL). */
+ " free_secure_context: \n"
+ " svc %0 \n" /* Secure context is freed in the supervisor call. */
+ " bx lr \n" /* Return. */
+ :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portasm.h b/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
new file mode 100644
index 0000000..2ecf04e
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
new file mode 100644
index 0000000..bbab1b7
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M23"
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portDONT_DISCARD __attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+ /**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+ #define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+ /**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+ /**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context.c b/Source/portable/GCC/ARM_CM23/secure/secure_context.c
new file mode 100644
index 0000000..53535cd
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
+ uint8_t *pucStackStart; /**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* No stack for thread mode until a task's context is loaded. */
+ secureportSET_PSPLIM( securecontextNO_STACK );
+ secureportSET_PSP( securecontextNO_STACK );
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Configure thread mode to use PSP and to be privileged.. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
+ #endif /* configENABLE_MPU */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+ uint8_t *pucStackMemory = NULL;
+ uint32_t ulIPSR;
+ SecureContextHandle_t xSecureContextHandle = NULL;
+ #if( configENABLE_MPU == 1 )
+ uint32_t *pulCurrentStackPointer = NULL;
+ #endif /* configENABLE_MPU */
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Allocate the context structure. */
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+ if( xSecureContextHandle != NULL )
+ {
+ /* Allocate the stack space. */
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+ if( pucStackMemory != NULL )
+ {
+ /* Since stack grows down, the starting point will be the last
+ * location. Note that this location is next to the last
+ * allocated byte because the hardware decrements the stack
+ * pointer before writing i.e. if stack pointer is 0x2, a push
+ * operation will decrement the stack pointer to 0x1 and then
+ * write at 0x1. */
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+ /* The stack cannot go beyond this location. This value is
+ * programmed in the PSPLIM register on context switch.*/
+ xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+ pulCurrentStackPointer--;
+ if( ulIsTaskPrivileged )
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+ }
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+ }
+ #endif /* configENABLE_MPU */
+ }
+ else
+ {
+ /* Free the context to avoid memory leak and make sure to return
+ * NULL to indicate failure. */
+ vPortFree( xSecureContextHandle );
+ xSecureContextHandle = NULL;
+ }
+ }
+ }
+
+ return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Ensure that valid parameters are passed. */
+ secureportASSERT( xSecureContextHandle != NULL );
+
+ /* Free the stack space. */
+ vPortFree( xSecureContextHandle->pucStackLimit );
+
+ /* Free the context itself. */
+ vPortFree( xSecureContextHandle );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context.h b/Source/portable/GCC/ARM_CM23/secure/secure_context.h
new file mode 100644
index 0000000..e148bff
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK 0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext* SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
new file mode 100644
index 0000000..e703498
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
@@ -0,0 +1,91 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+#if( configENABLE_FPU == 1 )
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+ /* xSecureContextHandle value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+ #if( configENABLE_MPU == 1 )
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+ " msr control, r3 \n" /* CONTROL = r3. */
+ #endif /* configENABLE_MPU */
+ " msr psplim, r2 \n" /* PSPLIM = r2. */
+ " msr psp, r1 \n" /* PSP = r1. */
+ " \n"
+ " load_ctx_therad_mode: \n"
+ " nop \n"
+ " \n"
+ :::"r0", "r1", "r2"
+ );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+ /* xSecureContextHandle value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " mrs r1, psp \n" /* r1 = PSP. */
+ #if( configENABLE_MPU == 1 )
+ " mrs r2, control \n" /* r2 = CONTROL. */
+ " subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */
+ " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+ " stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */
+ #else /* configENABLE_MPU */
+ " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+ #endif /* configENABLE_MPU */
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+ " \n"
+ " save_ctx_therad_mode: \n"
+ " nop \n"
+ " \n"
+ :: "i" ( securecontextNO_STACK ) : "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_heap.c b/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
new file mode 100644
index 0000000..60fce5c
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+ #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+ #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+ #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+ /* The application writer has already defined the array used for the RTOS
+ * heap - probably so it can be placed in a special segment or address. */
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */
+ size_t xBlockSize; /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+ /* Ensure the heap starts on a correctly aligned boundary. */
+ uxAddress = ( size_t ) ucHeap;
+
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ }
+
+ pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ * blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted
+ * at the end of the heap space. */
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ uxAddress -= xHeapStructSize;
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ pxEnd = ( void * ) uxAddress;
+ pxEnd->xBlockSize = 0;
+ pxEnd->pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ * entire heap space, minus the space taken by pxEnd. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+ /* Only one block exists - and it covers the entire usable heap space. */
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+ /* Work out the position of the top bit in a size_t variable. */
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+ /* Iterate through the list until a block is found that has a higher address
+ * than the block being inserted. */
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ {
+ /* Nothing to do here, just iterate to the right position. */
+ }
+
+ /* Do the block being inserted, and the block it is being inserted after
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxIterator;
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ {
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ pxBlockToInsert = pxIterator;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Do the block being inserted, and the block it is being inserted before
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxBlockToInsert;
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ {
+ if( pxIterator->pxNextFreeBlock != pxEnd )
+ {
+ /* Form one big block from the two blocks. */
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ }
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ }
+
+ /* If the block being inserted plugged a gab, so was merged with the block
+ * before and the block after, then it's pxNextFreeBlock pointer will have
+ * already been set, and should not be set here as that would make it point
+ * to itself. */
+ if( pxIterator != pxBlockToInsert )
+ {
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+ /* If this is the first call to malloc then the heap will require
+ * initialisation to setup the list of free blocks. */
+ if( pxEnd == NULL )
+ {
+ prvHeapInit();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ {
+ /* The wanted size is increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( xWantedSize > 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number of
+ * bytes. */
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ {
+ /* Traverse the list from the start (lowest address) block until
+ * one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If the end marker was reached then a block of adequate size was
+ * not found. */
+ if( pxBlock != pxEnd )
+ {
+ /* Return the memory space pointed to - jumping over the
+ * BlockLink_t structure at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+ /* This block is being returned for use so must be taken out
+ * of the list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into
+ * two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new
+ * block following the number of bytes requested. The void
+ * cast is used to prevent byte alignment warnings from the
+ * compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+ /* Calculate the sizes of two blocks split from the single
+ * block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ prvInsertBlockIntoFreeList( pxNewBlockLink );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ {
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The block is being returned - it is allocated and owned by
+ * the application and has no "next" block. */
+ pxBlock->xBlockSize |= xBlockAllocatedBit;
+ pxBlock->pxNextFreeBlock = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceMALLOC( pvReturn, xWantedSize );
+
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif
+
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ * before it. */
+ puc -= xHeapStructSize;
+
+ /* This casting is to keep the compiler from issuing warnings. */
+ pxLink = ( void * ) puc;
+
+ /* Check the block is actually allocated. */
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ {
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ * allocated. */
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+ secureportDISABLE_NON_SECURE_INTERRUPTS();
+ {
+ /* Add this block to the list of free blocks. */
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ }
+ secureportENABLE_NON_SECURE_INTERRUPTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+ return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+ /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_heap.h b/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
new file mode 100644
index 0000000..69e4f2a
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_init.c b/Source/portable/GCC/ARM_CM23/secure/secure_init.c
new file mode 100644
index 0000000..c6525f7
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS ( 26UL )
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS ( 10UL )
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS ( 11UL )
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+ * permitted. CP11 should be programmed to the same value as CP10. */
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ * that we can enable/disable lazy stacking in port.c file. */
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+ * registers (S16-S31) are also pushed to stack on exception entry and
+ * restored on exception return. */
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_init.h b/Source/portable/GCC/ARM_CM23/secure/secure_init.h
new file mode 100644
index 0000000..6c5bc71
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
new file mode 100644
index 0000000..760edab
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT 8
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
+#else
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x ) \
+ if( ( x ) == 0 ) \
+ { \
+ secureportDISABLE_SECURE_INTERRUPTS(); \
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+ for( ;; ); \
+ }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
new file mode 100644
index 0000000..bd85a6f
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )
+#define portNVIC_SYSTICK_INT ( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )
+#define portNVIC_PENDSVSET ( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Stop and reset the SysTick. */
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Check that the MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0;
+ #if( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ 6 ];
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+ {
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != NULL );
+ SecureContext_LoadContext( xSecureContext );
+ }
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+ {
+ /* R0 contains the secure context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+ }
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ }
+ break;
+
+ #if( configENABLE_MPU == 1 )
+ case portSVC_RAISE_PRIVILEGE:
+ {
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+ {
+ vRaisePrivilege();
+ }
+ }
+ break;
+ #endif /* configENABLE_MPU */
+
+ default:
+ {
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ prvSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( ulStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr1 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
new file mode 100644
index 0000000..5b8e604
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -0,0 +1,381 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configENABLE_FPU == 1 )
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
+ " movs r4, #1 \n" /* r4 = 1. */
+ " bics r3, r4 \n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+ " str r3, [r2] \n" /* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r4, [r1] \n" /* r4 = *r1 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n" /* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " movs r4, #4 \n" /* r4 = 4. */
+ " str r4, [r2] \n" /* Program RNR = 4. */
+ " ldmia r1!, {r5,r6} \n" /* Read first set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n" /* Write first set of RBAR/RLAR registers. */
+ " movs r4, #5 \n" /* r4 = 5. */
+ " str r4, [r2] \n" /* Program RNR = 5. */
+ " ldmia r1!, {r5,r6} \n" /* Read second set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n" /* Write second set of RBAR/RLAR registers. */
+ " movs r4, #6 \n" /* r4 = 6. */
+ " str r4, [r2] \n" /* Program RNR = 6. */
+ " ldmia r1!, {r5,r6} \n" /* Read third set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n" /* Write third set of RBAR/RLAR registers. */
+ " movs r4, #7 \n" /* r4 = 7. */
+ " str r4, [r2] \n" /* Program RNR = 7. */
+ " ldmia r1!, {r5,r6} \n" /* Read fourth set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n" /* Write fourth set of RBAR/RLAR registers. */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
+ " movs r4, #1 \n" /* r4 = 1. */
+ " orrs r3, r4 \n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+ " str r3, [r2] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
+ " msr control, r2 \n" /* Set this task's CONTROL value. */
+ " adds r0, #32 \n" /* Discard everything up to r0. */
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */
+ #else /* configENABLE_MPU */
+ " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
+ " movs r1, #2 \n" /* r1 = 2. */
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n" /* Discard everything up to r0. */
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r2 \n" /* Finally, branch to EXC_RETURN. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ #if( configENABLE_MPU == 1 )
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+ " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */
+ " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " bx lr \n" /* Return. */
+ " running_privileged: \n"
+ " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n" /* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* Read the CONTROL register. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " bics r0, r1 \n" /* Clear the bit 0. */
+ " msr control, r0 \n" /* Write back the new CONTROL value. */
+ " bx lr \n" /* Return to the caller. */
+ ::: "r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " movs r1, #1 \n" /* r1 = 1. */
+ " orrs r0, r1 \n" /* r0 = r0 | r1. */
+ " msr control, r0 \n" /* CONTROL = r0. */
+ " bx lr \n" /* Return to the caller. */
+ :::"r0", "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
+ " cpsie i \n" /* Globally enable interrupts. */
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n" /* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " mrs r0, PRIMASK \n"
+ " cpsid i \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ /* To avoid compiler warnings. The return statement will never be reached,
+ * but some compilers warn if it is not included, while others won't compile
+ * if it is. */
+ return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " msr PRIMASK, r0 \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ /* Just to avoid compiler warning. ulMask is used from the asm code but
+ * the compiler can't see that. Some compilers generate warnings without
+ * the following line, while others generate warnings if the line is
+ * included. */
+ ( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, psp \n" /* Read PSP in r0. */
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
+ #if( configENABLE_MPU == 1 )
+ " subs r0, r0, #44 \n" /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */
+ " mrs r1, psplim \n" /* r1 = PSPLIM. */
+ " mrs r2, control \n" /* r2 = CONTROL. */
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
+ " stmia r0!, {r1-r7} \n" /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+ " mov r4, r8 \n" /* r4 = r8. */
+ " mov r5, r9 \n" /* r5 = r9. */
+ " mov r6, r10 \n" /* r6 = r10. */
+ " mov r7, r11 \n" /* r7 = r11. */
+ " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
+ #else /* configENABLE_MPU */
+ " subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
+ " stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+ " mov r4, r8 \n" /* r4 = r8. */
+ " mov r5, r9 \n" /* r5 = r9. */
+ " mov r6, r10 \n" /* r6 = r10. */
+ " mov r7, r11 \n" /* r7 = r11. */
+ " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " cpsid i \n"
+ " bl vTaskSwitchContext \n"
+ " cpsie i \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
+ " movs r4, #1 \n" /* r4 = 1. */
+ " bics r3, r4 \n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+ " str r3, [r2] \n" /* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r4, [r1] \n" /* r4 = *r1 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n" /* Program MAIR0. */
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " movs r4, #4 \n" /* r4 = 4. */
+ " str r4, [r2] \n" /* Program RNR = 4. */
+ " ldmia r1!, {r5,r6} \n" /* Read first set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n" /* Write first set of RBAR/RLAR registers. */
+ " movs r4, #5 \n" /* r4 = 5. */
+ " str r4, [r2] \n" /* Program RNR = 5. */
+ " ldmia r1!, {r5,r6} \n" /* Read second set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n" /* Write second set of RBAR/RLAR registers. */
+ " movs r4, #6 \n" /* r4 = 6. */
+ " str r4, [r2] \n" /* Program RNR = 6. */
+ " ldmia r1!, {r5,r6} \n" /* Read third set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n" /* Write third set of RBAR/RLAR registers. */
+ " movs r4, #7 \n" /* r4 = 7. */
+ " str r4, [r2] \n" /* Program RNR = 7. */
+ " ldmia r1!, {r5,r6} \n" /* Read fourth set of RBAR/RLAR from TCB. */
+ " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
+ " stmia r3!, {r5,r6} \n" /* Write fourth set of RBAR/RLAR registers. */
+ " \n"
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
+ " movs r4, #1 \n" /* r4 = 1. */
+ " orrs r3, r4 \n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+ " str r3, [r2] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " adds r0, r0, #28 \n" /* Move to the high registers. */
+ " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */
+ " mov r8, r4 \n" /* r8 = r4. */
+ " mov r9, r5 \n" /* r9 = r5. */
+ " mov r10, r6 \n" /* r10 = r6. */
+ " mov r11, r7 \n" /* r11 = r7. */
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */
+ " subs r0, r0, #44 \n" /* Move to the starting of the saved context. */
+ " ldmia r0!, {r1-r7} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+ " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */
+ " msr control, r2 \n" /* Restore the CONTROL register value for the task. */
+ " bx r3 \n"
+ #else /* configENABLE_MPU */
+ " adds r0, r0, #24 \n" /* Move to the high registers. */
+ " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */
+ " mov r8, r4 \n" /* r8 = r4. */
+ " mov r9, r5 \n" /* r9 = r5. */
+ " mov r10, r6 \n" /* r10 = r6. */
+ " mov r11, r7 \n" /* r11 = r7. */
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */
+ " subs r0, r0, #40 \n" /* Move to the starting of the saved context. */
+ " ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
+ " bx r3 \n"
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ #if( configENABLE_MPU == 1 )
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " movs r0, #4 \n"
+ " mov r1, lr \n"
+ " tst r0, r1 \n"
+ " beq stacking_used_msp \n"
+ " mrs r0, psp \n"
+ " ldr r2, svchandler_address_const \n"
+ " bx r2 \n"
+ " stacking_used_msp: \n"
+ " mrs r0, msp \n"
+ " ldr r2, svchandler_address_const \n"
+ " bx r2 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..2ecf04e
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..bbab1b7
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M23"
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portDONT_DISCARD __attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+ /**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+ #define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+ /**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+ /**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Source/portable/GCC/ARM_CM3/port.c b/Source/portable/GCC/ARM_CM3/port.c
index d7709c0..7451fee 100644
--- a/Source/portable/GCC/ARM_CM3/port.c
+++ b/Source/portable/GCC/ARM_CM3/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/GCC/ARM_CM3/portmacro.h b/Source/portable/GCC/ARM_CM3/portmacro.h
index 77a5d27..f1becb3 100644
--- a/Source/portable/GCC/ARM_CM3/portmacro.h
+++ b/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -233,6 +233,7 @@
}
/*-----------------------------------------------------------*/
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/port.c b/Source/portable/GCC/ARM_CM33/non_secure/port.c
new file mode 100644
index 0000000..bd85a6f
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )
+#define portNVIC_SYSTICK_INT ( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )
+#define portNVIC_PENDSVSET ( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Stop and reset the SysTick. */
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Check that the MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0;
+ #if( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ 6 ];
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+ {
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != NULL );
+ SecureContext_LoadContext( xSecureContext );
+ }
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+ {
+ /* R0 contains the secure context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+ }
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ }
+ break;
+
+ #if( configENABLE_MPU == 1 )
+ case portSVC_RAISE_PRIVILEGE:
+ {
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+ {
+ vRaisePrivilege();
+ }
+ }
+ break;
+ #endif /* configENABLE_MPU */
+
+ default:
+ {
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ prvSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( ulStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr1 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portasm.c b/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
new file mode 100644
index 0000000..3a24f3a
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -0,0 +1,415 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */
+ " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n" /* Disable MPU. */
+ " \n"
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n" /* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #4 \n" /* r4 = 4. */
+ " str r4, [r2] \n" /* Program RNR = 4. */
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+ " ldr r5, xSecureContextConst2 \n"
+ " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */
+ " msr control, r3 \n" /* Set this task's CONTROL value. */
+ " adds r0, #32 \n" /* Discard everything up to r0. */
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r4 \n" /* Finally, branch to EXC_RETURN. */
+ #else /* configENABLE_MPU */
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+ " ldr r4, xSecureContextConst2 \n"
+ " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
+ " msr psplim, r2 \n" /* Set this task's PSPLIM value. */
+ " movs r1, #2 \n" /* r1 = 2. */
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n" /* Discard everything up to r0. */
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ "xSecureContextConst2: .word xSecureContext \n"
+ #if( configENABLE_MPU == 1 )
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n" /* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* Read the CONTROL register. */
+ " bic r0, #1 \n" /* Clear the bit 0. */
+ " msr control, r0 \n" /* Write back the new CONTROL value. */
+ " bx lr \n" /* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " orr r0, #1 \n" /* r0 = r0 | 1. */
+ " msr control, r0 \n" /* CONTROL = r0. */
+ " bx lr \n" /* Return to the caller. */
+ :::"r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
+ " cpsie i \n" /* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n" /* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " mrs r0, PRIMASK \n"
+ " cpsid i \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ /* To avoid compiler warnings. The return statement will never be reached,
+ * but some compilers warn if it is not included, while others won't compile
+ * if it is. */
+ return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " msr PRIMASK, r0 \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ /* Just to avoid compiler warning. ulMask is used from the asm code but
+ * the compiler can't see that. Some compilers generate warnings without
+ * the following line, while others generate warnings if the line is
+ * included. */
+ ( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " .extern SecureContext_SaveContext \n"
+ " .extern SecureContext_LoadContext \n"
+ " \n"
+ " mrs r1, psp \n" /* Read PSP in r1. */
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+ " \n"
+ " cbz r0, save_ns_context \n" /* No secure context to save. */
+ " push {r0-r2, r14} \n"
+ " bl SecureContext_SaveContext \n"
+ " pop {r0-r3} \n" /* LR is now in r3. */
+ " mov lr, r3 \n" /* LR = r3. */
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */
+ #if( configENABLE_MPU == 1 )
+ " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ " mrs r3, control \n" /* r3 = CONTROL. */
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */
+ " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #endif /* configENABLE_MPU */
+ " b select_next_task \n"
+ " \n"
+ " save_ns_context: \n"
+ " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r2, [r3] \n" /* Read pxCurrentTCB. */
+ #if( configENABLE_FPU == 1 )
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ " it eq \n"
+ " vstmdbeq r1!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */
+ #endif /* configENABLE_FPU */
+ #if( configENABLE_MPU == 1 )
+ " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */
+ " adds r1, r1, #16 \n" /* r1 = r1 + 16. */
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ " mrs r3, control \n" /* r3 = CONTROL. */
+ " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */
+ " subs r1, r1, #16 \n" /* r1 = r1 - 16. */
+ " stm r1, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+ " str r1, [r2] \n" /* Save the new top of stack in TCB. */
+ " adds r1, r1, #12 \n" /* r1 = r1 + 12. */
+ " stm r1, {r4-r11} \n" /* Store the registers that are not saved automatically. */
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
+ " subs r1, r1, #12 \n" /* r1 = r1 - 12. */
+ " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " select_next_task: \n"
+ " cpsid i \n"
+ " bl vTaskSwitchContext \n"
+ " cpsie i \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r3, [r2] \n" /* Read pxCurrentTCB. */
+ " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n" /* Disable MPU. */
+ " \n"
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r4, [r2] \n" /* Program MAIR0. */
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r4, #4 \n" /* r4 = 4. */
+ " str r4, [r2] \n" /* Program RNR = 4. */
+ " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r3!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
+ " msr control, r3 \n" /* Restore the CONTROL register value for the task. */
+ " mov lr, r4 \n" /* LR = r4. */
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
+ " push {r1,r4} \n"
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */
+ " pop {r1,r4} \n"
+ " mov lr, r4 \n" /* LR = r4. */
+ " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */
+ " bx lr \n"
+ #else /* configENABLE_MPU */
+ " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
+ " mov lr, r3 \n" /* LR = r3. */
+ " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ " str r0, [r2] \n" /* Restore the task's xSecureContext. */
+ " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
+ " push {r1,r3} \n"
+ " bl SecureContext_LoadContext \n" /* Restore the secure context. */
+ " pop {r1,r3} \n"
+ " mov lr, r3 \n" /* LR = r3. */
+ " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */
+ " bx lr \n"
+ #endif /* configENABLE_MPU */
+ " \n"
+ " restore_ns_context: \n"
+ " ldmia r1!, {r4-r11} \n" /* Restore the registers that are not automatically restored. */
+ #if( configENABLE_FPU == 1 )
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ " it eq \n"
+ " vldmiaeq r1!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */
+ #endif /* configENABLE_FPU */
+ " msr psp, r1 \n" /* Remember the new top of stack for the task. */
+ " bx lr \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ "xSecureContextConst: .word xSecureContext \n"
+ #if( configENABLE_MPU == 1 )
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ " ldr r1, svchandler_address_const \n"
+ " bx r1 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " svc %0 \n" /* Secure context is allocated in the supervisor call. */
+ " bx lr \n" /* Return. */
+ :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */
+ " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */
+ " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */
+ " it ne \n"
+ " svcne %0 \n" /* Secure context is freed in the supervisor call. */
+ " bx lr \n" /* Return. */
+ :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portasm.h b/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
new file mode 100644
index 0000000..2ecf04e
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
new file mode 100644
index 0000000..d051ddc
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M33"
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portDONT_DISCARD __attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+ /**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+ #define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+ /**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+ /**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context.c b/Source/portable/GCC/ARM_CM33/secure/secure_context.c
new file mode 100644
index 0000000..53535cd
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
+ uint8_t *pucStackStart; /**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* No stack for thread mode until a task's context is loaded. */
+ secureportSET_PSPLIM( securecontextNO_STACK );
+ secureportSET_PSP( securecontextNO_STACK );
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Configure thread mode to use PSP and to be privileged.. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
+ #endif /* configENABLE_MPU */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+ uint8_t *pucStackMemory = NULL;
+ uint32_t ulIPSR;
+ SecureContextHandle_t xSecureContextHandle = NULL;
+ #if( configENABLE_MPU == 1 )
+ uint32_t *pulCurrentStackPointer = NULL;
+ #endif /* configENABLE_MPU */
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Allocate the context structure. */
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+ if( xSecureContextHandle != NULL )
+ {
+ /* Allocate the stack space. */
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+ if( pucStackMemory != NULL )
+ {
+ /* Since stack grows down, the starting point will be the last
+ * location. Note that this location is next to the last
+ * allocated byte because the hardware decrements the stack
+ * pointer before writing i.e. if stack pointer is 0x2, a push
+ * operation will decrement the stack pointer to 0x1 and then
+ * write at 0x1. */
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+ /* The stack cannot go beyond this location. This value is
+ * programmed in the PSPLIM register on context switch.*/
+ xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+ pulCurrentStackPointer--;
+ if( ulIsTaskPrivileged )
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+ }
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+ }
+ #endif /* configENABLE_MPU */
+ }
+ else
+ {
+ /* Free the context to avoid memory leak and make sure to return
+ * NULL to indicate failure. */
+ vPortFree( xSecureContextHandle );
+ xSecureContextHandle = NULL;
+ }
+ }
+ }
+
+ return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Ensure that valid parameters are passed. */
+ secureportASSERT( xSecureContextHandle != NULL );
+
+ /* Free the stack space. */
+ vPortFree( xSecureContextHandle->pucStackLimit );
+
+ /* Free the context itself. */
+ vPortFree( xSecureContextHandle );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context.h b/Source/portable/GCC/ARM_CM33/secure/secure_context.h
new file mode 100644
index 0000000..e148bff
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK 0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext* SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c b/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
new file mode 100644
index 0000000..7c556f5
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
@@ -0,0 +1,88 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+ /* xSecureContextHandle value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " ldmia r0!, {r1, r2} \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+ #if( configENABLE_MPU == 1 )
+ " ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+ " msr control, r3 \n" /* CONTROL = r3. */
+ #endif /* configENABLE_MPU */
+ " msr psplim, r2 \n" /* PSPLIM = r2. */
+ " msr psp, r1 \n" /* PSP = r1. */
+ " \n"
+ " load_ctx_therad_mode: \n"
+ " nop \n"
+ " \n"
+ :::"r0", "r1", "r2"
+ );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+ /* xSecureContextHandle value is in r0. */
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r1, ipsr \n" /* r1 = IPSR. */
+ " cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
+ " mrs r1, psp \n" /* r1 = PSP. */
+ #if( configENABLE_FPU == 1 )
+ " vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */
+ " vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */
+ #endif /* configENABLE_FPU */
+ #if( configENABLE_MPU == 1 )
+ " mrs r2, control \n" /* r2 = CONTROL. */
+ " stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */
+ #endif /* configENABLE_MPU */
+ " str r1, [r0] \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+ " movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
+ " msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
+ " msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+ " \n"
+ " save_ctx_therad_mode: \n"
+ " nop \n"
+ " \n"
+ :: "i" ( securecontextNO_STACK ) : "r1", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_heap.c b/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
new file mode 100644
index 0000000..60fce5c
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+ #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+ #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+ #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+ /* The application writer has already defined the array used for the RTOS
+ * heap - probably so it can be placed in a special segment or address. */
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */
+ size_t xBlockSize; /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+ /* Ensure the heap starts on a correctly aligned boundary. */
+ uxAddress = ( size_t ) ucHeap;
+
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ }
+
+ pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ * blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted
+ * at the end of the heap space. */
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ uxAddress -= xHeapStructSize;
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ pxEnd = ( void * ) uxAddress;
+ pxEnd->xBlockSize = 0;
+ pxEnd->pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ * entire heap space, minus the space taken by pxEnd. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+ /* Only one block exists - and it covers the entire usable heap space. */
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+ /* Work out the position of the top bit in a size_t variable. */
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+ /* Iterate through the list until a block is found that has a higher address
+ * than the block being inserted. */
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ {
+ /* Nothing to do here, just iterate to the right position. */
+ }
+
+ /* Do the block being inserted, and the block it is being inserted after
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxIterator;
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ {
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ pxBlockToInsert = pxIterator;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Do the block being inserted, and the block it is being inserted before
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxBlockToInsert;
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ {
+ if( pxIterator->pxNextFreeBlock != pxEnd )
+ {
+ /* Form one big block from the two blocks. */
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ }
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ }
+
+ /* If the block being inserted plugged a gab, so was merged with the block
+ * before and the block after, then it's pxNextFreeBlock pointer will have
+ * already been set, and should not be set here as that would make it point
+ * to itself. */
+ if( pxIterator != pxBlockToInsert )
+ {
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+ /* If this is the first call to malloc then the heap will require
+ * initialisation to setup the list of free blocks. */
+ if( pxEnd == NULL )
+ {
+ prvHeapInit();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ {
+ /* The wanted size is increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( xWantedSize > 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number of
+ * bytes. */
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ {
+ /* Traverse the list from the start (lowest address) block until
+ * one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If the end marker was reached then a block of adequate size was
+ * not found. */
+ if( pxBlock != pxEnd )
+ {
+ /* Return the memory space pointed to - jumping over the
+ * BlockLink_t structure at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+ /* This block is being returned for use so must be taken out
+ * of the list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into
+ * two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new
+ * block following the number of bytes requested. The void
+ * cast is used to prevent byte alignment warnings from the
+ * compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+ /* Calculate the sizes of two blocks split from the single
+ * block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ prvInsertBlockIntoFreeList( pxNewBlockLink );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ {
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The block is being returned - it is allocated and owned by
+ * the application and has no "next" block. */
+ pxBlock->xBlockSize |= xBlockAllocatedBit;
+ pxBlock->pxNextFreeBlock = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceMALLOC( pvReturn, xWantedSize );
+
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif
+
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ * before it. */
+ puc -= xHeapStructSize;
+
+ /* This casting is to keep the compiler from issuing warnings. */
+ pxLink = ( void * ) puc;
+
+ /* Check the block is actually allocated. */
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ {
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ * allocated. */
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+ secureportDISABLE_NON_SECURE_INTERRUPTS();
+ {
+ /* Add this block to the list of free blocks. */
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ }
+ secureportENABLE_NON_SECURE_INTERRUPTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+ return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+ /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_heap.h b/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
new file mode 100644
index 0000000..69e4f2a
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_init.c b/Source/portable/GCC/ARM_CM33/secure/secure_init.c
new file mode 100644
index 0000000..c6525f7
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS ( 26UL )
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS ( 10UL )
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS ( 11UL )
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+ * permitted. CP11 should be programmed to the same value as CP10. */
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ * that we can enable/disable lazy stacking in port.c file. */
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+ * registers (S16-S31) are also pushed to stack on exception entry and
+ * restored on exception return. */
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_init.h b/Source/portable/GCC/ARM_CM33/secure/secure_init.h
new file mode 100644
index 0000000..6c5bc71
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
new file mode 100644
index 0000000..760edab
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT 8
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
+#else
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x ) \
+ if( ( x ) == 0 ) \
+ { \
+ secureportDISABLE_SECURE_INTERRUPTS(); \
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+ for( ;; ); \
+ }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
new file mode 100644
index 0000000..bd85a6f
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )
+#define portNVIC_SYSTICK_INT ( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )
+#define portNVIC_PENDSVSET ( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Stop and reset the SysTick. */
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Check that the MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0;
+ #if( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ 6 ];
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+ {
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != NULL );
+ SecureContext_LoadContext( xSecureContext );
+ }
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+ {
+ /* R0 contains the secure context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+ }
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ }
+ break;
+
+ #if( configENABLE_MPU == 1 )
+ case portSVC_RAISE_PRIVILEGE:
+ {
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+ {
+ vRaisePrivilege();
+ }
+ }
+ break;
+ #endif /* configENABLE_MPU */
+
+ default:
+ {
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ prvSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( ulStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr1 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
new file mode 100644
index 0000000..ba4a69c
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -0,0 +1,321 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n" /* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */
+ " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r3, [r2] \n" /* Program MAIR0. */
+ " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #4 \n" /* r3 = 4. */
+ " str r3, [r2] \n" /* Program RNR = 4. */
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
+ " msr control, r2 \n" /* Set this task's CONTROL value. */
+ " adds r0, #32 \n" /* Discard everything up to r0. */
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r3 \n" /* Finally, branch to EXC_RETURN. */
+ #else /* configENABLE_MPU */
+ " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+ " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
+ " movs r1, #2 \n" /* r1 = 2. */
+ " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
+ " adds r0, #32 \n" /* Discard everything up to r0. */
+ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
+ " isb \n"
+ " bx r2 \n" /* Finally, branch to EXC_RETURN. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ #if( configENABLE_MPU == 1 )
+ "xMPUCTRLConst2: .word 0xe000ed94 \n"
+ "xMAIR0Const2: .word 0xe000edc0 \n"
+ "xRNRConst2: .word 0xe000ed98 \n"
+ "xRBARConst2: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n" /* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* Read the CONTROL register. */
+ " bic r0, #1 \n" /* Clear the bit 0. */
+ " msr control, r0 \n" /* Write back the new CONTROL value. */
+ " bx lr \n" /* Return to the caller. */
+ ::: "r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " orr r0, #1 \n" /* r0 = r0 | 1. */
+ " msr control, r0 \n" /* CONTROL = r0. */
+ " bx lr \n" /* Return to the caller. */
+ :::"r0", "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
+ " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
+ " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
+ " cpsie i \n" /* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc %0 \n" /* System call to start the first task. */
+ " nop \n"
+ " \n"
+ " .align 4 \n"
+ "xVTORConst: .word 0xe000ed08 \n"
+ :: "i" ( portSVC_START_SCHEDULER ) : "memory"
+ );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " mrs r0, PRIMASK \n"
+ " cpsid i \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ /* To avoid compiler warnings. The return statement will never be reached,
+ * but some compilers warn if it is not included, while others won't compile
+ * if it is. */
+ return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " msr PRIMASK, r0 \n"
+ " bx lr \n"
+ ::: "memory"
+ );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ /* Just to avoid compiler warning. ulMask is used from the asm code but
+ * the compiler can't see that. Some compilers generate warnings without
+ * the following line, while others generate warnings if the line is
+ * included. */
+ ( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " .syntax unified \n"
+ " \n"
+ " mrs r0, psp \n" /* Read PSP in r0. */
+ #if( configENABLE_FPU == 1 )
+ " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ " it eq \n"
+ " vstmdbeq r0!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */
+ #endif /* configENABLE_FPU */
+ #if( configENABLE_MPU == 1 )
+ " mrs r1, psplim \n" /* r1 = PSPLIM. */
+ " mrs r2, control \n" /* r2 = CONTROL. */
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
+ " stmdb r0!, {r1-r11} \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+ #else /* configENABLE_MPU */
+ " mrs r2, psplim \n" /* r2 = PSPLIM. */
+ " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
+ " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
+ " str r0, [r1] \n" /* Save the new top of stack in TCB. */
+ " \n"
+ " cpsid i \n"
+ " bl vTaskSwitchContext \n"
+ " cpsie i \n"
+ " \n"
+ " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " dmb \n" /* Complete outstanding transfers before disabling MPU. */
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ " str r4, [r2] \n" /* Disable MPU. */
+ " \n"
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */
+ " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ " str r3, [r2] \n" /* Program MAIR0. */
+ " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+ " movs r3, #4 \n" /* r3 = 4. */
+ " str r3, [r2] \n" /* Program RNR = 4. */
+ " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+ " ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+ " \n"
+ " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
+ " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ " str r4, [r2] \n" /* Enable MPU. */
+ " dsb \n" /* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " ldmia r0!, {r1-r11} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+ #else /* configENABLE_MPU */
+ " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+ #endif /* configENABLE_MPU */
+ " \n"
+ #if( configENABLE_FPU == 1 )
+ " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ " it eq \n"
+ " vldmiaeq r0!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */
+ #endif /* configENABLE_FPU */
+ " \n"
+ #if( configENABLE_MPU == 1 )
+ " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */
+ " msr control, r2 \n" /* Restore the CONTROL register value for the task. */
+ #else /* configENABLE_MPU */
+ " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
+ #endif /* configENABLE_MPU */
+ " msr psp, r0 \n" /* Remember the new top of stack for the task. */
+ " bx r3 \n"
+ " \n"
+ " .align 4 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ #if( configENABLE_MPU == 1 )
+ "xMPUCTRLConst: .word 0xe000ed94 \n"
+ "xMAIR0Const: .word 0xe000edc0 \n"
+ "xRNRConst: .word 0xe000ed98 \n"
+ "xRBARConst: .word 0xe000ed9c \n"
+ #endif /* configENABLE_MPU */
+ );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+ __asm volatile
+ (
+ " tst lr, #4 \n"
+ " ite eq \n"
+ " mrseq r0, msp \n"
+ " mrsne r0, psp \n"
+ " ldr r1, svchandler_address_const \n"
+ " bx r1 \n"
+ " \n"
+ " .align 4 \n"
+ "svchandler_address_const: .word vPortSVCHandler_C \n"
+ );
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..2ecf04e
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..d051ddc
--- /dev/null
+++ b/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M33"
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portDONT_DISCARD __attribute__(( used ))
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+ /**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+ #define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+ /**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+ /**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Source/portable/GCC/ARM_CM3_MPU/port.c b/Source/portable/GCC/ARM_CM3_MPU/port.c
index 39cfbfc..454f90f 100644
--- a/Source/portable/GCC/ARM_CM3_MPU/port.c
+++ b/Source/portable/GCC/ARM_CM3_MPU/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -115,13 +115,6 @@
static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
-
-/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
* generate the tick interrupt.
@@ -146,6 +139,35 @@
*/
static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
/*-----------------------------------------------------------*/
/* Each task maintains its own interrupt status in the critical nesting
@@ -585,21 +607,33 @@
}
/*-----------------------------------------------------------*/
-BaseType_t xPortRaisePrivilege( void )
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
{
__asm volatile
(
- " mrs r0, control \n"
- " tst r0, #1 \n" /* Is the task running privileged? */
- " itte ne \n"
- " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */
- " svcne %0 \n" /* Switch to privileged. */
- " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */
- " bx lr \n"
- :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n" /* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "memory"
);
+}
+/*-----------------------------------------------------------*/
- return 0;
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " orr r0, #1 \n" /* r0 = r0 | 1. */
+ " msr control, r0 \n" /* CONTROL = r0. */
+ " bx lr \n" /* Return to the caller. */
+ :::"r0", "memory"
+ );
}
/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
index 6057f1c..3458b0e 100644
--- a/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ b/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -200,18 +200,28 @@
#ifndef portFORCE_INLINE
#define portFORCE_INLINE inline __attribute__(( always_inline))
#endif
+/*-----------------------------------------------------------*/
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
- if( xRunningPrivileged != pdTRUE )
- {
- __asm volatile ( " mrs r0, control \n" \
- " orr r0, #1 \n" \
- " msr control, r0 \n" \
- :::"r0", "memory" );
- }
-}
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE() vResetPrivilege()
/*-----------------------------------------------------------*/
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
@@ -281,6 +291,7 @@
}
/*-----------------------------------------------------------*/
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM4F/port.c b/Source/portable/GCC/ARM_CM4F/port.c
index ae96b4c..a065abf 100644
--- a/Source/portable/GCC/ARM_CM4F/port.c
+++ b/Source/portable/GCC/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/GCC/ARM_CM4F/portmacro.h b/Source/portable/GCC/ARM_CM4F/portmacro.h
index 1a95016..fd31d22 100644
--- a/Source/portable/GCC/ARM_CM4F/portmacro.h
+++ b/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -233,6 +233,7 @@
}
/*-----------------------------------------------------------*/
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM4_MPU/port.c b/Source/portable/GCC/ARM_CM4_MPU/port.c
index 5a881f4..9c68178 100644
--- a/Source/portable/GCC/ARM_CM4_MPU/port.c
+++ b/Source/portable/GCC/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -124,13 +124,6 @@
static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
-
-/*
* Setup the timer to generate the tick interrupts. The implementation in this
* file is weak to allow application writers to change the timer used to
* generate the tick interrupt.
@@ -160,6 +153,35 @@
*/
static void vPortEnableVFP( void ) __attribute__ (( naked ));
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
/*-----------------------------------------------------------*/
/* Each task maintains its own interrupt status in the critical nesting
@@ -573,7 +595,7 @@
( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
( portMPU_REGION_ENABLE );
- /* Setup the first 16K for privileged only access (even though less
+ /* Setup the first nK for privileged only access (even though less
than 10K is actually being used). This is where the kernel code is
placed. */
portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
@@ -639,21 +661,33 @@
}
/*-----------------------------------------------------------*/
-BaseType_t xPortRaisePrivilege( void )
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
{
__asm volatile
(
- " mrs r0, control \n"
- " tst r0, #1 \n" /* Is the task running privileged? */
- " itte ne \n"
- " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */
- " svcne %0 \n" /* Switch to privileged. */
- " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */
- " bx lr \n"
- :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n" /* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "memory"
);
+}
+/*-----------------------------------------------------------*/
- return 0;
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " orr r0, #1 \n" /* r0 = r0 | 1. */
+ " msr control, r0 \n" /* CONTROL = r0. */
+ " bx lr \n" /* Return to the caller. */
+ :::"r0", "memory"
+ );
}
/*-----------------------------------------------------------*/
diff --git a/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
index 6057f1c..3458b0e 100644
--- a/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ b/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -200,18 +200,28 @@
#ifndef portFORCE_INLINE
#define portFORCE_INLINE inline __attribute__(( always_inline))
#endif
+/*-----------------------------------------------------------*/
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
- if( xRunningPrivileged != pdTRUE )
- {
- __asm volatile ( " mrs r0, control \n" \
- " orr r0, #1 \n" \
- " msr control, r0 \n" \
- :::"r0", "memory" );
- }
-}
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE() vResetPrivilege()
/*-----------------------------------------------------------*/
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
@@ -281,6 +291,7 @@
}
/*-----------------------------------------------------------*/
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM7/r0p1/port.c b/Source/portable/GCC/ARM_CM7/r0p1/port.c
index 325264d..ce867ee 100644
--- a/Source/portable/GCC/ARM_CM7/r0p1/port.c
+++ b/Source/portable/GCC/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
index 5f912ae..62543ac 100644
--- a/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ b/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -237,6 +237,7 @@
}
/*-----------------------------------------------------------*/
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
diff --git a/Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c b/Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c
index 1243f47..6e8a933 100644
--- a/Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c
+++ b/Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -47,12 +47,18 @@
#ifndef configSYSTICK_CLOCK_HZ
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
+#else
+ /* The way the SysTick is clocked is not modified in case it is not the same
+ as the core. */
+ #define portNVIC_SYSTICK_CLK ( 0 )
#endif
/* Constants required to access and manipulate the NVIC. */
#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
#define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
#define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
@@ -73,9 +79,7 @@
#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
/* Constants required to access and manipulate the SysTick. */
-#define portNVIC_SYSTICK_CLK ( 0x00000004UL )
#define portNVIC_SYSTICK_INT ( 0x00000002UL )
-#define portNVIC_SYSTICK_COUNT_FLAG ( 1UL << 16UL )
#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
@@ -87,7 +91,7 @@
/* Constants required to set up the initial stack. */
#define portINITIAL_XPSR ( 0x01000000UL )
-#define portINITIAL_EXEC_RETURN ( 0xfffffffdUL )
+#define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
@@ -141,11 +145,11 @@
static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
+ * Setup the timer to generate the tick interrupts. The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
*/
-BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
+void vPortSetupTimerInterrupt( void );
/*
* Standard FreeRTOS exception handlers.
@@ -169,43 +173,43 @@
* Function to enable the VFP.
*/
static void vPortEnableVFP( void ) __attribute__ (( naked ));
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if configUSE_TICKLESS_IDLE == 1
- static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
*/
-#if configUSE_TICKLESS_IDLE == 1
- static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
*/
-#if configUSE_TICKLESS_IDLE == 1
- static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
+void vResetPrivilege( void ) __attribute__ (( naked ));
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
*/
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+
#if ( configASSERT_DEFINED == 1 )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
-
/*
* See header file for description.
*/
@@ -221,12 +225,12 @@
*pxTopOfStack = 0; /* LR */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-
+
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXEC_RETURN;
-
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
if( xRunPrivileged == pdTRUE )
@@ -256,7 +260,7 @@
" mrs r0, psp \n"
#endif
" b %0 \n"
- ::"i"(prvSVCHandler):"r0"
+ ::"i"(prvSVCHandler):"r0", "memory"
);
}
/*-----------------------------------------------------------*/
@@ -279,7 +283,7 @@
but do ensure the code is completely
within the specified behaviour for the
architecture. */
- __asm volatile( "dsb" );
+ __asm volatile( "dsb" ::: "memory" );
__asm volatile( "isb" );
break;
@@ -289,7 +293,7 @@
" mrs r1, control \n" /* Obtain current control value. */
" bic r1, #1 \n" /* Set privilege bit. */
" msr control, r1 \n" /* Write back new control value. */
- :::"r1"
+ ::: "r1", "memory"
);
break;
@@ -369,6 +373,24 @@
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ priority bits matches the number of priority bits actually queried
+ from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ priority bits matches the number of priority bits actually queried
+ from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
@@ -402,19 +424,24 @@
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
- /* Start the first task. */
+ /* Start the first task. This also clears the bit that indicates the FPU is
+ in use in case the FPU was used before the scheduler was started - which
+ would otherwise result in the unnecessary leaving of space in the SVC stack
+ for lazy saving of FPU registers. */
__asm volatile(
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, [r0] \n"
" ldr r0, [r0] \n"
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
+ " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
+ " msr control, r0 \n"
" cpsie i \n" /* Globally enable interrupts. */
" cpsie f \n"
" dsb \n"
" isb \n"
" svc %0 \n" /* System call to start first task. */
" nop \n"
- :: "i" (portSVC_START_SCHEDULER) );
+ :: "i" (portSVC_START_SCHEDULER) : "memory" );
/* Should not get here! */
return 0;
@@ -461,6 +488,7 @@
__asm volatile
(
" mrs r0, psp \n"
+ " isb \n"
" \n"
" ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
" ldr r2, [r3] \n"
@@ -473,7 +501,7 @@
" stmdb r0!, {r1, r4-r11, r14} \n" /* Save the remaining registers. */
" str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
" \n"
- " stmdb sp!, {r3} \n"
+ " stmdb sp!, {r0, r3} \n"
" mov r0, %0 \n"
" cpsid i \n" /* Errata workaround. */
" msr basepri, r0 \n"
@@ -483,8 +511,8 @@
" bl vTaskSwitchContext \n"
" mov r0, #0 \n"
" msr basepri, r0 \n"
- " ldmia sp!, {r3} \n"
- " \n" /* Restore the context. */
+ " ldmia sp!, {r0, r3} \n"
+ " \n" /* Restore the context. */
" ldr r1, [r3] \n"
" ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
" add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
@@ -686,14 +714,9 @@
*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
- /* Calculate the constants required to configure the tick interrupt. */
- #if configUSE_TICKLESS_IDLE == 1
- {
- ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
- #endif /* configUSE_TICKLESS_IDLE */
+ /* Stop and clear the SysTick. */
+ portNVIC_SYSTICK_CTRL_REG = 0UL;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
@@ -725,6 +748,9 @@
extern uint32_t __privileged_data_start__[];
extern uint32_t __privileged_data_end__[];
+ /* Check the expected MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
/* First setup the entire flash for unprivileged read only access. */
portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
@@ -735,7 +761,7 @@
( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
( portMPU_REGION_ENABLE );
- /* Setup the first 16K for privileged only access (even though less
+ /* Setup the first nK for privileged only access (even though less
than 10K is actually being used). This is where the kernel code is
placed. */
portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
@@ -773,6 +799,7 @@
/* Enable the MPU with the background region configured. */
portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+ }
}
/*-----------------------------------------------------------*/
@@ -800,21 +827,33 @@
}
/*-----------------------------------------------------------*/
-BaseType_t xPortRaisePrivilege( void )
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
{
__asm volatile
(
- " mrs r0, control \n"
- " tst r0, #1 \n" /* Is the task running privileged? */
- " itte ne \n"
- " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */
- " svcne %0 \n" /* Switch to privileged. */
- " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */
- " bx lr \n"
- :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ " ite ne \n"
+ " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ " bx lr \n" /* Return. */
+ " \n"
+ " .align 4 \n"
+ ::: "r0", "memory"
);
+}
+/*-----------------------------------------------------------*/
- return 0;
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+ __asm volatile
+ (
+ " mrs r0, control \n" /* r0 = CONTROL. */
+ " orr r0, #1 \n" /* r0 = r0 | 1. */
+ " msr control, r0 \n" /* CONTROL = r0. */
+ " bx lr \n" /* Return to the caller. */
+ :::"r0", "memory"
+ );
}
/*-----------------------------------------------------------*/
@@ -922,7 +961,7 @@
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
diff --git a/Source/portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h b/Source/portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h
index be1d742..3a2d604 100644
--- a/Source/portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h
+++ b/Source/portable/GCC/ARM_CM7_MPU/r0p1/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -89,7 +89,7 @@
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" )
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
typedef struct MPU_REGION_REGISTERS
{
@@ -116,7 +116,7 @@
/* Scheduler utilities. */
-#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) )
+#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) : "memory" )
#define portYIELD_WITHIN_API() \
{ \
/* Set a PendSV to request a context switch. */ \
@@ -124,7 +124,7 @@
\
/* Barriers are normally not required but do ensure the code is completely \
within the specified behaviour for the architecture. */ \
- __asm volatile( "dsb" ); \
+ __asm volatile( "dsb" ::: "memory" ); \
__asm volatile( "isb" ); \
}
@@ -165,7 +165,7 @@
{
uint8_t ucReturn;
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
return ucReturn;
}
@@ -199,18 +199,28 @@
#ifndef portFORCE_INLINE
#define portFORCE_INLINE inline __attribute__(( always_inline))
#endif
+/*-----------------------------------------------------------*/
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
- if( xRunningPrivileged != pdTRUE )
- {
- __asm volatile ( " mrs r0, control \n" \
- " orr r0, #1 \n" \
- " msr control, r0 \n" \
- :::"r0" );
- }
-}
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE() vResetPrivilege()
/*-----------------------------------------------------------*/
portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
@@ -219,7 +229,7 @@
BaseType_t xReturn;
/* Obtain the number of the currently executing interrupt. */
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
if( ulCurrentInterrupt == 0 )
{
@@ -247,7 +257,7 @@
" isb \n" \
" dsb \n" \
" cpsie i \n" \
- :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
@@ -266,7 +276,7 @@
" isb \n" \
" dsb \n" \
" cpsie i \n" \
- :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+ :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
/* This return will not be reached but is necessary to prevent compiler
@@ -279,11 +289,12 @@
{
__asm volatile
(
- " msr basepri, %0 " :: "r" ( ulNewMaskValue )
+ " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
);
}
/*-----------------------------------------------------------*/
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
#ifdef __cplusplus
}
diff --git a/Source/portable/IAR/ARM_CM0/port.c b/Source/portable/IAR/ARM_CM0/port.c
index aaa1801..36b81aa 100644
--- a/Source/portable/IAR/ARM_CM0/port.c
+++ b/Source/portable/IAR/ARM_CM0/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/IAR/ARM_CM0/portasm.s b/Source/portable/IAR/ARM_CM0/portasm.s
index ec98a86..a2e3ce8 100644
--- a/Source/portable/IAR/ARM_CM0/portasm.s
+++ b/Source/portable/IAR/ARM_CM0/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/IAR/ARM_CM0/portmacro.h b/Source/portable/IAR/ARM_CM0/portmacro.h
index 02e2cbd..758f80f 100644
--- a/Source/portable/IAR/ARM_CM0/portmacro.h
+++ b/Source/portable/IAR/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/port.c b/Source/portable/IAR/ARM_CM23/non_secure/port.c
new file mode 100644
index 0000000..bd85a6f
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )
+#define portNVIC_SYSTICK_INT ( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )
+#define portNVIC_PENDSVSET ( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Stop and reset the SysTick. */
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Check that the MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0;
+ #if( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ 6 ];
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+ {
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != NULL );
+ SecureContext_LoadContext( xSecureContext );
+ }
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+ {
+ /* R0 contains the secure context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+ }
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ }
+ break;
+
+ #if( configENABLE_MPU == 1 )
+ case portSVC_RAISE_PRIVILEGE:
+ {
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+ {
+ vRaisePrivilege();
+ }
+ }
+ break;
+ #endif /* configENABLE_MPU */
+
+ default:
+ {
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ prvSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( ulStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr1 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portasm.h b/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
new file mode 100644
index 0000000..2ecf04e
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portasm.s b/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
new file mode 100644
index 0000000..b1a543a
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
@@ -0,0 +1,377 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+ EXTERN pxCurrentTCB
+ EXTERN xSecureContext
+ EXTERN vTaskSwitchContext
+ EXTERN vPortSVCHandler_C
+ EXTERN SecureContext_SaveContext
+ EXTERN SecureContext_LoadContext
+
+ PUBLIC xIsPrivileged
+ PUBLIC vResetPrivilege
+ PUBLIC vPortAllocateSecureContext
+ PUBLIC vRestoreContextOfFirstTask
+ PUBLIC vRaisePrivilege
+ PUBLIC vStartFirstTask
+ PUBLIC ulSetInterruptMaskFromISR
+ PUBLIC vClearInterruptMaskFromISR
+ PUBLIC PendSV_Handler
+ PUBLIC SVC_Handler
+ PUBLIC vPortFreeSecureContext
+
+#if ( configENABLE_FPU == 1 )
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+ mrs r0, control /* r0 = CONTROL. */
+ movs r1, #1 /* r1 = 1. */
+ tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+ beq running_privileged /* If the result of previous AND operation was 0, branch. */
+ movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ bx lr /* Return. */
+ running_privileged:
+ movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+ mrs r0, control /* r0 = CONTROL. */
+ movs r1, #1 /* r1 = 1. */
+ orrs r0, r1 /* r0 = r0 | r1. */
+ msr control, r0 /* CONTROL = r0. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+ svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION privileged_functions:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r3, [r2] /* Read pxCurrentTCB. */
+ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ movs r5, #1 /* r5 = 1. */
+ bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+ str r4, [r2] /* Disable MPU. */
+
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r4, [r2] /* Program MAIR0. */
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ movs r5, #4 /* r5 = 4. */
+ str r5, [r2] /* Program RNR = 4. */
+ ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
+ stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */
+ movs r5, #5 /* r5 = 5. */
+ str r5, [r2] /* Program RNR = 5. */
+ ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
+ stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */
+ movs r5, #6 /* r5 = 6. */
+ str r5, [r2] /* Program RNR = 6. */
+ ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
+ stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */
+ movs r5, #7 /* r5 = 7. */
+ str r5, [r2] /* Program RNR = 7. */
+ ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
+ stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */
+
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ movs r5, #1 /* r5 = 1. */
+ orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+ str r4, [r2] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+ ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+ ldr r5, =xSecureContext
+ str r1, [r5] /* Set xSecureContext to this task's value for the same. */
+ msr psplim, r2 /* Set this task's PSPLIM value. */
+ msr control, r3 /* Set this task's CONTROL value. */
+ adds r0, #32 /* Discard everything up to r0. */
+ msr psp, r0 /* This is now the new top of stack to use in the task. */
+ isb
+ bx r4 /* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+ ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+ ldr r4, =xSecureContext
+ str r1, [r4] /* Set xSecureContext to this task's value for the same. */
+ msr psplim, r2 /* Set this task's PSPLIM value. */
+ movs r1, #2 /* r1 = 2. */
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
+ adds r0, #32 /* Discard everything up to r0. */
+ msr psp, r0 /* This is now the new top of stack to use in the task. */
+ isb
+ bx r3 /* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+ mrs r0, control /* Read the CONTROL register. */
+ movs r1, #1 /* r1 = 1. */
+ bics r0, r1 /* Clear the bit 0. */
+ msr control, r0 /* Write back the new CONTROL value. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */
+ msr msp, r0 /* Set the MSP back to the start of the stack. */
+ cpsie i /* Globally enable interrupts. */
+ dsb
+ isb
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+ msr PRIMASK, r0
+ bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+ mrs r1, psp /* Read PSP in r1. */
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+ cbz r0, save_ns_context /* No secure context to save. */
+ push {r0-r2, r14}
+ bl SecureContext_SaveContext
+ pop {r0-r3} /* LR is now in r3. */
+ mov lr, r3 /* LR = r3. */
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r2, [r3] /* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+ subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ str r1, [r2] /* Save the new top of stack in TCB. */
+ mrs r2, psplim /* r2 = PSPLIM. */
+ mrs r3, control /* r3 = CONTROL. */
+ mov r4, lr /* r4 = LR/EXC_RETURN. */
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+ subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+ str r1, [r2] /* Save the new top of stack in TCB. */
+ mrs r2, psplim /* r2 = PSPLIM. */
+ mov r3, lr /* r3 = LR/EXC_RETURN. */
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+ b select_next_task
+
+ save_ns_context:
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r2, [r3] /* Read pxCurrentTCB. */
+ #if ( configENABLE_MPU == 1 )
+ subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+ str r1, [r2] /* Save the new top of stack in TCB. */
+ adds r1, r1, #16 /* r1 = r1 + 16. */
+ stmia r1!, {r4-r7} /* Store the low registers that are not saved automatically. */
+ mov r4, r8 /* r4 = r8. */
+ mov r5, r9 /* r5 = r9. */
+ mov r6, r10 /* r6 = r10. */
+ mov r7, r11 /* r7 = r11. */
+ stmia r1!, {r4-r7} /* Store the high registers that are not saved automatically. */
+ mrs r2, psplim /* r2 = PSPLIM. */
+ mrs r3, control /* r3 = CONTROL. */
+ mov r4, lr /* r4 = LR/EXC_RETURN. */
+ subs r1, r1, #48 /* r1 = r1 - 48. */
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+ str r1, [r2] /* Save the new top of stack in TCB. */
+ mrs r2, psplim /* r2 = PSPLIM. */
+ mov r3, lr /* r3 = LR/EXC_RETURN. */
+ stmia r1!, {r0, r2-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+ mov r4, r8 /* r4 = r8. */
+ mov r5, r9 /* r5 = r9. */
+ mov r6, r10 /* r6 = r10. */
+ mov r7, r11 /* r7 = r11. */
+ stmia r1!, {r4-r7} /* Store the high registers that are not saved automatically. */
+ #endif /* configENABLE_MPU */
+
+ select_next_task:
+ cpsid i
+ bl vTaskSwitchContext
+ cpsie i
+
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r3, [r2] /* Read pxCurrentTCB. */
+ ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+ #if ( configENABLE_MPU == 1 )
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ movs r5, #1 /* r5 = 1. */
+ bics r4, r5 /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+ str r4, [r2] /* Disable MPU. */
+
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r4, [r2] /* Program MAIR0. */
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ movs r5, #4 /* r5 = 4. */
+ str r5, [r2] /* Program RNR = 4. */
+ ldmia r3!, {r6,r7} /* Read first set of RBAR/RLAR from TCB. */
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
+ stmia r4!, {r6,r7} /* Write first set of RBAR/RLAR registers. */
+ movs r5, #5 /* r5 = 5. */
+ str r5, [r2] /* Program RNR = 5. */
+ ldmia r3!, {r6,r7} /* Read second set of RBAR/RLAR from TCB. */
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
+ stmia r4!, {r6,r7} /* Write second set of RBAR/RLAR registers. */
+ movs r5, #6 /* r5 = 6. */
+ str r5, [r2] /* Program RNR = 6. */
+ ldmia r3!, {r6,r7} /* Read third set of RBAR/RLAR from TCB. */
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
+ stmia r4!, {r6,r7} /* Write third set of RBAR/RLAR registers. */
+ movs r5, #7 /* r5 = 7. */
+ str r5, [r2] /* Program RNR = 7. */
+ ldmia r3!, {r6,r7} /* Read fourth set of RBAR/RLAR from TCB. */
+ ldr r4, =0xe000ed9c /* r4 = 0xe000ed9c [Location of RBAR]. */
+ stmia r4!, {r6,r7} /* Write fourth set of RBAR/RLAR registers. */
+
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ movs r5, #1 /* r5 = 1. */
+ orrs r4, r5 /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+ str r4, [r2] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+
+ #if ( configENABLE_MPU == 1 )
+ ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */
+ msr control, r3 /* Restore the CONTROL register value for the task. */
+ mov lr, r4 /* LR = r4. */
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ str r0, [r2] /* Restore the task's xSecureContext. */
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
+ push {r1,r4}
+ bl SecureContext_LoadContext /* Restore the secure context. */
+ pop {r1,r4}
+ mov lr, r4 /* LR = r4. */
+ lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ msr psp, r1 /* Remember the new top of stack for the task. */
+ bx lr
+ #else /* configENABLE_MPU */
+ ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */
+ mov lr, r3 /* LR = r3. */
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ str r0, [r2] /* Restore the task's xSecureContext. */
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
+ push {r1,r3}
+ bl SecureContext_LoadContext /* Restore the secure context. */
+ pop {r1,r3}
+ mov lr, r3 /* LR = r3. */
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ msr psp, r1 /* Remember the new top of stack for the task. */
+ bx lr
+ #endif /* configENABLE_MPU */
+
+ restore_ns_context:
+ adds r1, r1, #16 /* Move to the high registers. */
+ ldmia r1!, {r4-r7} /* Restore the high registers that are not automatically restored. */
+ mov r8, r4 /* r8 = r4. */
+ mov r9, r5 /* r9 = r5. */
+ mov r10, r6 /* r10 = r6. */
+ mov r11, r7 /* r11 = r7. */
+ msr psp, r1 /* Remember the new top of stack for the task. */
+ subs r1, r1, #32 /* Go back to the low registers. */
+ ldmia r1!, {r4-r7} /* Restore the low registers that are not automatically restored. */
+ bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+ movs r0, #4
+ mov r1, lr
+ tst r0, r1
+ beq stacking_used_msp
+ mrs r0, psp
+ b vPortSVCHandler_C
+ stacking_used_msp:
+ mrs r0, msp
+ b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+ ldr r1, [r0] /* The first item in the TCB is the top of the stack. */
+ ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */
+ cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */
+ beq free_secure_context
+ bx lr /* There is no secure context (xSecureContext is NULL). */
+ free_secure_context:
+ svc 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+ END
diff --git a/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
new file mode 100644
index 0000000..8ea5340
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -0,0 +1,306 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M23"
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portDONT_DISCARD __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+ /**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+ #define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+ /**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+ /**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context.c b/Source/portable/IAR/ARM_CM23/secure/secure_context.c
new file mode 100644
index 0000000..53535cd
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
+ uint8_t *pucStackStart; /**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* No stack for thread mode until a task's context is loaded. */
+ secureportSET_PSPLIM( securecontextNO_STACK );
+ secureportSET_PSP( securecontextNO_STACK );
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Configure thread mode to use PSP and to be privileged.. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
+ #endif /* configENABLE_MPU */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+ uint8_t *pucStackMemory = NULL;
+ uint32_t ulIPSR;
+ SecureContextHandle_t xSecureContextHandle = NULL;
+ #if( configENABLE_MPU == 1 )
+ uint32_t *pulCurrentStackPointer = NULL;
+ #endif /* configENABLE_MPU */
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Allocate the context structure. */
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+ if( xSecureContextHandle != NULL )
+ {
+ /* Allocate the stack space. */
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+ if( pucStackMemory != NULL )
+ {
+ /* Since stack grows down, the starting point will be the last
+ * location. Note that this location is next to the last
+ * allocated byte because the hardware decrements the stack
+ * pointer before writing i.e. if stack pointer is 0x2, a push
+ * operation will decrement the stack pointer to 0x1 and then
+ * write at 0x1. */
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+ /* The stack cannot go beyond this location. This value is
+ * programmed in the PSPLIM register on context switch.*/
+ xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+ pulCurrentStackPointer--;
+ if( ulIsTaskPrivileged )
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+ }
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+ }
+ #endif /* configENABLE_MPU */
+ }
+ else
+ {
+ /* Free the context to avoid memory leak and make sure to return
+ * NULL to indicate failure. */
+ vPortFree( xSecureContextHandle );
+ xSecureContextHandle = NULL;
+ }
+ }
+ }
+
+ return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Ensure that valid parameters are passed. */
+ secureportASSERT( xSecureContextHandle != NULL );
+
+ /* Free the stack space. */
+ vPortFree( xSecureContextHandle->pucStackLimit );
+
+ /* Free the context itself. */
+ vPortFree( xSecureContextHandle );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context.h b/Source/portable/IAR/ARM_CM23/secure/secure_context.h
new file mode 100644
index 0000000..e148bff
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK 0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext* SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c b/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c
new file mode 100644
index 0000000..619db1e
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+ SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+ SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
new file mode 100644
index 0000000..65cee0c
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
@@ -0,0 +1,76 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+
+ PUBLIC SecureContext_LoadContextAsm
+ PUBLIC SecureContext_SaveContextAsm
+
+#if ( configENABLE_FPU == 1 )
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+ /* xSecureContextHandle value is in r0. */
+ mrs r1, ipsr /* r1 = IPSR. */
+ cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
+ ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+ ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+ msr control, r3 /* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+ msr psplim, r2 /* PSPLIM = r2. */
+ msr psp, r1 /* PSP = r1. */
+
+ load_ctx_therad_mode:
+ bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+ /* xSecureContextHandle value is in r0. */
+ mrs r1, ipsr /* r1 = IPSR. */
+ cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
+ mrs r1, psp /* r1 = PSP. */
+#if ( configENABLE_MPU == 1 )
+ mrs r2, control /* r2 = CONTROL. */
+ subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */
+ str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+ stmia r1!, {r2} /* Store CONTROL value on the stack. */
+#else /* configENABLE_MPU */
+ str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+#endif /* configENABLE_MPU */
+ movs r1, #0 /* r1 = securecontextNO_STACK. */
+ msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
+ msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+ save_ctx_therad_mode:
+ bx lr
+/*-----------------------------------------------------------*/
+
+ END
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_heap.c b/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
new file mode 100644
index 0000000..60fce5c
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+ #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+ #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+ #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+ /* The application writer has already defined the array used for the RTOS
+ * heap - probably so it can be placed in a special segment or address. */
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */
+ size_t xBlockSize; /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+ /* Ensure the heap starts on a correctly aligned boundary. */
+ uxAddress = ( size_t ) ucHeap;
+
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ }
+
+ pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ * blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted
+ * at the end of the heap space. */
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ uxAddress -= xHeapStructSize;
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ pxEnd = ( void * ) uxAddress;
+ pxEnd->xBlockSize = 0;
+ pxEnd->pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ * entire heap space, minus the space taken by pxEnd. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+ /* Only one block exists - and it covers the entire usable heap space. */
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+ /* Work out the position of the top bit in a size_t variable. */
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+ /* Iterate through the list until a block is found that has a higher address
+ * than the block being inserted. */
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ {
+ /* Nothing to do here, just iterate to the right position. */
+ }
+
+ /* Do the block being inserted, and the block it is being inserted after
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxIterator;
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ {
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ pxBlockToInsert = pxIterator;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Do the block being inserted, and the block it is being inserted before
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxBlockToInsert;
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ {
+ if( pxIterator->pxNextFreeBlock != pxEnd )
+ {
+ /* Form one big block from the two blocks. */
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ }
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ }
+
+ /* If the block being inserted plugged a gab, so was merged with the block
+ * before and the block after, then it's pxNextFreeBlock pointer will have
+ * already been set, and should not be set here as that would make it point
+ * to itself. */
+ if( pxIterator != pxBlockToInsert )
+ {
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+ /* If this is the first call to malloc then the heap will require
+ * initialisation to setup the list of free blocks. */
+ if( pxEnd == NULL )
+ {
+ prvHeapInit();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ {
+ /* The wanted size is increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( xWantedSize > 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number of
+ * bytes. */
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ {
+ /* Traverse the list from the start (lowest address) block until
+ * one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If the end marker was reached then a block of adequate size was
+ * not found. */
+ if( pxBlock != pxEnd )
+ {
+ /* Return the memory space pointed to - jumping over the
+ * BlockLink_t structure at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+ /* This block is being returned for use so must be taken out
+ * of the list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into
+ * two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new
+ * block following the number of bytes requested. The void
+ * cast is used to prevent byte alignment warnings from the
+ * compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+ /* Calculate the sizes of two blocks split from the single
+ * block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ prvInsertBlockIntoFreeList( pxNewBlockLink );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ {
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The block is being returned - it is allocated and owned by
+ * the application and has no "next" block. */
+ pxBlock->xBlockSize |= xBlockAllocatedBit;
+ pxBlock->pxNextFreeBlock = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceMALLOC( pvReturn, xWantedSize );
+
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif
+
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ * before it. */
+ puc -= xHeapStructSize;
+
+ /* This casting is to keep the compiler from issuing warnings. */
+ pxLink = ( void * ) puc;
+
+ /* Check the block is actually allocated. */
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ {
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ * allocated. */
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+ secureportDISABLE_NON_SECURE_INTERRUPTS();
+ {
+ /* Add this block to the list of free blocks. */
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ }
+ secureportENABLE_NON_SECURE_INTERRUPTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+ return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+ /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_heap.h b/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
new file mode 100644
index 0000000..69e4f2a
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_init.c b/Source/portable/IAR/ARM_CM23/secure/secure_init.c
new file mode 100644
index 0000000..c6525f7
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS ( 26UL )
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS ( 10UL )
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS ( 11UL )
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+ * permitted. CP11 should be programmed to the same value as CP10. */
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ * that we can enable/disable lazy stacking in port.c file. */
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+ * registers (S16-S31) are also pushed to stack on exception entry and
+ * restored on exception return. */
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_init.h b/Source/portable/IAR/ARM_CM23/secure/secure_init.h
new file mode 100644
index 0000000..6c5bc71
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
new file mode 100644
index 0000000..760edab
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT 8
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
+#else
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x ) \
+ if( ( x ) == 0 ) \
+ { \
+ secureportDISABLE_SECURE_INTERRUPTS(); \
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+ for( ;; ); \
+ }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
new file mode 100644
index 0000000..bd85a6f
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )
+#define portNVIC_SYSTICK_INT ( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )
+#define portNVIC_PENDSVSET ( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Stop and reset the SysTick. */
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Check that the MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0;
+ #if( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ 6 ];
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+ {
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != NULL );
+ SecureContext_LoadContext( xSecureContext );
+ }
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+ {
+ /* R0 contains the secure context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+ }
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ }
+ break;
+
+ #if( configENABLE_MPU == 1 )
+ case portSVC_RAISE_PRIVILEGE:
+ {
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+ {
+ vRaisePrivilege();
+ }
+ }
+ break;
+ #endif /* configENABLE_MPU */
+
+ default:
+ {
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ prvSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( ulStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr1 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..2ecf04e
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
new file mode 100644
index 0000000..3121df6
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
@@ -0,0 +1,303 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+ EXTERN pxCurrentTCB
+ EXTERN vTaskSwitchContext
+ EXTERN vPortSVCHandler_C
+
+ PUBLIC xIsPrivileged
+ PUBLIC vResetPrivilege
+ PUBLIC vRestoreContextOfFirstTask
+ PUBLIC vRaisePrivilege
+ PUBLIC vStartFirstTask
+ PUBLIC ulSetInterruptMaskFromISR
+ PUBLIC vClearInterruptMaskFromISR
+ PUBLIC PendSV_Handler
+ PUBLIC SVC_Handler
+
+#if ( configENABLE_FPU == 1 )
+ #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+ mrs r0, control /* r0 = CONTROL. */
+ movs r1, #1 /* r1 = 1. */
+ tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+ beq running_privileged /* If the result of previous AND operation was 0, branch. */
+ movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ bx lr /* Return. */
+ running_privileged:
+ movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ bx lr /* Return. */
+
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+ mrs r0, control /* r0 = CONTROL. */
+ movs r1, #1 /* r1 = 1. */
+ orrs r0, r1 /* r0 = r0 | r1. */
+ msr control, r0 /* CONTROL = r0. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION privileged_functions:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r2] /* Read pxCurrentTCB. */
+ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */
+ movs r4, #1 /* r4 = 1. */
+ bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+ str r3, [r2] /* Disable MPU. */
+
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r4, [r2] /* Program MAIR0. */
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ movs r4, #4 /* r4 = 4. */
+ str r4, [r2] /* Program RNR = 4. */
+ ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
+ stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */
+ movs r4, #5 /* r4 = 5. */
+ str r4, [r2] /* Program RNR = 5. */
+ ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
+ stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */
+ movs r4, #6 /* r4 = 6. */
+ str r4, [r2] /* Program RNR = 6. */
+ ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
+ stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */
+ movs r4, #7 /* r4 = 7. */
+ str r4, [r2] /* Program RNR = 7. */
+ ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
+ stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */
+
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */
+ movs r4, #1 /* r4 = 1. */
+ orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+ str r3, [r2] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+ ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+ msr psplim, r1 /* Set this task's PSPLIM value. */
+ msr control, r2 /* Set this task's CONTROL value. */
+ adds r0, #32 /* Discard everything up to r0. */
+ msr psp, r0 /* This is now the new top of stack to use in the task. */
+ isb
+ bx r3 /* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+ msr psplim, r1 /* Set this task's PSPLIM value. */
+ movs r1, #2 /* r1 = 2. */
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
+ adds r0, #32 /* Discard everything up to r0. */
+ msr psp, r0 /* This is now the new top of stack to use in the task. */
+ isb
+ bx r2 /* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+ mrs r0, control /* Read the CONTROL register. */
+ movs r1, #1 /* r1 = 1. */
+ bics r0, r1 /* Clear the bit 0. */
+ msr control, r0 /* Write back the new CONTROL value. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */
+ msr msp, r0 /* Set the MSP back to the start of the stack. */
+ cpsie i /* Globally enable interrupts. */
+ dsb
+ isb
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+ nop
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+ msr PRIMASK, r0
+ bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+ mrs r0, psp /* Read PSP in r0. */
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r2] /* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+ subs r0, r0, #44 /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+ str r0, [r1] /* Save the new top of stack in TCB. */
+ mrs r1, psplim /* r1 = PSPLIM. */
+ mrs r2, control /* r2 = CONTROL. */
+ mov r3, lr /* r3 = LR/EXC_RETURN. */
+ stmia r0!, {r1-r7} /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+ mov r4, r8 /* r4 = r8. */
+ mov r5, r9 /* r5 = r9. */
+ mov r6, r10 /* r6 = r10. */
+ mov r7, r11 /* r7 = r11. */
+ stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */
+#else /* configENABLE_MPU */
+ subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */
+ str r0, [r1] /* Save the new top of stack in TCB. */
+ mrs r2, psplim /* r2 = PSPLIM. */
+ mov r3, lr /* r3 = LR/EXC_RETURN. */
+ stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+ mov r4, r8 /* r4 = r8. */
+ mov r5, r9 /* r5 = r9. */
+ mov r6, r10 /* r6 = r10. */
+ mov r7, r11 /* r7 = r11. */
+ stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */
+#endif /* configENABLE_MPU */
+
+ cpsid i
+ bl vTaskSwitchContext
+ cpsie i
+
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r2] /* Read pxCurrentTCB. */
+ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */
+ movs r4, #1 /* r4 = 1. */
+ bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+ str r3, [r2] /* Disable MPU. */
+
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r4, [r2] /* Program MAIR0. */
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ movs r4, #4 /* r4 = 4. */
+ str r4, [r2] /* Program RNR = 4. */
+ ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
+ stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */
+ movs r4, #5 /* r4 = 5. */
+ str r4, [r2] /* Program RNR = 5. */
+ ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
+ stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */
+ movs r4, #6 /* r4 = 6. */
+ str r4, [r2] /* Program RNR = 6. */
+ ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
+ stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */
+ movs r4, #7 /* r4 = 7. */
+ str r4, [r2] /* Program RNR = 7. */
+ ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */
+ ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
+ stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */
+
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r3, [r2] /* Read the value of MPU_CTRL. */
+ movs r4, #1 /* r4 = 1. */
+ orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+ str r3, [r2] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+ adds r0, r0, #28 /* Move to the high registers. */
+ ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */
+ mov r8, r4 /* r8 = r4. */
+ mov r9, r5 /* r9 = r5. */
+ mov r10, r6 /* r10 = r6. */
+ mov r11, r7 /* r11 = r7. */
+ msr psp, r0 /* Remember the new top of stack for the task. */
+ subs r0, r0, #44 /* Move to the starting of the saved context. */
+ ldmia r0!, {r1-r7} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+ msr psplim, r1 /* Restore the PSPLIM register value for the task. */
+ msr control, r2 /* Restore the CONTROL register value for the task. */
+ bx r3
+#else /* configENABLE_MPU */
+ adds r0, r0, #24 /* Move to the high registers. */
+ ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */
+ mov r8, r4 /* r8 = r4. */
+ mov r9, r5 /* r9 = r5. */
+ mov r10, r6 /* r10 = r6. */
+ mov r11, r7 /* r11 = r7. */
+ msr psp, r0 /* Remember the new top of stack for the task. */
+ subs r0, r0, #40 /* Move to the starting of the saved context. */
+ ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */
+ bx r3
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+ movs r0, #4
+ mov r1, lr
+ tst r0, r1
+ beq stacking_used_msp
+ mrs r0, psp
+ b vPortSVCHandler_C
+ stacking_used_msp:
+ mrs r0, msp
+ b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+ END
diff --git a/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..8ea5340
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -0,0 +1,306 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M23"
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portDONT_DISCARD __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+ /**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+ #define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+ /**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+ /**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Source/portable/IAR/ARM_CM3/port.c b/Source/portable/IAR/ARM_CM3/port.c
index 7bf366e..f13aa84 100644
--- a/Source/portable/IAR/ARM_CM3/port.c
+++ b/Source/portable/IAR/ARM_CM3/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/IAR/ARM_CM3/portasm.s b/Source/portable/IAR/ARM_CM3/portasm.s
index cf2e13e..fbc278a 100644
--- a/Source/portable/IAR/ARM_CM3/portasm.s
+++ b/Source/portable/IAR/ARM_CM3/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/IAR/ARM_CM3/portmacro.h b/Source/portable/IAR/ARM_CM3/portmacro.h
index 7fc59c2..1d69069 100644
--- a/Source/portable/IAR/ARM_CM3/portmacro.h
+++ b/Source/portable/IAR/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -78,6 +78,12 @@
#define portBYTE_ALIGNMENT 8
/*-----------------------------------------------------------*/
+/* Compiler directives. */
+#define portWEAK_SYMBOL __attribute__( ( weak ) )
+
+/*-----------------------------------------------------------*/
+
+
/* Scheduler utilities. */
#define portYIELD() \
{ \
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/port.c b/Source/portable/IAR/ARM_CM33/non_secure/port.c
new file mode 100644
index 0000000..bd85a6f
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )
+#define portNVIC_SYSTICK_INT ( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )
+#define portNVIC_PENDSVSET ( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Stop and reset the SysTick. */
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Check that the MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0;
+ #if( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ 6 ];
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+ {
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != NULL );
+ SecureContext_LoadContext( xSecureContext );
+ }
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+ {
+ /* R0 contains the secure context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+ }
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ }
+ break;
+
+ #if( configENABLE_MPU == 1 )
+ case portSVC_RAISE_PRIVILEGE:
+ {
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+ {
+ vRaisePrivilege();
+ }
+ }
+ break;
+ #endif /* configENABLE_MPU */
+
+ default:
+ {
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ prvSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( ulStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr1 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portasm.h b/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
new file mode 100644
index 0000000..2ecf04e
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portasm.s b/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
new file mode 100644
index 0000000..e38104c
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -0,0 +1,326 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+ EXTERN pxCurrentTCB
+ EXTERN xSecureContext
+ EXTERN vTaskSwitchContext
+ EXTERN vPortSVCHandler_C
+ EXTERN SecureContext_SaveContext
+ EXTERN SecureContext_LoadContext
+
+ PUBLIC xIsPrivileged
+ PUBLIC vResetPrivilege
+ PUBLIC vPortAllocateSecureContext
+ PUBLIC vRestoreContextOfFirstTask
+ PUBLIC vRaisePrivilege
+ PUBLIC vStartFirstTask
+ PUBLIC ulSetInterruptMaskFromISR
+ PUBLIC vClearInterruptMaskFromISR
+ PUBLIC PendSV_Handler
+ PUBLIC SVC_Handler
+ PUBLIC vPortFreeSecureContext
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+ mrs r0, control /* r0 = CONTROL. */
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ ite ne
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+ mrs r0, control /* r0 = CONTROL. */
+ orr r0, r0, #1 /* r0 = r0 | 1. */
+ msr control, r0 /* CONTROL = r0. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+ svc 0 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION privileged_functions:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r3, [r2] /* Read pxCurrentTCB. */
+ ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ str r4, [r2] /* Disable MPU. */
+
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r4, [r2] /* Program MAIR0. */
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
+ movs r4, #4 /* r4 = 4. */
+ str r4, [r2] /* Program RNR = 4. */
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
+ ldmia r3!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ str r4, [r2] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+ ldm r0!, {r1-r4} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+ ldr r5, =xSecureContext
+ str r1, [r5] /* Set xSecureContext to this task's value for the same. */
+ msr psplim, r2 /* Set this task's PSPLIM value. */
+ msr control, r3 /* Set this task's CONTROL value. */
+ adds r0, #32 /* Discard everything up to r0. */
+ msr psp, r0 /* This is now the new top of stack to use in the task. */
+ isb
+ bx r4 /* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+ ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+ ldr r4, =xSecureContext
+ str r1, [r4] /* Set xSecureContext to this task's value for the same. */
+ msr psplim, r2 /* Set this task's PSPLIM value. */
+ movs r1, #2 /* r1 = 2. */
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
+ adds r0, #32 /* Discard everything up to r0. */
+ msr psp, r0 /* This is now the new top of stack to use in the task. */
+ isb
+ bx r3 /* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+ mrs r0, control /* Read the CONTROL register. */
+ bic r0, r0, #1 /* Clear the bit 0. */
+ msr control, r0 /* Write back the new CONTROL value. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */
+ msr msp, r0 /* Set the MSP back to the start of the stack. */
+ cpsie i /* Globally enable interrupts. */
+ cpsie f
+ dsb
+ isb
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+ msr PRIMASK, r0
+ bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+ mrs r1, psp /* Read PSP in r1. */
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+ cbz r0, save_ns_context /* No secure context to save. */
+ push {r0-r2, r14}
+ bl SecureContext_SaveContext
+ pop {r0-r3} /* LR is now in r3. */
+ mov lr, r3 /* LR = r3. */
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r2, [r3] /* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+ subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ str r1, [r2] /* Save the new top of stack in TCB. */
+ mrs r2, psplim /* r2 = PSPLIM. */
+ mrs r3, control /* r3 = CONTROL. */
+ mov r4, lr /* r4 = LR/EXC_RETURN. */
+ stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+ subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+ str r1, [r2] /* Save the new top of stack in TCB. */
+ mrs r2, psplim /* r2 = PSPLIM. */
+ mov r3, lr /* r3 = LR/EXC_RETURN. */
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+ b select_next_task
+
+ save_ns_context:
+ ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r2, [r3] /* Read pxCurrentTCB. */
+ #if ( configENABLE_FPU == 1 )
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ it eq
+ vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */
+ #endif /* configENABLE_FPU */
+ #if ( configENABLE_MPU == 1 )
+ subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+ str r1, [r2] /* Save the new top of stack in TCB. */
+ adds r1, r1, #16 /* r1 = r1 + 16. */
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */
+ mrs r2, psplim /* r2 = PSPLIM. */
+ mrs r3, control /* r3 = CONTROL. */
+ mov r4, lr /* r4 = LR/EXC_RETURN. */
+ subs r1, r1, #16 /* r1 = r1 - 16. */
+ stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+ #else /* configENABLE_MPU */
+ subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+ str r1, [r2] /* Save the new top of stack in TCB. */
+ adds r1, r1, #12 /* r1 = r1 + 12. */
+ stm r1, {r4-r11} /* Store the registers that are not saved automatically. */
+ mrs r2, psplim /* r2 = PSPLIM. */
+ mov r3, lr /* r3 = LR/EXC_RETURN. */
+ subs r1, r1, #12 /* r1 = r1 - 12. */
+ stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
+ #endif /* configENABLE_MPU */
+
+ select_next_task:
+ cpsid i
+ bl vTaskSwitchContext
+ cpsie i
+
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r3, [r2] /* Read pxCurrentTCB. */
+ ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+ #if ( configENABLE_MPU == 1 )
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ str r4, [r2] /* Disable MPU. */
+
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+ ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r4, [r2] /* Program MAIR0. */
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
+ movs r4, #4 /* r4 = 4. */
+ str r4, [r2] /* Program RNR = 4. */
+ adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
+ ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ str r4, [r2] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+ #endif /* configENABLE_MPU */
+
+ #if ( configENABLE_MPU == 1 )
+ ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */
+ msr control, r3 /* Restore the CONTROL register value for the task. */
+ mov lr, r4 /* LR = r4. */
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ str r0, [r2] /* Restore the task's xSecureContext. */
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
+ push {r1,r4}
+ bl SecureContext_LoadContext /* Restore the secure context. */
+ pop {r1,r4}
+ mov lr, r4 /* LR = r4. */
+ lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ msr psp, r1 /* Remember the new top of stack for the task. */
+ bx lr
+ #else /* configENABLE_MPU */
+ ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */
+ mov lr, r3 /* LR = r3. */
+ ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+ str r0, [r2] /* Restore the task's xSecureContext. */
+ cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
+ push {r1,r3}
+ bl SecureContext_LoadContext /* Restore the secure context. */
+ pop {r1,r3}
+ mov lr, r3 /* LR = r3. */
+ lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+ bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+ msr psp, r1 /* Remember the new top of stack for the task. */
+ bx lr
+ #endif /* configENABLE_MPU */
+
+ restore_ns_context:
+ ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */
+ #if ( configENABLE_FPU == 1 )
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ it eq
+ vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */
+ #endif /* configENABLE_FPU */
+ msr psp, r1 /* Remember the new top of stack for the task. */
+ bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+ tst lr, #4
+ ite eq
+ mrseq r0, msp
+ mrsne r0, psp
+ b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+ /* r0 = uint32_t *pulTCB. */
+ ldr r1, [r0] /* The first item in the TCB is the top of the stack. */
+ ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */
+ cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */
+ it ne
+ svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+ END
diff --git a/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
new file mode 100644
index 0000000..43a11d4
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -0,0 +1,306 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M33"
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portDONT_DISCARD __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+ /**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+ #define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+ /**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+ /**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context.c b/Source/portable/IAR/ARM_CM33/secure/secure_context.c
new file mode 100644
index 0000000..53535cd
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_context.c
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED 0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED 0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+ uint8_t *pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+ uint8_t *pucStackLimit; /**< Last location of the stack memory (PSPLIM). */
+ uint8_t *pucStackStart; /**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* No stack for thread mode until a task's context is loaded. */
+ secureportSET_PSPLIM( securecontextNO_STACK );
+ secureportSET_PSP( securecontextNO_STACK );
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Configure thread mode to use PSP and to be unprivileged. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Configure thread mode to use PSP and to be privileged.. */
+ secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+ }
+ #endif /* configENABLE_MPU */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+ secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+ uint8_t *pucStackMemory = NULL;
+ uint32_t ulIPSR;
+ SecureContextHandle_t xSecureContextHandle = NULL;
+ #if( configENABLE_MPU == 1 )
+ uint32_t *pulCurrentStackPointer = NULL;
+ #endif /* configENABLE_MPU */
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Allocate the context structure. */
+ xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+ if( xSecureContextHandle != NULL )
+ {
+ /* Allocate the stack space. */
+ pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+ if( pucStackMemory != NULL )
+ {
+ /* Since stack grows down, the starting point will be the last
+ * location. Note that this location is next to the last
+ * allocated byte because the hardware decrements the stack
+ * pointer before writing i.e. if stack pointer is 0x2, a push
+ * operation will decrement the stack pointer to 0x1 and then
+ * write at 0x1. */
+ xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+ /* The stack cannot go beyond this location. This value is
+ * programmed in the PSPLIM register on context switch.*/
+ xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Store the correct CONTROL value for the task on the stack.
+ * This value is programmed in the CONTROL register on
+ * context switch. */
+ pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+ pulCurrentStackPointer--;
+ if( ulIsTaskPrivileged )
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+ }
+ else
+ {
+ *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+ }
+
+ /* Store the current stack pointer. This value is programmed in
+ * the PSP register on context switch. */
+ xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+ }
+ #else /* configENABLE_MPU */
+ {
+ /* Current SP is set to the starting of the stack. This
+ * value programmed in the PSP register on context switch. */
+ xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+ }
+ #endif /* configENABLE_MPU */
+ }
+ else
+ {
+ /* Free the context to avoid memory leak and make sure to return
+ * NULL to indicate failure. */
+ vPortFree( xSecureContextHandle );
+ xSecureContextHandle = NULL;
+ }
+ }
+ }
+
+ return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* Ensure that valid parameters are passed. */
+ secureportASSERT( xSecureContextHandle != NULL );
+
+ /* Free the stack space. */
+ vPortFree( xSecureContextHandle->pucStackLimit );
+
+ /* Free the context itself. */
+ vPortFree( xSecureContextHandle );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context.h b/Source/portable/IAR/ARM_CM33/secure/secure_context.h
new file mode 100644
index 0000000..e148bff
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_context.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK 0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext* SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+ SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c b/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c
new file mode 100644
index 0000000..619db1e
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+ SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+ SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
new file mode 100644
index 0000000..0cbfe6e
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
@@ -0,0 +1,73 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+
+ PUBLIC SecureContext_LoadContextAsm
+ PUBLIC SecureContext_SaveContextAsm
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+ /* xSecureContextHandle value is in r0. */
+ mrs r1, ipsr /* r1 = IPSR. */
+ cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
+ ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+ ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+ msr control, r3 /* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+ msr psplim, r2 /* PSPLIM = r2. */
+ msr psp, r1 /* PSP = r1. */
+
+ load_ctx_therad_mode:
+ bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+ /* xSecureContextHandle value is in r0. */
+ mrs r1, ipsr /* r1 = IPSR. */
+ cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
+ mrs r1, psp /* r1 = PSP. */
+#if ( configENABLE_FPU == 1 )
+ vstmdb r1!, {s0} /* Trigger the defferred stacking of FPU registers. */
+ vldmia r1!, {s0} /* Nullify the effect of the pervious statement. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+ mrs r2, control /* r2 = CONTROL. */
+ stmdb r1!, {r2} /* Store CONTROL value on the stack. */
+#endif /* configENABLE_MPU */
+ str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+ movs r1, #0 /* r1 = securecontextNO_STACK. */
+ msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
+ msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+ save_ctx_therad_mode:
+ bx lr
+/*-----------------------------------------------------------*/
+
+ END
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_heap.c b/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
new file mode 100644
index 0000000..60fce5c
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE ( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+ #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+ #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+ #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+ /* The application writer has already defined the array used for the RTOS
+ * heap - probably so it can be placed in a special segment or address. */
+ extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+ static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK *pxNextFreeBlock; /**< The next free block in the list. */
+ size_t xBlockSize; /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+ /* Ensure the heap starts on a correctly aligned boundary. */
+ uxAddress = ( size_t ) ucHeap;
+
+ if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+ }
+
+ pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ * blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted
+ * at the end of the heap space. */
+ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+ uxAddress -= xHeapStructSize;
+ uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+ pxEnd = ( void * ) uxAddress;
+ pxEnd->xBlockSize = 0;
+ pxEnd->pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ * entire heap space, minus the space taken by pxEnd. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+ /* Only one block exists - and it covers the entire usable heap space. */
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+ /* Work out the position of the top bit in a size_t variable. */
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+ /* Iterate through the list until a block is found that has a higher address
+ * than the block being inserted. */
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ {
+ /* Nothing to do here, just iterate to the right position. */
+ }
+
+ /* Do the block being inserted, and the block it is being inserted after
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxIterator;
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ {
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ pxBlockToInsert = pxIterator;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Do the block being inserted, and the block it is being inserted before
+ * make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxBlockToInsert;
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ {
+ if( pxIterator->pxNextFreeBlock != pxEnd )
+ {
+ /* Form one big block from the two blocks. */
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ }
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ }
+
+ /* If the block being inserted plugged a gab, so was merged with the block
+ * before and the block after, then it's pxNextFreeBlock pointer will have
+ * already been set, and should not be set here as that would make it point
+ * to itself. */
+ if( pxIterator != pxBlockToInsert )
+ {
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+ /* If this is the first call to malloc then the heap will require
+ * initialisation to setup the list of free blocks. */
+ if( pxEnd == NULL )
+ {
+ prvHeapInit();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Check the requested block size is not so large that the top bit is set.
+ * The top bit of the block size member of the BlockLink_t structure is used
+ * to determine who owns the block - the application or the kernel, so it
+ * must be free. */
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ {
+ /* The wanted size is increased so it can contain a BlockLink_t
+ * structure in addition to the requested amount of bytes. */
+ if( xWantedSize > 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number of
+ * bytes. */
+ if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+ secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ {
+ /* Traverse the list from the start (lowest address) block until
+ * one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If the end marker was reached then a block of adequate size was
+ * not found. */
+ if( pxBlock != pxEnd )
+ {
+ /* Return the memory space pointed to - jumping over the
+ * BlockLink_t structure at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+ /* This block is being returned for use so must be taken out
+ * of the list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into
+ * two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new
+ * block following the number of bytes requested. The void
+ * cast is used to prevent byte alignment warnings from the
+ * compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+ /* Calculate the sizes of two blocks split from the single
+ * block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ prvInsertBlockIntoFreeList( pxNewBlockLink );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ {
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The block is being returned - it is allocated and owned by
+ * the application and has no "next" block. */
+ pxBlock->xBlockSize |= xBlockAllocatedBit;
+ pxBlock->pxNextFreeBlock = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceMALLOC( pvReturn, xWantedSize );
+
+ #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif
+
+ secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ * before it. */
+ puc -= xHeapStructSize;
+
+ /* This casting is to keep the compiler from issuing warnings. */
+ pxLink = ( void * ) puc;
+
+ /* Check the block is actually allocated. */
+ secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ {
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ * allocated. */
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+ secureportDISABLE_NON_SECURE_INTERRUPTS();
+ {
+ /* Add this block to the list of free blocks. */
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ }
+ secureportENABLE_NON_SECURE_INTERRUPTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+ return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+ /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_heap.h b/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
new file mode 100644
index 0000000..69e4f2a
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_init.c b/Source/portable/IAR/ARM_CM33/secure/secure_init.c
new file mode 100644
index 0000000..c6525f7
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS ( 26UL )
+#define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS ( 10UL )
+#define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS ( 11UL )
+#define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+ ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+ ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+ uint32_t ulIPSR;
+
+ /* Read the Interrupt Program Status Register (IPSR) value. */
+ secureportREAD_IPSR( ulIPSR );
+
+ /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+ * when the processor is running in the Thread Mode. */
+ if( ulIPSR != 0 )
+ {
+ /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+ * permitted. CP11 should be programmed to the same value as CP10. */
+ *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+ /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+ * that we can enable/disable lazy stacking in port.c file. */
+ *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+ /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+ * registers (S16-S31) are also pushed to stack on exception entry and
+ * restored on exception return. */
+ *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+ }
+}
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_init.h b/Source/portable/IAR/ARM_CM33/secure/secure_init.h
new file mode 100644
index 0000000..6c5bc71
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
new file mode 100644
index 0000000..760edab
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT 8
+#define secureportBYTE_ALIGNMENT_MASK ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+ #define secureportNON_SECURE_CALLABLE __cmse_nonsecure_entry __root
+#else
+ #define secureportNON_SECURE_CALLABLE __attribute__((cmse_nonsecure_entry)) __attribute__((used))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+ __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+ __asm volatile ( "mrs %0, psp" : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+ __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+ __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+ __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+ __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+ __asm volatile ( "mrs %0, ipsr" : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL 0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL 1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS() secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS() secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x ) \
+ if( ( x ) == 0 ) \
+ { \
+ secureportDISABLE_SECURE_INTERRUPTS(); \
+ secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+ for( ;; ); \
+ }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
new file mode 100644
index 0000000..bd85a6f
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -0,0 +1,899 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /* Secure components includes. */
+ #include "secure_context.h"
+ #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ * configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ * configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+ #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK ( 0x00000004 )
+#define portNVIC_SYSTICK_INT ( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE ( 0x00000001 )
+#define portNVIC_PENDSVSET ( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE ( 3UL )
+#define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS ( 20UL )
+#define portCPACR_CP11_POS ( 22UL )
+
+#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS ( 31UL )
+#define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS ( 30UL )
+#define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR ( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF FD
+ * 1111 1111 1111 1111 1111 1111 1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#else
+ /**
+ * @brief Initial EXC_RETURN value.
+ *
+ * FF FF FF BC
+ * 1111 1111 1111 1111 1111 1111 1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+ #define portINITIAL_EXC_RETURN ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ * Bit[0] = 0 ==> The task is privileged.
+ * Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS 1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT 0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+ /**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+ static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+ portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Stop and reset the SysTick. */
+ *( portNVIC_SYSTICK_CTRL ) = 0UL;
+ *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+ /* A function that implements a task must not exit or attempt to return to
+ * its caller as there is nothing to return to. If a task wants to exit it
+ * should instead call vTaskDelete( NULL ). Artificially force an assert()
+ * to be triggered if configASSERT() is defined, then stop here so
+ * application writers can catch the error. */
+ configASSERT( ulCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+
+ while( ulDummy == 0 )
+ {
+ /* This file calls prvTaskExitError() after the scheduler has been
+ * started to remove a compiler warning about the function being
+ * defined but never called. ulDummy is used purely to quieten other
+ * warnings about code appearing after this function is called - making
+ * ulDummy volatile makes the compiler think the function could return
+ * and therefore not output an 'unreachable code' warning for code that
+ * appears after it. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __privileged_functions_start__;
+ extern uint32_t * __privileged_functions_end__;
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ extern uint32_t * __unprivileged_flash_start__;
+ extern uint32_t * __unprivileged_flash_end__;
+ extern uint32_t * __privileged_sram_start__;
+ extern uint32_t * __privileged_sram_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __privileged_functions_start__[];
+ extern uint32_t __privileged_functions_end__[];
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ extern uint32_t __unprivileged_flash_start__[];
+ extern uint32_t __unprivileged_flash_end__[];
+ extern uint32_t __privileged_sram_start__[];
+ extern uint32_t __privileged_sram_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+
+ /* Check that the MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
+ /* MAIR0 - Index 0. */
+ portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ /* MAIR0 - Index 1. */
+ portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* Setup privileged flash as Read Only so that privileged tasks can
+ * read it but not modify. */
+ portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged flash as Read Only by both privileged and
+ * unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup unprivileged syscalls flash as Read Only by both privileged
+ * and unprivileged tasks. All tasks can read it but no-one can modify. */
+ portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_ONLY );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Setup RAM containing kernel data for privileged access only. */
+ portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+ portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+ portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Enable mem fault. */
+ portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+ /* Enable MPU with privileged background access i.e. unmapped
+ * regions have privileged access. */
+ portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+ static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* Enable non-secure access to the FPU. */
+ SecureInit_EnableNSFPUAccess();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+ * unprivileged code should be able to access FPU. CP11 should be
+ * programmed to the same value as CP10. */
+ *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+ ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+ );
+
+ /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+ * context on exception entry and restore on exception return.
+ * LSPEN = 1 ==> Enable lazy context save of FP state. */
+ *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+ }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Set a PendSV to request a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ portDISABLE_INTERRUPTS();
+ ulCriticalNesting++;
+
+ /* Barriers are normally not required but do ensure the code is
+ * completely within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+ configASSERT( ulCriticalNesting );
+ ulCriticalNesting--;
+
+ if( ulCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+#if( configENABLE_MPU == 1 )
+ #if defined( __ARMCC_VERSION )
+ /* Declaration when these variable are defined in code instead of being
+ * exported from linker scripts. */
+ extern uint32_t * __syscalls_flash_start__;
+ extern uint32_t * __syscalls_flash_end__;
+ #else
+ /* Declaration when these variable are exported from linker scripts. */
+ extern uint32_t __syscalls_flash_start__[];
+ extern uint32_t __syscalls_flash_end__[];
+ #endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ uint32_t ulR0;
+ #if( configENABLE_MPU == 1 )
+ uint32_t ulControl, ulIsTaskPrivileged;
+ #endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+ /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+ * R12, LR, PC, xPSR. */
+ ulPC = pulCallerStackAddress[ 6 ];
+ ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+ switch( ucSVCNumber )
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ case portSVC_ALLOCATE_SECURE_CONTEXT:
+ {
+ /* R0 contains the stack size passed as parameter to the
+ * vPortAllocateSecureContext function. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Read the CONTROL register value. */
+ __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
+
+ /* The task that raised the SVC is privileged if Bit[0]
+ * in the CONTROL register is 0. */
+ ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+ }
+ #else
+ {
+ /* Allocate and load a context for the secure task. */
+ xSecureContext = SecureContext_AllocateContext( ulR0 );
+ }
+ #endif /* configENABLE_MPU */
+
+ configASSERT( xSecureContext != NULL );
+ SecureContext_LoadContext( xSecureContext );
+ }
+ break;
+
+ case portSVC_FREE_SECURE_CONTEXT:
+ {
+ /* R0 contains the secure context handle to be freed. */
+ ulR0 = pulCallerStackAddress[ 0 ];
+
+ /* Free the secure context. */
+ SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+ }
+ break;
+ #endif /* configENABLE_TRUSTZONE */
+
+ case portSVC_START_SCHEDULER:
+ {
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ /* De-prioritize the non-secure exceptions so that the
+ * non-secure pendSV runs at the lowest priority. */
+ SecureInit_DePrioritizeNSExceptions();
+
+ /* Initialize the secure context management system. */
+ SecureContext_Init();
+ }
+ #endif /* configENABLE_TRUSTZONE */
+
+ #if( configENABLE_FPU == 1 )
+ {
+ /* Setup the Floating Point Unit (FPU). */
+ prvSetupFPU();
+ }
+ #endif /* configENABLE_FPU */
+
+ /* Setup the context of the first task so that the first task starts
+ * executing. */
+ vRestoreContextOfFirstTask();
+ }
+ break;
+
+ #if( configENABLE_MPU == 1 )
+ case portSVC_RAISE_PRIVILEGE:
+ {
+ /* Only raise the privilege, if the svc was raised from any of
+ * the system calls. */
+ if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+ ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+ {
+ vRaisePrivilege();
+ }
+ }
+ break;
+ #endif /* configENABLE_MPU */
+
+ default:
+ {
+ /* Incorrect SVC call. */
+ configASSERT( pdFALSE );
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ * interrupt. */
+ #if( portPRELOAD_REGISTERS == 0 )
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #else /* portPRELOAD_REGISTERS */
+ {
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
+ pxTopOfStack--;
+ *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
+
+ #if( configENABLE_MPU == 1 )
+ {
+ pxTopOfStack--;
+ if( xRunPrivileged == pdTRUE )
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ else
+ {
+ *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+ }
+ }
+ #endif /* configENABLE_MPU */
+
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+ #if( configENABLE_TRUSTZONE == 1 )
+ {
+ pxTopOfStack--;
+ *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+ }
+ #endif /* configENABLE_TRUSTZONE */
+ }
+ #endif /* portPRELOAD_REGISTERS */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+ *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+ *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+ #if( configENABLE_MPU == 1 )
+ {
+ /* Setup the Memory Protection Unit (MPU). */
+ prvSetupMPU();
+ }
+ #endif /* configENABLE_MPU */
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ * here already. */
+ prvSetupTimerInterrupt();
+
+ /* Initialize the critical nesting count ready for the first task. */
+ ulCriticalNesting = 0;
+
+ /* Start the first task. */
+ vStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing. Call the task
+ * exit error function to prevent compiler warnings about a static function
+ * not being called in the case that the application writer overrides this
+ * functionality by defining configTASK_RETURN_ADDRESS. Call
+ * vTaskSwitchContext() so link time optimization does not remove the
+ * symbol. */
+ vTaskSwitchContext();
+ prvTaskExitError();
+
+ /* Should not get here. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+ /* Not implemented in ports where there is nothing to return to.
+ * Artificially force an assert. */
+ configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+ {
+ uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+ int32_t lIndex = 0;
+
+ /* Setup MAIR0. */
+ xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+ xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+ /* This function is called automatically when the task is created - in
+ * which case the stack region parameters will be valid. At all other
+ * times the stack parameters will not be valid and it is assumed that
+ * the stack region has already been configured. */
+ if( ulStackDepth > 0 )
+ {
+ /* Define the region that allows access to the stack. */
+ ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE ) |
+ ( portMPU_REGION_READ_WRITE ) |
+ ( portMPU_REGION_EXECUTE_NEVER );
+
+ xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_ATTR_INDEX0 ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+ }
+
+ /* User supplied configurable regions. */
+ for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+ {
+ /* If xRegions is NULL i.e. the task has not specified any MPU
+ * region, the else part ensures that all the configurable MPU
+ * regions are invalidated. */
+ if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+ {
+ /* Translate the generic region definition contained in xRegions
+ * into the ARMv8 specific MPU settings that are then stored in
+ * xMPUSettings. */
+ ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+ ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+ ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+ /* Start address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+ ( portMPU_REGION_NON_SHAREABLE );
+
+ /* RO/RW. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+ }
+ else
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+ }
+
+ /* XN. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+ {
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+ }
+
+ /* End Address. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+ ( portMPU_RLAR_REGION_ENABLE );
+
+ /* Normal memory/ Device memory. */
+ if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+ {
+ /* Attr1 in MAIR0 is configured as device memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+ }
+ else
+ {
+ /* Attr1 in MAIR0 is configured as normal memory. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+ }
+ }
+ else
+ {
+ /* Invalidate the region. */
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+ xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+ }
+
+ lIndex++;
+ }
+ }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..2ecf04e
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
new file mode 100644
index 0000000..400755b
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -0,0 +1,242 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+ EXTERN pxCurrentTCB
+ EXTERN vTaskSwitchContext
+ EXTERN vPortSVCHandler_C
+
+ PUBLIC xIsPrivileged
+ PUBLIC vResetPrivilege
+ PUBLIC vRestoreContextOfFirstTask
+ PUBLIC vRaisePrivilege
+ PUBLIC vStartFirstTask
+ PUBLIC ulSetInterruptMaskFromISR
+ PUBLIC vClearInterruptMaskFromISR
+ PUBLIC PendSV_Handler
+ PUBLIC SVC_Handler
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+ mrs r0, control /* r0 = CONTROL. */
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ ite ne
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+ mrs r0, control /* r0 = CONTROL. */
+ orr r0, r0, #1 /* r0 = r0 | 1. */
+ msr control, r0 /* CONTROL = r0. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+ SECTION privileged_functions:CODE:NOROOT(2)
+ THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r2] /* Read pxCurrentTCB. */
+ ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ str r4, [r2] /* Disable MPU. */
+
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r3, [r2] /* Program MAIR0. */
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
+ movs r3, #4 /* r3 = 4. */
+ str r3, [r2] /* Program RNR = 4. */
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ str r4, [r2] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+ ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+ msr psplim, r1 /* Set this task's PSPLIM value. */
+ msr control, r2 /* Set this task's CONTROL value. */
+ adds r0, #32 /* Discard everything up to r0. */
+ msr psp, r0 /* This is now the new top of stack to use in the task. */
+ isb
+ bx r3 /* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+ ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+ msr psplim, r1 /* Set this task's PSPLIM value. */
+ movs r1, #2 /* r1 = 2. */
+ msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
+ adds r0, #32 /* Discard everything up to r0. */
+ msr psp, r0 /* This is now the new top of stack to use in the task. */
+ isb
+ bx r2 /* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+ mrs r0, control /* Read the CONTROL register. */
+ bic r0, r0, #1 /* Clear the bit 0. */
+ msr control, r0 /* Write back the new CONTROL value. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+ ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
+ ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
+ ldr r0, [r0] /* The first entry in vector table is stack pointer. */
+ msr msp, r0 /* Set the MSP back to the start of the stack. */
+ cpsie i /* Globally enable interrupts. */
+ cpsie f
+ dsb
+ isb
+ svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+ mrs r0, PRIMASK
+ cpsid i
+ bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+ msr PRIMASK, r0
+ bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+ mrs r0, psp /* Read PSP in r0. */
+#if ( configENABLE_FPU == 1 )
+ tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ it eq
+ vstmdbeq r0!, {s16-s31} /* Store the FPU registers which are not saved automatically. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+ mrs r1, psplim /* r1 = PSPLIM. */
+ mrs r2, control /* r2 = CONTROL. */
+ mov r3, lr /* r3 = LR/EXC_RETURN. */
+ stmdb r0!, {r1-r11} /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+#else /* configENABLE_MPU */
+ mrs r2, psplim /* r2 = PSPLIM. */
+ mov r3, lr /* r3 = LR/EXC_RETURN. */
+ stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
+#endif /* configENABLE_MPU */
+
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r2] /* Read pxCurrentTCB. */
+ str r0, [r1] /* Save the new top of stack in TCB. */
+
+ cpsid i
+ bl vTaskSwitchContext
+ cpsie i
+
+ ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+ ldr r1, [r2] /* Read pxCurrentTCB. */
+ ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+ dmb /* Complete outstanding transfers before disabling MPU. */
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+ str r4, [r2] /* Disable MPU. */
+
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+ ldr r3, [r1] /* r3 = *r1 i.e. r3 = MAIR0. */
+ ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
+ str r3, [r2] /* Program MAIR0. */
+ ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
+ movs r3, #4 /* r3 = 4. */
+ str r3, [r2] /* Program RNR = 4. */
+ adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+ ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
+ ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
+ stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+ ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+ ldr r4, [r2] /* Read the value of MPU_CTRL. */
+ orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+ str r4, [r2] /* Enable MPU. */
+ dsb /* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+ ldmia r0!, {r1-r11} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+#else /* configENABLE_MPU */
+ ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+ tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+ it eq
+ vldmiaeq r0!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */
+#endif /* configENABLE_FPU */
+
+ #if ( configENABLE_MPU == 1 )
+ msr psplim, r1 /* Restore the PSPLIM register value for the task. */
+ msr control, r2 /* Restore the CONTROL register value for the task. */
+#else /* configENABLE_MPU */
+ msr psplim, r2 /* Restore the PSPLIM register value for the task. */
+#endif /* configENABLE_MPU */
+ msr psp, r0 /* Remember the new top of stack for the task. */
+ bx r3
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+ tst lr, #4
+ ite eq
+ mrseq r0, msp
+ mrsne r0, psp
+ b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+ END
diff --git a/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..43a11d4
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -0,0 +1,306 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+ #define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME "Cortex-M33"
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+#define portNOP()
+#define portINLINE __inline
+#ifndef portFORCE_INLINE
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING 1
+#define portDONT_DISCARD __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+ #define portUSING_MPU_WRAPPERS 1
+ #define portPRIVILEGE_BIT ( 0x80000000UL )
+#else
+ #define portPRIVILEGE_BIT ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )
+#define portPRIVILEGED_RAM_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ * Bit[7:4] - 0000 - Device Memory
+ * Bit[3:2] - 00 --> Device-nGnRnE
+ * 01 --> Device-nGnRE
+ * 10 --> Device-nGRE
+ * 11 --> Device-GRE
+ * Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+ uint32_t ulRBAR; /**< RBAR for the region. */
+ uint32_t ulRLAR; /**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0
+#define portSVC_FREE_SECURE_CONTEXT 1
+#define portSVC_START_SCHEDULER 2
+#define portSVC_RAISE_PRIVILEGE 3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD() vPortYield()
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+ /**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )
+
+ /**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+ #define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+ /**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+ #define portIS_PRIVILEGED() xIsPrivileged()
+
+ /**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+ /**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+ #define portRESET_PRIVILEGE() vResetPrivilege()
+#else
+ #define portIS_PRIVILEGED()
+ #define portRAISE_PRIVILEGE()
+ #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/Source/portable/IAR/ARM_CM4F/port.c b/Source/portable/IAR/ARM_CM4F/port.c
index 2710d2f..f405163 100644
--- a/Source/portable/IAR/ARM_CM4F/port.c
+++ b/Source/portable/IAR/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/IAR/ARM_CM4F/portasm.s b/Source/portable/IAR/ARM_CM4F/portasm.s
index 20fd9d2..da715ae 100644
--- a/Source/portable/IAR/ARM_CM4F/portasm.s
+++ b/Source/portable/IAR/ARM_CM4F/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/IAR/ARM_CM4F/portmacro.h b/Source/portable/IAR/ARM_CM4F/portmacro.h
index f19ef45..08f5d1c 100644
--- a/Source/portable/IAR/ARM_CM4F/portmacro.h
+++ b/Source/portable/IAR/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/IAR/ARM_CM4_MPU/port.c b/Source/portable/IAR/ARM_CM4_MPU/port.c
index a13af49..b843e56 100644
--- a/Source/portable/IAR/ARM_CM4_MPU/port.c
+++ b/Source/portable/IAR/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -10,8 +10,7 @@
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ * copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
@@ -143,21 +142,14 @@
/*
* Configure a number of standard MPU regions that are used by all tasks.
*/
-PRIVILEGED_FUNCTION static void prvSetupMPU( void );
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
/*
* Return the smallest MPU region size that a given number of bytes will fit
* into. The region size is returned as the value that should be programmed
* into the region attribute register for that region.
*/
-PRIVILEGED_FUNCTION static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes );
-
-/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-extern BaseType_t xPortRaisePrivilege( void );
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
/*
* Setup the timer to generate the tick interrupts. The implementation in this
@@ -169,12 +161,12 @@
/*
* Exception handlers.
*/
-PRIVILEGED_FUNCTION void xPortSysTickHandler( void );
+void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
/*
* Start first task is a separate function so it can be tested in isolation.
*/
-PRIVILEGED_FUNCTION extern void vPortStartFirstTask( void );
+extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
/*
* Turn the VFP on.
@@ -189,8 +181,20 @@
/*
* Called from the SVC handler used to start the scheduler.
*/
-PRIVILEGED_FUNCTION extern void vPortRestoreContextOfFirstTask( void );
+extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
/*-----------------------------------------------------------*/
/* Each task maintains its own interrupt status in the critical nesting
@@ -484,6 +488,9 @@
extern uint32_t __privileged_data_start__;
extern uint32_t __privileged_data_end__;
+ /* Check the expected MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
/* First setup the entire flash for unprivileged read only access. */
portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
@@ -532,6 +539,7 @@
/* Enable the MPU with the background region configured. */
portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+ }
}
/*-----------------------------------------------------------*/
@@ -559,18 +567,6 @@
}
/*-----------------------------------------------------------*/
-void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
- if( xRunningPrivileged != pdTRUE )
- {
- __asm volatile ( " mrs r0, control \n" \
- " orr r0, r0, #1 \n" \
- " msr control, r0 \n" \
- :::"r0", "memory" );
- }
-}
-/*-----------------------------------------------------------*/
-
void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
{
extern uint32_t __SRAM_segment_start__;
diff --git a/Source/portable/IAR/ARM_CM4_MPU/portasm.s b/Source/portable/IAR/ARM_CM4_MPU/portasm.s
index f741069..37f1a80 100644
--- a/Source/portable/IAR/ARM_CM4_MPU/portasm.s
+++ b/Source/portable/IAR/ARM_CM4_MPU/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -10,8 +10,7 @@
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ * copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
@@ -40,7 +39,8 @@
PUBLIC vPortStartFirstTask
PUBLIC vPortEnableVFP
PUBLIC vPortRestoreContextOfFirstTask
- PUBLIC xPortRaisePrivilege
+ PUBLIC xIsPrivileged
+ PUBLIC vResetPrivilege
/*-----------------------------------------------------------*/
@@ -115,7 +115,7 @@
/*-----------------------------------------------------------*/
-vPortStartFirstTask
+vPortStartFirstTask:
/* Use the NVIC offset register to locate the stack. */
ldr r0, =0xE000ED08
ldr r0, [r0]
@@ -137,7 +137,7 @@
/*-----------------------------------------------------------*/
-vPortRestoreContextOfFirstTask
+vPortRestoreContextOfFirstTask:
/* Use the NVIC offset register to locate the stack. */
ldr r0, =0xE000ED08
ldr r0, [r0]
@@ -168,7 +168,7 @@
/*-----------------------------------------------------------*/
-vPortEnableVFP
+vPortEnableVFP:
/* The FPU enable bits are in the CPACR. */
ldr.w r0, =0xE000ED88
ldr r1, [r0]
@@ -180,19 +180,20 @@
/*-----------------------------------------------------------*/
-xPortRaisePrivilege
- mrs r0, control
- /* Is the task running privileged? */
- tst r0, #1
- itte ne
- /* CONTROL[0]!=0, return false. */
- movne r0, #0
- /* Switch to privileged. */
- svcne 2 /* 2 == portSVC_RAISE_PRIVILEGE */
- /* CONTROL[0]==0, return true. */
- moveq r0, #1
- bx lr
+xIsPrivileged:
+ mrs r0, control /* r0 = CONTROL. */
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ ite ne
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
+vResetPrivilege:
+ mrs r0, control /* r0 = CONTROL. */
+ orr r0, r0, #1 /* r0 = r0 | 1. */
+ msr control, r0 /* CONTROL = r0. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
END
-
diff --git a/Source/portable/IAR/ARM_CM4_MPU/portmacro.h b/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
index 59d9c8b..ecdd0cf 100644
--- a/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
+++ b/Source/portable/IAR/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -10,8 +10,7 @@
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ * copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
@@ -191,11 +190,28 @@
/* portNOP() is not required by this port. */
#define portNOP()
+/*-----------------------------------------------------------*/
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED() xIsPrivileged()
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE() vResetPrivilege()
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/port.c b/Source/portable/IAR/ARM_CM7/r0p1/port.c
index ee846da..503f5db 100644
--- a/Source/portable/IAR/ARM_CM7/r0p1/port.c
+++ b/Source/portable/IAR/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/portasm.s b/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
index 5b492f1..ad8070c 100644
--- a/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
+++ b/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h b/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
index 21146f4..9f3c261 100644
--- a/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
+++ b/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c b/Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c
index 43c1278..b884ba0 100644
--- a/Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c
+++ b/Source/portable/IAR/ARM_CM7_MPU/r0p1/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -29,7 +29,7 @@
* Implementation of functions defined in portable.h for the ARM CM4F port.
*----------------------------------------------------------*/
-/* Compiler includes. */
+/* IAR includes. */
#include <intrinsics.h>
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
@@ -42,16 +42,15 @@
#include "task.h"
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
#ifndef __ARMVFP__
#error This port can only be used when the project options are configured to enable hardware floating point support.
#endif
-#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
+#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
#endif
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
#ifndef configSYSTICK_CLOCK_HZ
#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
/* Ensure the SysTick is clocked at the same frequency as the core. */
@@ -63,36 +62,13 @@
#endif
/* Constants required to manipulate the core. Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
#define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
#define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
-#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT ( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK ( 0xFFUL )
/* Constants required to access and manipulate the MPU. */
#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
@@ -108,15 +84,39 @@
#define portPERIPHERALS_START_ADDRESS 0x40000000UL
#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK ( 0xFFUL )
+
/* Constants required to manipulate the VFP. */
#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR ( 0x01000000UL )
-#define portINITIAL_EXEC_RETURN ( 0xfffffffdUL )
-#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
-#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
+#define portINITIAL_XPSR ( 0x01000000 )
+#define portINITIAL_EXC_RETURN ( 0xfffffffd )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
/* Offsets in the stack to the parameters when inside the SVC handler. */
#define portOFFSET_TO_PC ( 6 )
@@ -133,9 +133,17 @@
have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into. The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
/*
* Setup the timer to generate the tick interrupts. The implementation in this
@@ -145,56 +153,63 @@
void vPortSetupTimerInterrupt( void );
/*
- * Configure a number of standard MPU regions that are used by all tasks.
- */
-PRIVILEGED_FUNCTION static void prvSetupMPU( void );
-
-/*
- * Return the smallest MPU region size that a given number of bytes will fit
- * into. The region size is returned as the value that should be programmed
- * into the region attribute register for that region.
- */
-PRIVILEGED_FUNCTION static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes );
-
-/*
* Exception handlers.
*/
-void xPortSysTickHandler( void );
+void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
/*
* Start first task is a separate function so it can be tested in isolation.
*/
-extern void vPortStartFirstTask( void );
-
-extern void vRestoreContextOfFirstTask( void );
+extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
/*
* Turn the VFP on.
*/
extern void vPortEnableVFP( void );
+/*
+ * The C portion of the SVC handler.
+ */
+void vPortSVCHandler_C( uint32_t *pulParam );
+
+/*
+ * Called from the SVC handler used to start the scheduler.
+ */
+extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
/*-----------------------------------------------------------*/
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+#if( configUSE_TICKLESS_IDLE == 1 )
/*
* The number of SysTick increments that make up one tick period.
*/
-#if configUSE_TICKLESS_IDLE == 1
static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
/*
* The maximum number of tick periods that can be suppressed is limited by the
* 24 bit resolution of the SysTick timer.
*/
-#if configUSE_TICKLESS_IDLE == 1
static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
/*
* Compensate for the CPU cycles that pass while the SysTick is stopped (low
* power functionality only.
*/
-#if configUSE_TICKLESS_IDLE == 1
static uint32_t ulStoppedTimerCompensation = 0;
#endif /* configUSE_TICKLESS_IDLE */
@@ -203,7 +218,7 @@
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
*/
-#if ( configASSERT_DEFINED == 1 )
+#if( configASSERT_DEFINED == 1 )
static uint8_t ucMaxSysCallPriority = 0;
static uint32_t ulMaxPRIGROUPValue = 0;
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
@@ -236,61 +251,59 @@
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXEC_RETURN;
-
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
+
pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
- if( xRunPrivileged == pdTRUE )
+
+ if( xRunPrivileged == pdTRUE )
{
- *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+ *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
}
else
{
- *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+ *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
}
-
+
return pxTopOfStack;
}
-
/*-----------------------------------------------------------*/
-void vSVCHandler( uint32_t *pulParam )
+
+void vPortSVCHandler_C( uint32_t *pulParam )
{
uint8_t ucSVCNumber;
-uint32_t ulReg;
/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
xPSR. The first argument (r0) is pulParam[ 0 ]. */
ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
switch( ucSVCNumber )
{
- case portSVC_START_SCHEDULER :
- portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
- vRestoreContextOfFirstTask();
- break;
+ case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
+ vPortRestoreContextOfFirstTask();
+ break;
- case portSVC_YIELD :
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- /* Barriers are normally not required
- but do ensure the code is completely
- within the specified behaviour for the
- architecture. */
- __DSB();
- __ISB();
- break;
+ case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ /* Barriers are normally not required
+ but do ensure the code is completely
+ within the specified behaviour for the
+ architecture. */
+ __asm volatile( "dsb" ::: "memory" );
+ __asm volatile( "isb" );
- case portSVC_RAISE_PRIVILEGE :
+ break;
- ulReg = __get_CONTROL();
- ulReg &= 0xFFFFFFFE;
- __set_CONTROL(ulReg);
-
- break;
+ case portSVC_RAISE_PRIVILEGE : __asm volatile
+ (
+ " mrs r1, control \n" /* Obtain current control value. */
+ " bic r1, r1, #1 \n" /* Set privilege bit. */
+ " msr control, r1 \n" /* Write back new control value. */
+ ::: "r1", "memory"
+ );
+ break;
- default : /* Unknown SVC call. */
- break;
+ default : /* Unknown SVC call. */
+ break;
}
}
-
/*-----------------------------------------------------------*/
/*
@@ -298,6 +311,10 @@
*/
BaseType_t xPortStartScheduler( void )
{
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
#if( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
@@ -331,6 +348,24 @@
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ priority bits matches the number of priority bits actually queried
+ from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ priority bits matches the number of priority bits actually queried
+ from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
@@ -345,7 +380,7 @@
/* Make PendSV and SysTick the lowest priority interrupts. */
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
+
/* Configure the regions in the MPU that are common to all tasks. */
prvSetupMPU();
@@ -380,9 +415,13 @@
void vPortEnterCritical( void )
{
+ BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
+ vPortResetPrivilege( xRunningPrivileged );
+
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
@@ -397,12 +436,17 @@
void vPortExitCritical( void )
{
+BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
configASSERT( uxCriticalNesting );
+
uxCriticalNesting--;
if( uxCriticalNesting == 0 )
{
portENABLE_INTERRUPTS();
}
+
+ vPortResetPrivilege( xRunningPrivileged );
}
/*-----------------------------------------------------------*/
@@ -424,24 +468,9 @@
}
portENABLE_INTERRUPTS();
}
-
/*-----------------------------------------------------------*/
-void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-uint32_t ulReg;
-
- if( xRunningPrivileged != pdTRUE )
- {
- ulReg = __get_CONTROL();
- ulReg |= 0x1;
- __set_CONTROL(ulReg);
- }
-}
-
-/*-----------------------------------------------------------*/
-
-#if configUSE_TICKLESS_IDLE == 1
+#if( configUSE_TICKLESS_IDLE == 1 )
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
@@ -594,7 +623,6 @@
}
#endif /* #if configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
/*
* Setup the systick timer to generate the tick interrupts at the required
@@ -602,14 +630,18 @@
*/
__weak void vPortSetupTimerInterrupt( void )
{
+ /* Stop and clear the SysTick. */
+ portNVIC_SYSTICK_CTRL_REG = 0UL;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
/* Calculate the constants required to configure the tick interrupt. */
- #if( configUSE_TICKLESS_IDLE == 1 )
+#if( configUSE_TICKLESS_IDLE == 1 )
{
ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
- #endif /* configUSE_TICKLESS_IDLE */
+#endif /* configUSE_TICKLESS_IDLE */
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
@@ -625,6 +657,9 @@
extern uint32_t __privileged_data_start__;
extern uint32_t __privileged_data_end__;
+ /* Check the expected MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
/* First setup the entire flash for unprivileged read only access. */
portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
@@ -673,6 +708,7 @@
/* Enable the MPU with the background region configured. */
portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+ }
}
/*-----------------------------------------------------------*/
@@ -699,14 +735,13 @@
return ( ulReturnValue << 1UL );
}
/*-----------------------------------------------------------*/
+
void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
{
extern uint32_t __SRAM_segment_start__;
extern uint32_t __SRAM_segment_end__;
extern uint32_t __privileged_data_start__;
extern uint32_t __privileged_data_end__;
-
-
int32_t lIndex;
uint32_t ul;
@@ -795,7 +830,6 @@
}
}
}
-
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
@@ -806,7 +840,7 @@
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
@@ -852,7 +886,7 @@
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
scheduler. Note however that some vendor specific peripheral libraries
assume a non-zero priority group setting, in which cases using a value
- of zero will result in unpredicable behaviour. */
+ of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
}
diff --git a/Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s b/Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s
index 47e8f31..86d5b29 100644
--- a/Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s
+++ b/Source/portable/IAR/ARM_CM7_MPU/r0p1/portasm.s
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -32,17 +32,15 @@
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
- EXTERN vSVCHandler
+ EXTERN vPortSVCHandler_C
PUBLIC xPortPendSVHandler
PUBLIC vPortSVCHandler
PUBLIC vPortStartFirstTask
- PUBLIC vRestoreContextOfFirstTask
PUBLIC vPortEnableVFP
- PUBLIC xPortRaisePrivilege
- PUBLIC vPortSwitchToUserMode
-
-
+ PUBLIC vPortRestoreContextOfFirstTask
+ PUBLIC xIsPrivileged
+ PUBLIC vResetPrivilege
/*-----------------------------------------------------------*/
@@ -58,37 +56,39 @@
it eq
vstmdbeq r0!, {s16-s31}
+ /* Save the core registers. */
mrs r1, control
- /* Save the core registers. */
stmdb r0!, {r1, r4-r11, r14}
/* Save the new top of stack into the first member of the TCB. */
str r0, [r2]
- stmdb sp!, {r3}
+ stmdb sp!, {r0, r3}
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- cpsid i
+ cpsid i
msr basepri, r0
dsb
isb
- cpsie i
+ cpsie i
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
- ldmia sp!, {r3}
+ ldmia sp!, {r0, r3}
/* The first item in pxCurrentTCB is the task top of stack. */
ldr r1, [r3]
ldr r0, [r1]
-
- add r1, r1, #4 /* Move onto the second item in the TCB... */
- ldr r2, =0xe000ed9c /* Region Base Address register. */
- ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers. */
- stmia r2!, {r4-r11} /* Write 4 sets of MPU registers. */
-
- /* Pop the core registers. */
+ /* Move onto the second item in the TCB... */
+ add r1, r1, #4
+ /* Region Base Address register. */
+ ldr r2, =0xe000ed9c
+ /* Read 4 sets of MPU registers. */
+ ldmia r1!, {r4-r11}
+ /* Write 4 sets of MPU registers. */
+ stmia r2!, {r4-r11}
+ /* Pop the registers that are not automatically saved on exception entry. */
ldmia r0!, {r3-r11, r14}
- msr control, r3
+ msr control, r3
/* Is the task using the FPU context? If so, pop the high vfp registers
too. */
@@ -98,12 +98,6 @@
msr psp, r0
isb
- #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
- #if WORKAROUND_PMU_CM001 == 1
- push { r14 }
- pop { pc }
- #endif
- #endif
bx r14
@@ -111,7 +105,6 @@
/*-----------------------------------------------------------*/
vPortSVCHandler:
- /* Assumes psp was in use. */
#ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
tst lr, #4
ite eq
@@ -120,7 +113,7 @@
#else
mrs r0, psp
#endif
- b vSVCHandler
+ b vPortSVCHandler_C
/*-----------------------------------------------------------*/
@@ -131,33 +124,50 @@
ldr r0, [r0]
/* Set the msp back to the start of the stack. */
msr msp, r0
+ /* Clear the bit that indicates the FPU is in use in case the FPU was used
+ before the scheduler was started - which would otherwise result in the
+ unnecessary leaving of space in the SVC stack for lazy saving of FPU
+ registers. */
+ mov r0, #0
+ msr control, r0
/* Call SVC to start the first task. */
cpsie i
cpsie f
dsb
isb
- svc 0 /* System call to start first task. */
-
-vRestoreContextOfFirstTask:
+ svc 0
- ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
+/*-----------------------------------------------------------*/
+
+vPortRestoreContextOfFirstTask:
+ /* Use the NVIC offset register to locate the stack. */
+ ldr r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
- msr msp, r0 /* Set the msp back to the start of the stack. */
- ldr r3, =pxCurrentTCB /* Restore the context. */
+ /* Set the msp back to the start of the stack. */
+ msr msp, r0
+ /* Restore the context. */
+ ldr r3, =pxCurrentTCB
ldr r1, [r3]
- ldr r0, [r1] /* The first item in the TCB is the task top of stack. */
- add r1, r1, #4 /* Move onto the second item in the TCB... */
- ldr r2, =0xe000ed9c /* Region Base Address register. */
- ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers. */
- stmia r2!, {r4-r11} /* Write 4 sets of MPU registers. */
- ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
+ /* The first item in the TCB is the task top of stack. */
+ ldr r0, [r1]
+ /* Move onto the second item in the TCB... */
+ add r1, r1, #4
+ /* Region Base Address register. */
+ ldr r2, =0xe000ed9c
+ /* Read 4 sets of MPU registers. */
+ ldmia r1!, {r4-r11}
+ /* Write 4 sets of MPU registers. */
+ stmia r2!, {r4-r11}
+ /* Pop the registers that are not automatically saved on exception entry. */
+ ldmia r0!, {r3-r11, r14}
msr control, r3
- msr psp, r0 /* Restore the task stack pointer. */
+ /* Restore the task stack pointer. */
+ msr psp, r0
mov r0, #0
msr basepri, r0
bx r14
-
+
/*-----------------------------------------------------------*/
vPortEnableVFP:
@@ -170,25 +180,22 @@
str r1, [r0]
bx r14
-xPortRaisePrivilege:
- mrs r0, control
- tst r0, #1 /* Is the task running privileged? */
- itte ne
- movne r0, #0 /* CONTROL[0]!=0, return false. */
- svcne 2 /* Switch to privileged. */
- moveq r0, #1 /* CONTROL[0]==0, return true. */
- bx lr
-
/*-----------------------------------------------------------*/
+xIsPrivileged:
+ mrs r0, control /* r0 = CONTROL. */
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ ite ne
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ bx lr /* Return. */
+/*-----------------------------------------------------------*/
-
-vPortSwitchToUserMode:
-
- mrs r0, control
- orr r0, r0, #1
- msr control, r0
- bx r14
+vResetPrivilege:
+ mrs r0, control /* r0 = CONTROL. */
+ orr r0, r0, #1 /* r0 = r0 | 1. */
+ msr control, r0 /* CONTROL = r0. */
+ bx lr /* Return to the caller. */
+/*-----------------------------------------------------------*/
END
-
diff --git a/Source/portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h b/Source/portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h
index 43d4e45..315e47c 100644
--- a/Source/portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h
+++ b/Source/portable/IAR/ARM_CM7_MPU/r0p1/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -42,6 +42,9 @@
*-----------------------------------------------------------
*/
+/* IAR includes. */
+#include <intrinsics.h>
+
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
@@ -66,8 +69,8 @@
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#endif
-
/*-----------------------------------------------------------*/
+
/* MPU specific constants. */
#define portUSING_MPU_WRAPPERS 1
#define portPRIVILEGE_BIT ( 0x80000000UL )
@@ -79,18 +82,17 @@
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
-#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
-#define portPRIVILEGED_FLASH_REGION ( 1UL )
-#define portPRIVILEGED_RAM_REGION ( 2UL )
-#define portGENERAL_PERIPHERALS_REGION ( 3UL )
-#define portSTACK_REGION ( 4UL )
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )
-#define portLAST_CONFIGURABLE_REGION ( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
+#define portPRIVILEGED_FLASH_REGION ( 1UL )
+#define portPRIVILEGED_RAM_REGION ( 2UL )
+#define portGENERAL_PERIPHERALS_REGION ( 3UL )
+#define portSTACK_REGION ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portLAST_CONFIGURABLE_REGION ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-void vPortSwitchToUserMode( void );
-#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
typedef struct MPU_REGION_REGISTERS
{
@@ -105,20 +107,20 @@
} xMPU_SETTINGS;
-
/* Architecture specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 8
+/*-----------------------------------------------------------*/
/* SVC numbers for various services. */
#define portSVC_START_SCHEDULER 0
#define portSVC_YIELD 1
#define portSVC_RAISE_PRIVILEGE 2
-/*-----------------------------------------------------------*/
/* Scheduler utilities. */
-#define portYIELD() \
+#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) : "memory" )
+#define portYIELD_WITHIN_API() \
{ \
/* Set a PendSV to request a context switch. */ \
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
@@ -126,11 +128,9 @@
__ISB(); \
}
-
-
#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API()
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@@ -140,7 +140,7 @@
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#endif
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
/* Check the configuration. */
#if( configMAX_PRIORITIES > 32 )
@@ -153,7 +153,6 @@
/*-----------------------------------------------------------*/
- #include <intrinsics.h>
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
@@ -165,12 +164,11 @@
#define portDISABLE_INTERRUPTS() \
{ \
- /* Errata work around. */ \
- __disable_interrupt(); \
+ __disable_interrupt(); \
__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
__DSB(); \
__ISB(); \
- __enable_interrupt(); \
+ __enable_interrupt(); \
}
#define portENABLE_INTERRUPTS() __set_BASEPRI( 0 )
@@ -180,14 +178,6 @@
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) __set_BASEPRI( x )
/*-----------------------------------------------------------*/
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
- extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
- #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
/* Task function macros as described on the FreeRTOS.org WEB site. These are
not necessary for to use this port. They are defined so the common demo files
(which build with all the ports) will build. */
@@ -200,9 +190,30 @@
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
#endif
-void vSVCHandler( uint32_t *pulParam );
-void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/* portNOP() is not required by this port. */
+#define portNOP()
+/*-----------------------------------------------------------*/
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE() vResetPrivilege()
/*-----------------------------------------------------------*/
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
diff --git a/Source/portable/MemMang/heap_1.c b/Source/portable/MemMang/heap_1.c
index 7ff6dfa..542317d 100644
--- a/Source/portable/MemMang/heap_1.c
+++ b/Source/portable/MemMang/heap_1.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -53,7 +53,6 @@
#define configADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
/* Allocate the memory for the heap. */
-/* Allocate the memory for the heap. */
#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
/* The application writer has already defined the array used for the RTOS
heap - probably so it can be placed in a special segment or address. */
diff --git a/Source/portable/MemMang/heap_2.c b/Source/portable/MemMang/heap_2.c
index 941b4f2..7d06921 100644
--- a/Source/portable/MemMang/heap_2.c
+++ b/Source/portable/MemMang/heap_2.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/MemMang/heap_3.c b/Source/portable/MemMang/heap_3.c
index c8c3f54..e6a2990 100644
--- a/Source/portable/MemMang/heap_3.c
+++ b/Source/portable/MemMang/heap_3.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/MemMang/heap_4.c b/Source/portable/MemMang/heap_4.c
index 02251c0..d7cd8a5 100644
--- a/Source/portable/MemMang/heap_4.c
+++ b/Source/portable/MemMang/heap_4.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/MemMang/heap_5.c b/Source/portable/MemMang/heap_5.c
index 51c53a9..b52d61c 100644
--- a/Source/portable/MemMang/heap_5.c
+++ b/Source/portable/MemMang/heap_5.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/RVDS/ARM_CM0/port.c b/Source/portable/RVDS/ARM_CM0/port.c
index 6e1ce5f..33bf3eb 100644
--- a/Source/portable/RVDS/ARM_CM0/port.c
+++ b/Source/portable/RVDS/ARM_CM0/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -193,7 +193,7 @@
*/
BaseType_t xPortStartScheduler( void )
{
- /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
diff --git a/Source/portable/RVDS/ARM_CM0/portmacro.h b/Source/portable/RVDS/ARM_CM0/portmacro.h
index 4f9f7a5..9843778 100644
--- a/Source/portable/RVDS/ARM_CM0/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM0/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/RVDS/ARM_CM3/port.c b/Source/portable/RVDS/ARM_CM3/port.c
index fab5a4d..9d5755b 100644
--- a/Source/portable/RVDS/ARM_CM3/port.c
+++ b/Source/portable/RVDS/ARM_CM3/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/RVDS/ARM_CM3/portmacro.h b/Source/portable/RVDS/ARM_CM3/portmacro.h
index a2bf018..65cd27e 100644
--- a/Source/portable/RVDS/ARM_CM3/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM3/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/RVDS/ARM_CM4F/port.c b/Source/portable/RVDS/ARM_CM4F/port.c
index 4292826..a7658c3 100644
--- a/Source/portable/RVDS/ARM_CM4F/port.c
+++ b/Source/portable/RVDS/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/RVDS/ARM_CM4F/portmacro.h b/Source/portable/RVDS/ARM_CM4F/portmacro.h
index a2bf018..65cd27e 100644
--- a/Source/portable/RVDS/ARM_CM4F/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/RVDS/ARM_CM4_MPU/port.c b/Source/portable/RVDS/ARM_CM4_MPU/port.c
index 621bc06..79557fe 100644
--- a/Source/portable/RVDS/ARM_CM4_MPU/port.c
+++ b/Source/portable/RVDS/ARM_CM4_MPU/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -130,13 +130,6 @@
static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-BaseType_t xPortRaisePrivilege( void );
-
-/*
* Standard FreeRTOS exception handlers.
*/
void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
@@ -175,6 +168,35 @@
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void );
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
/*-----------------------------------------------------------*/
/*
@@ -651,15 +673,27 @@
}
/*-----------------------------------------------------------*/
-__asm BaseType_t xPortRaisePrivilege( void )
+__asm BaseType_t xIsPrivileged( void )
{
- mrs r0, control
- tst r0, #1 /* Is the task running privileged? */
- itte ne
- movne r0, #0 /* CONTROL[0]!=0, return false. */
- svcne portSVC_RAISE_PRIVILEGE /* Switch to privileged. */
- moveq r0, #1 /* CONTROL[0]==0, return true. */
- bx lr
+ PRESERVE8
+
+ mrs r0, control /* r0 = CONTROL. */
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ ite ne
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ bx lr /* Return. */
+}
+/*-----------------------------------------------------------*/
+
+__asm void vResetPrivilege( void )
+{
+ PRESERVE8
+
+ mrs r0, control /* r0 = CONTROL. */
+ orrs r0, #1 /* r0 = r0 | 1. */
+ msr control, r0 /* CONTROL = r0. */
+ bx lr /* Return. */
}
/*-----------------------------------------------------------*/
diff --git a/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h b/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
index 8e1ad96..9a37600 100644
--- a/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -85,7 +85,7 @@
#define portPRIVILEGED_RAM_REGION ( 2UL )
#define portGENERAL_PERIPHERALS_REGION ( 3UL )
#define portSTACK_REGION ( 4UL )
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
#define portLAST_CONFIGURABLE_REGION ( 7UL )
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
@@ -197,7 +197,28 @@
#ifndef portFORCE_INLINE
#define portFORCE_INLINE __forceinline
#endif
+/*-----------------------------------------------------------*/
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ */
+#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE }
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE() vResetPrivilege()
/*-----------------------------------------------------------*/
static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
@@ -280,24 +301,6 @@
}
/*-----------------------------------------------------------*/
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-uint32_t ulReg;
-
- if( xRunningPrivileged != pdTRUE )
- {
- __asm
- {
- mrs ulReg, control
- orr ulReg, #1
- msr control, ulReg
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Source/portable/RVDS/ARM_CM7/r0p1/port.c b/Source/portable/RVDS/ARM_CM7/r0p1/port.c
index f5e348f..f430e8e 100644
--- a/Source/portable/RVDS/ARM_CM7/r0p1/port.c
+++ b/Source/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
index 75934ec..7004756 100644
--- a/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c b/Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c
index dba729c..f0982ca 100644
--- a/Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c
+++ b/Source/portable/RVDS/ARM_CM7_MPU/r0p1/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -52,6 +52,24 @@
#define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
#define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
+#else
+ /* The way the SysTick is clocked is not modified in case it is not the same
+ as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT ( 0 )
+#endif
+
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+#define portMISSED_COUNTS_FACTOR ( 45UL )
/* Constants required to access and manipulate the MPU. */
#define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
@@ -71,7 +89,6 @@
#define portNVIC_SYSTICK_CLK ( 0x00000004UL )
#define portNVIC_SYSTICK_INT ( 0x00000002UL )
#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
-#define portNVIC_SYSTICK_COUNT_FLAG ( 1UL << 16UL )
#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
@@ -82,7 +99,7 @@
/* Constants required to set up the initial stack. */
#define portINITIAL_XPSR ( 0x01000000UL )
-#define portINITIAL_EXEC_RETURN ( 0xfffffffdUL )
+#define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
@@ -99,14 +116,6 @@
/* Offsets in the stack to the parameters when inside the SVC handler. */
#define portOFFSET_TO_PC ( 6 )
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR ( 45UL )
-
/* For strict compliance with the Cortex-M spec the task start address should
have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
@@ -116,12 +125,30 @@
switches can only occur when uxCriticalNesting is zero. */
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+#if( configUSE_TICKLESS_IDLE == 1 )
/*
- * Setup the timer to generate the tick interrupts. The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
+ * The number of SysTick increments that make up one tick period.
*/
-void vPortSetupTimerInterrupt( void );
+ static uint32_t ulTimerCountsForOneTick = 0;
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+ static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
/*
* Configure a number of standard MPU regions that are used by all tasks.
@@ -141,13 +168,6 @@
static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-BaseType_t xPortRaisePrivilege( void );
-
-/*
* Standard FreeRTOS exception handlers.
*/
void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
@@ -176,29 +196,6 @@
static uint32_t prvPortGetIPSR( void );
/*
- * The number of SysTick increments that make up one tick period.
- */
-#if configUSE_TICKLESS_IDLE == 1
- static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if configUSE_TICKLESS_IDLE == 1
- static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if configUSE_TICKLESS_IDLE == 1
- static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
* FreeRTOS API functions are not called from interrupts that have been assigned
* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
@@ -209,6 +206,35 @@
static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
#endif /* configASSERT_DEFINED */
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ * Bit[0] = 0 --> The processor is running privileged
+ * Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void );
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
/*-----------------------------------------------------------*/
/*
@@ -230,7 +256,7 @@
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
- *pxTopOfStack = portINITIAL_EXEC_RETURN;
+ *pxTopOfStack = portINITIAL_EXC_RETURN;
pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
@@ -371,6 +397,24 @@
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
+ #ifdef __NVIC_PRIO_BITS
+ {
+ /* Check the CMSIS configuration that defines the number of
+ priority bits matches the number of priority bits actually queried
+ from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+ }
+ #endif
+
+ #ifdef configPRIO_BITS
+ {
+ /* Check the FreeRTOS configuration that defines the number of
+ priority bits matches the number of priority bits actually queried
+ from the hardware. */
+ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+ }
+ #endif
+
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
@@ -393,7 +437,7 @@
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
- vPortSetupTimerInterrupt();
+ prvSetupTimerInterrupt();
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
@@ -415,12 +459,21 @@
__asm void prvStartFirstTask( void )
{
PRESERVE8
-
- ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
+
+ /* Use the NVIC offset register to locate the stack. */
+ ldr r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
- msr msp, r0 /* Set the msp back to the start of the stack. */
- cpsie i /* Globally enable interrupts. */
+ /* Set the msp back to the start of the stack. */
+ msr msp, r0
+ /* Clear the bit that indicates the FPU is in use in case the FPU was used
+ before the scheduler was started - which would otherwise result in the
+ unnecessary leaving of space in the SVC stack for lazy saving of FPU
+ registers. */
+ mov r0, #0
+ msr control, r0
+ /* Globally enable interrupts. */
+ cpsie i
cpsie f
dsb
isb
@@ -472,8 +525,8 @@
mrs r0, psp
- ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
- ldr r2, [r3]
+ ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
+ ldr r2, [r3]
tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
it eq
@@ -483,9 +536,8 @@
stmdb r0!, {r1, r4-r11, r14} /* Save the remaining registers. */
str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
- stmdb sp!, {r3}
+ stmdb sp!, {r0, r3}
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
- cpsid i
msr basepri, r0
dsb
isb
@@ -493,7 +545,7 @@
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
- ldmia sp!, {r3}
+ ldmia sp!, {r0, r3}
/* Restore the context. */
ldr r1, [r3]
ldr r0, [r1] /* The first item in the TCB is the task top of stack. */
@@ -511,29 +563,16 @@
msr psp, r0
bx r14
nop
+ nop
}
+
/*-----------------------------------------------------------*/
-void xPortSysTickHandler( void )
-{
-uint32_t ulDummy;
+#if( configUSE_TICKLESS_IDLE == 1 )
- ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
- {
- /* Increment the RTOS tick. */
- if( xTaskIncrementTick() != pdFALSE )
- {
- /* Pend a context switch. */
- portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
- }
- }
- portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
-/*-----------------------------------------------------------*/
-#if configUSE_TICKLESS_IDLE == 1
__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
- uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
@@ -546,7 +585,7 @@
is accounted for as best it can be, but using the tickless mode will
inevitably result in some tiny drift of the time maintained by the
kernel with respect to calendar time. */
- portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE;
+ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
/* Calculate the reload value required to wait xExpectedIdleTime
tick periods. -1 is used because this code will execute part way
@@ -572,7 +611,7 @@
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE;
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
periods. */
@@ -592,7 +631,7 @@
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE;
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
set its parameter to 0 to indicate that its implementation contains
@@ -609,23 +648,41 @@
}
configPOST_SLEEP_PROCESSING( &xExpectedIdleTime );
- /* Stop SysTick. Again, the time the SysTick is stopped for is
- accounted for as best it can be, but using the tickless mode will
- inevitably result in some tiny drift of the time maintained by the
- kernel with respect to calendar time. */
- ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
- portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE );
-
- /* Re-enable interrupts - see comments above __disable_irq() call
- above. */
+ /* Re-enable interrupts to allow the interrupt that brought the MCU
+ out of sleep mode to execute immediately. see comments above
+ __disable_interrupt() call above. */
__enable_irq();
+ __dsb( portSY_FULL_READ_WRITE );
+ __isb( portSY_FULL_READ_WRITE );
- if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG ) != 0 )
+ /* Disable interrupts again because the clock is about to be stopped
+ and interrupts that execute while the clock is stopped will increase
+ any slippage between the time maintained by the RTOS and calendar
+ time. */
+ __disable_irq();
+ __dsb( portSY_FULL_READ_WRITE );
+ __isb( portSY_FULL_READ_WRITE );
+
+ /* Disable the SysTick clock without reading the
+ portNVIC_SYSTICK_CTRL_REG register to ensure the
+ portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
+ the time the SysTick is stopped for is accounted for as best it can
+ be, but using the tickless mode will inevitably result in some tiny
+ drift of the time maintained by the kernel with respect to calendar
+ time*/
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+ /* Determine if the SysTick clock has already counted to zero and
+ been set back to the current reload value (the reload back being
+ correct for the entire expected idle time) or if the SysTick is yet
+ to count to zero (in which case an interrupt other than the SysTick
+ must have brought the system out of sleep mode). */
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
- /* The tick interrupt has already executed, and the SysTick
- count reloaded with ulReloadValue. Reset the
+ /* The tick interrupt is already pending, and the SysTick count
+ reloaded with ulReloadValue. Reset the
portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
@@ -640,11 +697,9 @@
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
- /* The tick interrupt handler will already have pended the tick
- processing in the kernel. As the pending tick will be
- processed as soon as this function exits, the tick value
- maintained by the tick is stepped forward by one less than the
- time spent waiting. */
+ /* As the pending tick will be processed as soon as this
+ function exits, the tick value maintained by the tick is stepped
+ forward by one less than the time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
@@ -666,63 +721,75 @@
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
- value. The critical section is used to ensure the tick interrupt
- can only execute once in the case that the reload register is near
- zero. */
+ value. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
- portENTER_CRITICAL();
- {
- portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE;
- vTaskStepTick( ulCompleteTickPeriods );
- portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
- }
- portEXIT_CRITICAL();
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ vTaskStepTick( ulCompleteTickPeriods );
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+ /* Exit with interrpts enabled. */
+ __enable_irq();
}
}
#endif /* #if configUSE_TICKLESS_IDLE */
+void xPortSysTickHandler( void )
+{
+uint32_t ulDummy;
+
+ ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* Pend a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
/*-----------------------------------------------------------*/
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
-#if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0
+static void prvSetupTimerInterrupt( void )
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+#if( configUSE_TICKLESS_IDLE == 1 )
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+#endif /* configUSE_TICKLESS_IDLE */
- void vPortSetupTimerInterrupt( void )
- {
- /* Calculate the constants required to configure the tick interrupt. */
- #if configUSE_TICKLESS_IDLE == 1
- {
- ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
- xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
- ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
- }
- #endif /* configUSE_TICKLESS_IDLE */
- /* Configure SysTick to interrupt at the requested rate. */
- portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
- portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
- }
-#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+ /* Reset the SysTick. */
+ portNVIC_SYSTICK_CTRL_REG = 0UL;
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
/*-----------------------------------------------------------*/
__asm void vPortSwitchToUserMode( void )
{
PRESERVE8
-
+
mrs r0, control
orr r0, #1
msr control, r0
bx r14
}
/*-----------------------------------------------------------*/
-
+
__asm void vPortEnableVFP( void )
{
PRESERVE8
-
+
ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
ldr r1, [r0]
@@ -742,6 +809,9 @@
extern uint32_t __privileged_data_start__;
extern uint32_t __privileged_data_end__;
+ /* Check the expected MPU is present. */
+ if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+ {
/* First setup the entire flash for unprivileged read only access. */
portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
( portMPU_REGION_VALID ) |
@@ -790,6 +860,7 @@
/* Enable the MPU with the background region configured. */
portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+ }
}
/*-----------------------------------------------------------*/
@@ -817,15 +888,27 @@
}
/*-----------------------------------------------------------*/
-__asm BaseType_t xPortRaisePrivilege( void )
+__asm BaseType_t xIsPrivileged( void )
{
- mrs r0, control
- tst r0, #1 /* Is the task running privileged? */
- itte ne
- movne r0, #0 /* CONTROL[0]!=0, return false. */
- svcne portSVC_RAISE_PRIVILEGE /* Switch to privileged. */
- moveq r0, #1 /* CONTROL[0]==0, return true. */
- bx lr
+ PRESERVE8
+
+ mrs r0, control /* r0 = CONTROL. */
+ tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+ ite ne
+ movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+ moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+ bx lr /* Return. */
+}
+/*-----------------------------------------------------------*/
+
+__asm void vResetPrivilege( void )
+{
+ PRESERVE8
+
+ mrs r0, control /* r0 = CONTROL. */
+ orrs r0, #1 /* r0 = r0 | 1. */
+ msr control, r0 /* CONTROL = r0. */
+ bx lr /* Return. */
}
/*-----------------------------------------------------------*/
diff --git a/Source/portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h b/Source/portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h
index 4957d43..3db6c16 100644
--- a/Source/portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM7_MPU/r0p1/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -85,7 +85,7 @@
#define portPRIVILEGED_RAM_REGION ( 2UL )
#define portGENERAL_PERIPHERALS_REGION ( 3UL )
#define portSTACK_REGION ( 4UL )
-#define portFIRST_CONFIGURABLE_REGION ( 5UL )
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )
#define portLAST_CONFIGURABLE_REGION ( 7UL )
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
@@ -197,7 +197,28 @@
#ifndef portFORCE_INLINE
#define portFORCE_INLINE __forceinline
#endif
+/*-----------------------------------------------------------*/
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED() xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ */
+#define portRAISE_PRIVILEGE() __asm { svc portSVC_RAISE_PRIVILEGE }
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE() vResetPrivilege()
/*-----------------------------------------------------------*/
static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
@@ -233,7 +254,7 @@
__asm
{
/* Set BASEPRI to 0 so no interrupts are masked. This function is only
- used to lower the mask in an interrupt, so memory barriers are not
+ used to lower the mask in an interrupt, so memory barriers are not
used. */
msr basepri, #0
}
@@ -284,24 +305,6 @@
}
/*-----------------------------------------------------------*/
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-uint32_t ulReg;
-
- if( xRunningPrivileged != pdTRUE )
- {
- __asm
- {
- mrs ulReg, control
- orr ulReg, #1
- msr control, ulReg
- }
- }
-}
-/*-----------------------------------------------------------*/
-
-
#ifdef __cplusplus
}
#endif
diff --git a/Source/portable/Tasking/ARM_CM4F/port.c b/Source/portable/Tasking/ARM_CM4F/port.c
index bb12747..af77fe3 100644
--- a/Source/portable/Tasking/ARM_CM4F/port.c
+++ b/Source/portable/Tasking/ARM_CM4F/port.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/Tasking/ARM_CM4F/port_asm.asm b/Source/portable/Tasking/ARM_CM4F/port_asm.asm
index 2b4f707..22928de 100644
--- a/Source/portable/Tasking/ARM_CM4F/port_asm.asm
+++ b/Source/portable/Tasking/ARM_CM4F/port_asm.asm
@@ -1,6 +1,6 @@
;/*
-; * FreeRTOS Kernel V10.0.1
-; * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+; * FreeRTOS Kernel V10.2.0
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/portable/Tasking/ARM_CM4F/portmacro.h b/Source/portable/Tasking/ARM_CM4F/portmacro.h
index a8c5670..e3f3c2c 100644
--- a/Source/portable/Tasking/ARM_CM4F/portmacro.h
+++ b/Source/portable/Tasking/ARM_CM4F/portmacro.h
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
diff --git a/Source/queue.c b/Source/queue.c
index 0730950..d882bf6 100644
--- a/Source/queue.c
+++ b/Source/queue.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -41,11 +41,11 @@
#include "croutine.h"
#endif
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
/* Constants used with the cRxLock and cTxLock structure members. */
@@ -56,17 +56,26 @@
pcTail members are used as pointers into the queue storage area. When the
Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
not necessary, and the pcHead pointer is set to NULL to indicate that the
-pcTail pointer actually points to the mutex holder (if any). Map alternative
-names to the pcHead and pcTail structure members to ensure the readability of
-the code is maintained despite this dual use of two structure members. An
-alternative implementation would be to use a union, but use of a union is
-against the coding standard (although an exception to the standard has been
-permitted where the dual use also significantly changes the type of the
-structure member). */
-#define pxMutexHolder pcTail
+structure instead holds a pointer to the mutex holder (if any). Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained. The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
#define uxQueueType pcHead
#define queueQUEUE_IS_MUTEX NULL
+typedef struct QueuePointers
+{
+ int8_t *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+ int8_t *pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+ TaskHandle_t xMutexHolder; /*< The handle of the task that holds the mutex. */
+ UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
/* Semaphores do not actually store or copy data, so have an item size of
zero. */
#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
@@ -83,18 +92,17 @@
/*
* Definition of the queue used by the scheduler.
* Items are queued by copy, not reference. See the following link for the
- * rationale: http://www.freertos.org/Embedded-RTOS-Queues.html
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
*/
-typedef struct QueueDefinition
+typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */
{
int8_t *pcHead; /*< Points to the beginning of the queue storage area. */
- int8_t *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
int8_t *pcWriteTo; /*< Points to the free next place in the storage area. */
- union /* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */
+ union
{
- int8_t *pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */
- UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+ QueuePointers_t xQueue; /*< Data required exclusively when this structure is used as a queue. */
+ SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
} u;
List_t xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */
@@ -246,16 +254,16 @@
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
configASSERT( pxQueue );
taskENTER_CRITICAL();
{
- pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
+ pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
pxQueue->pcWriteTo = pxQueue->pcHead;
- pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );
+ pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
pxQueue->cRxLock = queueUNLOCKED;
pxQueue->cTxLock = queueUNLOCKED;
@@ -321,13 +329,14 @@
the real queue and semaphore structures. */
volatile size_t xSize = sizeof( StaticQueue_t );
configASSERT( xSize == sizeof( Queue_t ) );
+ ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
}
#endif /* configASSERT_DEFINED */
/* The address of a statically allocated queue was passed in, use it.
The address of a statically allocated storage area was also passed in
but is already set. */
- pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
if( pxNewQueue != NULL )
{
@@ -345,6 +354,7 @@
else
{
traceQUEUE_CREATE_FAILED( ucQueueType );
+ mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
@@ -375,13 +385,23 @@
xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
}
- pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );
+ /* Allocate the queue and storage area. Justification for MISRA
+ deviation as follows: pvPortMalloc() always ensures returned memory
+ blocks are aligned per the requirements of the MCU stack. In this case
+ pvPortMalloc() must return a pointer that is guaranteed to meet the
+ alignment requirements of the Queue_t structure - which in this case
+ is an int8_t *. Therefore, whenever the stack alignment requirements
+ are greater than or equal to the pointer to char requirements the cast
+ is safe. In other cases alignment requirements are not strict (one or
+ two bytes). */
+ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
if( pxNewQueue != NULL )
{
/* Jump past the queue structure to find the location of the queue
storage area. */
- pucQueueStorage = ( ( uint8_t * ) pxNewQueue ) + sizeof( Queue_t );
+ pucQueueStorage = ( uint8_t * ) pxNewQueue;
+ pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
@@ -397,6 +417,7 @@
else
{
traceQUEUE_CREATE_FAILED( ucQueueType );
+ mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
@@ -457,11 +478,11 @@
correctly for a generic queue, but this function is creating a
mutex. Overwrite those members that need to be set differently -
in particular the information required for priority inheritance. */
- pxNewQueue->pxMutexHolder = NULL;
+ pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
/* In case this is a recursive mutex. */
- pxNewQueue->u.uxRecursiveCallCount = 0;
+ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
traceCREATE_MUTEX( pxNewQueue );
@@ -481,13 +502,13 @@
QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
{
- Queue_t *pxNewQueue;
+ QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
- pxNewQueue = ( Queue_t * ) xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
- prvInitialiseMutex( pxNewQueue );
+ xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+ prvInitialiseMutex( ( Queue_t * ) xNewQueue );
- return pxNewQueue;
+ return xNewQueue;
}
#endif /* configUSE_MUTEXES */
@@ -497,17 +518,17 @@
QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
{
- Queue_t *pxNewQueue;
+ QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
/* Prevent compiler warnings about unused parameters if
configUSE_TRACE_FACILITY does not equal 1. */
( void ) ucQueueType;
- pxNewQueue = ( Queue_t * ) xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
- prvInitialiseMutex( pxNewQueue );
+ xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+ prvInitialiseMutex( ( Queue_t * ) xNewQueue );
- return pxNewQueue;
+ return xNewQueue;
}
#endif /* configUSE_MUTEXES */
@@ -515,9 +536,10 @@
#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
- void* xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+ TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
{
- void *pxReturn;
+ TaskHandle_t pxReturn;
+ Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
/* This function is called by xSemaphoreGetMutexHolder(), and should not
be called directly. Note: This is a good way of determining if the
@@ -526,9 +548,9 @@
following critical section exiting and the function returning. */
taskENTER_CRITICAL();
{
- if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+ if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
{
- pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
+ pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
}
else
{
@@ -545,9 +567,9 @@
#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
- void* xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+ TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
{
- void *pxReturn;
+ TaskHandle_t pxReturn;
configASSERT( xSemaphore );
@@ -556,7 +578,7 @@
not required here. */
if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
{
- pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
+ pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
}
else
{
@@ -578,25 +600,25 @@
configASSERT( pxMutex );
- /* If this is the task that holds the mutex then pxMutexHolder will not
+ /* If this is the task that holds the mutex then xMutexHolder will not
change outside of this task. If this task does not hold the mutex then
pxMutexHolder can never coincidentally equal the tasks handle, and as
this is the only condition we are interested in it does not matter if
pxMutexHolder is accessed simultaneously by another task. Therefore no
mutual exclusion is required to test the pxMutexHolder variable. */
- if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */
+ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
{
traceGIVE_MUTEX_RECURSIVE( pxMutex );
- /* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to
+ /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
the task handle, therefore no underflow check is required. Also,
uxRecursiveCallCount is only modified by the mutex holder, and as
there can only be one, no mutual exclusion is required to modify the
uxRecursiveCallCount member. */
- ( pxMutex->u.uxRecursiveCallCount )--;
+ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
/* Has the recursive call count unwound to 0? */
- if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
{
/* Return the mutex. This will automatically unblock any other
task that might be waiting to access the mutex. */
@@ -638,9 +660,9 @@
traceTAKE_MUTEX_RECURSIVE( pxMutex );
- if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
{
- ( pxMutex->u.uxRecursiveCallCount )++;
+ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
xReturn = pdPASS;
}
else
@@ -652,7 +674,7 @@
before reaching here. */
if( xReturn != pdFAIL )
{
- ( pxMutex->u.uxRecursiveCallCount )++;
+ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
}
else
{
@@ -726,7 +748,7 @@
{
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
TimeOut_t xTimeOut;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
configASSERT( pxQueue );
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -738,9 +760,9 @@
#endif
- /* This function relaxes the coding standard somewhat to allow return
- statements within the function itself. This is done in the interest
- of execution time efficiency. */
+ /*lint -save -e904 This function relaxes the coding standard somewhat to
+ allow return statements within the function itself. This is done in the
+ interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
@@ -752,13 +774,23 @@
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
{
traceQUEUE_SEND( pxQueue );
- xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
#if ( configUSE_QUEUE_SETS == 1 )
{
+ UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+ xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
if( pxQueue->pxQueueSetContainer != NULL )
{
- if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+ if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+ {
+ /* Do not notify the queue set as an existing item
+ was overwritten in the queue so the number of items
+ in the queue has not changed. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+ else if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
{
/* The queue is a member of a queue set, and posting
to the queue set caused a higher priority task to
@@ -805,6 +837,8 @@
}
#else /* configUSE_QUEUE_SETS */
{
+ xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
/* If there was a task waiting for data to arrive on the
queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
@@ -916,7 +950,7 @@
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
}
- }
+ } /*lint -restore */
}
/*-----------------------------------------------------------*/
@@ -924,7 +958,7 @@
{
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
configASSERT( pxQueue );
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -1075,7 +1109,7 @@
{
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
item size is 0. Don't directly wake a task that was blocked on a queue
@@ -1092,7 +1126,7 @@
/* Normally a mutex would not be given from an interrupt, especially if
there is a mutex holder, as priority inheritance makes no sense for an
interrupts, only tasks. */
- configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->pxMutexHolder != NULL ) ) );
+ configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
/* RTOS ports that support interrupt nesting have the concept of a maximum
system call (or maximum API call) interrupt priority. Interrupts that are
@@ -1240,7 +1274,7 @@
{
BaseType_t xEntryTimeSet = pdFALSE;
TimeOut_t xTimeOut;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
@@ -1256,10 +1290,10 @@
}
#endif
- /* This function relaxes the coding standard somewhat to allow return
- statements within the function itself. This is done in the interest
- of execution time efficiency. */
+ /*lint -save -e904 This function relaxes the coding standard somewhat to
+ allow return statements within the function itself. This is done in the
+ interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
@@ -1373,7 +1407,7 @@
mtCOVERAGE_TEST_MARKER();
}
}
- }
+ } /*lint -restore */
}
/*-----------------------------------------------------------*/
@@ -1381,7 +1415,7 @@
{
BaseType_t xEntryTimeSet = pdFALSE;
TimeOut_t xTimeOut;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
#if( configUSE_MUTEXES == 1 )
BaseType_t xInheritanceOccurred = pdFALSE;
@@ -1402,10 +1436,9 @@
#endif
- /* This function relaxes the coding standard somewhat to allow return
+ /*lint -save -e904 This function relaxes the coding standard somewhat to allow return
statements within the function itself. This is done in the interest
of execution time efficiency. */
-
for( ;; )
{
taskENTER_CRITICAL();
@@ -1430,7 +1463,7 @@
{
/* Record the information required to implement
priority inheritance should it become necessary. */
- pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
}
else
{
@@ -1518,7 +1551,7 @@
{
taskENTER_CRITICAL();
{
- xInheritanceOccurred = xTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
+ xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
}
taskEXIT_CRITICAL();
}
@@ -1577,7 +1610,7 @@
again, but only as low as the next highest priority
task that is waiting for the same mutex. */
uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
- vTaskPriorityDisinheritAfterTimeout( ( void * ) pxQueue->pxMutexHolder, uxHighestWaitingPriority );
+ vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
}
taskEXIT_CRITICAL();
}
@@ -1592,7 +1625,7 @@
mtCOVERAGE_TEST_MARKER();
}
}
- }
+ } /*lint -restore */
}
/*-----------------------------------------------------------*/
@@ -1601,7 +1634,7 @@
BaseType_t xEntryTimeSet = pdFALSE;
TimeOut_t xTimeOut;
int8_t *pcOriginalReadPosition;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
@@ -1618,10 +1651,9 @@
#endif
- /* This function relaxes the coding standard somewhat to allow return
- statements within the function itself. This is done in the interest
- of execution time efficiency. */
-
+ /*lint -save -e904 This function relaxes the coding standard somewhat to
+ allow return statements within the function itself. This is done in the
+ interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
@@ -1635,13 +1667,13 @@
/* Remember the read position so it can be reset after the data
is read from the queue as this function is only peeking the
data, not removing it. */
- pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+ pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
prvCopyDataFromQueue( pxQueue, pvBuffer );
traceQUEUE_PEEK( pxQueue );
/* The data is not being removed, so reset the read pointer. */
- pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+ pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
/* The data is being left in the queue, so see if there are
any other tasks waiting for the data. */
@@ -1742,7 +1774,7 @@
mtCOVERAGE_TEST_MARKER();
}
}
- }
+ } /*lint -restore */
}
/*-----------------------------------------------------------*/
@@ -1750,7 +1782,7 @@
{
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
configASSERT( pxQueue );
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -1842,7 +1874,7 @@
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
int8_t *pcOriginalReadPosition;
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
configASSERT( pxQueue );
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
@@ -1873,9 +1905,9 @@
/* Remember the read position so it can be reset as nothing is
actually being removed from the queue. */
- pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+ pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
prvCopyDataFromQueue( pxQueue, pvBuffer );
- pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+ pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
xReturn = pdPASS;
}
@@ -1910,9 +1942,8 @@
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
{
UBaseType_t uxReturn;
-Queue_t *pxQueue;
+Queue_t * const pxQueue = xQueue;
- pxQueue = ( Queue_t * ) xQueue;
configASSERT( pxQueue );
taskENTER_CRITICAL();
@@ -1928,10 +1959,10 @@
UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
{
UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
- configASSERT( xQueue );
-
- uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+ configASSERT( pxQueue );
+ uxReturn = pxQueue->uxMessagesWaiting;
return uxReturn;
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
@@ -1939,7 +1970,7 @@
void vQueueDelete( QueueHandle_t xQueue )
{
-Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+Queue_t * const pxQueue = xQueue;
configASSERT( pxQueue );
traceQUEUE_DELETE( pxQueue );
@@ -2021,9 +2052,9 @@
other tasks that are waiting for the same mutex. For this purpose,
return the priority of the highest priority task that is waiting for the
mutex. */
- if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0 )
+ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
{
- uxHighestPriorityOfWaitingTasks = configMAX_PRIORITIES - listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+ uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
}
else
{
@@ -2052,8 +2083,8 @@
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
{
/* The mutex is no longer being held. */
- xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );
- pxQueue->pxMutexHolder = NULL;
+ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+ pxQueue->u.xSemaphore.xMutexHolder = NULL;
}
else
{
@@ -2064,9 +2095,9 @@
}
else if( xPosition == queueSEND_TO_BACK )
{
- ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */
- pxQueue->pcWriteTo += pxQueue->uxItemSize;
- if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+ pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+ if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
{
pxQueue->pcWriteTo = pxQueue->pcHead;
}
@@ -2077,11 +2108,11 @@
}
else
{
- ( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
- pxQueue->u.pcReadFrom -= pxQueue->uxItemSize;
- if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
+ pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+ if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
{
- pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );
+ pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
}
else
{
@@ -2119,16 +2150,16 @@
{
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
{
- pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
- if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+ pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+ if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
{
- pxQueue->u.pcReadFrom = pxQueue->pcHead;
+ pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
- ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */
+ ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
}
}
/*-----------------------------------------------------------*/
@@ -2277,9 +2308,10 @@
BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
{
BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
- configASSERT( xQueue );
- if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )
+ configASSERT( pxQueue );
+ if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
{
xReturn = pdTRUE;
}
@@ -2316,9 +2348,10 @@
BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
{
BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
- configASSERT( xQueue );
- if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )
+ configASSERT( pxQueue );
+ if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
{
xReturn = pdTRUE;
}
@@ -2336,7 +2369,7 @@
BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
{
BaseType_t xReturn;
- Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+ Queue_t * const pxQueue = xQueue;
/* If the queue is already full we may have to block. A critical section
is required to prevent an interrupt removing something from the queue
@@ -2413,7 +2446,7 @@
BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
{
BaseType_t xReturn;
- Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+ Queue_t * const pxQueue = xQueue;
/* If the queue is already empty we may have to block. A critical section
is required to prevent an interrupt adding something to the queue
@@ -2450,17 +2483,17 @@
if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
{
/* Data is available from the queue. */
- pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
- if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+ pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+ if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
{
- pxQueue->u.pcReadFrom = pxQueue->pcHead;
+ pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--( pxQueue->uxMessagesWaiting );
- ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+ ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
xReturn = pdPASS;
@@ -2502,7 +2535,7 @@
BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
{
- Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+ Queue_t * const pxQueue = xQueue;
/* Cannot block within an ISR so if there is no space on the queue then
exit without doing anything. */
@@ -2551,24 +2584,24 @@
BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
{
BaseType_t xReturn;
- Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+ Queue_t * const pxQueue = xQueue;
/* We cannot block from an ISR, so check there is data available. If
not then just leave without doing anything. */
if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
{
/* Copy the data from the queue. */
- pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
- if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+ pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+ if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
{
- pxQueue->u.pcReadFrom = pxQueue->pcHead;
+ pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--( pxQueue->uxMessagesWaiting );
- ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+ ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
if( ( *pxCoRoutineWoken ) == pdFALSE )
{
@@ -2699,7 +2732,7 @@
void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
{
- Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+ Queue_t * const pxQueue = xQueue;
/* This function should not be called by application code hence the
'Restricted' in its name. It is not part of the public API. It is
diff --git a/Source/st_readme.txt b/Source/st_readme.txt
index 4f12c01..8d4bc15 100644
--- a/Source/st_readme.txt
+++ b/Source/st_readme.txt
@@ -25,6 +25,42 @@
=======
+### 17-January-2020 ###
+=========================
+ + Fix compile error in the GCC CM7_MPU port caused by a duplicated variable declaration
+ - Source/portable/GCC/ARM_CM7_MPU/r0p1/port.c
+
+### 13-December-2019 ###
+=========================
+ + Remove warnings thrown by EWARM for CM33/CM23 ports
+ - IAR/ARM_CM23/non_secure/portmacro.h
+ - IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+ - IAR/ARM_CM33/non_secure/portmacro.h
+ - IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+
+### 19-July-2019 ###
+=========================
+ + Fix runtime error in the IAR/CM4_MPU port
+ - IAR/ARM_CM4_MPU/port.c
+
+### 12-July-2019 ###
+=========================
+ + FreeRTOS: Update against the FreeRTOS v10.2.1 release
+ - support for the CM33 and CM23 cores
+
+ + CMSIS_RTOS_V2: update against the latest CMSIS-FreeRTOS v10.2.0 release
+
+ + Add MPU support for the CM7/r0p1:
+ - GCC/ARM_CM7_MPU/r0p1/port.c
+ - GCC/ARM_CM7_MPU/r0p1/portmacro.h
+ - IAR/ARM_CM7_MPU/r0p1/port.c
+ - IAR/ARM_CM7_MPU/r0p1/portasm.s
+ - IAR/ARM_CM7_MPU/r0p1/portmacro.h
+ - RVDS/ARM_CM7_MPU/r0p1/port.c
+ - RVDS/ARM_CM7_MPU/r0p1/portmacro.h
+
+ + cmsis_os.c: Fix compile errors by using the correct TimerCallbackFunction_t type for timer creation
+
### 29-Mars-2019 ###
=========================
+ cmsis_os.c : Fix bug in osPoolAlloc(): memory blocks can't be reused after being free'd
diff --git a/Source/stream_buffer.c b/Source/stream_buffer.c
index c60045f..8551970 100644
--- a/Source/stream_buffer.c
+++ b/Source/stream_buffer.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -43,11 +43,11 @@
#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
#endif
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
/* If the user has not provided application specific Rx notification macros,
or #defined the notification macros away, them provide default implementations
@@ -129,7 +129,7 @@
/*lint -restore (9026) */
/* The number of bytes used to hold the length of a message in the buffer. */
-#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( size_t ) )
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
/* Bits stored in the ucFlags field of the stream buffer. */
#define sbFLAGS_IS_MESSAGE_BUFFER ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
@@ -138,7 +138,7 @@
/*-----------------------------------------------------------*/
/* Structure that hold state information on the buffer. */
-typedef struct xSTREAM_BUFFER /*lint !e9058 Style convention uses tag. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
{
volatile size_t xTail; /* Index to the next item to read within the buffer. */
volatile size_t xHead; /* Index to the next item to write within the buffer. */
@@ -200,7 +200,7 @@
static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
uint8_t *pucData,
size_t xMaxCount,
- size_t xBytesAvailable ); PRIVILEGED_FUNCTION
+ size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
/*
* Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
@@ -210,7 +210,7 @@
uint8_t * const pucBuffer,
size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+ uint8_t ucFlags ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
@@ -219,19 +219,31 @@
StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
{
uint8_t *pucAllocatedMemory;
+ uint8_t ucFlags;
/* In case the stream buffer is going to be used as a message buffer
(that is, it will hold discrete messages with a little meta data that
says how big the next message is) check the buffer will be large enough
to hold at least one message. */
- configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+ if( xIsMessageBuffer == pdTRUE )
+ {
+ /* Is a message buffer but not statically allocated. */
+ ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+ configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+ }
+ else
+ {
+ /* Not a message buffer and not statically allocated. */
+ ucFlags = 0;
+ configASSERT( xBufferSizeBytes > 0 );
+ }
configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
/* A trigger level of 0 would cause a waiting task to unblock even when
the buffer was empty. */
if( xTriggerLevelBytes == ( size_t ) 0 )
{
- xTriggerLevelBytes = ( size_t ) 1; /*lint !e9044 Parameter modified to ensure it doesn't have a dangerous value. */
+ xTriggerLevelBytes = ( size_t ) 1;
}
/* A stream buffer requires a StreamBuffer_t structure and a buffer.
@@ -251,7 +263,7 @@
pucAllocatedMemory + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
xBufferSizeBytes,
xTriggerLevelBytes,
- xIsMessageBuffer );
+ ucFlags );
traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
}
@@ -260,7 +272,7 @@
traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
}
- return ( StreamBufferHandle_t * ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+ return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
@@ -276,6 +288,7 @@
{
StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
StreamBufferHandle_t xReturn;
+ uint8_t ucFlags;
configASSERT( pucStreamBufferStorageArea );
configASSERT( pxStaticStreamBuffer );
@@ -285,7 +298,18 @@
the buffer was empty. */
if( xTriggerLevelBytes == ( size_t ) 0 )
{
- xTriggerLevelBytes = ( size_t ) 1; /*lint !e9044 Function parameter deliberately modified to ensure it is in range. */
+ xTriggerLevelBytes = ( size_t ) 1;
+ }
+
+ if( xIsMessageBuffer != pdFALSE )
+ {
+ /* Statically allocated message buffer. */
+ ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+ }
+ else
+ {
+ /* Statically allocated stream buffer. */
+ ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
}
/* In case the stream buffer is going to be used as a message buffer
@@ -301,7 +325,7 @@
message buffer structure. */
volatile size_t xSize = sizeof( StaticStreamBuffer_t );
configASSERT( xSize == sizeof( StreamBuffer_t ) );
- }
+ } /*lint !e529 xSize is referenced is configASSERT() is defined. */
#endif /* configASSERT_DEFINED */
if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
@@ -310,7 +334,7 @@
pucStreamBufferStorageArea,
xBufferSizeBytes,
xTriggerLevelBytes,
- xIsMessageBuffer );
+ ucFlags );
/* Remember this was statically allocated in case it is ever deleted
again. */
@@ -334,7 +358,7 @@
void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
{
-StreamBuffer_t * pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
configASSERT( pxStreamBuffer );
@@ -360,15 +384,15 @@
{
/* The structure and buffer were not allocated dynamically and cannot be
freed - just scrub the structure so future use will assert. */
- memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+ ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
}
}
/*-----------------------------------------------------------*/
BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
{
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
-BaseType_t xReturn = pdFAIL, xIsMessageBuffer;
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
#if( configUSE_TRACE_FACILITY == 1 )
UBaseType_t uxStreamBufferNumber;
@@ -385,35 +409,30 @@
#endif
/* Can only reset a message buffer if there are no tasks blocked on it. */
- if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+ taskENTER_CRITICAL();
{
- if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+ if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
{
- if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+ if( pxStreamBuffer->xTaskWaitingToSend == NULL )
{
- xIsMessageBuffer = pdTRUE;
- }
- else
- {
- xIsMessageBuffer = pdFALSE;
- }
+ prvInitialiseNewStreamBuffer( pxStreamBuffer,
+ pxStreamBuffer->pucBuffer,
+ pxStreamBuffer->xLength,
+ pxStreamBuffer->xTriggerLevelBytes,
+ pxStreamBuffer->ucFlags );
+ xReturn = pdPASS;
- prvInitialiseNewStreamBuffer( pxStreamBuffer,
- pxStreamBuffer->pucBuffer,
- pxStreamBuffer->xLength,
- pxStreamBuffer->xTriggerLevelBytes,
- xIsMessageBuffer );
- xReturn = pdPASS;
+ #if( configUSE_TRACE_FACILITY == 1 )
+ {
+ pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+ }
+ #endif
- #if( configUSE_TRACE_FACILITY == 1 )
- {
- pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+ traceSTREAM_BUFFER_RESET( xStreamBuffer );
}
- #endif
-
- traceSTREAM_BUFFER_RESET( xStreamBuffer );
}
}
+ taskEXIT_CRITICAL();
return xReturn;
}
@@ -421,7 +440,7 @@
BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
{
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
BaseType_t xReturn;
configASSERT( pxStreamBuffer );
@@ -429,7 +448,7 @@
/* It is not valid for the trigger level to be 0. */
if( xTriggerLevel == ( size_t ) 0 )
{
- xTriggerLevel = ( size_t ) 1; /*lint !e9044 Parameter modified to ensure it doesn't have a dangerous value. */
+ xTriggerLevel = ( size_t ) 1;
}
/* The trigger level is the number of bytes that must be in the stream
@@ -450,7 +469,7 @@
size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
{
-const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
size_t xSpace;
configASSERT( pxStreamBuffer );
@@ -474,7 +493,7 @@
size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
{
-const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
size_t xReturn;
configASSERT( pxStreamBuffer );
@@ -489,7 +508,7 @@
size_t xDataLengthBytes,
TickType_t xTicksToWait )
{
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
size_t xReturn, xSpace = 0;
size_t xRequiredSpace = xDataLengthBytes;
TimeOut_t xTimeOut;
@@ -504,6 +523,9 @@
if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
{
xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+ /* Overflow? */
+ configASSERT( xRequiredSpace > xDataLengthBytes );
}
else
{
@@ -540,7 +562,7 @@
taskEXIT_CRITICAL();
traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
- ( void ) xTaskNotifyWait( ( uint32_t ) 0, UINT32_MAX, NULL, xTicksToWait );
+ ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
pxStreamBuffer->xTaskWaitingToSend = NULL;
} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
@@ -590,7 +612,7 @@
size_t xDataLengthBytes,
BaseType_t * const pxHigherPriorityTaskWoken )
{
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
size_t xReturn, xSpace;
size_t xRequiredSpace = xDataLengthBytes;
@@ -657,7 +679,7 @@
stream of bytes rather than discrete messages. Write as many bytes as
possible. */
xShouldWrite = pdTRUE;
- xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); /*lint !e9044 Function parameter modified to ensure it is capped to available space. */
+ xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
}
else if( xSpace >= xRequiredSpace )
{
@@ -693,7 +715,7 @@
size_t xBufferLengthBytes,
TickType_t xTicksToWait )
{
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
configASSERT( pvRxData );
@@ -746,7 +768,7 @@
{
/* Wait for data to be available. */
traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
- ( void ) xTaskNotifyWait( ( uint32_t ) 0, UINT32_MAX, NULL, xTicksToWait );
+ ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
pxStreamBuffer->xTaskWaitingToReceive = NULL;
/* Recheck the data available after blocking. */
@@ -792,12 +814,56 @@
}
/*-----------------------------------------------------------*/
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+ configASSERT( pxStreamBuffer );
+
+ /* Ensure the stream buffer is being used as a message buffer. */
+ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+ {
+ xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+ if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+ {
+ /* The number of bytes available is greater than the number of bytes
+ required to hold the length of the next message, so another message
+ is available. Return its length without removing the length bytes
+ from the buffer. A copy of the tail is stored so the buffer can be
+ returned to its prior state as the message is not actually being
+ removed from the buffer. */
+ xOriginalTail = pxStreamBuffer->xTail;
+ ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+ xReturn = ( size_t ) xTempReturn;
+ pxStreamBuffer->xTail = xOriginalTail;
+ }
+ else
+ {
+ /* The minimum amount of bytes in a message buffer is
+ ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+ less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+ value is 0. */
+ configASSERT( xBytesAvailable == 0 );
+ xReturn = 0;
+ }
+ }
+ else
+ {
+ xReturn = 0;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
void *pvRxData,
size_t xBufferLengthBytes,
BaseType_t * const pxHigherPriorityTaskWoken )
{
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
configASSERT( pvRxData );
@@ -856,6 +922,7 @@
size_t xBytesToStoreMessageLength )
{
size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
if( xBytesToStoreMessageLength != ( size_t ) 0 )
{
@@ -864,7 +931,8 @@
returned to its prior state if the length of the message is too
large for the provided buffer. */
xOriginalTail = pxStreamBuffer->xTail;
- ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+ ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+ xNextMessageLength = ( size_t ) xTempNextMessageLength;
/* Reduce the number of bytes available by the number of bytes just
read out. */
@@ -901,7 +969,7 @@
BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
{
-const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
BaseType_t xReturn;
size_t xTail;
@@ -926,7 +994,7 @@
{
BaseType_t xReturn;
size_t xBytesToStoreMessageLength;
-const StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
configASSERT( pxStreamBuffer );
@@ -959,7 +1027,7 @@
BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
{
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
@@ -989,7 +1057,7 @@
BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
{
-StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) xStreamBuffer; /*lint !e9087 !e9079 Safe cast as StreamBufferHandle_t is opaque Streambuffer_t. */
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
@@ -1032,7 +1100,7 @@
/* Write as many bytes as can be written in the first write. */
configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
- memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+ ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
/* If the number of bytes written was less than the number that could be
written in the first write... */
@@ -1040,7 +1108,7 @@
{
/* ...then write the remaining bytes to the start of the buffer. */
configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
- memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+ ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
}
else
{
@@ -1083,7 +1151,7 @@
read. Asserts check bounds of read and write. */
configASSERT( xFirstLength <= xMaxCount );
configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
- memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+ ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
/* If the total number of wanted bytes is greater than the number
that could be read in the first read... */
@@ -1091,7 +1159,7 @@
{
/*...then read the remaining bytes from the start of the buffer. */
configASSERT( xCount <= xMaxCount );
- memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+ ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
}
else
{
@@ -1142,7 +1210,7 @@
uint8_t * const pucBuffer,
size_t xBufferSizeBytes,
size_t xTriggerLevelBytes,
- BaseType_t xIsMessageBuffer )
+ uint8_t ucFlags )
{
/* Assert here is deliberately writing to the entire buffer to ensure it can
be written to without generating exceptions, and is setting the buffer to a
@@ -1154,25 +1222,21 @@
result in confusion as to what is actually being observed. */
const BaseType_t xWriteValue = 0x55;
configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
- }
+ } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
#endif
- memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+ ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
pxStreamBuffer->pucBuffer = pucBuffer;
pxStreamBuffer->xLength = xBufferSizeBytes;
pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
-
- if( xIsMessageBuffer != pdFALSE )
- {
- pxStreamBuffer->ucFlags |= sbFLAGS_IS_MESSAGE_BUFFER;
- }
+ pxStreamBuffer->ucFlags = ucFlags;
}
#if ( configUSE_TRACE_FACILITY == 1 )
UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
{
- return ( ( StreamBuffer_t * ) xStreamBuffer )->uxStreamBufferNumber;
+ return xStreamBuffer->uxStreamBufferNumber;
}
#endif /* configUSE_TRACE_FACILITY */
@@ -1182,7 +1246,7 @@
void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
{
- ( ( StreamBuffer_t * ) xStreamBuffer )->uxStreamBufferNumber = uxStreamBufferNumber;
+ xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
}
#endif /* configUSE_TRACE_FACILITY */
@@ -1192,7 +1256,7 @@
uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
{
- return ( ( StreamBuffer_t * )xStreamBuffer )->ucFlags | sbFLAGS_IS_MESSAGE_BUFFER;
+ return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
}
#endif /* configUSE_TRACE_FACILITY */
diff --git a/Source/tasks.c b/Source/tasks.c
index e41d9d1..db0516d 100644
--- a/Source/tasks.c
+++ b/Source/tasks.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -40,11 +40,11 @@
#include "timers.h"
#include "stack_macros.h"
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
functions but without including stdio.h here. */
@@ -75,24 +75,7 @@
*/
#define tskSTACK_FILL_BYTE ( 0xa5U )
-/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
-dynamically allocated RAM, in which case when any task is deleted it is known
-that both the task's stack and TCB need to be freed. Sometimes the
-FreeRTOSConfig.h settings only allow a task to be created using statically
-allocated RAM, in which case when any task is deleted it is known that neither
-the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h
-settings allow a task to be created using either statically or dynamically
-allocated RAM, in which case a member of the TCB is used to record whether the
-stack and/or TCB were allocated statically or dynamically, so when a task is
-deleted the RAM that was allocated dynamically is freed again and no attempt is
-made to free the RAM that was allocated statically.
-tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
-task to be created using either statically or dynamically allocated RAM. Note
-that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
-a statically allocated stack and a dynamically allocated TCB.
-!!!NOTE!!! If the definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is
-changed then the definition of StaticTask_t must also be updated. */
-#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+/* Bits used to recored how a task's stack and TCB were allocated. */
#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 0 )
#define tskSTATICALLY_ALLOCATED_STACK_ONLY ( ( uint8_t ) 1 )
#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 2 )
@@ -100,7 +83,7 @@
/* If any of the following are set then task stacks are filled with a known
value so the high water mark can be determined. If none of the following are
set then don't fill the stack so there is no unnecessary dependency on memset. */
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
#define tskSET_NEW_STACKS_TO_KNOWN_VALUE 1
#else
#define tskSET_NEW_STACKS_TO_KNOWN_VALUE 0
@@ -245,7 +228,7 @@
* task should be used in place of the parameter. This macro simply checks to
* see if the parameter is NULL and returns a pointer to the appropriate TCB.
*/
-#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) )
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
/* The item value of the event list item is normally used to hold the priority
of the task to which it belongs (coded to allow it to be held in reverse
@@ -266,7 +249,7 @@
* and stores task state information, including a pointer to the task's context
* (the task's run time environment, including register values)
*/
-typedef struct tskTaskControlBlock
+typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */
{
volatile StackType_t *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
@@ -326,9 +309,9 @@
volatile uint8_t ucNotifyState;
#endif
- /* See the comments above the definition of
+ /* See the comments in FreeRTOS.h with the definition of
tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
- #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+ #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
#endif
@@ -336,6 +319,10 @@
uint8_t ucDelayAborted;
#endif
+ #if( configUSE_POSIX_ERRNO == 1 )
+ int iTaskErrno;
+ #endif
+
} tskTCB;
/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
@@ -344,30 +331,38 @@
/*lint -save -e956 A manual analysis and inspection has been used to determine
which static variables must be declared volatile. */
-
PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
-/* Lists for ready and blocked tasks. --------------------*/
-PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ] = {0}; /*< Prioritised ready tasks. */
-PRIVILEGED_DATA static List_t xDelayedTaskList1 = {0}; /*< Delayed tasks. */
-PRIVILEGED_DATA static List_t xDelayedTaskList2 = {0}; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
-PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList = NULL; /*< Points to the delayed task list currently being used. */
-PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList = NULL; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
-PRIVILEGED_DATA static List_t xPendingReadyList = {0}; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ] = { 0 };/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1 = { 0 }; /*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2 = { 0 }; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList = NULL; /*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList = NULL; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList = { 0 }; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */
#if( INCLUDE_vTaskDelete == 1 )
- PRIVILEGED_DATA static List_t xTasksWaitingTermination = {0}; /*< Tasks that have been deleted - but their memory not yet freed. */
+PRIVILEGED_DATA static List_t xTasksWaitingTermination = { 0 }; /*< Tasks that have been deleted - but their memory not yet freed. */
PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
- PRIVILEGED_DATA static List_t xSuspendedTaskList = {0}; /*< Tasks that are currently suspended. */
+ PRIVILEGED_DATA static List_t xSuspendedTaskList = { 0 }; /*< Tasks that are currently suspended. */
#endif
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+ int FreeRTOS_errno = 0;
+#endif
+
/* Other file private variables. --------------------------------*/
PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;
PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
@@ -392,6 +387,8 @@
#if ( configGENERATE_RUN_TIME_STATS == 1 )
+ /* Do not move these variables to function scope as doing so prevents the
+ code working with debuggers that need to remove the static qualifier. */
PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */
PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */
@@ -403,15 +400,21 @@
/* Callback function prototypes. --------------------------*/
#if( configCHECK_FOR_STACK_OVERFLOW > 0 )
+
extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
#endif
#if( configUSE_TICK_HOOK > 0 )
- extern void vApplicationTickHook( void );
+
+ extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
#endif
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
- extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
+
+ extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
#endif
/* File private functions. --------------------------------*/
@@ -501,9 +504,9 @@
* This function determines the 'high water mark' of the task stack by
* determining how much of the stack remains at the original preset value.
*/
-#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
- static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+ static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
#endif
@@ -593,6 +596,7 @@
structure. */
volatile size_t xSize = sizeof( StaticTask_t );
configASSERT( xSize == sizeof( TCB_t ) );
+ ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
}
#endif /* configASSERT_DEFINED */
@@ -601,16 +605,16 @@
{
/* The memory used for the task's TCB and stack are passed into this
function - use them. */
- pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
- #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+ #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created statically in case the task is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
}
- #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
prvAddNewTaskToReadyList( pxNewTCB );
@@ -652,7 +656,7 @@
task was created statically in case the task is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
}
- #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
pxTaskDefinition->pcName,
@@ -693,14 +697,14 @@
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+ #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
{
/* Tasks can be created statically or dynamically, so note
this task had a statically allocated stack in case it is
later deleted. The TCB was allocated dynamically. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
}
- #endif
+ #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
pxTaskDefinition->pcName,
@@ -763,12 +767,12 @@
StackType_t *pxStack;
/* Allocate space for the stack used by the task being created. */
- pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
if( pxStack != NULL )
{
/* Allocate space for the TCB. */
- pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e961 MISRA exception as the casts are only redundant for some paths. */
+ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
if( pxNewTCB != NULL )
{
@@ -791,13 +795,13 @@
if( pxNewTCB != NULL )
{
- #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+ #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created dynamically in case it is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
}
- #endif /* configSUPPORT_STATIC_ALLOCATION */
+ #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
prvAddNewTaskToReadyList( pxNewTCB );
@@ -854,8 +858,8 @@
by the port. */
#if( portSTACK_GROWTH < 0 )
{
- pxTopOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
- pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. */
+ pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+ pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
/* Check the alignment of the calculated top of stack is correct. */
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
@@ -882,26 +886,35 @@
#endif /* portSTACK_GROWTH */
/* Store the task name in the TCB. */
- for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+ if( pcName != NULL )
{
- pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+ for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+ {
+ pxNewTCB->pcTaskName[ x ] = pcName[ x ];
- /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
- configMAX_TASK_NAME_LEN characters just in case the memory after the
- string is not accessible (extremely unlikely). */
- if( pcName[ x ] == 0x00 )
- {
- break;
+ /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+ configMAX_TASK_NAME_LEN characters just in case the memory after the
+ string is not accessible (extremely unlikely). */
+ if( pcName[ x ] == ( char ) 0x00 )
+ {
+ break;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
}
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
+
+ /* Ensure the name string is terminated in the case that the string length
+ was greater or equal to configMAX_TASK_NAME_LEN. */
+ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
}
-
- /* Ensure the name string is terminated in the case that the string length
- was greater or equal to configMAX_TASK_NAME_LEN. */
- pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+ else
+ {
+ /* The task has not been given a name, so just ensure there is a NULL
+ terminator when it is read out. */
+ pxNewTCB->pcTaskName[ 0 ] = 0x00;
+ }
/* This is used as an array index so must ensure it's not too large. First
remove the privilege bit if one is present. */
@@ -997,15 +1010,53 @@
the top of stack variable is updated. */
#if( portUSING_MPU_WRAPPERS == 1 )
{
- pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+ /* If the port has capability to detect stack overflow,
+ pass the stack end address to the stack initialization
+ function as well. */
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+ {
+ #if( portSTACK_GROWTH < 0 )
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+ }
+ #else /* portSTACK_GROWTH */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+ }
+ #endif /* portSTACK_GROWTH */
+ }
+ #else /* portHAS_STACK_OVERFLOW_CHECKING */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+ }
+ #endif /* portHAS_STACK_OVERFLOW_CHECKING */
}
#else /* portUSING_MPU_WRAPPERS */
{
- pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+ /* If the port has capability to detect stack overflow,
+ pass the stack end address to the stack initialization
+ function as well. */
+ #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+ {
+ #if( portSTACK_GROWTH < 0 )
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+ }
+ #else /* portSTACK_GROWTH */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+ }
+ #endif /* portSTACK_GROWTH */
+ }
+ #else /* portHAS_STACK_OVERFLOW_CHECKING */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+ }
+ #endif /* portHAS_STACK_OVERFLOW_CHECKING */
}
#endif /* portUSING_MPU_WRAPPERS */
- if( ( void * ) pxCreatedTask != NULL )
+ if( pxCreatedTask != NULL )
{
/* Pass the handle out in an anonymous way. The handle can be used to
change the created task's priority, delete the created task, etc.*/
@@ -1322,13 +1373,13 @@
#endif /* INCLUDE_vTaskDelay */
/*-----------------------------------------------------------*/
-#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) )
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
eTaskState eTaskGetState( TaskHandle_t xTask )
{
eTaskState eReturn;
- List_t *pxStateList;
- const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+ List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+ const TCB_t * const pxTCB = xTask;
configASSERT( pxTCB );
@@ -1341,11 +1392,13 @@
{
taskENTER_CRITICAL();
{
- pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+ pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+ pxDelayedList = pxDelayedTaskList;
+ pxOverflowedDelayedList = pxOverflowDelayedTaskList;
}
taskEXIT_CRITICAL();
- if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )
+ if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
{
/* The task being queried is referenced from one of the Blocked
lists. */
@@ -1356,11 +1409,30 @@
else if( pxStateList == &xSuspendedTaskList )
{
/* The task being queried is referenced from the suspended
- list. Is it genuinely suspended or is it block
+ list. Is it genuinely suspended or is it blocked
indefinitely? */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
{
- eReturn = eSuspended;
+ #if( configUSE_TASK_NOTIFICATIONS == 1 )
+ {
+ /* The task does not appear on the event list item of
+ and of the RTOS objects, but could still be in the
+ blocked state if it is waiting on its notification
+ rather than waiting on an object. */
+ if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+ {
+ eReturn = eBlocked;
+ }
+ else
+ {
+ eReturn = eSuspended;
+ }
+ }
+ #else
+ {
+ eReturn = eSuspended;
+ }
+ #endif
}
else
{
@@ -1395,15 +1467,15 @@
#if ( INCLUDE_uxTaskPriorityGet == 1 )
- UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )
+ UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
{
- TCB_t *pxTCB;
+ TCB_t const *pxTCB;
UBaseType_t uxReturn;
taskENTER_CRITICAL();
{
- /* If null is passed in here then it is the priority of the that
- called uxTaskPriorityGet() that is being queried. */
+ /* If null is passed in here then it is the priority of the task
+ that called uxTaskPriorityGet() that is being queried. */
pxTCB = prvGetTCBFromHandle( xTask );
uxReturn = pxTCB->uxPriority;
}
@@ -1417,9 +1489,9 @@
#if ( INCLUDE_uxTaskPriorityGet == 1 )
- UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask )
+ UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
{
- TCB_t *pxTCB;
+ TCB_t const *pxTCB;
UBaseType_t uxReturn, uxSavedInterruptState;
/* RTOS ports that support interrupt nesting have the concept of a
@@ -1437,7 +1509,7 @@
separate interrupt safe API to ensure interrupt entry is as fast and as
simple as possible. More information (albeit Cortex-M specific) is
provided on the following link:
- http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ https://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
@@ -1697,7 +1769,7 @@
/* The scheduler is not running, but the task that was pointed
to by pxCurrentTCB has just been suspended and pxCurrentTCB
must be adjusted to point to a different task. */
- if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
+ if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
{
/* No other tasks are ready, so set pxCurrentTCB back to
NULL so when the next task is created pxCurrentTCB will
@@ -1725,7 +1797,7 @@
static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
{
BaseType_t xReturn = pdFALSE;
- const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+ const TCB_t * const pxTCB = xTask;
/* Accesses xPendingReadyList so must be called from a critical
section. */
@@ -1770,14 +1842,14 @@
void vTaskResume( TaskHandle_t xTaskToResume )
{
- TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+ TCB_t * const pxTCB = xTaskToResume;
/* It does not make sense to resume the calling task. */
configASSERT( xTaskToResume );
/* The parameter cannot be NULL as it is impossible to resume the
currently executing task. */
- if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )
+ if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
{
taskENTER_CRITICAL();
{
@@ -1825,7 +1897,7 @@
BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
{
BaseType_t xYieldRequired = pdFALSE;
- TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+ TCB_t * const pxTCB = xTaskToResume;
UBaseType_t uxSavedInterruptStatus;
configASSERT( xTaskToResume );
@@ -1845,7 +1917,7 @@
separate interrupt safe API to ensure interrupt entry is as fast and as
simple as possible. More information (albeit Cortex-M specific) is
provided on the following link:
- http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ https://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
@@ -1910,7 +1982,7 @@
configIDLE_TASK_NAME,
ulIdleTaskStackSize,
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
- ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
pxIdleTaskStackBuffer,
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
@@ -1930,7 +2002,7 @@
configIDLE_TASK_NAME,
configMINIMAL_STACK_SIZE,
( void * ) NULL,
- ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
@@ -1976,7 +2048,7 @@
xNextTaskUnblockTime = portMAX_DELAY;
xSchedulerRunning = pdTRUE;
- xTickCount = ( TickType_t ) 0U;
+ xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
/* If configGENERATE_RUN_TIME_STATS is defined then the following
macro must be defined to configure the timer/counter used to generate
@@ -1986,6 +2058,8 @@
FreeRTOSConfig.h file. */
portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+ traceTASK_SWITCHED_IN();
+
/* Setting up the timer tick is hardware specific and thus in the
portable interface. */
if( xPortStartScheduler() != pdFALSE )
@@ -2030,6 +2104,7 @@
post in the FreeRTOS support forum before reporting this as a bug! -
http://goo.gl/wu4acr */
++uxSchedulerSuspended;
+ portMEMORY_BARRIER();
}
/*----------------------------------------------------------*/
@@ -2122,7 +2197,7 @@
appropriate ready list. */
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
{
- pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
+ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
prvAddTaskToReadyList( pxTCB );
@@ -2239,7 +2314,7 @@
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
- link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
@@ -2279,19 +2354,21 @@
TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
UBaseType_t x;
char cNextChar;
+ BaseType_t xBreakLoop;
/* This function is called with the scheduler suspended. */
if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
{
- listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+ listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
do
{
- listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+ listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
/* Check each character in the name looking for a match or
mismatch. */
+ xBreakLoop = pdFALSE;
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
{
cNextChar = pxNextTCB->pcTaskName[ x ];
@@ -2299,19 +2376,24 @@
if( cNextChar != pcNameToQuery[ x ] )
{
/* Characters didn't match. */
- break;
+ xBreakLoop = pdTRUE;
}
- else if( cNextChar == 0x00 )
+ else if( cNextChar == ( char ) 0x00 )
{
/* Both strings terminated, a match must have been
found. */
pxReturn = pxNextTCB;
- break;
+ xBreakLoop = pdTRUE;
}
else
{
mtCOVERAGE_TEST_MARKER();
}
+
+ if( xBreakLoop != pdFALSE )
+ {
+ break;
+ }
}
if( pxReturn != NULL )
@@ -2392,7 +2474,7 @@
}
( void ) xTaskResumeAll();
- return ( TaskHandle_t ) pxTCB;
+ return pxTCB;
}
#endif /* INCLUDE_xTaskGetHandle */
@@ -2508,7 +2590,7 @@
BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
{
- TCB_t *pxTCB = ( TCB_t * ) xTask;
+ TCB_t *pxTCB = xTask;
BaseType_t xReturn;
configASSERT( pxTCB );
@@ -2633,7 +2715,7 @@
item at the head of the delayed list. This is the time
at which the task at the head of the delayed list must
be removed from the Blocked state. */
- pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
if( xConstTickCount < xItemValue )
@@ -2644,7 +2726,7 @@
state - so record the item value in
xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
- break;
+ break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
}
else
{
@@ -2766,13 +2848,15 @@
}
else
{
- xTCB = ( TCB_t * ) xTask;
+ xTCB = xTask;
}
/* Save the hook function in the TCB. A critical section is required as
the value can be accessed from an interrupt. */
taskENTER_CRITICAL();
+ {
xTCB->pxTaskTag = pxHookFunction;
+ }
taskEXIT_CRITICAL();
}
@@ -2783,24 +2867,17 @@
TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
{
- TCB_t *xTCB;
+ TCB_t *pxTCB;
TaskHookFunction_t xReturn;
- /* If xTask is NULL then we are setting our own task hook. */
- if( xTask == NULL )
- {
- xTCB = ( TCB_t * ) pxCurrentTCB;
- }
- else
- {
- xTCB = ( TCB_t * ) xTask;
- }
+ /* If xTask is NULL then set the calling task's hook. */
+ pxTCB = prvGetTCBFromHandle( xTask );
/* Save the hook function in the TCB. A critical section is required as
the value can be accessed from an interrupt. */
taskENTER_CRITICAL();
{
- xReturn = xTCB->pxTaskTag;
+ xReturn = pxTCB->pxTaskTag;
}
taskEXIT_CRITICAL();
@@ -2812,6 +2889,31 @@
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+ {
+ TCB_t *pxTCB;
+ TaskHookFunction_t xReturn;
+ UBaseType_t uxSavedInterruptStatus;
+
+ /* If xTask is NULL then set the calling task's hook. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+
+ /* Save the hook function in the TCB. A critical section is required as
+ the value can be accessed from an interrupt. */
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ xReturn = pxTCB->pxTaskTag;
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+ }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
{
TCB_t *xTCB;
@@ -2820,11 +2922,11 @@
/* If xTask is NULL then we are calling our own task hook. */
if( xTask == NULL )
{
- xTCB = ( TCB_t * ) pxCurrentTCB;
+ xTCB = pxCurrentTCB;
}
else
{
- xTCB = ( TCB_t * ) xTask;
+ xTCB = xTask;
}
if( xTCB->pxTaskTag != NULL )
@@ -2857,39 +2959,53 @@
#if ( configGENERATE_RUN_TIME_STATS == 1 )
{
- #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
- portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
- #else
- ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
- #endif
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+ #else
+ ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
- /* Add the amount of time the task has been running to the
- accumulated time so far. The time the task started running was
- stored in ulTaskSwitchedInTime. Note that there is no overflow
- protection here so count values are only valid until the timer
- overflows. The guard against negative values is to protect
- against suspect run time stat counter implementations - which
- are provided by the application, not the kernel. */
- if( ulTotalRunTime > ulTaskSwitchedInTime )
- {
- pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
- }
- else
- {
- mtCOVERAGE_TEST_MARKER();
- }
- ulTaskSwitchedInTime = ulTotalRunTime;
+ /* Add the amount of time the task has been running to the
+ accumulated time so far. The time the task started running was
+ stored in ulTaskSwitchedInTime. Note that there is no overflow
+ protection here so count values are only valid until the timer
+ overflows. The guard against negative values is to protect
+ against suspect run time stat counter implementations - which
+ are provided by the application, not the kernel. */
+ if( ulTotalRunTime > ulTaskSwitchedInTime )
+ {
+ pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ ulTaskSwitchedInTime = ulTotalRunTime;
}
#endif /* configGENERATE_RUN_TIME_STATS */
/* Check for stack overflow, if configured. */
taskCHECK_FOR_STACK_OVERFLOW();
+ /* Before the currently running task is switched out, save its errno. */
+ #if( configUSE_POSIX_ERRNO == 1 )
+ {
+ pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+ }
+ #endif
+
/* Select a new task to run using either the generic C or port
optimised asm code. */
- taskSELECT_HIGHEST_PRIORITY_TASK();
+ taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
traceTASK_SWITCHED_IN();
+ /* After the new task is switched in, update the global errno. */
+ #if( configUSE_POSIX_ERRNO == 1 )
+ {
+ FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+ }
+ #endif
+
#if ( configUSE_NEWLIB_REENTRANT == 1 )
{
/* Switch Newlib's _impure_ptr variable to point to the _reent
@@ -2993,7 +3109,7 @@
This function assumes that a check has already been made to ensure that
pxEventList is not empty. */
- pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
configASSERT( pxUnblockedTCB );
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
@@ -3001,6 +3117,20 @@
{
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
prvAddTaskToReadyList( pxUnblockedTCB );
+
+ #if( configUSE_TICKLESS_IDLE != 0 )
+ {
+ /* If a task is blocked on a kernel object then xNextTaskUnblockTime
+ might be set to the blocked task's time out time. If the task is
+ unblocked for a reason other than a timeout xNextTaskUnblockTime is
+ normally left unchanged, because it is automatically reset to a new
+ value when the tick count equals xNextTaskUnblockTime. However if
+ tickless idling is used it might be more important to enter sleep mode
+ at the earliest possible time - so reset xNextTaskUnblockTime here to
+ ensure it is updated at the earliest possible time. */
+ prvResetNextTaskUnblockTime();
+ }
+ #endif
}
else
{
@@ -3025,20 +3155,6 @@
xReturn = pdFALSE;
}
- #if( configUSE_TICKLESS_IDLE != 0 )
- {
- /* If a task is blocked on a kernel object then xNextTaskUnblockTime
- might be set to the blocked task's time out time. If the task is
- unblocked for a reason other than a timeout xNextTaskUnblockTime is
- normally left unchanged, because it is automatically reset to a new
- value when the tick count equals xNextTaskUnblockTime. However if
- tickless idling is used it might be more important to enter sleep mode
- at the earliest possible time - so reset xNextTaskUnblockTime here to
- ensure it is updated at the earliest possible time. */
- prvResetNextTaskUnblockTime();
- }
- #endif
-
return xReturn;
}
/*-----------------------------------------------------------*/
@@ -3056,7 +3172,7 @@
/* Remove the event list form the event flag. Interrupts do not access
event flags. */
- pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );
+ pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
configASSERT( pxUnblockedTCB );
( void ) uxListRemove( pxEventListItem );
@@ -3111,7 +3227,7 @@
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
#if( INCLUDE_xTaskAbortDelay == 1 )
- if( pxCurrentTCB->ucDelayAborted != pdFALSE )
+ if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
{
/* The delay was aborted, which is not the same as a time out,
but has the same result. */
@@ -3171,11 +3287,11 @@
UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
{
UBaseType_t uxReturn;
- TCB_t *pxTCB;
+ TCB_t const *pxTCB;
if( xTask != NULL )
{
- pxTCB = ( TCB_t * ) xTask;
+ pxTCB = xTask;
uxReturn = pxTCB->uxTaskNumber;
}
else
@@ -3193,11 +3309,11 @@
void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
{
- TCB_t *pxTCB;
+ TCB_t * pxTCB;
if( xTask != NULL )
{
- pxTCB = ( TCB_t * ) xTask;
+ pxTCB = xTask;
pxTCB->uxTaskNumber = uxHandle;
}
}
@@ -3226,7 +3342,7 @@
/* In case a task that has a secure context deletes itself, in which case
the idle task is responsible for deleting the task's secure context, if
any. */
- portTASK_CALLS_SECURE_FUNCTIONS();
+ portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
for( ;; )
{
@@ -3468,13 +3584,13 @@
{
TCB_t *pxTCB;
- /* uxDeletedTasksWaitingCleanUp is used to prevent vTaskSuspendAll()
+ /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
being called too often in the idle task. */
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
{
taskENTER_CRITICAL();
{
- pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
+ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
--uxCurrentNumberOfTasks;
--uxDeletedTasksWaitingCleanUp;
@@ -3593,7 +3709,7 @@
if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
{
- listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+ listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
/* Populate an TaskStatus_t structure within the
pxTaskStatusArray array for each task that is referenced from
@@ -3601,7 +3717,7 @@
meaning of each TaskStatus_t structure member. */
do
{
- listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+ listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
uxTask++;
} while( pxNextTCB != pxFirstTCB );
@@ -3617,9 +3733,9 @@
#endif /* configUSE_TRACE_FACILITY */
/*-----------------------------------------------------------*/
-#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
- static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+ static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
{
uint32_t ulCount = 0U;
@@ -3631,10 +3747,50 @@
ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
- return ( uint16_t ) ulCount;
+ return ( configSTACK_DEPTH_TYPE ) ulCount;
}
-#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+ /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ same except for their return type. Using configSTACK_DEPTH_TYPE allows the
+ user to determine the return type. It gets around the problem of the value
+ overflowing on 8-bit types without breaking backward compatibility for
+ applications that expect an 8-bit return type. */
+ configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+ {
+ TCB_t *pxTCB;
+ uint8_t *pucEndOfStack;
+ configSTACK_DEPTH_TYPE uxReturn;
+
+ /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+ the same except for their return type. Using configSTACK_DEPTH_TYPE
+ allows the user to determine the return type. It gets around the
+ problem of the value overflowing on 8-bit types without breaking
+ backward compatibility for applications that expect an 8-bit return
+ type. */
+
+ pxTCB = prvGetTCBFromHandle( xTask );
+
+ #if portSTACK_GROWTH < 0
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+ }
+ #else
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+ }
+ #endif
+
+ uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+ return uxReturn;
+ }
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
/*-----------------------------------------------------------*/
#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
@@ -3689,7 +3845,7 @@
vPortFree( pxTCB->pxStack );
vPortFree( pxTCB );
}
- #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 Macro has been consolidated for readability reasons. */
+ #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* The task could have been allocated statically or dynamically, so
check what was statically allocated before trying to free the
@@ -3739,7 +3895,7 @@
the item at the head of the delayed list. This is the time at
which the task at the head of the delayed list should be removed
from the Blocked state. */
- ( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
}
}
@@ -3794,7 +3950,7 @@
BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
{
- TCB_t * const pxMutexHolderTCB = ( TCB_t * ) pxMutexHolder;
+ TCB_t * const pxMutexHolderTCB = pxMutexHolder;
BaseType_t xReturn = pdFALSE;
/* If the mutex was given back by an interrupt while the queue was
@@ -3881,7 +4037,7 @@
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
{
- TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+ TCB_t * const pxTCB = pxMutexHolder;
BaseType_t xReturn = pdFALSE;
if( pxMutexHolder != NULL )
@@ -3961,7 +4117,7 @@
void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
{
- TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+ TCB_t * const pxTCB = pxMutexHolder;
UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
@@ -4139,7 +4295,7 @@
}
/* Terminate. */
- pcBuffer[ x ] = 0x00;
+ pcBuffer[ x ] = ( char ) 0x00;
/* Return the new end of string. */
return &( pcBuffer[ x ] );
@@ -4153,7 +4309,7 @@
void vTaskList( char * pcWriteBuffer )
{
TaskStatus_t *pxTaskStatusArray;
- volatile UBaseType_t uxArraySize, x;
+ UBaseType_t uxArraySize, x;
char cStatus;
/*
@@ -4182,7 +4338,7 @@
/* Make sure the write buffer does not contain a string. */
- *pcWriteBuffer = 0x00;
+ *pcWriteBuffer = ( char ) 0x00;
/* Take a snapshot of the number of tasks in case it changes while this
function is executing. */
@@ -4191,7 +4347,7 @@
/* Allocate an array index for each task. NOTE! if
configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
equate to NULL. */
- pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+ pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
if( pxTaskStatusArray != NULL )
{
@@ -4218,9 +4374,10 @@
case eDeleted: cStatus = tskDELETED_CHAR;
break;
+ case eInvalid: /* Fall through. */
default: /* Should not get here, but it is included
to prevent static checking errors. */
- cStatus = 0x00;
+ cStatus = ( char ) 0x00;
break;
}
@@ -4229,8 +4386,8 @@
pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
/* Write the rest of the string. */
- sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
- pcWriteBuffer += strlen( pcWriteBuffer );
+ sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+ pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
}
/* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION
@@ -4251,7 +4408,7 @@
void vTaskGetRunTimeStats( char *pcWriteBuffer )
{
TaskStatus_t *pxTaskStatusArray;
- volatile UBaseType_t uxArraySize, x;
+ UBaseType_t uxArraySize, x;
uint32_t ulTotalTime, ulStatsAsPercentage;
#if( configUSE_TRACE_FACILITY != 1 )
@@ -4286,7 +4443,7 @@
*/
/* Make sure the write buffer does not contain a string. */
- *pcWriteBuffer = 0x00;
+ *pcWriteBuffer = ( char ) 0x00;
/* Take a snapshot of the number of tasks in case it changes while this
function is executing. */
@@ -4295,7 +4452,7 @@
/* Allocate an array index for each task. NOTE! If
configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
equate to NULL. */
- pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+ pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
if( pxTaskStatusArray != NULL )
{
@@ -4306,7 +4463,7 @@
ulTotalTime /= 100UL;
/* Avoid divide by zero errors. */
- if( ulTotalTime > 0 )
+ if( ulTotalTime > 0UL )
{
/* Create a human readable table from the binary data. */
for( x = 0; x < uxArraySize; x++ )
@@ -4331,7 +4488,7 @@
{
/* sizeof( int ) == sizeof( long ) so a smaller
printf() library can be used. */
- sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );
+ sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
}
#endif
}
@@ -4347,12 +4504,12 @@
{
/* sizeof( int ) == sizeof( long ) so a smaller
printf() library can be used. */
- sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
+ sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
}
#endif
}
- pcWriteBuffer += strlen( pcWriteBuffer );
+ pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
}
}
else
@@ -4389,7 +4546,7 @@
#if ( configUSE_MUTEXES == 1 )
- void *pvTaskIncrementMutexHeldCount( void )
+ TaskHandle_t pvTaskIncrementMutexHeldCount( void )
{
/* If xSemaphoreCreateMutex() is called before any tasks have been created
then pxCurrentTCB will be NULL. */
@@ -4561,7 +4718,7 @@
uint8_t ucOriginalNotifyState;
configASSERT( xTaskToNotify );
- pxTCB = ( TCB_t * ) xTaskToNotify;
+ pxTCB = xTaskToNotify;
taskENTER_CRITICAL();
{
@@ -4604,6 +4761,14 @@
/* The task is being notified without its notify value being
updated. */
break;
+
+ default:
+ /* Should not get here if all enums are handled.
+ Artificially force an assert by testing a value the
+ compiler can't assume is const. */
+ configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+ break;
}
traceTASK_NOTIFY();
@@ -4687,7 +4852,7 @@
http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
- pxTCB = ( TCB_t * ) xTaskToNotify;
+ pxTCB = xTaskToNotify;
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
@@ -4729,6 +4894,13 @@
/* The task is being notified without its notify value being
updated. */
break;
+
+ default:
+ /* Should not get here if all enums are handled.
+ Artificially force an assert by testing a value the
+ compiler can't assume is const. */
+ configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+ break;
}
traceTASK_NOTIFY_FROM_ISR();
@@ -4760,13 +4932,11 @@
{
*pxHigherPriorityTaskWoken = pdTRUE;
}
- else
- {
- /* Mark that a yield is pending in case the user is not
- using the "xHigherPriorityTaskWoken" parameter to an ISR
- safe FreeRTOS function. */
- xYieldPending = pdTRUE;
- }
+
+ /* Mark that a yield is pending in case the user is not
+ using the "xHigherPriorityTaskWoken" parameter to an ISR
+ safe FreeRTOS function. */
+ xYieldPending = pdTRUE;
}
else
{
@@ -4810,7 +4980,7 @@
http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
- pxTCB = ( TCB_t * ) xTaskToNotify;
+ pxTCB = xTaskToNotify;
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
@@ -4850,13 +5020,11 @@
{
*pxHigherPriorityTaskWoken = pdTRUE;
}
- else
- {
- /* Mark that a yield is pending in case the user is not
- using the "xHigherPriorityTaskWoken" parameter in an ISR
- safe FreeRTOS function. */
- xYieldPending = pdTRUE;
- }
+
+ /* Mark that a yield is pending in case the user is not
+ using the "xHigherPriorityTaskWoken" parameter in an ISR
+ safe FreeRTOS function. */
+ xYieldPending = pdTRUE;
}
else
{
@@ -4902,6 +5070,13 @@
#endif /* configUSE_TASK_NOTIFICATIONS */
/*-----------------------------------------------------------*/
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+ TickType_t xTaskGetIdleRunTimeCounter( void )
+ {
+ return xIdleTaskHandle->ulRunTimeCounter;
+ }
+#endif
+/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
@@ -4923,7 +5098,7 @@
{
/* The current task must be in a ready list, so there is no need to
check, and the port reset macro can be called directly. */
- portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+ portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
}
else
{
@@ -5027,12 +5202,12 @@
#include "freertos_tasks_c_additions.h"
- static void freertos_tasks_c_additions_init( void )
- {
- #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+ #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+ static void freertos_tasks_c_additions_init( void )
+ {
FREERTOS_TASKS_C_ADDITIONS_INIT();
- #endif
- }
+ }
+ #endif
#endif
diff --git a/Source/timers.c b/Source/timers.c
index 002dd8b..59b3840 100644
--- a/Source/timers.c
+++ b/Source/timers.c
@@ -1,6 +1,6 @@
/*
- * FreeRTOS Kernel V10.0.1
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
@@ -42,11 +42,11 @@
#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
#endif
-/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
-MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
-header files above, but not in this file, in order to generate the correct
-privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
/* This entire source file will be skipped if the application is not configured
@@ -64,22 +64,23 @@
#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
#endif
+/* Bit definitions used in the ucStatus member of a timer structure. */
+#define tmrSTATUS_IS_ACTIVE ( ( uint8_t ) 0x01 )
+#define tmrSTATUS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 0x02 )
+#define tmrSTATUS_IS_AUTORELOAD ( ( uint8_t ) 0x04 )
+
/* The definition of the timers themselves. */
-typedef struct tmrTimerControl
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
{
const char *pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
ListItem_t xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */
TickType_t xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
- UBaseType_t uxAutoReload; /*<< Set to pdTRUE if the timer should be automatically restarted once expired. Set to pdFALSE if the timer is, in effect, a one-shot timer. */
void *pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */
TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */
#if( configUSE_TRACE_FACILITY == 1 )
UBaseType_t uxTimerNumber; /*<< An ID assigned by trace tools such as FreeRTOS+Trace */
#endif
-
- #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
- uint8_t ucStaticallyAllocated; /*<< Set to pdTRUE if the timer was created statically so no attempt is made to free the memory again if the timer is later deleted. */
- #endif
+ uint8_t ucStatus; /*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
} xTIMER;
/* The old xTIMER name is maintained above then typedefed to the new Timer_t
@@ -127,9 +128,12 @@
/* The list in which active timers are stored. Timers are referenced in expire
time order, with the nearest expiry time at the front of the list. Only the
-timer service task is allowed to access these lists. */
-PRIVILEGED_DATA static List_t xActiveTimerList1 = {0};
-PRIVILEGED_DATA static List_t xActiveTimerList2 = {0};
+timer service task is allowed to access these lists.
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
+PRIVILEGED_DATA static List_t xActiveTimerList1 = { 0 };
+PRIVILEGED_DATA static List_t xActiveTimerList2 = { 0 };
PRIVILEGED_DATA static List_t *pxCurrentTimerList = NULL;
PRIVILEGED_DATA static List_t *pxOverflowTimerList = NULL;
@@ -162,7 +166,7 @@
* task. Other tasks communicate with the timer service task using the
* xTimerQueue queue.
*/
-static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;
+static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
/*
* Called by the timer service task to interpret and process a command it
@@ -283,26 +287,21 @@
{
Timer_t *pxNewTimer;
- pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );
+ pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
if( pxNewTimer != NULL )
{
+ /* Status is thus far zero as the timer is not created statically
+ and has not been started. The autoreload bit may get set in
+ prvInitialiseNewTimer. */
+ pxNewTimer->ucStatus = 0x00;
prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
-
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
- {
- /* Timers can be created statically or dynamically, so note this
- timer was created dynamically in case the timer is later
- deleted. */
- pxNewTimer->ucStaticallyAllocated = pdFALSE;
- }
- #endif /* configSUPPORT_STATIC_ALLOCATION */
}
return pxNewTimer;
}
-#endif /* configSUPPORT_STATIC_ALLOCATION */
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
@@ -323,24 +322,22 @@
structure. */
volatile size_t xSize = sizeof( StaticTimer_t );
configASSERT( xSize == sizeof( Timer_t ) );
+ ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
}
#endif /* configASSERT_DEFINED */
/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
configASSERT( pxTimerBuffer );
- pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+ pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
if( pxNewTimer != NULL )
{
- prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+ /* Timers can be created statically or dynamically so note this
+ timer was created statically in case it is later deleted. The
+ autoreload bit may get set in prvInitialiseNewTimer(). */
+ pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
- #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
- {
- /* Timers can be created statically or dynamically so note this
- timer was created statically in case it is later deleted. */
- pxNewTimer->ucStaticallyAllocated = pdTRUE;
- }
- #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+ prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
}
return pxNewTimer;
@@ -369,10 +366,13 @@
parameters. */
pxNewTimer->pcTimerName = pcTimerName;
pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
- pxNewTimer->uxAutoReload = uxAutoReload;
pxNewTimer->pvTimerID = pvTimerID;
pxNewTimer->pxCallbackFunction = pxCallbackFunction;
vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+ if( uxAutoReload != pdFALSE )
+ {
+ pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+ }
traceTIMER_CREATE( pxNewTimer );
}
}
@@ -392,7 +392,7 @@
/* Send a command to the timer service task to start the xTimer timer. */
xMessage.xMessageID = xCommandID;
xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
- xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;
+ xMessage.u.xTimerParameters.pxTimer = xTimer;
if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
{
@@ -432,16 +432,36 @@
TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
{
-Timer_t *pxTimer = ( Timer_t * ) xTimer;
+Timer_t *pxTimer = xTimer;
configASSERT( xTimer );
return pxTimer->xTimerPeriodInTicks;
}
/*-----------------------------------------------------------*/
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
+{
+Timer_t * pxTimer = xTimer;
+
+ configASSERT( xTimer );
+ taskENTER_CRITICAL();
+ {
+ if( uxAutoReload != pdFALSE )
+ {
+ pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+ }
+ else
+ {
+ pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+ }
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
{
-Timer_t * pxTimer = ( Timer_t * ) xTimer;
+Timer_t * pxTimer = xTimer;
TickType_t xReturn;
configASSERT( xTimer );
@@ -452,7 +472,7 @@
const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
{
-Timer_t *pxTimer = ( Timer_t * ) xTimer;
+Timer_t *pxTimer = xTimer;
configASSERT( xTimer );
return pxTimer->pcTimerName;
@@ -462,7 +482,7 @@
static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
{
BaseType_t xResult;
-Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
/* Remove the timer from the list of active timers. A check has already
been performed to ensure the list is not empty. */
@@ -471,7 +491,7 @@
/* If the timer is an auto reload timer then calculate the next
expiry time and re-insert the timer in the list of active timers. */
- if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
{
/* The timer is inserted into a list using a time relative to anything
other than the current time. It will therefore be inserted into the
@@ -491,6 +511,7 @@
}
else
{
+ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
mtCOVERAGE_TEST_MARKER();
}
@@ -499,7 +520,7 @@
}
/*-----------------------------------------------------------*/
-static void prvTimerTask( void *pvParameters )
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
{
TickType_t xNextExpireTime;
BaseType_t xListWasEmpty;
@@ -747,11 +768,12 @@
switch( xMessage.xMessageID )
{
case tmrCOMMAND_START :
- case tmrCOMMAND_START_FROM_ISR :
- case tmrCOMMAND_RESET :
- case tmrCOMMAND_RESET_FROM_ISR :
+ case tmrCOMMAND_START_FROM_ISR :
+ case tmrCOMMAND_RESET :
+ case tmrCOMMAND_RESET_FROM_ISR :
case tmrCOMMAND_START_DONT_TRACE :
/* Start or restart a timer. */
+ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
{
/* The timer expired before it was added to the active
@@ -759,7 +781,7 @@
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
traceTIMER_EXPIRED( pxTimer );
- if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
{
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
configASSERT( xResult );
@@ -778,12 +800,13 @@
case tmrCOMMAND_STOP :
case tmrCOMMAND_STOP_FROM_ISR :
- /* The timer has already been removed from the active list.
- There is nothing to do here. */
+ /* The timer has already been removed from the active list. */
+ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
break;
case tmrCOMMAND_CHANGE_PERIOD :
case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
@@ -797,29 +820,28 @@
break;
case tmrCOMMAND_DELETE :
- /* The timer has already been removed from the active list,
- just free up the memory if the memory was dynamically
- allocated. */
- #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+ #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
- /* The timer can only have been allocated dynamically -
- free it again. */
- vPortFree( pxTimer );
- }
- #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
- {
- /* The timer could have been allocated statically or
- dynamically, so check before attempting to free the
- memory. */
- if( pxTimer->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+ /* The timer has already been removed from the active list,
+ just free up the memory if the memory was dynamically
+ allocated. */
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
{
vPortFree( pxTimer );
}
else
{
- mtCOVERAGE_TEST_MARKER();
+ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
}
}
+ #else
+ {
+ /* If dynamic allocation is not enabled, the memory
+ could not have been dynamically allocated. So there is
+ no need to free the memory - just mark the timer as
+ "not active". */
+ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+ }
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
break;
@@ -848,7 +870,7 @@
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
/* Remove the timer from the list. */
- pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
traceTIMER_EXPIRED( pxTimer );
@@ -857,7 +879,7 @@
have not yet been switched. */
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
- if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
{
/* Calculate the reload value, and if the reload value results in
the timer going into the same timer list then it has already expired
@@ -944,28 +966,32 @@
BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
{
-BaseType_t xTimerIsInActiveList;
-Timer_t *pxTimer = ( Timer_t * ) xTimer;
+BaseType_t xReturn;
+Timer_t *pxTimer = xTimer;
configASSERT( xTimer );
/* Is the timer in the list of active timers? */
taskENTER_CRITICAL();
{
- /* Checking to see if it is in the NULL list in effect checks to see if
- it is referenced from either the current or the overflow timer lists in
- one go, but the logic has to be reversed, hence the '!'. */
- xTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) ); /*lint !e961. Cast is only redundant when NULL is passed into the macro. */
+ if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+ {
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
}
taskEXIT_CRITICAL();
- return xTimerIsInActiveList;
+ return xReturn;
} /*lint !e818 Can't be pointer to const due to the typedef. */
/*-----------------------------------------------------------*/
void *pvTimerGetTimerID( const TimerHandle_t xTimer )
{
-Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+Timer_t * const pxTimer = xTimer;
void *pvReturn;
configASSERT( xTimer );
@@ -982,7 +1008,7 @@
void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
{
-Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+Timer_t * const pxTimer = xTimer;
configASSERT( xTimer );
diff --git a/links_to_doc_pages_for_the_demo_projects.url b/links_to_doc_pages_for_the_demo_projects.url
deleted file mode 100644
index cfd5526..0000000
--- a/links_to_doc_pages_for_the_demo_projects.url
+++ /dev/null
@@ -1,5 +0,0 @@
-[{000214A0-0000-0000-C000-000000000046}]
-Prop3=19,2
-[InternetShortcut]
-URL=http://www.freertos.org/a00090.html
-IDList=
diff --git a/readme.txt b/readme.txt
deleted file mode 100644
index e69de29..0000000
--- a/readme.txt
+++ /dev/null
