blob: d21ebcdaad2b4fb8f1568761046d3823e46edae4 [file] [log] [blame]
Eyade129f12020-01-29 12:19:47 +01001/**
2 ******************************************************************************
3 * @file stm32f1xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
Ali Labbenef7a58ae2022-02-08 14:48:32 +01009 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
Eyade129f12020-01-29 12:19:47 +010011 *
Ali Labbenef7a58ae2022-02-08 14:48:32 +010012 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
Eyade129f12020-01-29 12:19:47 +010015 *
16 ******************************************************************************
17 */
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F1xx_LL_SPI_H
21#define STM32F1xx_LL_SPI_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f1xx.h"
29
30/** @addtogroup STM32F1xx_LL_Driver
31 * @{
32 */
33
34#if defined (SPI1) || defined (SPI2) || defined (SPI3)
35
36/** @defgroup SPI_LL SPI
37 * @{
38 */
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42/* Private macros ------------------------------------------------------------*/
43
44/* Exported types ------------------------------------------------------------*/
45#if defined(USE_FULL_LL_DRIVER)
46/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
47 * @{
48 */
49
50/**
51 * @brief SPI Init structures definition
52 */
53typedef struct
54{
55 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
56 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
57
58 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
59
60 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
61 This parameter can be a value of @ref SPI_LL_EC_MODE.
62
63 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
64
65 uint32_t DataWidth; /*!< Specifies the SPI data width.
66 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
67
68 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
69
70 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
71 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
72
73 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
74
75 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
76 This parameter can be a value of @ref SPI_LL_EC_PHASE.
77
78 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
79
80 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
81 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
82
83 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
84
85 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
86 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
87 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
88
89 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
90
91 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
92 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
93
94 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
95
96 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
97 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
98
99 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
100
101 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
102 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
103
104 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
105
106} LL_SPI_InitTypeDef;
107
108/**
109 * @}
110 */
111#endif /* USE_FULL_LL_DRIVER */
112
113/* Exported constants --------------------------------------------------------*/
114/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
115 * @{
116 */
117
118/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
119 * @brief Flags defines which can be used with LL_SPI_ReadReg function
120 * @{
121 */
122#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
123#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
124#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
125#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
126#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
127#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
128#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
129/**
130 * @}
131 */
132
133/** @defgroup SPI_LL_EC_IT IT Defines
134 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
135 * @{
136 */
137#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
138#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
139#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
140/**
141 * @}
142 */
143
144/** @defgroup SPI_LL_EC_MODE Operation Mode
145 * @{
146 */
147#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
148#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
149/**
150 * @}
151 */
152
153
154/** @defgroup SPI_LL_EC_PHASE Clock Phase
155 * @{
156 */
157#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
158#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
159/**
160 * @}
161 */
162
163/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
164 * @{
165 */
166#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
167#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
168/**
169 * @}
170 */
171
172/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
173 * @{
174 */
175#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
176#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
177#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
178#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
179#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
180#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
181#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
182#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
183/**
184 * @}
185 */
186
187/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
188 * @{
189 */
190#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
191#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
192/**
193 * @}
194 */
195
196/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
197 * @{
198 */
199#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
200#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
201#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
202#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
203/**
204 * @}
205 */
206
207/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
208 * @{
209 */
210#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
211#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
212#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
213/**
214 * @}
215 */
216
217/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
218 * @{
219 */
220#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
221#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
222/**
223 * @}
224 */
225#if defined(USE_FULL_LL_DRIVER)
226
227/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
228 * @{
229 */
230#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
231#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
232/**
233 * @}
234 */
235#endif /* USE_FULL_LL_DRIVER */
236
237/**
238 * @}
239 */
240
241/* Exported macro ------------------------------------------------------------*/
242/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
243 * @{
244 */
245
246/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
247 * @{
248 */
249
250/**
251 * @brief Write a value in SPI register
252 * @param __INSTANCE__ SPI Instance
253 * @param __REG__ Register to be written
254 * @param __VALUE__ Value to be written in the register
255 * @retval None
256 */
257#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
258
259/**
260 * @brief Read a value in SPI register
261 * @param __INSTANCE__ SPI Instance
262 * @param __REG__ Register to be read
263 * @retval Register value
264 */
265#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
266/**
267 * @}
268 */
269
270/**
271 * @}
272 */
273
274/* Exported functions --------------------------------------------------------*/
275/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
276 * @{
277 */
278
279/** @defgroup SPI_LL_EF_Configuration Configuration
280 * @{
281 */
282
283/**
284 * @brief Enable SPI peripheral
285 * @rmtoll CR1 SPE LL_SPI_Enable
286 * @param SPIx SPI Instance
287 * @retval None
288 */
289__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
290{
291 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
292}
293
294/**
295 * @brief Disable SPI peripheral
296 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
297 * @rmtoll CR1 SPE LL_SPI_Disable
298 * @param SPIx SPI Instance
299 * @retval None
300 */
301__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
302{
303 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
304}
305
306/**
307 * @brief Check if SPI peripheral is enabled
308 * @rmtoll CR1 SPE LL_SPI_IsEnabled
309 * @param SPIx SPI Instance
310 * @retval State of bit (1 or 0).
311 */
312__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
313{
314 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
315}
316
317/**
318 * @brief Set SPI operation mode to Master or Slave
319 * @note This bit should not be changed when communication is ongoing.
320 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
321 * CR1 SSI LL_SPI_SetMode
322 * @param SPIx SPI Instance
323 * @param Mode This parameter can be one of the following values:
324 * @arg @ref LL_SPI_MODE_MASTER
325 * @arg @ref LL_SPI_MODE_SLAVE
326 * @retval None
327 */
328__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
329{
330 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
331}
332
333/**
334 * @brief Get SPI operation mode (Master or Slave)
335 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
336 * CR1 SSI LL_SPI_GetMode
337 * @param SPIx SPI Instance
338 * @retval Returned value can be one of the following values:
339 * @arg @ref LL_SPI_MODE_MASTER
340 * @arg @ref LL_SPI_MODE_SLAVE
341 */
342__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
343{
344 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
345}
346
347
348/**
349 * @brief Set clock phase
350 * @note This bit should not be changed when communication is ongoing.
351 * This bit is not used in SPI TI mode.
352 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
353 * @param SPIx SPI Instance
354 * @param ClockPhase This parameter can be one of the following values:
355 * @arg @ref LL_SPI_PHASE_1EDGE
356 * @arg @ref LL_SPI_PHASE_2EDGE
357 * @retval None
358 */
359__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
360{
361 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
362}
363
364/**
365 * @brief Get clock phase
366 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
367 * @param SPIx SPI Instance
368 * @retval Returned value can be one of the following values:
369 * @arg @ref LL_SPI_PHASE_1EDGE
370 * @arg @ref LL_SPI_PHASE_2EDGE
371 */
372__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
373{
374 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
375}
376
377/**
378 * @brief Set clock polarity
379 * @note This bit should not be changed when communication is ongoing.
380 * This bit is not used in SPI TI mode.
381 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
382 * @param SPIx SPI Instance
383 * @param ClockPolarity This parameter can be one of the following values:
384 * @arg @ref LL_SPI_POLARITY_LOW
385 * @arg @ref LL_SPI_POLARITY_HIGH
386 * @retval None
387 */
388__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
389{
390 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
391}
392
393/**
394 * @brief Get clock polarity
395 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
396 * @param SPIx SPI Instance
397 * @retval Returned value can be one of the following values:
398 * @arg @ref LL_SPI_POLARITY_LOW
399 * @arg @ref LL_SPI_POLARITY_HIGH
400 */
401__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
402{
403 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
404}
405
406/**
407 * @brief Set baud rate prescaler
408 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
409 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
410 * @param SPIx SPI Instance
411 * @param BaudRate This parameter can be one of the following values:
412 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
413 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
414 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
415 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
416 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
417 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
418 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
419 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
420 * @retval None
421 */
422__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
423{
424 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
425}
426
427/**
428 * @brief Get baud rate prescaler
429 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
430 * @param SPIx SPI Instance
431 * @retval Returned value can be one of the following values:
432 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
433 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
434 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
435 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
436 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
437 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
438 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
439 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
440 */
441__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
442{
443 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
444}
445
446/**
447 * @brief Set transfer bit order
448 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
449 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
450 * @param SPIx SPI Instance
451 * @param BitOrder This parameter can be one of the following values:
452 * @arg @ref LL_SPI_LSB_FIRST
453 * @arg @ref LL_SPI_MSB_FIRST
454 * @retval None
455 */
456__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
457{
458 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
459}
460
461/**
462 * @brief Get transfer bit order
463 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
464 * @param SPIx SPI Instance
465 * @retval Returned value can be one of the following values:
466 * @arg @ref LL_SPI_LSB_FIRST
467 * @arg @ref LL_SPI_MSB_FIRST
468 */
469__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
470{
471 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
472}
473
474/**
475 * @brief Set transfer direction mode
476 * @note For Half-Duplex mode, Rx Direction is set by default.
477 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
478 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
479 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
480 * CR1 BIDIOE LL_SPI_SetTransferDirection
481 * @param SPIx SPI Instance
482 * @param TransferDirection This parameter can be one of the following values:
483 * @arg @ref LL_SPI_FULL_DUPLEX
484 * @arg @ref LL_SPI_SIMPLEX_RX
485 * @arg @ref LL_SPI_HALF_DUPLEX_RX
486 * @arg @ref LL_SPI_HALF_DUPLEX_TX
487 * @retval None
488 */
489__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
490{
491 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
492}
493
494/**
495 * @brief Get transfer direction mode
496 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
497 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
498 * CR1 BIDIOE LL_SPI_GetTransferDirection
499 * @param SPIx SPI Instance
500 * @retval Returned value can be one of the following values:
501 * @arg @ref LL_SPI_FULL_DUPLEX
502 * @arg @ref LL_SPI_SIMPLEX_RX
503 * @arg @ref LL_SPI_HALF_DUPLEX_RX
504 * @arg @ref LL_SPI_HALF_DUPLEX_TX
505 */
506__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
507{
508 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
509}
510
511/**
512 * @brief Set frame data width
513 * @rmtoll CR1 DFF LL_SPI_SetDataWidth
514 * @param SPIx SPI Instance
515 * @param DataWidth This parameter can be one of the following values:
516 * @arg @ref LL_SPI_DATAWIDTH_8BIT
517 * @arg @ref LL_SPI_DATAWIDTH_16BIT
518 * @retval None
519 */
520__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
521{
522 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
523}
524
525/**
526 * @brief Get frame data width
527 * @rmtoll CR1 DFF LL_SPI_GetDataWidth
528 * @param SPIx SPI Instance
529 * @retval Returned value can be one of the following values:
530 * @arg @ref LL_SPI_DATAWIDTH_8BIT
531 * @arg @ref LL_SPI_DATAWIDTH_16BIT
532 */
533__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
534{
535 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
536}
537
538/**
539 * @}
540 */
541
542/** @defgroup SPI_LL_EF_CRC_Management CRC Management
543 * @{
544 */
545
546/**
547 * @brief Enable CRC
548 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
549 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
550 * @param SPIx SPI Instance
551 * @retval None
552 */
553__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
554{
555 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
556}
557
558/**
559 * @brief Disable CRC
560 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
561 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
562 * @param SPIx SPI Instance
563 * @retval None
564 */
565__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
566{
567 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
568}
569
570/**
571 * @brief Check if CRC is enabled
572 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
573 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
574 * @param SPIx SPI Instance
575 * @retval State of bit (1 or 0).
576 */
577__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
578{
579 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
580}
581
582/**
583 * @brief Set CRCNext to transfer CRC on the line
584 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
585 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
586 * @param SPIx SPI Instance
587 * @retval None
588 */
589__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
590{
591 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
592}
593
594/**
595 * @brief Set polynomial for CRC calculation
596 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
597 * @param SPIx SPI Instance
598 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
599 * @retval None
600 */
601__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
602{
603 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
604}
605
606/**
607 * @brief Get polynomial for CRC calculation
608 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
609 * @param SPIx SPI Instance
610 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
611 */
612__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
613{
614 return (uint32_t)(READ_REG(SPIx->CRCPR));
615}
616
617/**
618 * @brief Get Rx CRC
619 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
620 * @param SPIx SPI Instance
621 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
622 */
623__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
624{
625 return (uint32_t)(READ_REG(SPIx->RXCRCR));
626}
627
628/**
629 * @brief Get Tx CRC
630 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
631 * @param SPIx SPI Instance
632 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
633 */
634__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
635{
636 return (uint32_t)(READ_REG(SPIx->TXCRCR));
637}
638
639/**
640 * @}
641 */
642
643/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
644 * @{
645 */
646
647/**
648 * @brief Set NSS mode
649 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
650 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
651 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
652 * @param SPIx SPI Instance
653 * @param NSS This parameter can be one of the following values:
654 * @arg @ref LL_SPI_NSS_SOFT
655 * @arg @ref LL_SPI_NSS_HARD_INPUT
656 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
657 * @retval None
658 */
659__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
660{
661 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
662 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
663}
664
665/**
666 * @brief Get NSS mode
667 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
668 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
669 * @param SPIx SPI Instance
670 * @retval Returned value can be one of the following values:
671 * @arg @ref LL_SPI_NSS_SOFT
672 * @arg @ref LL_SPI_NSS_HARD_INPUT
673 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
674 */
675__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
676{
rihab kouki1dd9d362020-10-05 09:08:15 +0100677 uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
678 uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
Eyade129f12020-01-29 12:19:47 +0100679 return (Ssm | Ssoe);
680}
681
682/**
683 * @}
684 */
685
686/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
687 * @{
688 */
689
690/**
691 * @brief Check if Rx buffer is not empty
692 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
693 * @param SPIx SPI Instance
694 * @retval State of bit (1 or 0).
695 */
696__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
697{
698 return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
699}
700
701/**
702 * @brief Check if Tx buffer is empty
703 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
704 * @param SPIx SPI Instance
705 * @retval State of bit (1 or 0).
706 */
707__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
708{
709 return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
710}
711
712/**
713 * @brief Get CRC error flag
714 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
715 * @param SPIx SPI Instance
716 * @retval State of bit (1 or 0).
717 */
718__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
719{
720 return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
721}
722
723/**
724 * @brief Get mode fault error flag
725 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
726 * @param SPIx SPI Instance
727 * @retval State of bit (1 or 0).
728 */
729__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
730{
731 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
732}
733
734/**
735 * @brief Get overrun error flag
736 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
737 * @param SPIx SPI Instance
738 * @retval State of bit (1 or 0).
739 */
740__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
741{
742 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
743}
744
745/**
746 * @brief Get busy flag
747 * @note The BSY flag is cleared under any one of the following conditions:
748 * -When the SPI is correctly disabled
749 * -When a fault is detected in Master mode (MODF bit set to 1)
750 * -In Master mode, when it finishes a data transmission and no new data is ready to be
751 * sent
752 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
753 * each data transfer.
754 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
755 * @param SPIx SPI Instance
756 * @retval State of bit (1 or 0).
757 */
758__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
759{
760 return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
761}
762
763
764/**
765 * @brief Clear CRC error flag
766 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
767 * @param SPIx SPI Instance
768 * @retval None
769 */
770__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
771{
772 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
773}
774
775/**
776 * @brief Clear mode fault error flag
777 * @note Clearing this flag is done by a read access to the SPIx_SR
778 * register followed by a write access to the SPIx_CR1 register
779 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
780 * @param SPIx SPI Instance
781 * @retval None
782 */
783__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
784{
785 __IO uint32_t tmpreg_sr;
786 tmpreg_sr = SPIx->SR;
787 (void) tmpreg_sr;
788 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
789}
790
791/**
792 * @brief Clear overrun error flag
793 * @note Clearing this flag is done by a read access to the SPIx_DR
794 * register followed by a read access to the SPIx_SR register
795 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
796 * @param SPIx SPI Instance
797 * @retval None
798 */
799__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
800{
801 __IO uint32_t tmpreg;
802 tmpreg = SPIx->DR;
803 (void) tmpreg;
804 tmpreg = SPIx->SR;
805 (void) tmpreg;
806}
807
808/**
809 * @brief Clear frame format error flag
810 * @note Clearing this flag is done by reading SPIx_SR register
811 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
812 * @param SPIx SPI Instance
813 * @retval None
814 */
815__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
816{
817 __IO uint32_t tmpreg;
818 tmpreg = SPIx->SR;
819 (void) tmpreg;
820}
821
822/**
823 * @}
824 */
825
826/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
827 * @{
828 */
829
830/**
831 * @brief Enable error interrupt
832 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
833 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
834 * @param SPIx SPI Instance
835 * @retval None
836 */
837__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
838{
839 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
840}
841
842/**
843 * @brief Enable Rx buffer not empty interrupt
844 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
845 * @param SPIx SPI Instance
846 * @retval None
847 */
848__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
849{
850 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
851}
852
853/**
854 * @brief Enable Tx buffer empty interrupt
855 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
856 * @param SPIx SPI Instance
857 * @retval None
858 */
859__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
860{
861 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
862}
863
864/**
865 * @brief Disable error interrupt
866 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
867 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
868 * @param SPIx SPI Instance
869 * @retval None
870 */
871__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
872{
873 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
874}
875
876/**
877 * @brief Disable Rx buffer not empty interrupt
878 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
879 * @param SPIx SPI Instance
880 * @retval None
881 */
882__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
883{
884 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
885}
886
887/**
888 * @brief Disable Tx buffer empty interrupt
889 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
890 * @param SPIx SPI Instance
891 * @retval None
892 */
893__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
894{
895 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
896}
897
898/**
899 * @brief Check if error interrupt is enabled
900 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
901 * @param SPIx SPI Instance
902 * @retval State of bit (1 or 0).
903 */
904__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
905{
906 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
907}
908
909/**
910 * @brief Check if Rx buffer not empty interrupt is enabled
911 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
912 * @param SPIx SPI Instance
913 * @retval State of bit (1 or 0).
914 */
915__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
916{
917 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
918}
919
920/**
921 * @brief Check if Tx buffer empty interrupt
922 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
923 * @param SPIx SPI Instance
924 * @retval State of bit (1 or 0).
925 */
926__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
927{
928 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
929}
930
931/**
932 * @}
933 */
934
935/** @defgroup SPI_LL_EF_DMA_Management DMA Management
936 * @{
937 */
938
939/**
940 * @brief Enable DMA Rx
941 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
942 * @param SPIx SPI Instance
943 * @retval None
944 */
945__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
946{
947 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
948}
949
950/**
951 * @brief Disable DMA Rx
952 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
953 * @param SPIx SPI Instance
954 * @retval None
955 */
956__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
957{
958 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
959}
960
961/**
962 * @brief Check if DMA Rx is enabled
963 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
964 * @param SPIx SPI Instance
965 * @retval State of bit (1 or 0).
966 */
967__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
968{
969 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
970}
971
972/**
973 * @brief Enable DMA Tx
974 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
975 * @param SPIx SPI Instance
976 * @retval None
977 */
978__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
979{
980 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
981}
982
983/**
984 * @brief Disable DMA Tx
985 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
986 * @param SPIx SPI Instance
987 * @retval None
988 */
989__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
990{
991 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
992}
993
994/**
995 * @brief Check if DMA Tx is enabled
996 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
997 * @param SPIx SPI Instance
998 * @retval State of bit (1 or 0).
999 */
1000__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1001{
1002 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
1003}
1004
1005/**
1006 * @brief Get the data register address used for DMA transfer
1007 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1008 * @param SPIx SPI Instance
1009 * @retval Address of data register
1010 */
1011__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
1012{
1013 return (uint32_t) &(SPIx->DR);
1014}
1015
1016/**
1017 * @}
1018 */
1019
1020/** @defgroup SPI_LL_EF_DATA_Management DATA Management
1021 * @{
1022 */
1023
1024/**
1025 * @brief Read 8-Bits in the data register
1026 * @rmtoll DR DR LL_SPI_ReceiveData8
1027 * @param SPIx SPI Instance
1028 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1029 */
1030__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1031{
Eyafccac442021-06-07 16:52:38 +01001032 return (*((__IO uint8_t *)&SPIx->DR));
Eyade129f12020-01-29 12:19:47 +01001033}
1034
1035/**
1036 * @brief Read 16-Bits in the data register
1037 * @rmtoll DR DR LL_SPI_ReceiveData16
1038 * @param SPIx SPI Instance
1039 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1040 */
1041__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1042{
1043 return (uint16_t)(READ_REG(SPIx->DR));
1044}
1045
1046/**
1047 * @brief Write 8-Bits in the data register
1048 * @rmtoll DR DR LL_SPI_TransmitData8
1049 * @param SPIx SPI Instance
1050 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1051 * @retval None
1052 */
1053__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1054{
1055#if defined (__GNUC__)
1056 __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
1057 *spidr = TxData;
1058#else
1059 *((__IO uint8_t *)&SPIx->DR) = TxData;
1060#endif /* __GNUC__ */
1061}
1062
1063/**
1064 * @brief Write 16-Bits in the data register
1065 * @rmtoll DR DR LL_SPI_TransmitData16
1066 * @param SPIx SPI Instance
1067 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1068 * @retval None
1069 */
1070__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1071{
1072#if defined (__GNUC__)
1073 __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
1074 *spidr = TxData;
1075#else
1076 SPIx->DR = TxData;
1077#endif /* __GNUC__ */
1078}
1079
1080/**
1081 * @}
1082 */
1083#if defined(USE_FULL_LL_DRIVER)
1084/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1085 * @{
1086 */
1087
1088ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
1089ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1090void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1091
1092/**
1093 * @}
1094 */
1095#endif /* USE_FULL_LL_DRIVER */
1096/**
1097 * @}
1098 */
1099
1100/**
1101 * @}
1102 */
1103
1104#if defined(SPI_I2S_SUPPORT)
1105/** @defgroup I2S_LL I2S
1106 * @{
1107 */
1108
1109/* Private variables ---------------------------------------------------------*/
1110/* Private constants ---------------------------------------------------------*/
1111/* Private macros ------------------------------------------------------------*/
1112
1113/* Exported types ------------------------------------------------------------*/
1114#if defined(USE_FULL_LL_DRIVER)
1115/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
1116 * @{
1117 */
1118
1119/**
1120 * @brief I2S Init structure definition
1121 */
1122
1123typedef struct
1124{
1125 uint32_t Mode; /*!< Specifies the I2S operating mode.
1126 This parameter can be a value of @ref I2S_LL_EC_MODE
1127
1128 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
1129
1130 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
1131 This parameter can be a value of @ref I2S_LL_EC_STANDARD
1132
1133 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
1134
1135
1136 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
1137 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
1138
1139 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
1140
1141
1142 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
1143 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
1144
1145 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
1146
1147
1148 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
1149 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
1150
1151 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
1152 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
1153
1154
1155 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
1156 This parameter can be a value of @ref I2S_LL_EC_POLARITY
1157
1158 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
1159
1160} LL_I2S_InitTypeDef;
1161
1162/**
1163 * @}
1164 */
1165#endif /*USE_FULL_LL_DRIVER*/
1166
1167/* Exported constants --------------------------------------------------------*/
1168/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
1169 * @{
1170 */
1171
1172/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
1173 * @brief Flags defines which can be used with LL_I2S_ReadReg function
1174 * @{
1175 */
1176#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
1177#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
1178#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
1179#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
1180#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
1181#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
1182/**
1183 * @}
1184 */
1185
1186/** @defgroup SPI_LL_EC_IT IT Defines
1187 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
1188 * @{
1189 */
1190#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
1191#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
1192#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
1193/**
1194 * @}
1195 */
1196
1197/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1198 * @{
1199 */
rihab kouki1dd9d362020-10-05 09:08:15 +01001200#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
1201#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
1202#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
1203#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
Eyade129f12020-01-29 12:19:47 +01001204/**
1205 * @}
1206 */
1207
1208/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
1209 * @{
1210 */
1211#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
1212#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
1213/**
1214 * @}
1215 */
1216
1217/** @defgroup I2S_LL_EC_STANDARD I2s Standard
1218 * @{
1219 */
1220#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
1221#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
1222#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
1223#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
1224#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
1225/**
1226 * @}
1227 */
1228
1229/** @defgroup I2S_LL_EC_MODE Operation Mode
1230 * @{
1231 */
1232#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
1233#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
1234#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
1235#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
1236/**
1237 * @}
1238 */
1239
1240/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
1241 * @{
1242 */
1243#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
1244#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
1245/**
1246 * @}
1247 */
1248
1249#if defined(USE_FULL_LL_DRIVER)
1250
1251/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
1252 * @{
1253 */
1254#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
1255#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
1256/**
1257 * @}
1258 */
1259
1260/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
1261 * @{
1262 */
1263
1264#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
1265#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
1266#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
1267#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
1268#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
1269#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
1270#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
1271#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
1272#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
1273#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
1274/**
1275 * @}
1276 */
1277#endif /* USE_FULL_LL_DRIVER */
1278
1279/**
1280 * @}
1281 */
1282
1283/* Exported macro ------------------------------------------------------------*/
1284/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
1285 * @{
1286 */
1287
1288/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
1289 * @{
1290 */
1291
1292/**
1293 * @brief Write a value in I2S register
1294 * @param __INSTANCE__ I2S Instance
1295 * @param __REG__ Register to be written
1296 * @param __VALUE__ Value to be written in the register
1297 * @retval None
1298 */
1299#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1300
1301/**
1302 * @brief Read a value in I2S register
1303 * @param __INSTANCE__ I2S Instance
1304 * @param __REG__ Register to be read
1305 * @retval Register value
1306 */
1307#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1308/**
1309 * @}
1310 */
1311
1312/**
1313 * @}
1314 */
1315
1316
1317/* Exported functions --------------------------------------------------------*/
1318
1319/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
1320 * @{
1321 */
1322
1323/** @defgroup I2S_LL_EF_Configuration Configuration
1324 * @{
1325 */
1326
1327/**
1328 * @brief Select I2S mode and Enable I2S peripheral
1329 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
1330 * I2SCFGR I2SE LL_I2S_Enable
1331 * @param SPIx SPI Instance
1332 * @retval None
1333 */
1334__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1335{
1336 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1337}
1338
1339/**
1340 * @brief Disable I2S peripheral
1341 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
1342 * @param SPIx SPI Instance
1343 * @retval None
1344 */
1345__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1346{
1347 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1348}
1349
1350/**
1351 * @brief Check if I2S peripheral is enabled
1352 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
1353 * @param SPIx SPI Instance
1354 * @retval State of bit (1 or 0).
1355 */
1356__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
1357{
1358 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
1359}
1360
1361/**
1362 * @brief Set I2S data frame length
1363 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
1364 * I2SCFGR CHLEN LL_I2S_SetDataFormat
1365 * @param SPIx SPI Instance
1366 * @param DataFormat This parameter can be one of the following values:
1367 * @arg @ref LL_I2S_DATAFORMAT_16B
1368 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1369 * @arg @ref LL_I2S_DATAFORMAT_24B
1370 * @arg @ref LL_I2S_DATAFORMAT_32B
1371 * @retval None
1372 */
1373__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1374{
1375 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1376}
1377
1378/**
1379 * @brief Get I2S data frame length
1380 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
1381 * I2SCFGR CHLEN LL_I2S_GetDataFormat
1382 * @param SPIx SPI Instance
1383 * @retval Returned value can be one of the following values:
1384 * @arg @ref LL_I2S_DATAFORMAT_16B
1385 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1386 * @arg @ref LL_I2S_DATAFORMAT_24B
1387 * @arg @ref LL_I2S_DATAFORMAT_32B
1388 */
1389__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
1390{
1391 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1392}
1393
1394/**
1395 * @brief Set I2S clock polarity
1396 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
1397 * @param SPIx SPI Instance
1398 * @param ClockPolarity This parameter can be one of the following values:
1399 * @arg @ref LL_I2S_POLARITY_LOW
1400 * @arg @ref LL_I2S_POLARITY_HIGH
1401 * @retval None
1402 */
1403__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1404{
1405 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1406}
1407
1408/**
1409 * @brief Get I2S clock polarity
1410 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
1411 * @param SPIx SPI Instance
1412 * @retval Returned value can be one of the following values:
1413 * @arg @ref LL_I2S_POLARITY_LOW
1414 * @arg @ref LL_I2S_POLARITY_HIGH
1415 */
1416__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
1417{
1418 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1419}
1420
1421/**
1422 * @brief Set I2S standard protocol
1423 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
1424 * I2SCFGR PCMSYNC LL_I2S_SetStandard
1425 * @param SPIx SPI Instance
1426 * @param Standard This parameter can be one of the following values:
1427 * @arg @ref LL_I2S_STANDARD_PHILIPS
1428 * @arg @ref LL_I2S_STANDARD_MSB
1429 * @arg @ref LL_I2S_STANDARD_LSB
1430 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1431 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1432 * @retval None
1433 */
1434__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1435{
1436 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1437}
1438
1439/**
1440 * @brief Get I2S standard protocol
1441 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
1442 * I2SCFGR PCMSYNC LL_I2S_GetStandard
1443 * @param SPIx SPI Instance
1444 * @retval Returned value can be one of the following values:
1445 * @arg @ref LL_I2S_STANDARD_PHILIPS
1446 * @arg @ref LL_I2S_STANDARD_MSB
1447 * @arg @ref LL_I2S_STANDARD_LSB
1448 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1449 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1450 */
1451__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
1452{
1453 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1454}
1455
1456/**
1457 * @brief Set I2S transfer mode
1458 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
1459 * @param SPIx SPI Instance
1460 * @param Mode This parameter can be one of the following values:
1461 * @arg @ref LL_I2S_MODE_SLAVE_TX
1462 * @arg @ref LL_I2S_MODE_SLAVE_RX
1463 * @arg @ref LL_I2S_MODE_MASTER_TX
1464 * @arg @ref LL_I2S_MODE_MASTER_RX
1465 * @retval None
1466 */
1467__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1468{
1469 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1470}
1471
1472/**
1473 * @brief Get I2S transfer mode
1474 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
1475 * @param SPIx SPI Instance
1476 * @retval Returned value can be one of the following values:
1477 * @arg @ref LL_I2S_MODE_SLAVE_TX
1478 * @arg @ref LL_I2S_MODE_SLAVE_RX
1479 * @arg @ref LL_I2S_MODE_MASTER_TX
1480 * @arg @ref LL_I2S_MODE_MASTER_RX
1481 */
1482__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
1483{
1484 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1485}
1486
1487/**
1488 * @brief Set I2S linear prescaler
1489 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
1490 * @param SPIx SPI Instance
1491 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1492 * @retval None
1493 */
1494__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1495{
1496 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1497}
1498
1499/**
1500 * @brief Get I2S linear prescaler
1501 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
1502 * @param SPIx SPI Instance
1503 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1504 */
1505__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
1506{
1507 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1508}
1509
1510/**
1511 * @brief Set I2S parity prescaler
1512 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
1513 * @param SPIx SPI Instance
1514 * @param PrescalerParity This parameter can be one of the following values:
1515 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1516 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1517 * @retval None
1518 */
1519__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1520{
1521 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1522}
1523
1524/**
1525 * @brief Get I2S parity prescaler
1526 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
1527 * @param SPIx SPI Instance
1528 * @retval Returned value can be one of the following values:
1529 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1530 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1531 */
1532__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
1533{
1534 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1535}
1536
1537/**
rihab kouki1dd9d362020-10-05 09:08:15 +01001538 * @brief Enable the master clock output (Pin MCK)
Eyade129f12020-01-29 12:19:47 +01001539 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1540 * @param SPIx SPI Instance
1541 * @retval None
1542 */
1543__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1544{
1545 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1546}
1547
1548/**
rihab kouki1dd9d362020-10-05 09:08:15 +01001549 * @brief Disable the master clock output (Pin MCK)
Eyade129f12020-01-29 12:19:47 +01001550 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1551 * @param SPIx SPI Instance
1552 * @retval None
1553 */
1554__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1555{
1556 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1557}
1558
1559/**
rihab kouki1dd9d362020-10-05 09:08:15 +01001560 * @brief Check if the master clock output (Pin MCK) is enabled
Eyade129f12020-01-29 12:19:47 +01001561 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1562 * @param SPIx SPI Instance
1563 * @retval State of bit (1 or 0).
1564 */
1565__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
1566{
1567 return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
1568}
1569
1570/**
1571 * @}
1572 */
1573
1574/** @defgroup I2S_LL_EF_FLAG FLAG Management
1575 * @{
1576 */
1577
1578/**
1579 * @brief Check if Rx buffer is not empty
1580 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
1581 * @param SPIx SPI Instance
1582 * @retval State of bit (1 or 0).
1583 */
1584__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
1585{
1586 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1587}
1588
1589/**
1590 * @brief Check if Tx buffer is empty
1591 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
1592 * @param SPIx SPI Instance
1593 * @retval State of bit (1 or 0).
1594 */
1595__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
1596{
1597 return LL_SPI_IsActiveFlag_TXE(SPIx);
1598}
1599
1600/**
1601 * @brief Get busy flag
1602 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
1603 * @param SPIx SPI Instance
1604 * @retval State of bit (1 or 0).
1605 */
1606__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
1607{
1608 return LL_SPI_IsActiveFlag_BSY(SPIx);
1609}
1610
1611/**
1612 * @brief Get overrun error flag
1613 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
1614 * @param SPIx SPI Instance
1615 * @retval State of bit (1 or 0).
1616 */
1617__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1618{
1619 return LL_SPI_IsActiveFlag_OVR(SPIx);
1620}
1621
1622/**
1623 * @brief Get underrun error flag
1624 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
1625 * @param SPIx SPI Instance
1626 * @retval State of bit (1 or 0).
1627 */
1628__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1629{
1630 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1631}
1632
1633
1634/**
1635 * @brief Get channel side flag.
1636 * @note 0: Channel Left has to be transmitted or has been received\n
1637 * 1: Channel Right has to be transmitted or has been received\n
1638 * It has no significance in PCM mode.
1639 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
1640 * @param SPIx SPI Instance
1641 * @retval State of bit (1 or 0).
1642 */
1643__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
1644{
1645 return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
1646}
1647
1648/**
1649 * @brief Clear overrun error flag
1650 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
1651 * @param SPIx SPI Instance
1652 * @retval None
1653 */
1654__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
1655{
1656 LL_SPI_ClearFlag_OVR(SPIx);
1657}
1658
1659/**
1660 * @brief Clear underrun error flag
1661 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
1662 * @param SPIx SPI Instance
1663 * @retval None
1664 */
1665__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
1666{
1667 __IO uint32_t tmpreg;
1668 tmpreg = SPIx->SR;
1669 (void)tmpreg;
1670}
1671
1672/**
1673 * @brief Clear frame format error flag
1674 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
1675 * @param SPIx SPI Instance
1676 * @retval None
1677 */
1678__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
1679{
1680 LL_SPI_ClearFlag_FRE(SPIx);
1681}
1682
1683/**
1684 * @}
1685 */
1686
1687/** @defgroup I2S_LL_EF_IT Interrupt Management
1688 * @{
1689 */
1690
1691/**
1692 * @brief Enable error IT
1693 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1694 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
1695 * @param SPIx SPI Instance
1696 * @retval None
1697 */
1698__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
1699{
1700 LL_SPI_EnableIT_ERR(SPIx);
1701}
1702
1703/**
1704 * @brief Enable Rx buffer not empty IT
1705 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
1706 * @param SPIx SPI Instance
1707 * @retval None
1708 */
1709__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
1710{
1711 LL_SPI_EnableIT_RXNE(SPIx);
1712}
1713
1714/**
1715 * @brief Enable Tx buffer empty IT
1716 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
1717 * @param SPIx SPI Instance
1718 * @retval None
1719 */
1720__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
1721{
1722 LL_SPI_EnableIT_TXE(SPIx);
1723}
1724
1725/**
1726 * @brief Disable error IT
1727 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
1728 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
1729 * @param SPIx SPI Instance
1730 * @retval None
1731 */
1732__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
1733{
1734 LL_SPI_DisableIT_ERR(SPIx);
1735}
1736
1737/**
1738 * @brief Disable Rx buffer not empty IT
1739 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
1740 * @param SPIx SPI Instance
1741 * @retval None
1742 */
1743__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
1744{
1745 LL_SPI_DisableIT_RXNE(SPIx);
1746}
1747
1748/**
1749 * @brief Disable Tx buffer empty IT
1750 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
1751 * @param SPIx SPI Instance
1752 * @retval None
1753 */
1754__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
1755{
1756 LL_SPI_DisableIT_TXE(SPIx);
1757}
1758
1759/**
1760 * @brief Check if ERR IT is enabled
1761 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
1762 * @param SPIx SPI Instance
1763 * @retval State of bit (1 or 0).
1764 */
1765__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
1766{
1767 return LL_SPI_IsEnabledIT_ERR(SPIx);
1768}
1769
1770/**
1771 * @brief Check if RXNE IT is enabled
1772 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
1773 * @param SPIx SPI Instance
1774 * @retval State of bit (1 or 0).
1775 */
1776__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
1777{
1778 return LL_SPI_IsEnabledIT_RXNE(SPIx);
1779}
1780
1781/**
1782 * @brief Check if TXE IT is enabled
1783 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
1784 * @param SPIx SPI Instance
1785 * @retval State of bit (1 or 0).
1786 */
1787__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
1788{
1789 return LL_SPI_IsEnabledIT_TXE(SPIx);
1790}
1791
1792/**
1793 * @}
1794 */
1795
1796/** @defgroup I2S_LL_EF_DMA DMA Management
1797 * @{
1798 */
1799
1800/**
1801 * @brief Enable DMA Rx
1802 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
1803 * @param SPIx SPI Instance
1804 * @retval None
1805 */
1806__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1807{
1808 LL_SPI_EnableDMAReq_RX(SPIx);
1809}
1810
1811/**
1812 * @brief Disable DMA Rx
1813 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
1814 * @param SPIx SPI Instance
1815 * @retval None
1816 */
1817__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1818{
1819 LL_SPI_DisableDMAReq_RX(SPIx);
1820}
1821
1822/**
1823 * @brief Check if DMA Rx is enabled
1824 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
1825 * @param SPIx SPI Instance
1826 * @retval State of bit (1 or 0).
1827 */
1828__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1829{
1830 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
1831}
1832
1833/**
1834 * @brief Enable DMA Tx
1835 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
1836 * @param SPIx SPI Instance
1837 * @retval None
1838 */
1839__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1840{
1841 LL_SPI_EnableDMAReq_TX(SPIx);
1842}
1843
1844/**
1845 * @brief Disable DMA Tx
1846 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
1847 * @param SPIx SPI Instance
1848 * @retval None
1849 */
1850__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1851{
1852 LL_SPI_DisableDMAReq_TX(SPIx);
1853}
1854
1855/**
1856 * @brief Check if DMA Tx is enabled
1857 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
1858 * @param SPIx SPI Instance
1859 * @retval State of bit (1 or 0).
1860 */
1861__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1862{
1863 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
1864}
1865
1866/**
1867 * @}
1868 */
1869
1870/** @defgroup I2S_LL_EF_DATA DATA Management
1871 * @{
1872 */
1873
1874/**
1875 * @brief Read 16-Bits in data register
1876 * @rmtoll DR DR LL_I2S_ReceiveData16
1877 * @param SPIx SPI Instance
1878 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1879 */
1880__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
1881{
1882 return LL_SPI_ReceiveData16(SPIx);
1883}
1884
1885/**
1886 * @brief Write 16-Bits in data register
1887 * @rmtoll DR DR LL_I2S_TransmitData16
1888 * @param SPIx SPI Instance
1889 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
1890 * @retval None
1891 */
1892__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1893{
1894 LL_SPI_TransmitData16(SPIx, TxData);
1895}
1896
1897/**
1898 * @}
1899 */
1900
1901#if defined(USE_FULL_LL_DRIVER)
1902/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
1903 * @{
1904 */
1905
1906ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
1907ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
1908void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
1909void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
1910
1911/**
1912 * @}
1913 */
1914#endif /* USE_FULL_LL_DRIVER */
1915
1916/**
1917 * @}
1918 */
1919
1920/**
1921 * @}
1922 */
1923#endif /* SPI_I2S_SUPPORT */
1924
1925#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
1926
1927/**
1928 * @}
1929 */
1930
1931#ifdef __cplusplus
1932}
1933#endif
1934
1935#endif /* STM32F1xx_LL_SPI_H */