| /** |
| ****************************************************************************** |
| * @file stm32f2xx_ll_rcc.h |
| * @author MCD Application Team |
| * @brief Header file of RCC LL module. |
| ****************************************************************************** |
| * @attention |
| * |
| * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
| * All rights reserved.</center></h2> |
| * |
| * This software component is licensed by ST under BSD 3-Clause license, |
| * the "License"; You may not use this file except in compliance with the |
| * License. You may obtain a copy of the License at: |
| * opensource.org/licenses/BSD-3-Clause |
| * |
| ****************************************************************************** |
| */ |
| |
| /* Define to prevent recursive inclusion -------------------------------------*/ |
| #ifndef __STM32F2xx_LL_RCC_H |
| #define __STM32F2xx_LL_RCC_H |
| |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| /* Includes ------------------------------------------------------------------*/ |
| #include "stm32f2xx.h" |
| |
| /** @addtogroup STM32F2xx_LL_Driver |
| * @{ |
| */ |
| |
| #if defined(RCC) |
| |
| /** @defgroup RCC_LL RCC |
| * @{ |
| */ |
| |
| /* Private types -------------------------------------------------------------*/ |
| /* Private variables ---------------------------------------------------------*/ |
| /** @defgroup RCC_LL_Private_Variables RCC Private Variables |
| * @{ |
| */ |
| |
| /** |
| * @} |
| */ |
| /* Private constants ---------------------------------------------------------*/ |
| /* Private macros ------------------------------------------------------------*/ |
| #if defined(USE_FULL_LL_DRIVER) |
| /** @defgroup RCC_LL_Private_Macros RCC Private Macros |
| * @{ |
| */ |
| /** |
| * @} |
| */ |
| #endif /*USE_FULL_LL_DRIVER*/ |
| |
| /* Exported types ------------------------------------------------------------*/ |
| #if defined(USE_FULL_LL_DRIVER) |
| /** @defgroup RCC_LL_Exported_Types RCC Exported Types |
| * @{ |
| */ |
| |
| /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure |
| * @{ |
| */ |
| |
| /** |
| * @brief RCC Clocks Frequency Structure |
| */ |
| typedef struct |
| { |
| uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ |
| uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ |
| uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ |
| uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ |
| } LL_RCC_ClocksTypeDef; |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| #endif /* USE_FULL_LL_DRIVER */ |
| |
| /* Exported constants --------------------------------------------------------*/ |
| /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants |
| * @{ |
| */ |
| |
| /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation |
| * @brief Defines used to adapt values of different oscillators |
| * @note These values could be modified in the user environment according to |
| * HW set-up. |
| * @{ |
| */ |
| #if !defined (HSE_VALUE) |
| #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ |
| #endif /* HSE_VALUE */ |
| |
| #if !defined (HSI_VALUE) |
| #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ |
| #endif /* HSI_VALUE */ |
| |
| #if !defined (LSE_VALUE) |
| #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ |
| #endif /* LSE_VALUE */ |
| |
| #if !defined (LSI_VALUE) |
| #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ |
| #endif /* LSI_VALUE */ |
| |
| #if !defined (EXTERNAL_CLOCK_VALUE) |
| #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ |
| #endif /* EXTERNAL_CLOCK_VALUE */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines |
| * @brief Flags defines which can be used with LL_RCC_WriteReg function |
| * @{ |
| */ |
| #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ |
| #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ |
| #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ |
| #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ |
| #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ |
| #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ |
| #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines |
| * @brief Flags defines which can be used with LL_RCC_ReadReg function |
| * @{ |
| */ |
| #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ |
| #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ |
| #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ |
| #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ |
| #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ |
| #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ |
| #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ |
| #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ |
| #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ |
| #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ |
| #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ |
| #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ |
| #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ |
| #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_IT IT Defines |
| * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions |
| * @{ |
| */ |
| #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ |
| #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ |
| #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ |
| #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ |
| #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ |
| #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch |
| * @{ |
| */ |
| #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ |
| #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ |
| #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status |
| * @{ |
| */ |
| #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
| #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
| #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler |
| * @{ |
| */ |
| #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ |
| #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ |
| #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ |
| #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ |
| #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ |
| #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ |
| #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ |
| #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ |
| #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) |
| * @{ |
| */ |
| #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ |
| #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ |
| #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ |
| #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ |
| #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) |
| * @{ |
| */ |
| #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ |
| #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ |
| #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ |
| #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ |
| #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection |
| * @{ |
| */ |
| #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */ |
| #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */ |
| #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */ |
| #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */ |
| #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */ |
| #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */ |
| #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */ |
| #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler |
| * @{ |
| */ |
| #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */ |
| #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */ |
| #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */ |
| #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */ |
| #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */ |
| #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */ |
| #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */ |
| #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */ |
| #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */ |
| #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock |
| * @{ |
| */ |
| #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ |
| #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ |
| #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */ |
| #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ |
| #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */ |
| #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */ |
| #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */ |
| #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ |
| #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */ |
| #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */ |
| #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */ |
| #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */ |
| #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */ |
| #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */ |
| #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */ |
| #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ |
| #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */ |
| #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */ |
| #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */ |
| #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */ |
| #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */ |
| #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */ |
| #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */ |
| #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */ |
| #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */ |
| #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */ |
| #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */ |
| #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */ |
| #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */ |
| #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */ |
| #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */ |
| /** |
| * @} |
| */ |
| |
| #if defined(USE_FULL_LL_DRIVER) |
| /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency |
| * @{ |
| */ |
| #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ |
| #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ |
| /** |
| * @} |
| */ |
| #endif /* USE_FULL_LL_DRIVER */ |
| |
| /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection |
| * @{ |
| */ |
| #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */ |
| #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source |
| * @{ |
| */ |
| #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection |
| * @{ |
| */ |
| #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ |
| #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ |
| #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ |
| #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_PLLSOURCE PLL and PLLI2S entry clock source |
| * @{ |
| */ |
| #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ |
| #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_PLLM_DIV PLL and PLLI2S division factor |
| * @{ |
| */ |
| #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 2 */ |
| #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 3 */ |
| #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 4 */ |
| #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 5 */ |
| #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 6 */ |
| #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 7 */ |
| #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 8 */ |
| #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 9 */ |
| #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 10 */ |
| #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 11 */ |
| #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 12 */ |
| #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 13 */ |
| #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 14 */ |
| #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 15 */ |
| #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL and PLLI2S division factor by 16 */ |
| #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 17 */ |
| #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 18 */ |
| #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 19 */ |
| #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 20 */ |
| #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 21 */ |
| #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 22 */ |
| #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 23 */ |
| #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 24 */ |
| #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 25 */ |
| #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 26 */ |
| #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 27 */ |
| #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 28 */ |
| #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 29 */ |
| #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 30 */ |
| #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 31 */ |
| #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL and PLLI2S division factor by 32 */ |
| #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 33 */ |
| #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 34 */ |
| #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 35 */ |
| #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 36 */ |
| #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 37 */ |
| #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 38 */ |
| #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 39 */ |
| #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 40 */ |
| #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 41 */ |
| #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 42 */ |
| #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 43 */ |
| #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 44 */ |
| #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 45 */ |
| #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 46 */ |
| #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 47 */ |
| #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL and PLLI2S division factor by 48 */ |
| #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 49 */ |
| #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 50 */ |
| #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 51 */ |
| #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 52 */ |
| #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 53 */ |
| #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 54 */ |
| #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 55 */ |
| #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 56 */ |
| #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 57 */ |
| #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 58 */ |
| #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 59 */ |
| #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 60 */ |
| #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 61 */ |
| #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 62 */ |
| #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 63 */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) |
| * @{ |
| */ |
| #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */ |
| #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */ |
| #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */ |
| #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) |
| * @{ |
| */ |
| #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */ |
| #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */ |
| #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */ |
| #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */ |
| #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ |
| #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */ |
| #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */ |
| #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */ |
| #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */ |
| #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */ |
| #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */ |
| #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */ |
| #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */ |
| #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection |
| * @{ |
| */ |
| #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */ |
| #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */ |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) |
| * @{ |
| */ |
| #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */ |
| #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */ |
| #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */ |
| #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */ |
| #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */ |
| #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */ |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| /* Exported macro ------------------------------------------------------------*/ |
| /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros |
| * @{ |
| */ |
| |
| /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros |
| * @{ |
| */ |
| |
| /** |
| * @brief Write a value in RCC register |
| * @param __REG__ Register to be written |
| * @param __VALUE__ Value to be written in the register |
| * @retval None |
| */ |
| #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) |
| |
| /** |
| * @brief Read a value in RCC register |
| * @param __REG__ Register to be read |
| * @retval Register value |
| */ |
| #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies |
| * @{ |
| */ |
| |
| /** |
| * @brief Helper macro to calculate the PLLCLK frequency on system domain |
| * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), |
| * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); |
| * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) |
| * @param __PLLM__ This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLM_DIV_2 |
| * @arg @ref LL_RCC_PLLM_DIV_3 |
| * @arg @ref LL_RCC_PLLM_DIV_4 |
| * @arg @ref LL_RCC_PLLM_DIV_5 |
| * @arg @ref LL_RCC_PLLM_DIV_6 |
| * @arg @ref LL_RCC_PLLM_DIV_7 |
| * @arg @ref LL_RCC_PLLM_DIV_8 |
| * @arg @ref LL_RCC_PLLM_DIV_9 |
| * @arg @ref LL_RCC_PLLM_DIV_10 |
| * @arg @ref LL_RCC_PLLM_DIV_11 |
| * @arg @ref LL_RCC_PLLM_DIV_12 |
| * @arg @ref LL_RCC_PLLM_DIV_13 |
| * @arg @ref LL_RCC_PLLM_DIV_14 |
| * @arg @ref LL_RCC_PLLM_DIV_15 |
| * @arg @ref LL_RCC_PLLM_DIV_16 |
| * @arg @ref LL_RCC_PLLM_DIV_17 |
| * @arg @ref LL_RCC_PLLM_DIV_18 |
| * @arg @ref LL_RCC_PLLM_DIV_19 |
| * @arg @ref LL_RCC_PLLM_DIV_20 |
| * @arg @ref LL_RCC_PLLM_DIV_21 |
| * @arg @ref LL_RCC_PLLM_DIV_22 |
| * @arg @ref LL_RCC_PLLM_DIV_23 |
| * @arg @ref LL_RCC_PLLM_DIV_24 |
| * @arg @ref LL_RCC_PLLM_DIV_25 |
| * @arg @ref LL_RCC_PLLM_DIV_26 |
| * @arg @ref LL_RCC_PLLM_DIV_27 |
| * @arg @ref LL_RCC_PLLM_DIV_28 |
| * @arg @ref LL_RCC_PLLM_DIV_29 |
| * @arg @ref LL_RCC_PLLM_DIV_30 |
| * @arg @ref LL_RCC_PLLM_DIV_31 |
| * @arg @ref LL_RCC_PLLM_DIV_32 |
| * @arg @ref LL_RCC_PLLM_DIV_33 |
| * @arg @ref LL_RCC_PLLM_DIV_34 |
| * @arg @ref LL_RCC_PLLM_DIV_35 |
| * @arg @ref LL_RCC_PLLM_DIV_36 |
| * @arg @ref LL_RCC_PLLM_DIV_37 |
| * @arg @ref LL_RCC_PLLM_DIV_38 |
| * @arg @ref LL_RCC_PLLM_DIV_39 |
| * @arg @ref LL_RCC_PLLM_DIV_40 |
| * @arg @ref LL_RCC_PLLM_DIV_41 |
| * @arg @ref LL_RCC_PLLM_DIV_42 |
| * @arg @ref LL_RCC_PLLM_DIV_43 |
| * @arg @ref LL_RCC_PLLM_DIV_44 |
| * @arg @ref LL_RCC_PLLM_DIV_45 |
| * @arg @ref LL_RCC_PLLM_DIV_46 |
| * @arg @ref LL_RCC_PLLM_DIV_47 |
| * @arg @ref LL_RCC_PLLM_DIV_48 |
| * @arg @ref LL_RCC_PLLM_DIV_49 |
| * @arg @ref LL_RCC_PLLM_DIV_50 |
| * @arg @ref LL_RCC_PLLM_DIV_51 |
| * @arg @ref LL_RCC_PLLM_DIV_52 |
| * @arg @ref LL_RCC_PLLM_DIV_53 |
| * @arg @ref LL_RCC_PLLM_DIV_54 |
| * @arg @ref LL_RCC_PLLM_DIV_55 |
| * @arg @ref LL_RCC_PLLM_DIV_56 |
| * @arg @ref LL_RCC_PLLM_DIV_57 |
| * @arg @ref LL_RCC_PLLM_DIV_58 |
| * @arg @ref LL_RCC_PLLM_DIV_59 |
| * @arg @ref LL_RCC_PLLM_DIV_60 |
| * @arg @ref LL_RCC_PLLM_DIV_61 |
| * @arg @ref LL_RCC_PLLM_DIV_62 |
| * @arg @ref LL_RCC_PLLM_DIV_63 |
| * @param __PLLN__ Between 192 and 432 |
| * @param __PLLP__ This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLP_DIV_2 |
| * @arg @ref LL_RCC_PLLP_DIV_4 |
| * @arg @ref LL_RCC_PLLP_DIV_6 |
| * @arg @ref LL_RCC_PLLP_DIV_8 |
| * @retval PLL clock frequency (in Hz) |
| */ |
| #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ |
| ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) |
| |
| /** |
| * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain |
| * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), |
| * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); |
| * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) |
| * @param __PLLM__ This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLM_DIV_2 |
| * @arg @ref LL_RCC_PLLM_DIV_3 |
| * @arg @ref LL_RCC_PLLM_DIV_4 |
| * @arg @ref LL_RCC_PLLM_DIV_5 |
| * @arg @ref LL_RCC_PLLM_DIV_6 |
| * @arg @ref LL_RCC_PLLM_DIV_7 |
| * @arg @ref LL_RCC_PLLM_DIV_8 |
| * @arg @ref LL_RCC_PLLM_DIV_9 |
| * @arg @ref LL_RCC_PLLM_DIV_10 |
| * @arg @ref LL_RCC_PLLM_DIV_11 |
| * @arg @ref LL_RCC_PLLM_DIV_12 |
| * @arg @ref LL_RCC_PLLM_DIV_13 |
| * @arg @ref LL_RCC_PLLM_DIV_14 |
| * @arg @ref LL_RCC_PLLM_DIV_15 |
| * @arg @ref LL_RCC_PLLM_DIV_16 |
| * @arg @ref LL_RCC_PLLM_DIV_17 |
| * @arg @ref LL_RCC_PLLM_DIV_18 |
| * @arg @ref LL_RCC_PLLM_DIV_19 |
| * @arg @ref LL_RCC_PLLM_DIV_20 |
| * @arg @ref LL_RCC_PLLM_DIV_21 |
| * @arg @ref LL_RCC_PLLM_DIV_22 |
| * @arg @ref LL_RCC_PLLM_DIV_23 |
| * @arg @ref LL_RCC_PLLM_DIV_24 |
| * @arg @ref LL_RCC_PLLM_DIV_25 |
| * @arg @ref LL_RCC_PLLM_DIV_26 |
| * @arg @ref LL_RCC_PLLM_DIV_27 |
| * @arg @ref LL_RCC_PLLM_DIV_28 |
| * @arg @ref LL_RCC_PLLM_DIV_29 |
| * @arg @ref LL_RCC_PLLM_DIV_30 |
| * @arg @ref LL_RCC_PLLM_DIV_31 |
| * @arg @ref LL_RCC_PLLM_DIV_32 |
| * @arg @ref LL_RCC_PLLM_DIV_33 |
| * @arg @ref LL_RCC_PLLM_DIV_34 |
| * @arg @ref LL_RCC_PLLM_DIV_35 |
| * @arg @ref LL_RCC_PLLM_DIV_36 |
| * @arg @ref LL_RCC_PLLM_DIV_37 |
| * @arg @ref LL_RCC_PLLM_DIV_38 |
| * @arg @ref LL_RCC_PLLM_DIV_39 |
| * @arg @ref LL_RCC_PLLM_DIV_40 |
| * @arg @ref LL_RCC_PLLM_DIV_41 |
| * @arg @ref LL_RCC_PLLM_DIV_42 |
| * @arg @ref LL_RCC_PLLM_DIV_43 |
| * @arg @ref LL_RCC_PLLM_DIV_44 |
| * @arg @ref LL_RCC_PLLM_DIV_45 |
| * @arg @ref LL_RCC_PLLM_DIV_46 |
| * @arg @ref LL_RCC_PLLM_DIV_47 |
| * @arg @ref LL_RCC_PLLM_DIV_48 |
| * @arg @ref LL_RCC_PLLM_DIV_49 |
| * @arg @ref LL_RCC_PLLM_DIV_50 |
| * @arg @ref LL_RCC_PLLM_DIV_51 |
| * @arg @ref LL_RCC_PLLM_DIV_52 |
| * @arg @ref LL_RCC_PLLM_DIV_53 |
| * @arg @ref LL_RCC_PLLM_DIV_54 |
| * @arg @ref LL_RCC_PLLM_DIV_55 |
| * @arg @ref LL_RCC_PLLM_DIV_56 |
| * @arg @ref LL_RCC_PLLM_DIV_57 |
| * @arg @ref LL_RCC_PLLM_DIV_58 |
| * @arg @ref LL_RCC_PLLM_DIV_59 |
| * @arg @ref LL_RCC_PLLM_DIV_60 |
| * @arg @ref LL_RCC_PLLM_DIV_61 |
| * @arg @ref LL_RCC_PLLM_DIV_62 |
| * @arg @ref LL_RCC_PLLM_DIV_63 |
| * @param __PLLN__ Between 192 and 432 |
| * @param __PLLQ__ This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLQ_DIV_2 |
| * @arg @ref LL_RCC_PLLQ_DIV_3 |
| * @arg @ref LL_RCC_PLLQ_DIV_4 |
| * @arg @ref LL_RCC_PLLQ_DIV_5 |
| * @arg @ref LL_RCC_PLLQ_DIV_6 |
| * @arg @ref LL_RCC_PLLQ_DIV_7 |
| * @arg @ref LL_RCC_PLLQ_DIV_8 |
| * @arg @ref LL_RCC_PLLQ_DIV_9 |
| * @arg @ref LL_RCC_PLLQ_DIV_10 |
| * @arg @ref LL_RCC_PLLQ_DIV_11 |
| * @arg @ref LL_RCC_PLLQ_DIV_12 |
| * @arg @ref LL_RCC_PLLQ_DIV_13 |
| * @arg @ref LL_RCC_PLLQ_DIV_14 |
| * @arg @ref LL_RCC_PLLQ_DIV_15 |
| * @retval PLL clock frequency (in Hz) |
| */ |
| #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ |
| ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) |
| |
| /** |
| * @retval PLLI2S clock frequency (in Hz) |
| */ |
| |
| /** |
| * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain |
| * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), |
| * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); |
| * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) |
| * @param __PLLM__ This parameter can be one of the following values: |
| * @param __PLLI2SN__ Between 192 and 432 |
| * @param __PLLI2SR__ This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLI2SR_DIV_2 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_3 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_4 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_5 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_6 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_7 |
| * @retval PLLI2S clock frequency (in Hz) |
| */ |
| #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ |
| ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) |
| |
| /** |
| * @brief Helper macro to calculate the HCLK frequency |
| * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) |
| * @param __AHBPRESCALER__ This parameter can be one of the following values: |
| * @arg @ref LL_RCC_SYSCLK_DIV_1 |
| * @arg @ref LL_RCC_SYSCLK_DIV_2 |
| * @arg @ref LL_RCC_SYSCLK_DIV_4 |
| * @arg @ref LL_RCC_SYSCLK_DIV_8 |
| * @arg @ref LL_RCC_SYSCLK_DIV_16 |
| * @arg @ref LL_RCC_SYSCLK_DIV_64 |
| * @arg @ref LL_RCC_SYSCLK_DIV_128 |
| * @arg @ref LL_RCC_SYSCLK_DIV_256 |
| * @arg @ref LL_RCC_SYSCLK_DIV_512 |
| * @retval HCLK clock frequency (in Hz) |
| */ |
| #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) |
| |
| /** |
| * @brief Helper macro to calculate the PCLK1 frequency (ABP1) |
| * @param __HCLKFREQ__ HCLK frequency |
| * @param __APB1PRESCALER__ This parameter can be one of the following values: |
| * @arg @ref LL_RCC_APB1_DIV_1 |
| * @arg @ref LL_RCC_APB1_DIV_2 |
| * @arg @ref LL_RCC_APB1_DIV_4 |
| * @arg @ref LL_RCC_APB1_DIV_8 |
| * @arg @ref LL_RCC_APB1_DIV_16 |
| * @retval PCLK1 clock frequency (in Hz) |
| */ |
| #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) |
| |
| /** |
| * @brief Helper macro to calculate the PCLK2 frequency (ABP2) |
| * @param __HCLKFREQ__ HCLK frequency |
| * @param __APB2PRESCALER__ This parameter can be one of the following values: |
| * @arg @ref LL_RCC_APB2_DIV_1 |
| * @arg @ref LL_RCC_APB2_DIV_2 |
| * @arg @ref LL_RCC_APB2_DIV_4 |
| * @arg @ref LL_RCC_APB2_DIV_8 |
| * @arg @ref LL_RCC_APB2_DIV_16 |
| * @retval PCLK2 clock frequency (in Hz) |
| */ |
| #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| /* Exported functions --------------------------------------------------------*/ |
| /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions |
| * @{ |
| */ |
| |
| /** @defgroup RCC_LL_EF_HSE HSE |
| * @{ |
| */ |
| |
| /** |
| * @brief Enable the Clock Security System. |
| * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) |
| { |
| SET_BIT(RCC->CR, RCC_CR_CSSON); |
| } |
| |
| /** |
| * @brief Enable HSE external oscillator (HSE Bypass) |
| * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) |
| { |
| SET_BIT(RCC->CR, RCC_CR_HSEBYP); |
| } |
| |
| /** |
| * @brief Disable HSE external oscillator (HSE Bypass) |
| * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) |
| { |
| CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
| } |
| |
| /** |
| * @brief Enable HSE crystal oscillator (HSE ON) |
| * @rmtoll CR HSEON LL_RCC_HSE_Enable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_HSE_Enable(void) |
| { |
| SET_BIT(RCC->CR, RCC_CR_HSEON); |
| } |
| |
| /** |
| * @brief Disable HSE crystal oscillator (HSE ON) |
| * @rmtoll CR HSEON LL_RCC_HSE_Disable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_HSE_Disable(void) |
| { |
| CLEAR_BIT(RCC->CR, RCC_CR_HSEON); |
| } |
| |
| /** |
| * @brief Check if HSE oscillator Ready |
| * @rmtoll CR HSERDY LL_RCC_HSE_IsReady |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) |
| { |
| return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_HSI HSI |
| * @{ |
| */ |
| |
| /** |
| * @brief Enable HSI oscillator |
| * @rmtoll CR HSION LL_RCC_HSI_Enable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_HSI_Enable(void) |
| { |
| SET_BIT(RCC->CR, RCC_CR_HSION); |
| } |
| |
| /** |
| * @brief Disable HSI oscillator |
| * @rmtoll CR HSION LL_RCC_HSI_Disable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_HSI_Disable(void) |
| { |
| CLEAR_BIT(RCC->CR, RCC_CR_HSION); |
| } |
| |
| /** |
| * @brief Check if HSI clock is ready |
| * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) |
| { |
| return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); |
| } |
| |
| /** |
| * @brief Get HSI Calibration value |
| * @note When HSITRIM is written, HSICAL is updated with the sum of |
| * HSITRIM and the factory trim value |
| * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration |
| * @retval Between Min_Data = 0x00 and Max_Data = 0xFF |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); |
| } |
| |
| /** |
| * @brief Set HSI Calibration trimming |
| * @note user-programmable trimming value that is added to the HSICAL |
| * @note Default value is 16, which, when added to the HSICAL value, |
| * should trim the HSI to 16 MHz +/- 1 % |
| * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming |
| * @param Value Between Min_Data = 0 and Max_Data = 31 |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) |
| { |
| MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); |
| } |
| |
| /** |
| * @brief Get HSI Calibration trimming |
| * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming |
| * @retval Between Min_Data = 0 and Max_Data = 31 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_LSE LSE |
| * @{ |
| */ |
| |
| /** |
| * @brief Enable Low Speed External (LSE) crystal. |
| * @rmtoll BDCR LSEON LL_RCC_LSE_Enable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_LSE_Enable(void) |
| { |
| SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); |
| } |
| |
| /** |
| * @brief Disable Low Speed External (LSE) crystal. |
| * @rmtoll BDCR LSEON LL_RCC_LSE_Disable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_LSE_Disable(void) |
| { |
| CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); |
| } |
| |
| /** |
| * @brief Enable external clock source (LSE bypass). |
| * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) |
| { |
| SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); |
| } |
| |
| /** |
| * @brief Disable external clock source (LSE bypass). |
| * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) |
| { |
| CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); |
| } |
| |
| /** |
| * @brief Check if LSE oscillator Ready |
| * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) |
| { |
| return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_LSI LSI |
| * @{ |
| */ |
| |
| /** |
| * @brief Enable LSI Oscillator |
| * @rmtoll CSR LSION LL_RCC_LSI_Enable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_LSI_Enable(void) |
| { |
| SET_BIT(RCC->CSR, RCC_CSR_LSION); |
| } |
| |
| /** |
| * @brief Disable LSI Oscillator |
| * @rmtoll CSR LSION LL_RCC_LSI_Disable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_LSI_Disable(void) |
| { |
| CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); |
| } |
| |
| /** |
| * @brief Check if LSI is Ready |
| * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) |
| { |
| return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_System System |
| * @{ |
| */ |
| |
| /** |
| * @brief Configure the system clock source |
| * @rmtoll CFGR SW LL_RCC_SetSysClkSource |
| * @param Source This parameter can be one of the following values: |
| * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI |
| * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE |
| * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) |
| { |
| MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); |
| } |
| |
| /** |
| * @brief Get the system clock source |
| * @rmtoll CFGR SWS LL_RCC_GetSysClkSource |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI |
| * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE |
| * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); |
| } |
| |
| /** |
| * @brief Set AHB prescaler |
| * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler |
| * @param Prescaler This parameter can be one of the following values: |
| * @arg @ref LL_RCC_SYSCLK_DIV_1 |
| * @arg @ref LL_RCC_SYSCLK_DIV_2 |
| * @arg @ref LL_RCC_SYSCLK_DIV_4 |
| * @arg @ref LL_RCC_SYSCLK_DIV_8 |
| * @arg @ref LL_RCC_SYSCLK_DIV_16 |
| * @arg @ref LL_RCC_SYSCLK_DIV_64 |
| * @arg @ref LL_RCC_SYSCLK_DIV_128 |
| * @arg @ref LL_RCC_SYSCLK_DIV_256 |
| * @arg @ref LL_RCC_SYSCLK_DIV_512 |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) |
| { |
| MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); |
| } |
| |
| /** |
| * @brief Set APB1 prescaler |
| * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler |
| * @param Prescaler This parameter can be one of the following values: |
| * @arg @ref LL_RCC_APB1_DIV_1 |
| * @arg @ref LL_RCC_APB1_DIV_2 |
| * @arg @ref LL_RCC_APB1_DIV_4 |
| * @arg @ref LL_RCC_APB1_DIV_8 |
| * @arg @ref LL_RCC_APB1_DIV_16 |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) |
| { |
| MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); |
| } |
| |
| /** |
| * @brief Set APB2 prescaler |
| * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler |
| * @param Prescaler This parameter can be one of the following values: |
| * @arg @ref LL_RCC_APB2_DIV_1 |
| * @arg @ref LL_RCC_APB2_DIV_2 |
| * @arg @ref LL_RCC_APB2_DIV_4 |
| * @arg @ref LL_RCC_APB2_DIV_8 |
| * @arg @ref LL_RCC_APB2_DIV_16 |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) |
| { |
| MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); |
| } |
| |
| /** |
| * @brief Get AHB prescaler |
| * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_SYSCLK_DIV_1 |
| * @arg @ref LL_RCC_SYSCLK_DIV_2 |
| * @arg @ref LL_RCC_SYSCLK_DIV_4 |
| * @arg @ref LL_RCC_SYSCLK_DIV_8 |
| * @arg @ref LL_RCC_SYSCLK_DIV_16 |
| * @arg @ref LL_RCC_SYSCLK_DIV_64 |
| * @arg @ref LL_RCC_SYSCLK_DIV_128 |
| * @arg @ref LL_RCC_SYSCLK_DIV_256 |
| * @arg @ref LL_RCC_SYSCLK_DIV_512 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); |
| } |
| |
| /** |
| * @brief Get APB1 prescaler |
| * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_APB1_DIV_1 |
| * @arg @ref LL_RCC_APB1_DIV_2 |
| * @arg @ref LL_RCC_APB1_DIV_4 |
| * @arg @ref LL_RCC_APB1_DIV_8 |
| * @arg @ref LL_RCC_APB1_DIV_16 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); |
| } |
| |
| /** |
| * @brief Get APB2 prescaler |
| * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_APB2_DIV_1 |
| * @arg @ref LL_RCC_APB2_DIV_2 |
| * @arg @ref LL_RCC_APB2_DIV_4 |
| * @arg @ref LL_RCC_APB2_DIV_8 |
| * @arg @ref LL_RCC_APB2_DIV_16 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_MCO MCO |
| * @{ |
| */ |
| |
| /** |
| * @brief Configure MCOx |
| * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n |
| * CFGR MCO1PRE LL_RCC_ConfigMCO\n |
| * CFGR MCO2 LL_RCC_ConfigMCO\n |
| * CFGR MCO2PRE LL_RCC_ConfigMCO |
| * @param MCOxSource This parameter can be one of the following values: |
| * @arg @ref LL_RCC_MCO1SOURCE_HSI |
| * @arg @ref LL_RCC_MCO1SOURCE_LSE |
| * @arg @ref LL_RCC_MCO1SOURCE_HSE |
| * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK |
| * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK |
| * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S |
| * @arg @ref LL_RCC_MCO2SOURCE_HSE |
| * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK |
| * @param MCOxPrescaler This parameter can be one of the following values: |
| * @arg @ref LL_RCC_MCO1_DIV_1 |
| * @arg @ref LL_RCC_MCO1_DIV_2 |
| * @arg @ref LL_RCC_MCO1_DIV_3 |
| * @arg @ref LL_RCC_MCO1_DIV_4 |
| * @arg @ref LL_RCC_MCO1_DIV_5 |
| * @arg @ref LL_RCC_MCO2_DIV_1 |
| * @arg @ref LL_RCC_MCO2_DIV_2 |
| * @arg @ref LL_RCC_MCO2_DIV_3 |
| * @arg @ref LL_RCC_MCO2_DIV_4 |
| * @arg @ref LL_RCC_MCO2_DIV_5 |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) |
| { |
| MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U)); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source |
| * @{ |
| */ |
| |
| /** |
| * @brief Configure I2S clock source |
| * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource |
| * @param Source This parameter can be one of the following values: |
| * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S |
| * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) |
| { |
| MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); |
| } |
| |
| /** |
| * @brief Get I2S Clock Source |
| * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource |
| * @param I2Sx This parameter can be one of the following values: |
| * @arg @ref LL_RCC_I2S1_CLKSOURCE |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S |
| * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) |
| { |
| return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_RTC RTC |
| * @{ |
| */ |
| |
| /** |
| * @brief Set RTC Clock Source |
| * @note Once the RTC clock source has been selected, it cannot be changed anymore unless |
| * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is |
| * set). The BDRST bit can be used to reset them. |
| * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource |
| * @param Source This parameter can be one of the following values: |
| * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
| * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
| * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
| * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) |
| { |
| MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); |
| } |
| |
| /** |
| * @brief Get RTC Clock Source |
| * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE |
| * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE |
| * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI |
| * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); |
| } |
| |
| /** |
| * @brief Enable RTC |
| * @rmtoll BDCR RTCEN LL_RCC_EnableRTC |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_EnableRTC(void) |
| { |
| SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); |
| } |
| |
| /** |
| * @brief Disable RTC |
| * @rmtoll BDCR RTCEN LL_RCC_DisableRTC |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_DisableRTC(void) |
| { |
| CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); |
| } |
| |
| /** |
| * @brief Check if RTC has been enabled or not |
| * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) |
| { |
| return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); |
| } |
| |
| /** |
| * @brief Force the Backup domain reset |
| * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) |
| { |
| SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); |
| } |
| |
| /** |
| * @brief Release the Backup domain reset |
| * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) |
| { |
| CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); |
| } |
| |
| /** |
| * @brief Set HSE Prescalers for RTC Clock |
| * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler |
| * @param Prescaler This parameter can be one of the following values: |
| * @arg @ref LL_RCC_RTC_NOCLOCK |
| * @arg @ref LL_RCC_RTC_HSE_DIV_2 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_3 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_4 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_5 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_6 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_7 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_8 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_9 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_10 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_11 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_12 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_13 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_14 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_15 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_16 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_17 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_18 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_19 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_20 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_21 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_22 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_23 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_24 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_25 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_26 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_27 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_28 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_29 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_30 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_31 |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) |
| { |
| MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); |
| } |
| |
| /** |
| * @brief Get HSE Prescalers for RTC Clock |
| * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_RTC_NOCLOCK |
| * @arg @ref LL_RCC_RTC_HSE_DIV_2 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_3 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_4 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_5 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_6 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_7 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_8 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_9 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_10 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_11 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_12 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_13 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_14 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_15 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_16 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_17 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_18 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_19 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_20 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_21 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_22 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_23 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_24 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_25 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_26 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_27 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_28 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_29 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_30 |
| * @arg @ref LL_RCC_RTC_HSE_DIV_31 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_PLL PLL |
| * @{ |
| */ |
| |
| /** |
| * @brief Enable PLL |
| * @rmtoll CR PLLON LL_RCC_PLL_Enable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_PLL_Enable(void) |
| { |
| SET_BIT(RCC->CR, RCC_CR_PLLON); |
| } |
| |
| /** |
| * @brief Disable PLL |
| * @note Cannot be disabled if the PLL clock is used as the system clock |
| * @rmtoll CR PLLON LL_RCC_PLL_Disable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_PLL_Disable(void) |
| { |
| CLEAR_BIT(RCC->CR, RCC_CR_PLLON); |
| } |
| |
| /** |
| * @brief Check if PLL Ready |
| * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) |
| { |
| return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); |
| } |
| |
| /** |
| * @brief Configure PLL used for SYSCLK Domain |
| * @note PLL Source and PLLM Divider can be written only when PLL, |
| * PLLI2S are disabled |
| * @note PLLN/PLLP can be written only when PLL is disabled |
| * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n |
| * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n |
| * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n |
| * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS |
| * @param Source This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLSOURCE_HSI |
| * @arg @ref LL_RCC_PLLSOURCE_HSE |
| * @param PLLM This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLM_DIV_2 |
| * @arg @ref LL_RCC_PLLM_DIV_3 |
| * @arg @ref LL_RCC_PLLM_DIV_4 |
| * @arg @ref LL_RCC_PLLM_DIV_5 |
| * @arg @ref LL_RCC_PLLM_DIV_6 |
| * @arg @ref LL_RCC_PLLM_DIV_7 |
| * @arg @ref LL_RCC_PLLM_DIV_8 |
| * @arg @ref LL_RCC_PLLM_DIV_9 |
| * @arg @ref LL_RCC_PLLM_DIV_10 |
| * @arg @ref LL_RCC_PLLM_DIV_11 |
| * @arg @ref LL_RCC_PLLM_DIV_12 |
| * @arg @ref LL_RCC_PLLM_DIV_13 |
| * @arg @ref LL_RCC_PLLM_DIV_14 |
| * @arg @ref LL_RCC_PLLM_DIV_15 |
| * @arg @ref LL_RCC_PLLM_DIV_16 |
| * @arg @ref LL_RCC_PLLM_DIV_17 |
| * @arg @ref LL_RCC_PLLM_DIV_18 |
| * @arg @ref LL_RCC_PLLM_DIV_19 |
| * @arg @ref LL_RCC_PLLM_DIV_20 |
| * @arg @ref LL_RCC_PLLM_DIV_21 |
| * @arg @ref LL_RCC_PLLM_DIV_22 |
| * @arg @ref LL_RCC_PLLM_DIV_23 |
| * @arg @ref LL_RCC_PLLM_DIV_24 |
| * @arg @ref LL_RCC_PLLM_DIV_25 |
| * @arg @ref LL_RCC_PLLM_DIV_26 |
| * @arg @ref LL_RCC_PLLM_DIV_27 |
| * @arg @ref LL_RCC_PLLM_DIV_28 |
| * @arg @ref LL_RCC_PLLM_DIV_29 |
| * @arg @ref LL_RCC_PLLM_DIV_30 |
| * @arg @ref LL_RCC_PLLM_DIV_31 |
| * @arg @ref LL_RCC_PLLM_DIV_32 |
| * @arg @ref LL_RCC_PLLM_DIV_33 |
| * @arg @ref LL_RCC_PLLM_DIV_34 |
| * @arg @ref LL_RCC_PLLM_DIV_35 |
| * @arg @ref LL_RCC_PLLM_DIV_36 |
| * @arg @ref LL_RCC_PLLM_DIV_37 |
| * @arg @ref LL_RCC_PLLM_DIV_38 |
| * @arg @ref LL_RCC_PLLM_DIV_39 |
| * @arg @ref LL_RCC_PLLM_DIV_40 |
| * @arg @ref LL_RCC_PLLM_DIV_41 |
| * @arg @ref LL_RCC_PLLM_DIV_42 |
| * @arg @ref LL_RCC_PLLM_DIV_43 |
| * @arg @ref LL_RCC_PLLM_DIV_44 |
| * @arg @ref LL_RCC_PLLM_DIV_45 |
| * @arg @ref LL_RCC_PLLM_DIV_46 |
| * @arg @ref LL_RCC_PLLM_DIV_47 |
| * @arg @ref LL_RCC_PLLM_DIV_48 |
| * @arg @ref LL_RCC_PLLM_DIV_49 |
| * @arg @ref LL_RCC_PLLM_DIV_50 |
| * @arg @ref LL_RCC_PLLM_DIV_51 |
| * @arg @ref LL_RCC_PLLM_DIV_52 |
| * @arg @ref LL_RCC_PLLM_DIV_53 |
| * @arg @ref LL_RCC_PLLM_DIV_54 |
| * @arg @ref LL_RCC_PLLM_DIV_55 |
| * @arg @ref LL_RCC_PLLM_DIV_56 |
| * @arg @ref LL_RCC_PLLM_DIV_57 |
| * @arg @ref LL_RCC_PLLM_DIV_58 |
| * @arg @ref LL_RCC_PLLM_DIV_59 |
| * @arg @ref LL_RCC_PLLM_DIV_60 |
| * @arg @ref LL_RCC_PLLM_DIV_61 |
| * @arg @ref LL_RCC_PLLM_DIV_62 |
| * @arg @ref LL_RCC_PLLM_DIV_63 |
| * @param PLLN Between 192 and 432 |
| * @param PLLP This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLP_DIV_2 |
| * @arg @ref LL_RCC_PLLP_DIV_4 |
| * @arg @ref LL_RCC_PLLP_DIV_6 |
| * @arg @ref LL_RCC_PLLP_DIV_8 |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) |
| { |
| MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, |
| Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); |
| } |
| |
| /** |
| * @brief Configure PLL used for 48Mhz domain clock |
| * @note PLL Source and PLLM Divider can be written only when PLL, |
| * PLLI2S are disabled |
| * @note PLLN/PLLQ can be written only when PLL is disabled |
| * @note This can be selected for USB, RNG, SDIO |
| * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n |
| * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n |
| * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n |
| * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M |
| * @param Source This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLSOURCE_HSI |
| * @arg @ref LL_RCC_PLLSOURCE_HSE |
| * @param PLLM This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLM_DIV_2 |
| * @arg @ref LL_RCC_PLLM_DIV_3 |
| * @arg @ref LL_RCC_PLLM_DIV_4 |
| * @arg @ref LL_RCC_PLLM_DIV_5 |
| * @arg @ref LL_RCC_PLLM_DIV_6 |
| * @arg @ref LL_RCC_PLLM_DIV_7 |
| * @arg @ref LL_RCC_PLLM_DIV_8 |
| * @arg @ref LL_RCC_PLLM_DIV_9 |
| * @arg @ref LL_RCC_PLLM_DIV_10 |
| * @arg @ref LL_RCC_PLLM_DIV_11 |
| * @arg @ref LL_RCC_PLLM_DIV_12 |
| * @arg @ref LL_RCC_PLLM_DIV_13 |
| * @arg @ref LL_RCC_PLLM_DIV_14 |
| * @arg @ref LL_RCC_PLLM_DIV_15 |
| * @arg @ref LL_RCC_PLLM_DIV_16 |
| * @arg @ref LL_RCC_PLLM_DIV_17 |
| * @arg @ref LL_RCC_PLLM_DIV_18 |
| * @arg @ref LL_RCC_PLLM_DIV_19 |
| * @arg @ref LL_RCC_PLLM_DIV_20 |
| * @arg @ref LL_RCC_PLLM_DIV_21 |
| * @arg @ref LL_RCC_PLLM_DIV_22 |
| * @arg @ref LL_RCC_PLLM_DIV_23 |
| * @arg @ref LL_RCC_PLLM_DIV_24 |
| * @arg @ref LL_RCC_PLLM_DIV_25 |
| * @arg @ref LL_RCC_PLLM_DIV_26 |
| * @arg @ref LL_RCC_PLLM_DIV_27 |
| * @arg @ref LL_RCC_PLLM_DIV_28 |
| * @arg @ref LL_RCC_PLLM_DIV_29 |
| * @arg @ref LL_RCC_PLLM_DIV_30 |
| * @arg @ref LL_RCC_PLLM_DIV_31 |
| * @arg @ref LL_RCC_PLLM_DIV_32 |
| * @arg @ref LL_RCC_PLLM_DIV_33 |
| * @arg @ref LL_RCC_PLLM_DIV_34 |
| * @arg @ref LL_RCC_PLLM_DIV_35 |
| * @arg @ref LL_RCC_PLLM_DIV_36 |
| * @arg @ref LL_RCC_PLLM_DIV_37 |
| * @arg @ref LL_RCC_PLLM_DIV_38 |
| * @arg @ref LL_RCC_PLLM_DIV_39 |
| * @arg @ref LL_RCC_PLLM_DIV_40 |
| * @arg @ref LL_RCC_PLLM_DIV_41 |
| * @arg @ref LL_RCC_PLLM_DIV_42 |
| * @arg @ref LL_RCC_PLLM_DIV_43 |
| * @arg @ref LL_RCC_PLLM_DIV_44 |
| * @arg @ref LL_RCC_PLLM_DIV_45 |
| * @arg @ref LL_RCC_PLLM_DIV_46 |
| * @arg @ref LL_RCC_PLLM_DIV_47 |
| * @arg @ref LL_RCC_PLLM_DIV_48 |
| * @arg @ref LL_RCC_PLLM_DIV_49 |
| * @arg @ref LL_RCC_PLLM_DIV_50 |
| * @arg @ref LL_RCC_PLLM_DIV_51 |
| * @arg @ref LL_RCC_PLLM_DIV_52 |
| * @arg @ref LL_RCC_PLLM_DIV_53 |
| * @arg @ref LL_RCC_PLLM_DIV_54 |
| * @arg @ref LL_RCC_PLLM_DIV_55 |
| * @arg @ref LL_RCC_PLLM_DIV_56 |
| * @arg @ref LL_RCC_PLLM_DIV_57 |
| * @arg @ref LL_RCC_PLLM_DIV_58 |
| * @arg @ref LL_RCC_PLLM_DIV_59 |
| * @arg @ref LL_RCC_PLLM_DIV_60 |
| * @arg @ref LL_RCC_PLLM_DIV_61 |
| * @arg @ref LL_RCC_PLLM_DIV_62 |
| * @arg @ref LL_RCC_PLLM_DIV_63 |
| * @param PLLN Between 192 and 432 |
| * @param PLLQ This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLQ_DIV_2 |
| * @arg @ref LL_RCC_PLLQ_DIV_3 |
| * @arg @ref LL_RCC_PLLQ_DIV_4 |
| * @arg @ref LL_RCC_PLLQ_DIV_5 |
| * @arg @ref LL_RCC_PLLQ_DIV_6 |
| * @arg @ref LL_RCC_PLLQ_DIV_7 |
| * @arg @ref LL_RCC_PLLQ_DIV_8 |
| * @arg @ref LL_RCC_PLLQ_DIV_9 |
| * @arg @ref LL_RCC_PLLQ_DIV_10 |
| * @arg @ref LL_RCC_PLLQ_DIV_11 |
| * @arg @ref LL_RCC_PLLQ_DIV_12 |
| * @arg @ref LL_RCC_PLLQ_DIV_13 |
| * @arg @ref LL_RCC_PLLQ_DIV_14 |
| * @arg @ref LL_RCC_PLLQ_DIV_15 |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) |
| { |
| MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, |
| Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); |
| } |
| |
| /** |
| * @brief Get Main PLL multiplication factor for VCO |
| * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN |
| * @retval Between 192 and 432 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); |
| } |
| |
| /** |
| * @brief Get Main PLL division factor for PLLP |
| * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_PLLP_DIV_2 |
| * @arg @ref LL_RCC_PLLP_DIV_4 |
| * @arg @ref LL_RCC_PLLP_DIV_6 |
| * @arg @ref LL_RCC_PLLP_DIV_8 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); |
| } |
| |
| /** |
| * @brief Get Main PLL division factor for PLLQ |
| * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock) |
| * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_PLLQ_DIV_2 |
| * @arg @ref LL_RCC_PLLQ_DIV_3 |
| * @arg @ref LL_RCC_PLLQ_DIV_4 |
| * @arg @ref LL_RCC_PLLQ_DIV_5 |
| * @arg @ref LL_RCC_PLLQ_DIV_6 |
| * @arg @ref LL_RCC_PLLQ_DIV_7 |
| * @arg @ref LL_RCC_PLLQ_DIV_8 |
| * @arg @ref LL_RCC_PLLQ_DIV_9 |
| * @arg @ref LL_RCC_PLLQ_DIV_10 |
| * @arg @ref LL_RCC_PLLQ_DIV_11 |
| * @arg @ref LL_RCC_PLLQ_DIV_12 |
| * @arg @ref LL_RCC_PLLQ_DIV_13 |
| * @arg @ref LL_RCC_PLLQ_DIV_14 |
| * @arg @ref LL_RCC_PLLQ_DIV_15 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); |
| } |
| |
| /** |
| * @brief Get the oscillator used as PLL clock source. |
| * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_PLLSOURCE_HSI |
| * @arg @ref LL_RCC_PLLSOURCE_HSE |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); |
| } |
| |
| /** |
| * @brief Get Division factor for the main PLL and other PLL |
| * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_PLLM_DIV_2 |
| * @arg @ref LL_RCC_PLLM_DIV_3 |
| * @arg @ref LL_RCC_PLLM_DIV_4 |
| * @arg @ref LL_RCC_PLLM_DIV_5 |
| * @arg @ref LL_RCC_PLLM_DIV_6 |
| * @arg @ref LL_RCC_PLLM_DIV_7 |
| * @arg @ref LL_RCC_PLLM_DIV_8 |
| * @arg @ref LL_RCC_PLLM_DIV_9 |
| * @arg @ref LL_RCC_PLLM_DIV_10 |
| * @arg @ref LL_RCC_PLLM_DIV_11 |
| * @arg @ref LL_RCC_PLLM_DIV_12 |
| * @arg @ref LL_RCC_PLLM_DIV_13 |
| * @arg @ref LL_RCC_PLLM_DIV_14 |
| * @arg @ref LL_RCC_PLLM_DIV_15 |
| * @arg @ref LL_RCC_PLLM_DIV_16 |
| * @arg @ref LL_RCC_PLLM_DIV_17 |
| * @arg @ref LL_RCC_PLLM_DIV_18 |
| * @arg @ref LL_RCC_PLLM_DIV_19 |
| * @arg @ref LL_RCC_PLLM_DIV_20 |
| * @arg @ref LL_RCC_PLLM_DIV_21 |
| * @arg @ref LL_RCC_PLLM_DIV_22 |
| * @arg @ref LL_RCC_PLLM_DIV_23 |
| * @arg @ref LL_RCC_PLLM_DIV_24 |
| * @arg @ref LL_RCC_PLLM_DIV_25 |
| * @arg @ref LL_RCC_PLLM_DIV_26 |
| * @arg @ref LL_RCC_PLLM_DIV_27 |
| * @arg @ref LL_RCC_PLLM_DIV_28 |
| * @arg @ref LL_RCC_PLLM_DIV_29 |
| * @arg @ref LL_RCC_PLLM_DIV_30 |
| * @arg @ref LL_RCC_PLLM_DIV_31 |
| * @arg @ref LL_RCC_PLLM_DIV_32 |
| * @arg @ref LL_RCC_PLLM_DIV_33 |
| * @arg @ref LL_RCC_PLLM_DIV_34 |
| * @arg @ref LL_RCC_PLLM_DIV_35 |
| * @arg @ref LL_RCC_PLLM_DIV_36 |
| * @arg @ref LL_RCC_PLLM_DIV_37 |
| * @arg @ref LL_RCC_PLLM_DIV_38 |
| * @arg @ref LL_RCC_PLLM_DIV_39 |
| * @arg @ref LL_RCC_PLLM_DIV_40 |
| * @arg @ref LL_RCC_PLLM_DIV_41 |
| * @arg @ref LL_RCC_PLLM_DIV_42 |
| * @arg @ref LL_RCC_PLLM_DIV_43 |
| * @arg @ref LL_RCC_PLLM_DIV_44 |
| * @arg @ref LL_RCC_PLLM_DIV_45 |
| * @arg @ref LL_RCC_PLLM_DIV_46 |
| * @arg @ref LL_RCC_PLLM_DIV_47 |
| * @arg @ref LL_RCC_PLLM_DIV_48 |
| * @arg @ref LL_RCC_PLLM_DIV_49 |
| * @arg @ref LL_RCC_PLLM_DIV_50 |
| * @arg @ref LL_RCC_PLLM_DIV_51 |
| * @arg @ref LL_RCC_PLLM_DIV_52 |
| * @arg @ref LL_RCC_PLLM_DIV_53 |
| * @arg @ref LL_RCC_PLLM_DIV_54 |
| * @arg @ref LL_RCC_PLLM_DIV_55 |
| * @arg @ref LL_RCC_PLLM_DIV_56 |
| * @arg @ref LL_RCC_PLLM_DIV_57 |
| * @arg @ref LL_RCC_PLLM_DIV_58 |
| * @arg @ref LL_RCC_PLLM_DIV_59 |
| * @arg @ref LL_RCC_PLLM_DIV_60 |
| * @arg @ref LL_RCC_PLLM_DIV_61 |
| * @arg @ref LL_RCC_PLLM_DIV_62 |
| * @arg @ref LL_RCC_PLLM_DIV_63 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); |
| } |
| |
| /** |
| * @brief Configure Spread Spectrum used for PLL |
| * @note These bits must be written before enabling PLL |
| * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n |
| * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n |
| * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum |
| * @param Mod Between Min_Data=0 and Max_Data=8191 |
| * @param Inc Between Min_Data=0 and Max_Data=32767 |
| * @param Sel This parameter can be one of the following values: |
| * @arg @ref LL_RCC_SPREAD_SELECT_CENTER |
| * @arg @ref LL_RCC_SPREAD_SELECT_DOWN |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) |
| { |
| MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel); |
| } |
| |
| /** |
| * @brief Get Spread Spectrum Modulation Period for PLL |
| * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation |
| * @retval Between Min_Data=0 and Max_Data=8191 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); |
| } |
| |
| /** |
| * @brief Get Spread Spectrum Incrementation Step for PLL |
| * @note Must be written before enabling PLL |
| * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation |
| * @retval Between Min_Data=0 and Max_Data=32767 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); |
| } |
| |
| /** |
| * @brief Get Spread Spectrum Selection for PLL |
| * @note Must be written before enabling PLL |
| * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_SPREAD_SELECT_CENTER |
| * @arg @ref LL_RCC_SPREAD_SELECT_DOWN |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); |
| } |
| |
| /** |
| * @brief Enable Spread Spectrum for PLL. |
| * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) |
| { |
| SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); |
| } |
| |
| /** |
| * @brief Disable Spread Spectrum for PLL. |
| * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) |
| { |
| CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_PLLI2S PLLI2S |
| * @{ |
| */ |
| |
| /** |
| * @brief Enable PLLI2S |
| * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) |
| { |
| SET_BIT(RCC->CR, RCC_CR_PLLI2SON); |
| } |
| |
| /** |
| * @brief Disable PLLI2S |
| * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) |
| { |
| CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); |
| } |
| |
| /** |
| * @brief Check if PLLI2S Ready |
| * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) |
| { |
| return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); |
| } |
| |
| /** |
| * @brief Configure PLLI2S used for I2S1 domain clock |
| * @note PLL Source and PLLM Divider can be written only when PLL, |
| * PLLI2S are disabled |
| * @note PLLN/PLLR can be written only when PLLI2S is disabled |
| * @note This can be selected for I2S |
| * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n |
| * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n |
| * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n |
| * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S |
| * @param Source This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLSOURCE_HSI |
| * @arg @ref LL_RCC_PLLSOURCE_HSE |
| * @param PLLM This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLM_DIV_2 |
| * @arg @ref LL_RCC_PLLM_DIV_3 |
| * @arg @ref LL_RCC_PLLM_DIV_4 |
| * @arg @ref LL_RCC_PLLM_DIV_5 |
| * @arg @ref LL_RCC_PLLM_DIV_6 |
| * @arg @ref LL_RCC_PLLM_DIV_7 |
| * @arg @ref LL_RCC_PLLM_DIV_8 |
| * @arg @ref LL_RCC_PLLM_DIV_9 |
| * @arg @ref LL_RCC_PLLM_DIV_10 |
| * @arg @ref LL_RCC_PLLM_DIV_11 |
| * @arg @ref LL_RCC_PLLM_DIV_12 |
| * @arg @ref LL_RCC_PLLM_DIV_13 |
| * @arg @ref LL_RCC_PLLM_DIV_14 |
| * @arg @ref LL_RCC_PLLM_DIV_15 |
| * @arg @ref LL_RCC_PLLM_DIV_16 |
| * @arg @ref LL_RCC_PLLM_DIV_17 |
| * @arg @ref LL_RCC_PLLM_DIV_18 |
| * @arg @ref LL_RCC_PLLM_DIV_19 |
| * @arg @ref LL_RCC_PLLM_DIV_20 |
| * @arg @ref LL_RCC_PLLM_DIV_21 |
| * @arg @ref LL_RCC_PLLM_DIV_22 |
| * @arg @ref LL_RCC_PLLM_DIV_23 |
| * @arg @ref LL_RCC_PLLM_DIV_24 |
| * @arg @ref LL_RCC_PLLM_DIV_25 |
| * @arg @ref LL_RCC_PLLM_DIV_26 |
| * @arg @ref LL_RCC_PLLM_DIV_27 |
| * @arg @ref LL_RCC_PLLM_DIV_28 |
| * @arg @ref LL_RCC_PLLM_DIV_29 |
| * @arg @ref LL_RCC_PLLM_DIV_30 |
| * @arg @ref LL_RCC_PLLM_DIV_31 |
| * @arg @ref LL_RCC_PLLM_DIV_32 |
| * @arg @ref LL_RCC_PLLM_DIV_33 |
| * @arg @ref LL_RCC_PLLM_DIV_34 |
| * @arg @ref LL_RCC_PLLM_DIV_35 |
| * @arg @ref LL_RCC_PLLM_DIV_36 |
| * @arg @ref LL_RCC_PLLM_DIV_37 |
| * @arg @ref LL_RCC_PLLM_DIV_38 |
| * @arg @ref LL_RCC_PLLM_DIV_39 |
| * @arg @ref LL_RCC_PLLM_DIV_40 |
| * @arg @ref LL_RCC_PLLM_DIV_41 |
| * @arg @ref LL_RCC_PLLM_DIV_42 |
| * @arg @ref LL_RCC_PLLM_DIV_43 |
| * @arg @ref LL_RCC_PLLM_DIV_44 |
| * @arg @ref LL_RCC_PLLM_DIV_45 |
| * @arg @ref LL_RCC_PLLM_DIV_46 |
| * @arg @ref LL_RCC_PLLM_DIV_47 |
| * @arg @ref LL_RCC_PLLM_DIV_48 |
| * @arg @ref LL_RCC_PLLM_DIV_49 |
| * @arg @ref LL_RCC_PLLM_DIV_50 |
| * @arg @ref LL_RCC_PLLM_DIV_51 |
| * @arg @ref LL_RCC_PLLM_DIV_52 |
| * @arg @ref LL_RCC_PLLM_DIV_53 |
| * @arg @ref LL_RCC_PLLM_DIV_54 |
| * @arg @ref LL_RCC_PLLM_DIV_55 |
| * @arg @ref LL_RCC_PLLM_DIV_56 |
| * @arg @ref LL_RCC_PLLM_DIV_57 |
| * @arg @ref LL_RCC_PLLM_DIV_58 |
| * @arg @ref LL_RCC_PLLM_DIV_59 |
| * @arg @ref LL_RCC_PLLM_DIV_60 |
| * @arg @ref LL_RCC_PLLM_DIV_61 |
| * @arg @ref LL_RCC_PLLM_DIV_62 |
| * @arg @ref LL_RCC_PLLM_DIV_63 |
| * @param PLLN Between 192 and 432 |
| * @param PLLR This parameter can be one of the following values: |
| * @arg @ref LL_RCC_PLLI2SR_DIV_2 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_3 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_4 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_5 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_6 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_7 |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) |
| { |
| MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); |
| MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR); |
| } |
| |
| /** |
| * @brief Get I2SPLL multiplication factor for VCO |
| * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN |
| * @retval Between 192 and 432 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); |
| } |
| |
| /** |
| * @brief Get I2SPLL division factor for PLLI2SR |
| * @note used for PLLI2SCLK (I2S clock) |
| * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR |
| * @retval Returned value can be one of the following values: |
| * @arg @ref LL_RCC_PLLI2SR_DIV_2 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_3 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_4 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_5 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_6 |
| * @arg @ref LL_RCC_PLLI2SR_DIV_7 |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) |
| { |
| return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management |
| * @{ |
| */ |
| |
| /** |
| * @brief Clear LSI ready interrupt flag |
| * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); |
| } |
| |
| /** |
| * @brief Clear LSE ready interrupt flag |
| * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); |
| } |
| |
| /** |
| * @brief Clear HSI ready interrupt flag |
| * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); |
| } |
| |
| /** |
| * @brief Clear HSE ready interrupt flag |
| * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); |
| } |
| |
| /** |
| * @brief Clear PLL ready interrupt flag |
| * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); |
| } |
| |
| /** |
| * @brief Clear PLLI2S ready interrupt flag |
| * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); |
| } |
| |
| /** |
| * @brief Clear Clock security system interrupt flag |
| * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_CSSC); |
| } |
| |
| /** |
| * @brief Check if LSI ready interrupt occurred or not |
| * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); |
| } |
| |
| /** |
| * @brief Check if LSE ready interrupt occurred or not |
| * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); |
| } |
| |
| /** |
| * @brief Check if HSI ready interrupt occurred or not |
| * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); |
| } |
| |
| /** |
| * @brief Check if HSE ready interrupt occurred or not |
| * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); |
| } |
| |
| /** |
| * @brief Check if PLL ready interrupt occurred or not |
| * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); |
| } |
| |
| /** |
| * @brief Check if PLLI2S ready interrupt occurred or not |
| * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF)); |
| } |
| |
| /** |
| * @brief Check if Clock security system interrupt occurred or not |
| * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); |
| } |
| |
| /** |
| * @brief Check if RCC flag Independent Watchdog reset is set or not. |
| * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) |
| { |
| return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); |
| } |
| |
| /** |
| * @brief Check if RCC flag Low Power reset is set or not. |
| * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) |
| { |
| return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); |
| } |
| |
| /** |
| * @brief Check if RCC flag Pin reset is set or not. |
| * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) |
| { |
| return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); |
| } |
| |
| /** |
| * @brief Check if RCC flag POR/PDR reset is set or not. |
| * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) |
| { |
| return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); |
| } |
| |
| /** |
| * @brief Check if RCC flag Software reset is set or not. |
| * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) |
| { |
| return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); |
| } |
| |
| /** |
| * @brief Check if RCC flag Window Watchdog reset is set or not. |
| * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) |
| { |
| return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); |
| } |
| |
| /** |
| * @brief Check if RCC flag BOR reset is set or not. |
| * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) |
| { |
| return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); |
| } |
| |
| /** |
| * @brief Set RMVF bit to clear the reset flags. |
| * @rmtoll CSR RMVF LL_RCC_ClearResetFlags |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_ClearResetFlags(void) |
| { |
| SET_BIT(RCC->CSR, RCC_CSR_RMVF); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_IT_Management IT Management |
| * @{ |
| */ |
| |
| /** |
| * @brief Enable LSI ready interrupt |
| * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
| } |
| |
| /** |
| * @brief Enable LSE ready interrupt |
| * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
| } |
| |
| /** |
| * @brief Enable HSI ready interrupt |
| * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
| } |
| |
| /** |
| * @brief Enable HSE ready interrupt |
| * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
| } |
| |
| /** |
| * @brief Enable PLL ready interrupt |
| * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
| } |
| |
| /** |
| * @brief Enable PLLI2S ready interrupt |
| * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) |
| { |
| SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); |
| } |
| |
| /** |
| * @brief Disable LSI ready interrupt |
| * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) |
| { |
| CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); |
| } |
| |
| /** |
| * @brief Disable LSE ready interrupt |
| * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) |
| { |
| CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); |
| } |
| |
| /** |
| * @brief Disable HSI ready interrupt |
| * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) |
| { |
| CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); |
| } |
| |
| /** |
| * @brief Disable HSE ready interrupt |
| * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) |
| { |
| CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); |
| } |
| |
| /** |
| * @brief Disable PLL ready interrupt |
| * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) |
| { |
| CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); |
| } |
| |
| /** |
| * @brief Disable PLLI2S ready interrupt |
| * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY |
| * @retval None |
| */ |
| __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) |
| { |
| CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); |
| } |
| |
| /** |
| * @brief Checks if LSI ready interrupt source is enabled or disabled. |
| * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); |
| } |
| |
| /** |
| * @brief Checks if LSE ready interrupt source is enabled or disabled. |
| * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); |
| } |
| |
| /** |
| * @brief Checks if HSI ready interrupt source is enabled or disabled. |
| * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); |
| } |
| |
| /** |
| * @brief Checks if HSE ready interrupt source is enabled or disabled. |
| * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); |
| } |
| |
| /** |
| * @brief Checks if PLL ready interrupt source is enabled or disabled. |
| * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); |
| } |
| |
| /** |
| * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. |
| * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY |
| * @retval State of bit (1 or 0). |
| */ |
| __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) |
| { |
| return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE)); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| #if defined(USE_FULL_LL_DRIVER) |
| /** @defgroup RCC_LL_EF_Init De-initialization function |
| * @{ |
| */ |
| ErrorStatus LL_RCC_DeInit(void); |
| /** |
| * @} |
| */ |
| |
| /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions |
| * @{ |
| */ |
| void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); |
| uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); |
| /** |
| * @} |
| */ |
| #endif /* USE_FULL_LL_DRIVER */ |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| #endif /* defined(RCC) */ |
| |
| /** |
| * @} |
| */ |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| |
| #endif /* __STM32F2xx_LL_RCC_H */ |
| |
| /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |