| /** |
| ****************************************************************************** |
| * @file stm32f2xx_ll_rcc.c |
| * @author MCD Application Team |
| * @brief RCC LL module driver. |
| ****************************************************************************** |
| * @attention |
| * |
| * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
| * All rights reserved.</center></h2> |
| * |
| * This software component is licensed by ST under BSD 3-Clause license, |
| * the "License"; You may not use this file except in compliance with the |
| * License. You may obtain a copy of the License at: |
| * opensource.org/licenses/BSD-3-Clause |
| * |
| ****************************************************************************** |
| */ |
| |
| #if defined(USE_FULL_LL_DRIVER) |
| |
| /* Includes ------------------------------------------------------------------*/ |
| #include "stm32f2xx_ll_rcc.h" |
| #ifdef USE_FULL_ASSERT |
| #include "stm32_assert.h" |
| #else |
| #define assert_param(expr) ((void)0U) |
| #endif |
| /** @addtogroup STM32F2xx_LL_Driver |
| * @{ |
| */ |
| |
| #if defined(RCC) |
| |
| /** @addtogroup RCC_LL |
| * @{ |
| */ |
| |
| /* Private types -------------------------------------------------------------*/ |
| /* Private variables ---------------------------------------------------------*/ |
| /* Private constants ---------------------------------------------------------*/ |
| /* Private macros ------------------------------------------------------------*/ |
| /** @addtogroup RCC_LL_Private_Macros |
| * @{ |
| */ |
| #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE)) |
| /** |
| * @} |
| */ |
| |
| /* Private function prototypes -----------------------------------------------*/ |
| /** @defgroup RCC_LL_Private_Functions RCC Private functions |
| * @{ |
| */ |
| uint32_t RCC_GetSystemClockFreq(void); |
| uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); |
| uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); |
| uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); |
| uint32_t RCC_PLL_GetFreqDomain_SYS(void); |
| uint32_t RCC_PLL_GetFreqDomain_48M(void); |
| uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void); |
| /** |
| * @} |
| */ |
| |
| /* Exported functions --------------------------------------------------------*/ |
| /** @addtogroup RCC_LL_Exported_Functions |
| * @{ |
| */ |
| |
| /** @addtogroup RCC_LL_EF_Init |
| * @{ |
| */ |
| |
| /** |
| * @brief Reset the RCC clock configuration to the default reset state. |
| * @note The default reset state of the clock configuration is given below: |
| * - HSI ON and used as system clock source |
| * - HSE, PLL, PLLI2S OFF |
| * - AHB, APB1 and APB2 prescaler set to 1. |
| * - CSS, MCO OFF |
| * - All interrupts disabled |
| * @note This function doesn't modify the configuration of the |
| * - Peripheral clocks |
| * - LSI, LSE and RTC clocks |
| * @retval An ErrorStatus enumeration value: |
| * - SUCCESS: RCC registers are de-initialized |
| * - ERROR: not applicable |
| */ |
| ErrorStatus LL_RCC_DeInit(void) |
| { |
| uint32_t vl_mask = 0U; |
| |
| /* Set HSION bit */ |
| LL_RCC_HSI_Enable(); |
| |
| /* Wait for HSI READY bit */ |
| while(LL_RCC_HSI_IsReady() != 1U) |
| {} |
| |
| /* Reset CFGR register */ |
| LL_RCC_WriteReg(CFGR, 0x00000000U); |
| |
| vl_mask = 0xFFFFFFFFU; |
| |
| /* Reset HSEON, PLLSYSON bits */ |
| CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON)); |
| |
| /* Reset PLLI2SON bit */ |
| CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON); |
| |
| /* Write new mask in CR register */ |
| LL_RCC_WriteReg(CR, vl_mask); |
| |
| /* Set HSITRIM bits to the reset value*/ |
| LL_RCC_HSI_SetCalibTrimming(0x10U); |
| |
| /* Wait for PLL READY bit to be reset */ |
| while(LL_RCC_PLL_IsReady() != 0U) |
| {} |
| |
| /* Wait for PLLI2S READY bit to be reset */ |
| while(LL_RCC_PLLI2S_IsReady() != 0U) |
| {} |
| |
| /* Reset PLLCFGR register */ |
| LL_RCC_WriteReg(PLLCFGR, 0x24003010U); |
| |
| /* Reset PLLI2SCFGR register */ |
| LL_RCC_WriteReg(PLLI2SCFGR, 0x20003000U); |
| |
| /* Disable all interrupts */ |
| LL_RCC_WriteReg(CIR, 0x00000000U); |
| |
| /* Clear reset flags */ |
| LL_RCC_ClearResetFlags(); |
| |
| return SUCCESS; |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup RCC_LL_EF_Get_Freq |
| * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks |
| * and different peripheral clocks available on the device. |
| * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) |
| * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) |
| * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) |
| * or HSI_VALUE(**) multiplied/divided by the PLL factors. |
| * @note (**) HSI_VALUE is a constant defined in this file (default value |
| * 16 MHz) but the real value may vary depending on the variations |
| * in voltage and temperature. |
| * @note (***) HSE_VALUE is a constant defined in this file (default value |
| * 25 MHz), user has to ensure that HSE_VALUE is same as the real |
| * frequency of the crystal used. Otherwise, this function may |
| * have wrong result. |
| * @note The result of this function could be incorrect when using fractional |
| * value for HSE crystal. |
| * @note This function can be used by the user application to compute the |
| * baud-rate for the communication peripherals or configure other parameters. |
| * @{ |
| */ |
| |
| /** |
| * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks |
| * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function |
| * must be called to update structure fields. Otherwise, any |
| * configuration based on this function will be incorrect. |
| * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies |
| * @retval None |
| */ |
| void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) |
| { |
| /* Get SYSCLK frequency */ |
| RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); |
| |
| /* HCLK clock frequency */ |
| RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); |
| |
| /* PCLK1 clock frequency */ |
| RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); |
| |
| /* PCLK2 clock frequency */ |
| RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); |
| } |
| |
| /** |
| * @brief Return I2Sx clock frequency |
| * @param I2SxSource This parameter can be one of the following values: |
| * @arg @ref LL_RCC_I2S1_CLKSOURCE |
| * @retval I2S clock frequency (in Hz) |
| * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready |
| */ |
| uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) |
| { |
| uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; |
| |
| /* Check parameter */ |
| assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); |
| |
| if (I2SxSource == LL_RCC_I2S1_CLKSOURCE) |
| { |
| /* I2S1 CLK clock frequency */ |
| switch (LL_RCC_GetI2SClockSource(I2SxSource)) |
| { |
| case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */ |
| if (LL_RCC_PLLI2S_IsReady()) |
| { |
| i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S(); |
| } |
| break; |
| |
| case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */ |
| default: |
| i2s_frequency = EXTERNAL_CLOCK_VALUE; |
| break; |
| } |
| } |
| |
| return i2s_frequency; |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| /** @addtogroup RCC_LL_Private_Functions |
| * @{ |
| */ |
| |
| /** |
| * @brief Return SYSTEM clock frequency |
| * @retval SYSTEM clock frequency (in Hz) |
| */ |
| uint32_t RCC_GetSystemClockFreq(void) |
| { |
| uint32_t frequency = 0U; |
| |
| /* Get SYSCLK source -------------------------------------------------------*/ |
| switch (LL_RCC_GetSysClkSource()) |
| { |
| case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ |
| frequency = HSI_VALUE; |
| break; |
| |
| case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ |
| frequency = HSE_VALUE; |
| break; |
| |
| case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ |
| frequency = RCC_PLL_GetFreqDomain_SYS(); |
| break; |
| |
| default: |
| frequency = HSI_VALUE; |
| break; |
| } |
| |
| return frequency; |
| } |
| |
| /** |
| * @brief Return HCLK clock frequency |
| * @param SYSCLK_Frequency SYSCLK clock frequency |
| * @retval HCLK clock frequency (in Hz) |
| */ |
| uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) |
| { |
| /* HCLK clock frequency */ |
| return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); |
| } |
| |
| /** |
| * @brief Return PCLK1 clock frequency |
| * @param HCLK_Frequency HCLK clock frequency |
| * @retval PCLK1 clock frequency (in Hz) |
| */ |
| uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) |
| { |
| /* PCLK1 clock frequency */ |
| return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); |
| } |
| |
| /** |
| * @brief Return PCLK2 clock frequency |
| * @param HCLK_Frequency HCLK clock frequency |
| * @retval PCLK2 clock frequency (in Hz) |
| */ |
| uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) |
| { |
| /* PCLK2 clock frequency */ |
| return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); |
| } |
| |
| /** |
| * @brief Return PLL clock frequency used for system domain |
| * @retval PLL clock frequency (in Hz) |
| */ |
| uint32_t RCC_PLL_GetFreqDomain_SYS(void) |
| { |
| uint32_t pllinputfreq = 0U, pllsource = 0U; |
| |
| /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN |
| */ |
| pllsource = LL_RCC_PLL_GetMainSource(); |
| |
| switch (pllsource) |
| { |
| case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ |
| pllinputfreq = HSI_VALUE; |
| break; |
| |
| case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ |
| pllinputfreq = HSE_VALUE; |
| break; |
| |
| default: |
| pllinputfreq = HSI_VALUE; |
| break; |
| } |
| return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), |
| LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); |
| } |
| |
| /** |
| * @brief Return PLL clock frequency used for 48 MHz domain |
| * @retval PLL clock frequency (in Hz) |
| */ |
| uint32_t RCC_PLL_GetFreqDomain_48M(void) |
| { |
| uint32_t pllinputfreq = 0U, pllsource = 0U; |
| |
| /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN |
| 48M Domain clock = PLL_VCO / PLLQ |
| */ |
| pllsource = LL_RCC_PLL_GetMainSource(); |
| |
| switch (pllsource) |
| { |
| case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ |
| pllinputfreq = HSI_VALUE; |
| break; |
| |
| case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ |
| pllinputfreq = HSE_VALUE; |
| break; |
| |
| default: |
| pllinputfreq = HSI_VALUE; |
| break; |
| } |
| return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), |
| LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); |
| } |
| |
| /** |
| * @brief Return PLLI2S clock frequency used for I2S domain |
| * @retval PLLI2S clock frequency (in Hz) |
| */ |
| uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void) |
| { |
| uint32_t pllinputfreq = 0U, pllsource = 0U; |
| |
| /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN |
| I2S Domain clock = PLLI2S_VCO / PLLI2SR |
| */ |
| pllsource = LL_RCC_PLL_GetMainSource(); |
| |
| switch (pllsource) |
| { |
| case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ |
| pllinputfreq = HSE_VALUE; |
| break; |
| |
| case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ |
| default: |
| pllinputfreq = HSI_VALUE; |
| break; |
| } |
| return __LL_RCC_CALC_PLLI2S_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), |
| LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR()); |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** |
| * @} |
| */ |
| |
| #endif /* defined(RCC) */ |
| |
| /** |
| * @} |
| */ |
| |
| #endif /* USE_FULL_LL_DRIVER */ |
| |
| /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |