| /** |
| ****************************************************************************** |
| * @file stm32f2xx_hal_tim.c |
| * @author MCD Application Team |
| * @brief TIM HAL module driver. |
| * This file provides firmware functions to manage the following |
| * functionalities of the Timer (TIM) peripheral: |
| * + TIM Time Base Initialization |
| * + TIM Time Base Start |
| * + TIM Time Base Start Interruption |
| * + TIM Time Base Start DMA |
| * + TIM Output Compare/PWM Initialization |
| * + TIM Output Compare/PWM Channel Configuration |
| * + TIM Output Compare/PWM Start |
| * + TIM Output Compare/PWM Start Interruption |
| * + TIM Output Compare/PWM Start DMA |
| * + TIM Input Capture Initialization |
| * + TIM Input Capture Channel Configuration |
| * + TIM Input Capture Start |
| * + TIM Input Capture Start Interruption |
| * + TIM Input Capture Start DMA |
| * + TIM One Pulse Initialization |
| * + TIM One Pulse Channel Configuration |
| * + TIM One Pulse Start |
| * + TIM Encoder Interface Initialization |
| * + TIM Encoder Interface Start |
| * + TIM Encoder Interface Start Interruption |
| * + TIM Encoder Interface Start DMA |
| * + Commutation Event configuration with Interruption and DMA |
| * + TIM OCRef clear configuration |
| * + TIM External Clock configuration |
| * |
| ****************************************************************************** |
| * @attention |
| * |
| * Copyright (c) 2016 STMicroelectronics. |
| * All rights reserved. |
| * |
| * This software is licensed under terms that can be found in the LICENSE file |
| * in the root directory of this software component. |
| * If no LICENSE file comes with this software, it is provided AS-IS. |
| * |
| ****************************************************************************** |
| @verbatim |
| ============================================================================== |
| ##### TIMER Generic features ##### |
| ============================================================================== |
| [..] The Timer features include: |
| (#) 16-bit up, down, up/down auto-reload counter. |
| (#) 16-bit programmable prescaler allowing dividing (also on the fly) the |
| counter clock frequency either by any factor between 1 and 65536. |
| (#) Up to 4 independent channels for: |
| (++) Input Capture |
| (++) Output Compare |
| (++) PWM generation (Edge and Center-aligned Mode) |
| (++) One-pulse mode output |
| (#) Synchronization circuit to control the timer with external signals and to interconnect |
| several timers together. |
| (#) Supports incremental encoder for positioning purposes |
| |
| ##### How to use this driver ##### |
| ============================================================================== |
| [..] |
| (#) Initialize the TIM low level resources by implementing the following functions |
| depending on the selected feature: |
| (++) Time Base : HAL_TIM_Base_MspInit() |
| (++) Input Capture : HAL_TIM_IC_MspInit() |
| (++) Output Compare : HAL_TIM_OC_MspInit() |
| (++) PWM generation : HAL_TIM_PWM_MspInit() |
| (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() |
| (++) Encoder mode output : HAL_TIM_Encoder_MspInit() |
| |
| (#) Initialize the TIM low level resources : |
| (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); |
| (##) TIM pins configuration |
| (+++) Enable the clock for the TIM GPIOs using the following function: |
| __HAL_RCC_GPIOx_CLK_ENABLE(); |
| (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); |
| |
| (#) The external Clock can be configured, if needed (the default clock is the |
| internal clock from the APBx), using the following function: |
| HAL_TIM_ConfigClockSource, the clock configuration should be done before |
| any start function. |
| |
| (#) Configure the TIM in the desired functioning mode using one of the |
| Initialization function of this driver: |
| (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base |
| (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an |
| Output Compare signal. |
| (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a |
| PWM signal. |
| (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an |
| external signal. |
| (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer |
| in One Pulse Mode. |
| (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. |
| |
| (#) Activate the TIM peripheral using one of the start functions depending from the feature used: |
| (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() |
| (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() |
| (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() |
| (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() |
| (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() |
| (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). |
| |
| (#) The DMA Burst is managed with the two following functions: |
| HAL_TIM_DMABurst_WriteStart() |
| HAL_TIM_DMABurst_ReadStart() |
| |
| *** Callback registration *** |
| ============================================= |
| |
| [..] |
| The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 |
| allows the user to configure dynamically the driver callbacks. |
| |
| [..] |
| Use Function @ref HAL_TIM_RegisterCallback() to register a callback. |
| @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, |
| the Callback ID and a pointer to the user callback function. |
| |
| [..] |
| Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default |
| weak function. |
| @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, |
| and the Callback ID. |
| |
| [..] |
| These functions allow to register/unregister following callbacks: |
| (+) Base_MspInitCallback : TIM Base Msp Init Callback. |
| (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. |
| (+) IC_MspInitCallback : TIM IC Msp Init Callback. |
| (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. |
| (+) OC_MspInitCallback : TIM OC Msp Init Callback. |
| (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. |
| (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. |
| (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. |
| (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. |
| (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. |
| (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. |
| (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. |
| (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. |
| (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. |
| (+) PeriodElapsedCallback : TIM Period Elapsed Callback. |
| (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. |
| (+) TriggerCallback : TIM Trigger Callback. |
| (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. |
| (+) IC_CaptureCallback : TIM Input Capture Callback. |
| (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. |
| (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. |
| (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. |
| (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. |
| (+) ErrorCallback : TIM Error Callback. |
| (+) CommutationCallback : TIM Commutation Callback. |
| (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. |
| (+) BreakCallback : TIM Break Callback. |
| |
| [..] |
| By default, after the Init and when the state is HAL_TIM_STATE_RESET |
| all interrupt callbacks are set to the corresponding weak functions: |
| examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). |
| |
| [..] |
| Exception done for MspInit and MspDeInit functions that are reset to the legacy weak |
| functionalities in the Init / DeInit only when these callbacks are null |
| (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit |
| keep and use the user MspInit / MspDeInit callbacks(registered beforehand) |
| |
| [..] |
| Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. |
| Exception done MspInit / MspDeInit that can be registered / unregistered |
| in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, |
| thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. |
| In that case first register the MspInit/MspDeInit user callbacks |
| using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. |
| |
| [..] |
| When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or |
| not defined, the callback registration feature is not available and all callbacks |
| are set to the corresponding weak functions. |
| |
| @endverbatim |
| ****************************************************************************** |
| */ |
| |
| /* Includes ------------------------------------------------------------------*/ |
| #include "stm32f2xx_hal.h" |
| |
| /** @addtogroup STM32F2xx_HAL_Driver |
| * @{ |
| */ |
| |
| /** @defgroup TIM TIM |
| * @brief TIM HAL module driver |
| * @{ |
| */ |
| |
| #ifdef HAL_TIM_MODULE_ENABLED |
| |
| /* Private typedef -----------------------------------------------------------*/ |
| /* Private define ------------------------------------------------------------*/ |
| /* Private macros ------------------------------------------------------------*/ |
| /* Private variables ---------------------------------------------------------*/ |
| /* Private function prototypes -----------------------------------------------*/ |
| /** @addtogroup TIM_Private_Functions |
| * @{ |
| */ |
| static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); |
| static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); |
| static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); |
| static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); |
| static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| uint32_t TIM_ICFilter); |
| static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); |
| static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| uint32_t TIM_ICFilter); |
| static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| uint32_t TIM_ICFilter); |
| static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); |
| static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); |
| static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); |
| static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
| static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); |
| static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); |
| static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, |
| const TIM_SlaveConfigTypeDef *sSlaveConfig); |
| /** |
| * @} |
| */ |
| /* Exported functions --------------------------------------------------------*/ |
| |
| /** @defgroup TIM_Exported_Functions TIM Exported Functions |
| * @{ |
| */ |
| |
| /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions |
| * @brief Time Base functions |
| * |
| @verbatim |
| ============================================================================== |
| ##### Time Base functions ##### |
| ============================================================================== |
| [..] |
| This section provides functions allowing to: |
| (+) Initialize and configure the TIM base. |
| (+) De-initialize the TIM base. |
| (+) Start the Time Base. |
| (+) Stop the Time Base. |
| (+) Start the Time Base and enable interrupt. |
| (+) Stop the Time Base and disable interrupt. |
| (+) Start the Time Base and enable DMA transfer. |
| (+) Stop the Time Base and disable DMA transfer. |
| |
| @endverbatim |
| * @{ |
| */ |
| /** |
| * @brief Initializes the TIM Time base Unit according to the specified |
| * parameters in the TIM_HandleTypeDef and initialize the associated handle. |
| * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) |
| * requires a timer reset to avoid unexpected direction |
| * due to DIR bit readonly in center aligned mode. |
| * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() |
| * @param htim TIM Base handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) |
| { |
| /* Check the TIM handle allocation */ |
| if (htim == NULL) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); |
| |
| if (htim->State == HAL_TIM_STATE_RESET) |
| { |
| /* Allocate lock resource and initialize it */ |
| htim->Lock = HAL_UNLOCKED; |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| /* Reset interrupt callbacks to legacy weak callbacks */ |
| TIM_ResetCallback(htim); |
| |
| if (htim->Base_MspInitCallback == NULL) |
| { |
| htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; |
| } |
| /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
| htim->Base_MspInitCallback(htim); |
| #else |
| /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
| HAL_TIM_Base_MspInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| } |
| |
| /* Set the TIM state */ |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Set the Time Base configuration */ |
| TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| |
| /* Initialize the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_READY; |
| |
| /* Initialize the TIM channels state */ |
| TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Initialize the TIM state*/ |
| htim->State = HAL_TIM_STATE_READY; |
| |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief DeInitializes the TIM Base peripheral |
| * @param htim TIM Base handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Disable the TIM Peripheral Clock */ |
| __HAL_TIM_DISABLE(htim); |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| if (htim->Base_MspDeInitCallback == NULL) |
| { |
| htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; |
| } |
| /* DeInit the low level hardware */ |
| htim->Base_MspDeInitCallback(htim); |
| #else |
| /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| HAL_TIM_Base_MspDeInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| |
| /* Change the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; |
| |
| /* Change the TIM channels state */ |
| TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); |
| TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); |
| |
| /* Change TIM state */ |
| htim->State = HAL_TIM_STATE_RESET; |
| |
| /* Release Lock */ |
| __HAL_UNLOCK(htim); |
| |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Initializes the TIM Base MSP. |
| * @param htim TIM Base handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_Base_MspInit could be implemented in the user file |
| */ |
| } |
| |
| /** |
| * @brief DeInitializes TIM Base MSP. |
| * @param htim TIM Base handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_Base_MspDeInit could be implemented in the user file |
| */ |
| } |
| |
| |
| /** |
| * @brief Starts the TIM Base generation. |
| * @param htim TIM Base handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) |
| { |
| uint32_t tmpsmcr; |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| |
| /* Check the TIM state */ |
| if (htim->State != HAL_TIM_STATE_READY) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Set the TIM state */ |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM Base generation. |
| * @param htim TIM Base handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM state */ |
| htim->State = HAL_TIM_STATE_READY; |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Starts the TIM Base generation in interrupt mode. |
| * @param htim TIM Base handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) |
| { |
| uint32_t tmpsmcr; |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| |
| /* Check the TIM state */ |
| if (htim->State != HAL_TIM_STATE_READY) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Set the TIM state */ |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Enable the TIM Update interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM Base generation in interrupt mode. |
| * @param htim TIM Base handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| |
| /* Disable the TIM Update interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM state */ |
| htim->State = HAL_TIM_STATE_READY; |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Starts the TIM Base generation in DMA mode. |
| * @param htim TIM Base handle |
| * @param pData The source Buffer address. |
| * @param Length The length of data to be transferred from memory to peripheral. |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) |
| { |
| uint32_t tmpsmcr; |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); |
| |
| /* Set the TIM state */ |
| if (htim->State == HAL_TIM_STATE_BUSY) |
| { |
| return HAL_BUSY; |
| } |
| else if (htim->State == HAL_TIM_STATE_READY) |
| { |
| if ((pData == NULL) && (Length > 0U)) |
| { |
| return HAL_ERROR; |
| } |
| else |
| { |
| htim->State = HAL_TIM_STATE_BUSY; |
| } |
| } |
| else |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Set the DMA Period elapsed callbacks */ |
| htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; |
| htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| |
| /* Enable the TIM Update DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM Base generation in DMA mode. |
| * @param htim TIM Base handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); |
| |
| /* Disable the TIM Update DMA request */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); |
| |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM state */ |
| htim->State = HAL_TIM_STATE_READY; |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions |
| * @brief TIM Output Compare functions |
| * |
| @verbatim |
| ============================================================================== |
| ##### TIM Output Compare functions ##### |
| ============================================================================== |
| [..] |
| This section provides functions allowing to: |
| (+) Initialize and configure the TIM Output Compare. |
| (+) De-initialize the TIM Output Compare. |
| (+) Start the TIM Output Compare. |
| (+) Stop the TIM Output Compare. |
| (+) Start the TIM Output Compare and enable interrupt. |
| (+) Stop the TIM Output Compare and disable interrupt. |
| (+) Start the TIM Output Compare and enable DMA transfer. |
| (+) Stop the TIM Output Compare and disable DMA transfer. |
| |
| @endverbatim |
| * @{ |
| */ |
| /** |
| * @brief Initializes the TIM Output Compare according to the specified |
| * parameters in the TIM_HandleTypeDef and initializes the associated handle. |
| * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) |
| * requires a timer reset to avoid unexpected direction |
| * due to DIR bit readonly in center aligned mode. |
| * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() |
| * @param htim TIM Output Compare handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) |
| { |
| /* Check the TIM handle allocation */ |
| if (htim == NULL) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); |
| |
| if (htim->State == HAL_TIM_STATE_RESET) |
| { |
| /* Allocate lock resource and initialize it */ |
| htim->Lock = HAL_UNLOCKED; |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| /* Reset interrupt callbacks to legacy weak callbacks */ |
| TIM_ResetCallback(htim); |
| |
| if (htim->OC_MspInitCallback == NULL) |
| { |
| htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; |
| } |
| /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
| htim->OC_MspInitCallback(htim); |
| #else |
| /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| HAL_TIM_OC_MspInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| } |
| |
| /* Set the TIM state */ |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Init the base time for the Output Compare */ |
| TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| |
| /* Initialize the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_READY; |
| |
| /* Initialize the TIM channels state */ |
| TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Initialize the TIM state*/ |
| htim->State = HAL_TIM_STATE_READY; |
| |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief DeInitializes the TIM peripheral |
| * @param htim TIM Output Compare handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Disable the TIM Peripheral Clock */ |
| __HAL_TIM_DISABLE(htim); |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| if (htim->OC_MspDeInitCallback == NULL) |
| { |
| htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; |
| } |
| /* DeInit the low level hardware */ |
| htim->OC_MspDeInitCallback(htim); |
| #else |
| /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ |
| HAL_TIM_OC_MspDeInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| |
| /* Change the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; |
| |
| /* Change the TIM channels state */ |
| TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); |
| TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); |
| |
| /* Change TIM state */ |
| htim->State = HAL_TIM_STATE_RESET; |
| |
| /* Release Lock */ |
| __HAL_UNLOCK(htim); |
| |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Initializes the TIM Output Compare MSP. |
| * @param htim TIM Output Compare handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_OC_MspInit could be implemented in the user file |
| */ |
| } |
| |
| /** |
| * @brief DeInitializes TIM Output Compare MSP. |
| * @param htim TIM Output Compare handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_OC_MspDeInit could be implemented in the user file |
| */ |
| } |
| |
| /** |
| * @brief Starts the TIM Output Compare signal generation. |
| * @param htim TIM Output Compare handle |
| * @param Channel TIM Channel to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| uint32_t tmpsmcr; |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| /* Check the TIM channel state */ |
| if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| |
| /* Enable the Output compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Enable the main output */ |
| __HAL_TIM_MOE_ENABLE(htim); |
| } |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM Output Compare signal generation. |
| * @param htim TIM Output Compare handle |
| * @param Channel TIM Channel to be disabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| /* Disable the Output compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Disable the Main Output */ |
| __HAL_TIM_MOE_DISABLE(htim); |
| } |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Starts the TIM Output Compare signal generation in interrupt mode. |
| * @param htim TIM Output Compare handle |
| * @param Channel TIM Channel to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| uint32_t tmpsmcr; |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| /* Check the TIM channel state */ |
| if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Enable the TIM Capture/Compare 1 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Enable the TIM Capture/Compare 2 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Enable the TIM Capture/Compare 3 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Enable the TIM Capture/Compare 4 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| |
| /* Enable the Output compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Enable the main output */ |
| __HAL_TIM_MOE_ENABLE(htim); |
| } |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM Output Compare signal generation in interrupt mode. |
| * @param htim TIM Output Compare handle |
| * @param Channel TIM Channel to be disabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Disable the TIM Capture/Compare 1 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Disable the TIM Capture/Compare 2 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Disable the TIM Capture/Compare 3 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Disable the TIM Capture/Compare 4 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| |
| /* Disable the Output compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Disable the Main Output */ |
| __HAL_TIM_MOE_DISABLE(htim); |
| } |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Starts the TIM Output Compare signal generation in DMA mode. |
| * @param htim TIM Output Compare handle |
| * @param Channel TIM Channel to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @param pData The source Buffer address. |
| * @param Length The length of data to be transferred from memory to TIM peripheral |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, |
| uint16_t Length) |
| { |
| uint32_t tmpsmcr; |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| /* Set the TIM channel state */ |
| if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) |
| { |
| return HAL_BUSY; |
| } |
| else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) |
| { |
| if ((pData == NULL) && (Length > 0U)) |
| { |
| return HAL_ERROR; |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| } |
| } |
| else |
| { |
| return HAL_ERROR; |
| } |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Set the DMA compare callbacks */ |
| htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| |
| /* Enable the TIM Capture/Compare 1 DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Set the DMA compare callbacks */ |
| htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| |
| /* Enable the TIM Capture/Compare 2 DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Set the DMA compare callbacks */ |
| htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| /* Enable the TIM Capture/Compare 3 DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Set the DMA compare callbacks */ |
| htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| /* Enable the TIM Capture/Compare 4 DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| |
| /* Enable the Output compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Enable the main output */ |
| __HAL_TIM_MOE_ENABLE(htim); |
| } |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM Output Compare signal generation in DMA mode. |
| * @param htim TIM Output Compare handle |
| * @param Channel TIM Channel to be disabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Disable the TIM Capture/Compare 1 DMA request */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Disable the TIM Capture/Compare 2 DMA request */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Disable the TIM Capture/Compare 3 DMA request */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Disable the TIM Capture/Compare 4 interrupt */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| |
| /* Disable the Output compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Disable the Main Output */ |
| __HAL_TIM_MOE_DISABLE(htim); |
| } |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions |
| * @brief TIM PWM functions |
| * |
| @verbatim |
| ============================================================================== |
| ##### TIM PWM functions ##### |
| ============================================================================== |
| [..] |
| This section provides functions allowing to: |
| (+) Initialize and configure the TIM PWM. |
| (+) De-initialize the TIM PWM. |
| (+) Start the TIM PWM. |
| (+) Stop the TIM PWM. |
| (+) Start the TIM PWM and enable interrupt. |
| (+) Stop the TIM PWM and disable interrupt. |
| (+) Start the TIM PWM and enable DMA transfer. |
| (+) Stop the TIM PWM and disable DMA transfer. |
| |
| @endverbatim |
| * @{ |
| */ |
| /** |
| * @brief Initializes the TIM PWM Time Base according to the specified |
| * parameters in the TIM_HandleTypeDef and initializes the associated handle. |
| * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) |
| * requires a timer reset to avoid unexpected direction |
| * due to DIR bit readonly in center aligned mode. |
| * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() |
| * @param htim TIM PWM handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) |
| { |
| /* Check the TIM handle allocation */ |
| if (htim == NULL) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); |
| |
| if (htim->State == HAL_TIM_STATE_RESET) |
| { |
| /* Allocate lock resource and initialize it */ |
| htim->Lock = HAL_UNLOCKED; |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| /* Reset interrupt callbacks to legacy weak callbacks */ |
| TIM_ResetCallback(htim); |
| |
| if (htim->PWM_MspInitCallback == NULL) |
| { |
| htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; |
| } |
| /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
| htim->PWM_MspInitCallback(htim); |
| #else |
| /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| HAL_TIM_PWM_MspInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| } |
| |
| /* Set the TIM state */ |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Init the base time for the PWM */ |
| TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| |
| /* Initialize the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_READY; |
| |
| /* Initialize the TIM channels state */ |
| TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Initialize the TIM state*/ |
| htim->State = HAL_TIM_STATE_READY; |
| |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief DeInitializes the TIM peripheral |
| * @param htim TIM PWM handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Disable the TIM Peripheral Clock */ |
| __HAL_TIM_DISABLE(htim); |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| if (htim->PWM_MspDeInitCallback == NULL) |
| { |
| htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; |
| } |
| /* DeInit the low level hardware */ |
| htim->PWM_MspDeInitCallback(htim); |
| #else |
| /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ |
| HAL_TIM_PWM_MspDeInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| |
| /* Change the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; |
| |
| /* Change the TIM channels state */ |
| TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); |
| TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); |
| |
| /* Change TIM state */ |
| htim->State = HAL_TIM_STATE_RESET; |
| |
| /* Release Lock */ |
| __HAL_UNLOCK(htim); |
| |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Initializes the TIM PWM MSP. |
| * @param htim TIM PWM handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_PWM_MspInit could be implemented in the user file |
| */ |
| } |
| |
| /** |
| * @brief DeInitializes TIM PWM MSP. |
| * @param htim TIM PWM handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_PWM_MspDeInit could be implemented in the user file |
| */ |
| } |
| |
| /** |
| * @brief Starts the PWM signal generation. |
| * @param htim TIM handle |
| * @param Channel TIM Channels to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| uint32_t tmpsmcr; |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| /* Check the TIM channel state */ |
| if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| |
| /* Enable the Capture compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Enable the main output */ |
| __HAL_TIM_MOE_ENABLE(htim); |
| } |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the PWM signal generation. |
| * @param htim TIM PWM handle |
| * @param Channel TIM Channels to be disabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| /* Disable the Capture compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Disable the Main Output */ |
| __HAL_TIM_MOE_DISABLE(htim); |
| } |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Starts the PWM signal generation in interrupt mode. |
| * @param htim TIM PWM handle |
| * @param Channel TIM Channel to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| uint32_t tmpsmcr; |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| /* Check the TIM channel state */ |
| if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Enable the TIM Capture/Compare 1 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Enable the TIM Capture/Compare 2 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Enable the TIM Capture/Compare 3 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Enable the TIM Capture/Compare 4 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| |
| /* Enable the Capture compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Enable the main output */ |
| __HAL_TIM_MOE_ENABLE(htim); |
| } |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the PWM signal generation in interrupt mode. |
| * @param htim TIM PWM handle |
| * @param Channel TIM Channels to be disabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Disable the TIM Capture/Compare 1 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Disable the TIM Capture/Compare 2 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Disable the TIM Capture/Compare 3 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Disable the TIM Capture/Compare 4 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| |
| /* Disable the Capture compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Disable the Main Output */ |
| __HAL_TIM_MOE_DISABLE(htim); |
| } |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Starts the TIM PWM signal generation in DMA mode. |
| * @param htim TIM PWM handle |
| * @param Channel TIM Channels to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @param pData The source Buffer address. |
| * @param Length The length of data to be transferred from memory to TIM peripheral |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, |
| uint16_t Length) |
| { |
| uint32_t tmpsmcr; |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| /* Set the TIM channel state */ |
| if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) |
| { |
| return HAL_BUSY; |
| } |
| else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) |
| { |
| if ((pData == NULL) && (Length > 0U)) |
| { |
| return HAL_ERROR; |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| } |
| } |
| else |
| { |
| return HAL_ERROR; |
| } |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Set the DMA compare callbacks */ |
| htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| |
| /* Enable the TIM Capture/Compare 1 DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Set the DMA compare callbacks */ |
| htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| /* Enable the TIM Capture/Compare 2 DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Set the DMA compare callbacks */ |
| htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| /* Enable the TIM Output Capture/Compare 3 request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Set the DMA compare callbacks */ |
| htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| /* Enable the TIM Capture/Compare 4 DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| |
| /* Enable the Capture compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Enable the main output */ |
| __HAL_TIM_MOE_ENABLE(htim); |
| } |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM PWM signal generation in DMA mode. |
| * @param htim TIM PWM handle |
| * @param Channel TIM Channels to be disabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Disable the TIM Capture/Compare 1 DMA request */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Disable the TIM Capture/Compare 2 DMA request */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Disable the TIM Capture/Compare 3 DMA request */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Disable the TIM Capture/Compare 4 interrupt */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| |
| /* Disable the Capture compare channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Disable the Main Output */ |
| __HAL_TIM_MOE_DISABLE(htim); |
| } |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions |
| * @brief TIM Input Capture functions |
| * |
| @verbatim |
| ============================================================================== |
| ##### TIM Input Capture functions ##### |
| ============================================================================== |
| [..] |
| This section provides functions allowing to: |
| (+) Initialize and configure the TIM Input Capture. |
| (+) De-initialize the TIM Input Capture. |
| (+) Start the TIM Input Capture. |
| (+) Stop the TIM Input Capture. |
| (+) Start the TIM Input Capture and enable interrupt. |
| (+) Stop the TIM Input Capture and disable interrupt. |
| (+) Start the TIM Input Capture and enable DMA transfer. |
| (+) Stop the TIM Input Capture and disable DMA transfer. |
| |
| @endverbatim |
| * @{ |
| */ |
| /** |
| * @brief Initializes the TIM Input Capture Time base according to the specified |
| * parameters in the TIM_HandleTypeDef and initializes the associated handle. |
| * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) |
| * requires a timer reset to avoid unexpected direction |
| * due to DIR bit readonly in center aligned mode. |
| * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() |
| * @param htim TIM Input Capture handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) |
| { |
| /* Check the TIM handle allocation */ |
| if (htim == NULL) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); |
| |
| if (htim->State == HAL_TIM_STATE_RESET) |
| { |
| /* Allocate lock resource and initialize it */ |
| htim->Lock = HAL_UNLOCKED; |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| /* Reset interrupt callbacks to legacy weak callbacks */ |
| TIM_ResetCallback(htim); |
| |
| if (htim->IC_MspInitCallback == NULL) |
| { |
| htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; |
| } |
| /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
| htim->IC_MspInitCallback(htim); |
| #else |
| /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| HAL_TIM_IC_MspInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| } |
| |
| /* Set the TIM state */ |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Init the base time for the input capture */ |
| TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| |
| /* Initialize the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_READY; |
| |
| /* Initialize the TIM channels state */ |
| TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Initialize the TIM state*/ |
| htim->State = HAL_TIM_STATE_READY; |
| |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief DeInitializes the TIM peripheral |
| * @param htim TIM Input Capture handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Disable the TIM Peripheral Clock */ |
| __HAL_TIM_DISABLE(htim); |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| if (htim->IC_MspDeInitCallback == NULL) |
| { |
| htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; |
| } |
| /* DeInit the low level hardware */ |
| htim->IC_MspDeInitCallback(htim); |
| #else |
| /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ |
| HAL_TIM_IC_MspDeInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| |
| /* Change the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; |
| |
| /* Change the TIM channels state */ |
| TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); |
| TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); |
| |
| /* Change TIM state */ |
| htim->State = HAL_TIM_STATE_RESET; |
| |
| /* Release Lock */ |
| __HAL_UNLOCK(htim); |
| |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Initializes the TIM Input Capture MSP. |
| * @param htim TIM Input Capture handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_IC_MspInit could be implemented in the user file |
| */ |
| } |
| |
| /** |
| * @brief DeInitializes TIM Input Capture MSP. |
| * @param htim TIM handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_IC_MspDeInit could be implemented in the user file |
| */ |
| } |
| |
| /** |
| * @brief Starts the TIM Input Capture measurement. |
| * @param htim TIM Input Capture handle |
| * @param Channel TIM Channels to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| uint32_t tmpsmcr; |
| HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| /* Check the TIM channel state */ |
| if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| |
| /* Enable the Input Capture channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM Input Capture measurement. |
| * @param htim TIM Input Capture handle |
| * @param Channel TIM Channels to be disabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| /* Disable the Input Capture channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Starts the TIM Input Capture measurement in interrupt mode. |
| * @param htim TIM Input Capture handle |
| * @param Channel TIM Channels to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| uint32_t tmpsmcr; |
| HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| /* Check the TIM channel state */ |
| if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Enable the TIM Capture/Compare 1 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Enable the TIM Capture/Compare 2 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Enable the TIM Capture/Compare 3 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Enable the TIM Capture/Compare 4 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| /* Enable the Input Capture channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM Input Capture measurement in interrupt mode. |
| * @param htim TIM Input Capture handle |
| * @param Channel TIM Channels to be disabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Disable the TIM Capture/Compare 1 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Disable the TIM Capture/Compare 2 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Disable the TIM Capture/Compare 3 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Disable the TIM Capture/Compare 4 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| |
| /* Disable the Input Capture channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Starts the TIM Input Capture measurement in DMA mode. |
| * @param htim TIM Input Capture handle |
| * @param Channel TIM Channels to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @param pData The destination Buffer address. |
| * @param Length The length of data to be transferred from TIM peripheral to memory. |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
| { |
| uint32_t tmpsmcr; |
| HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); |
| |
| /* Set the TIM channel state */ |
| if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) |
| || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) |
| { |
| return HAL_BUSY; |
| } |
| else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) |
| && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| if ((pData == NULL) && (Length > 0U)) |
| { |
| return HAL_ERROR; |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); |
| } |
| } |
| else |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Enable the Input Capture channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| |
| /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ |
| if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
| { |
| tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; |
| if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| } |
| else |
| { |
| __HAL_TIM_ENABLE(htim); |
| } |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Set the DMA capture callbacks */ |
| htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; |
| htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| /* Enable the TIM Capture/Compare 1 DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Set the DMA capture callbacks */ |
| htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; |
| htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| /* Enable the TIM Capture/Compare 2 DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Set the DMA capture callbacks */ |
| htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; |
| htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| /* Enable the TIM Capture/Compare 3 DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Set the DMA capture callbacks */ |
| htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; |
| htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; |
| |
| /* Set the DMA error callback */ |
| htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; |
| |
| /* Enable the DMA stream */ |
| if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, |
| Length) != HAL_OK) |
| { |
| /* Return error status */ |
| return HAL_ERROR; |
| } |
| /* Enable the TIM Capture/Compare 4 DMA request */ |
| __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM Input Capture measurement in DMA mode. |
| * @param htim TIM Input Capture handle |
| * @param Channel TIM Channels to be disabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); |
| |
| /* Disable the Input Capture channel */ |
| TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| /* Disable the TIM Capture/Compare 1 DMA request */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| /* Disable the TIM Capture/Compare 2 DMA request */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); |
| break; |
| } |
| |
| case TIM_CHANNEL_3: |
| { |
| /* Disable the TIM Capture/Compare 3 DMA request */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); |
| break; |
| } |
| |
| case TIM_CHANNEL_4: |
| { |
| /* Disable the TIM Capture/Compare 4 DMA request */ |
| __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); |
| (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); |
| break; |
| } |
| |
| default: |
| break; |
| } |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| /** |
| * @} |
| */ |
| |
| /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions |
| * @brief TIM One Pulse functions |
| * |
| @verbatim |
| ============================================================================== |
| ##### TIM One Pulse functions ##### |
| ============================================================================== |
| [..] |
| This section provides functions allowing to: |
| (+) Initialize and configure the TIM One Pulse. |
| (+) De-initialize the TIM One Pulse. |
| (+) Start the TIM One Pulse. |
| (+) Stop the TIM One Pulse. |
| (+) Start the TIM One Pulse and enable interrupt. |
| (+) Stop the TIM One Pulse and disable interrupt. |
| (+) Start the TIM One Pulse and enable DMA transfer. |
| (+) Stop the TIM One Pulse and disable DMA transfer. |
| |
| @endverbatim |
| * @{ |
| */ |
| /** |
| * @brief Initializes the TIM One Pulse Time Base according to the specified |
| * parameters in the TIM_HandleTypeDef and initializes the associated handle. |
| * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) |
| * requires a timer reset to avoid unexpected direction |
| * due to DIR bit readonly in center aligned mode. |
| * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() |
| * @note When the timer instance is initialized in One Pulse mode, timer |
| * channels 1 and channel 2 are reserved and cannot be used for other |
| * purpose. |
| * @param htim TIM One Pulse handle |
| * @param OnePulseMode Select the One pulse mode. |
| * This parameter can be one of the following values: |
| * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. |
| * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) |
| { |
| /* Check the TIM handle allocation */ |
| if (htim == NULL) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| assert_param(IS_TIM_OPM_MODE(OnePulseMode)); |
| assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); |
| |
| if (htim->State == HAL_TIM_STATE_RESET) |
| { |
| /* Allocate lock resource and initialize it */ |
| htim->Lock = HAL_UNLOCKED; |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| /* Reset interrupt callbacks to legacy weak callbacks */ |
| TIM_ResetCallback(htim); |
| |
| if (htim->OnePulse_MspInitCallback == NULL) |
| { |
| htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; |
| } |
| /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
| htim->OnePulse_MspInitCallback(htim); |
| #else |
| /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| HAL_TIM_OnePulse_MspInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| } |
| |
| /* Set the TIM state */ |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Configure the Time base in the One Pulse Mode */ |
| TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| |
| /* Reset the OPM Bit */ |
| htim->Instance->CR1 &= ~TIM_CR1_OPM; |
| |
| /* Configure the OPM Mode */ |
| htim->Instance->CR1 |= OnePulseMode; |
| |
| /* Initialize the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_READY; |
| |
| /* Initialize the TIM channels state */ |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Initialize the TIM state*/ |
| htim->State = HAL_TIM_STATE_READY; |
| |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief DeInitializes the TIM One Pulse |
| * @param htim TIM One Pulse handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Disable the TIM Peripheral Clock */ |
| __HAL_TIM_DISABLE(htim); |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| if (htim->OnePulse_MspDeInitCallback == NULL) |
| { |
| htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; |
| } |
| /* DeInit the low level hardware */ |
| htim->OnePulse_MspDeInitCallback(htim); |
| #else |
| /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| HAL_TIM_OnePulse_MspDeInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| |
| /* Change the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; |
| |
| /* Set the TIM channel state */ |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); |
| |
| /* Change TIM state */ |
| htim->State = HAL_TIM_STATE_RESET; |
| |
| /* Release Lock */ |
| __HAL_UNLOCK(htim); |
| |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Initializes the TIM One Pulse MSP. |
| * @param htim TIM One Pulse handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_OnePulse_MspInit could be implemented in the user file |
| */ |
| } |
| |
| /** |
| * @brief DeInitializes TIM One Pulse MSP. |
| * @param htim TIM One Pulse handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file |
| */ |
| } |
| |
| /** |
| * @brief Starts the TIM One Pulse signal generation. |
| * @note Though OutputChannel parameter is deprecated and ignored by the function |
| * it has been kept to avoid HAL_TIM API compatibility break. |
| * @note The pulse output channel is determined when calling |
| * @ref HAL_TIM_OnePulse_ConfigChannel(). |
| * @param htim TIM One Pulse handle |
| * @param OutputChannel See note above |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| { |
| HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); |
| HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); |
| |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(OutputChannel); |
| |
| /* Check the TIM channels state */ |
| if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Set the TIM channels state */ |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| |
| /* Enable the Capture compare and the Input Capture channels |
| (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together |
| |
| No need to enable the counter, it's enabled automatically by hardware |
| (the counter starts in response to a stimulus and generate a pulse */ |
| |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Enable the main output */ |
| __HAL_TIM_MOE_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM One Pulse signal generation. |
| * @note Though OutputChannel parameter is deprecated and ignored by the function |
| * it has been kept to avoid HAL_TIM API compatibility break. |
| * @note The pulse output channel is determined when calling |
| * @ref HAL_TIM_OnePulse_ConfigChannel(). |
| * @param htim TIM One Pulse handle |
| * @param OutputChannel See note above |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(OutputChannel); |
| |
| /* Disable the Capture compare and the Input Capture channels |
| (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ |
| |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Disable the Main Output */ |
| __HAL_TIM_MOE_DISABLE(htim); |
| } |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channels state */ |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Starts the TIM One Pulse signal generation in interrupt mode. |
| * @note Though OutputChannel parameter is deprecated and ignored by the function |
| * it has been kept to avoid HAL_TIM API compatibility break. |
| * @note The pulse output channel is determined when calling |
| * @ref HAL_TIM_OnePulse_ConfigChannel(). |
| * @param htim TIM One Pulse handle |
| * @param OutputChannel See note above |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| { |
| HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); |
| HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); |
| |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(OutputChannel); |
| |
| /* Check the TIM channels state */ |
| if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Set the TIM channels state */ |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| |
| /* Enable the Capture compare and the Input Capture channels |
| (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together |
| |
| No need to enable the counter, it's enabled automatically by hardware |
| (the counter starts in response to a stimulus and generate a pulse */ |
| |
| /* Enable the TIM Capture/Compare 1 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| |
| /* Enable the TIM Capture/Compare 2 interrupt */ |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Enable the main output */ |
| __HAL_TIM_MOE_ENABLE(htim); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM One Pulse signal generation in interrupt mode. |
| * @note Though OutputChannel parameter is deprecated and ignored by the function |
| * it has been kept to avoid HAL_TIM API compatibility break. |
| * @note The pulse output channel is determined when calling |
| * @ref HAL_TIM_OnePulse_ConfigChannel(). |
| * @param htim TIM One Pulse handle |
| * @param OutputChannel See note above |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(OutputChannel); |
| |
| /* Disable the TIM Capture/Compare 1 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| |
| /* Disable the TIM Capture/Compare 2 interrupt */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| |
| /* Disable the Capture compare and the Input Capture channels |
| (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| |
| if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) |
| { |
| /* Disable the Main Output */ |
| __HAL_TIM_MOE_DISABLE(htim); |
| } |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channels state */ |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @} |
| */ |
| |
| /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions |
| * @brief TIM Encoder functions |
| * |
| @verbatim |
| ============================================================================== |
| ##### TIM Encoder functions ##### |
| ============================================================================== |
| [..] |
| This section provides functions allowing to: |
| (+) Initialize and configure the TIM Encoder. |
| (+) De-initialize the TIM Encoder. |
| (+) Start the TIM Encoder. |
| (+) Stop the TIM Encoder. |
| (+) Start the TIM Encoder and enable interrupt. |
| (+) Stop the TIM Encoder and disable interrupt. |
| (+) Start the TIM Encoder and enable DMA transfer. |
| (+) Stop the TIM Encoder and disable DMA transfer. |
| |
| @endverbatim |
| * @{ |
| */ |
| /** |
| * @brief Initializes the TIM Encoder Interface and initialize the associated handle. |
| * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) |
| * requires a timer reset to avoid unexpected direction |
| * due to DIR bit readonly in center aligned mode. |
| * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() |
| * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together |
| * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource |
| * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa |
| * @note When the timer instance is initialized in Encoder mode, timer |
| * channels 1 and channel 2 are reserved and cannot be used for other |
| * purpose. |
| * @param htim TIM Encoder Interface handle |
| * @param sConfig TIM Encoder Interface configuration structure |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) |
| { |
| uint32_t tmpsmcr; |
| uint32_t tmpccmr1; |
| uint32_t tmpccer; |
| |
| /* Check the TIM handle allocation */ |
| if (htim == NULL) |
| { |
| return HAL_ERROR; |
| } |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); |
| assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); |
| assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); |
| assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); |
| assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); |
| assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); |
| assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); |
| assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); |
| assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); |
| assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); |
| assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); |
| |
| if (htim->State == HAL_TIM_STATE_RESET) |
| { |
| /* Allocate lock resource and initialize it */ |
| htim->Lock = HAL_UNLOCKED; |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| /* Reset interrupt callbacks to legacy weak callbacks */ |
| TIM_ResetCallback(htim); |
| |
| if (htim->Encoder_MspInitCallback == NULL) |
| { |
| htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; |
| } |
| /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
| htim->Encoder_MspInitCallback(htim); |
| #else |
| /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| HAL_TIM_Encoder_MspInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| } |
| |
| /* Set the TIM state */ |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Reset the SMS and ECE bits */ |
| htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); |
| |
| /* Configure the Time base in the Encoder Mode */ |
| TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| |
| /* Get the TIMx SMCR register value */ |
| tmpsmcr = htim->Instance->SMCR; |
| |
| /* Get the TIMx CCMR1 register value */ |
| tmpccmr1 = htim->Instance->CCMR1; |
| |
| /* Get the TIMx CCER register value */ |
| tmpccer = htim->Instance->CCER; |
| |
| /* Set the encoder Mode */ |
| tmpsmcr |= sConfig->EncoderMode; |
| |
| /* Select the Capture Compare 1 and the Capture Compare 2 as input */ |
| tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); |
| tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); |
| |
| /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ |
| tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); |
| tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); |
| tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); |
| tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); |
| |
| /* Set the TI1 and the TI2 Polarities */ |
| tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); |
| tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); |
| tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); |
| |
| /* Write to TIMx SMCR */ |
| htim->Instance->SMCR = tmpsmcr; |
| |
| /* Write to TIMx CCMR1 */ |
| htim->Instance->CCMR1 = tmpccmr1; |
| |
| /* Write to TIMx CCER */ |
| htim->Instance->CCER = tmpccer; |
| |
| /* Initialize the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_READY; |
| |
| /* Set the TIM channels state */ |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| |
| /* Initialize the TIM state*/ |
| htim->State = HAL_TIM_STATE_READY; |
| |
| return HAL_OK; |
| } |
| |
| |
| /** |
| * @brief DeInitializes the TIM Encoder interface |
| * @param htim TIM Encoder Interface handle |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| |
| htim->State = HAL_TIM_STATE_BUSY; |
| |
| /* Disable the TIM Peripheral Clock */ |
| __HAL_TIM_DISABLE(htim); |
| |
| #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| if (htim->Encoder_MspDeInitCallback == NULL) |
| { |
| htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; |
| } |
| /* DeInit the low level hardware */ |
| htim->Encoder_MspDeInitCallback(htim); |
| #else |
| /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| HAL_TIM_Encoder_MspDeInit(htim); |
| #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| |
| /* Change the DMA burst operation state */ |
| htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; |
| |
| /* Set the TIM channels state */ |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); |
| |
| /* Change TIM state */ |
| htim->State = HAL_TIM_STATE_RESET; |
| |
| /* Release Lock */ |
| __HAL_UNLOCK(htim); |
| |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Initializes the TIM Encoder Interface MSP. |
| * @param htim TIM Encoder Interface handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_Encoder_MspInit could be implemented in the user file |
| */ |
| } |
| |
| /** |
| * @brief DeInitializes TIM Encoder Interface MSP. |
| * @param htim TIM Encoder Interface handle |
| * @retval None |
| */ |
| __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) |
| { |
| /* Prevent unused argument(s) compilation warning */ |
| UNUSED(htim); |
| |
| /* NOTE : This function should not be modified, when the callback is needed, |
| the HAL_TIM_Encoder_MspDeInit could be implemented in the user file |
| */ |
| } |
| |
| /** |
| * @brief Starts the TIM Encoder Interface. |
| * @param htim TIM Encoder Interface handle |
| * @param Channel TIM Channels to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); |
| HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); |
| |
| /* Set the TIM channel(s) state */ |
| if (Channel == TIM_CHANNEL_1) |
| { |
| if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| return HAL_ERROR; |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| } |
| } |
| else if (Channel == TIM_CHANNEL_2) |
| { |
| if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| return HAL_ERROR; |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| } |
| } |
| else |
| { |
| if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| return HAL_ERROR; |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| } |
| } |
| |
| /* Enable the encoder interface channels */ |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| break; |
| } |
| |
| default : |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| break; |
| } |
| } |
| /* Enable the Peripheral */ |
| __HAL_TIM_ENABLE(htim); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM Encoder Interface. |
| * @param htim TIM Encoder Interface handle |
| * @param Channel TIM Channels to be disabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); |
| |
| /* Disable the Input Capture channels 1 and 2 |
| (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| break; |
| } |
| |
| default : |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| break; |
| } |
| } |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channel(s) state */ |
| if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) |
| { |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Starts the TIM Encoder Interface in interrupt mode. |
| * @param htim TIM Encoder Interface handle |
| * @param Channel TIM Channels to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); |
| HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); |
| |
| /* Set the TIM channel(s) state */ |
| if (Channel == TIM_CHANNEL_1) |
| { |
| if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| return HAL_ERROR; |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| } |
| } |
| else if (Channel == TIM_CHANNEL_2) |
| { |
| if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| return HAL_ERROR; |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| } |
| } |
| else |
| { |
| if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) |
| || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| return HAL_ERROR; |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); |
| } |
| } |
| |
| /* Enable the encoder interface channels */ |
| /* Enable the capture compare Interrupts 1 and/or 2 */ |
| switch (Channel) |
| { |
| case TIM_CHANNEL_1: |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| break; |
| } |
| |
| case TIM_CHANNEL_2: |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| break; |
| } |
| |
| default : |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| break; |
| } |
| } |
| |
| /* Enable the Peripheral */ |
| __HAL_TIM_ENABLE(htim); |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Stops the TIM Encoder Interface in interrupt mode. |
| * @param htim TIM Encoder Interface handle |
| * @param Channel TIM Channels to be disabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| { |
| /* Check the parameters */ |
| assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); |
| |
| /* Disable the Input Capture channels 1 and 2 |
| (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ |
| if (Channel == TIM_CHANNEL_1) |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| |
| /* Disable the capture compare Interrupts 1 */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| } |
| else if (Channel == TIM_CHANNEL_2) |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| |
| /* Disable the capture compare Interrupts 2 */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| } |
| else |
| { |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| |
| /* Disable the capture compare Interrupts 1 and 2 */ |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| } |
| |
| /* Disable the Peripheral */ |
| __HAL_TIM_DISABLE(htim); |
| |
| /* Set the TIM channel(s) state */ |
| if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) |
| { |
| TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); |
| } |
| |
| /* Return function status */ |
| return HAL_OK; |
| } |
| |
| /** |
| * @brief Starts the TIM Encoder Interface in DMA mode. |
| * @param htim TIM Encoder Interface handle |
| * @param Channel TIM Channels to be enabled |
| * This parameter can be one of the following values: |
| * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected |
| * @param pData1 The destination Buffer address for IC1. |
| * @param pData2 The destination Buffer address for IC2. |
| * @param Length The length of data to be transferred from TIM peripheral to memory. |
| * @retval HAL status |
| */ |
| HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, |
| uint32_t *pData2, uint16_t Length) |
| { |
| HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); |
| HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); |
| HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); |
| |
| /* Check the parameters */ |
| assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); |
| |
| /* Set the TIM channel(s) state */ |
| if (Channel == TIM_CHANNEL_1) |
| { |
| if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) |
| || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) |
| { |
| return HAL_BUSY; |
| } |
| else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) |
| && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| if ((pData1 == NULL) && (Length > 0U)) |
| { |
| return HAL_ERROR; |
| } |
| else |
| { |
| TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); |
| } |
| } |
| else |
| { |
| return HAL_ERROR; |
| } |
| } |
| else if (Channel == TIM_CHANNEL_2) |
| { |
| if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) |
| || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) |
| { |
| return HAL_BUSY; |
| } |
| else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) |
| && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) |
| { |
| if ((pData2 == NULL) && (Length > 0U)) |
| { |
| return HAL_ERROR; |
| } |