Release v1.2.9
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h index b59ff6d..94129b9 100644 --- a/Inc/Legacy/stm32_hal_legacy.h +++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -37,16 +37,12 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#if defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#if defined(STM32U5) -#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF -#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF -#endif /* STM32U5 */ -#endif /* STM32U5 || STM32H7 || STM32MP1 */ +#endif /* STM32H7 || STM32MP1 */ /** * @} */ @@ -279,7 +275,7 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif @@ -476,7 +472,9 @@ #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -552,6 +550,16 @@ #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ /** * @} @@ -800,6 +808,21 @@ #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -1243,10 +1266,10 @@ #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) +#if defined(STM32H5) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 */ +#endif /* STM32H5 || STM32H7RS */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1258,10 +1281,10 @@ #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1599,6 +1622,8 @@ #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1809,7 +1834,7 @@ #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1991,12 +2016,12 @@ /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS */ /** * @} @@ -2311,8 +2336,8 @@ #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2345,8 +2370,8 @@ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2403,8 +2428,8 @@ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2421,7 +2446,7 @@ __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -2723,6 +2748,12 @@ #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3646,8 +3677,12 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) + defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3749,8 +3784,10 @@ #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3894,9 +3931,9 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ - defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ + defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32WBA) || \ + defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3932,7 +3969,9 @@ #endif /* STM32F1 */ #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ - defined (STM32L0) || defined (STM32L1) + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG #endif @@ -4217,6 +4256,9 @@ #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */
diff --git a/Inc/Legacy/stm32f2xx_hal_can_legacy.h b/Inc/Legacy/stm32f2xx_hal_can_legacy.h index c48454e..7b7cf24 100644 --- a/Inc/Legacy/stm32f2xx_hal_can_legacy.h +++ b/Inc/Legacy/stm32f2xx_hal_can_legacy.h
@@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file
diff --git a/Inc/stm32f2xx_hal_can.h b/Inc/stm32f2xx_hal_can.h index 8022d29..1ac6199 100644 --- a/Inc/stm32f2xx_hal_can.h +++ b/Inc/stm32f2xx_hal_can.h
@@ -209,7 +209,11 @@ /** * @brief CAN handle Structure definition */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 typedef struct __CAN_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ { CAN_TypeDef *Instance; /*!< Register base address */
diff --git a/Inc/stm32f2xx_hal_cortex.h b/Inc/stm32f2xx_hal_cortex.h index 75d18c5..1528477 100644 --- a/Inc/stm32f2xx_hal_cortex.h +++ b/Inc/stm32f2xx_hal_cortex.h
@@ -6,9 +6,6 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.</center></h2> - * * Copyright (c) 2017 STMicroelectronics. * All rights reserved. * @@ -409,5 +406,4 @@ #endif #endif /* __STM32F2xx_HAL_CORTEX_H */ -
diff --git a/Inc/stm32f2xx_hal_dcmi.h b/Inc/stm32f2xx_hal_dcmi.h index b6ab036..17d4fe1 100644 --- a/Inc/stm32f2xx_hal_dcmi.h +++ b/Inc/stm32f2xx_hal_dcmi.h
@@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.</center></h2> + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -57,7 +56,7 @@ } HAL_DCMI_StateTypeDef; /** - * @brief DCMIEx Embedded Synchronisation CODE Init structure definition + * @brief DCMI Embedded Synchronisation CODE Init structure definition */ typedef struct { @@ -68,7 +67,7 @@ } DCMI_CodesInitTypeDef; /** - * @brief DCMI Embedded Synchronisation CODE Init structure definition + * @brief DCMI Embedded Synchronisation UNMASK Init structure definition */ typedef struct { @@ -110,7 +109,11 @@ /** * @brief DCMI handle Structure definition */ -typedef struct __DCMI_HandleTypeDef +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +typedef struct __DCMI_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ { DCMI_TypeDef *Instance; /*!< DCMI Register base address */ @@ -131,6 +134,7 @@ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */ __IO uint32_t ErrorCode; /*!< DCMI Error code */ + #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */ void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */ @@ -142,6 +146,9 @@ } DCMI_HandleTypeDef; #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DCMI Callback ID enumeration definition + */ typedef enum { HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */ @@ -153,7 +160,10 @@ } HAL_DCMI_CallbackIDTypeDef; -typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); +/** + * @brief HAL DCMI Callback pointer definition + */ +typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); /*!< pointer to a DCMI callback function */ #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ @@ -169,14 +179,14 @@ /** @defgroup DCMI_Error_Code DCMI Error Code * @{ */ -#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */ -#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */ -#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ -#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */ +#define HAL_DCMI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_DCMI_ERROR_OVR (0x00000001U) /*!< Overrun error */ +#define HAL_DCMI_ERROR_SYNC (0x00000002U) /*!< Synchronization error */ +#define HAL_DCMI_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_DCMI_ERROR_DMA (0x00000040U) /*!< DMA error */ #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) -#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid callback error */ -#endif +#define HAL_DCMI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid callback error */ +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ /** * @} */ @@ -184,10 +194,11 @@ /** @defgroup DCMI_Capture_Mode DCMI Capture Mode * @{ */ -#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously - into the destination memory through the DMA */ -#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of - frame and then transfers a single frame through the DMA */ +#define DCMI_MODE_CONTINUOUS (0x00000000U) /*!< The received data are transferred continuously + into the destination memory through the DMA */ +#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of + frame and then transfers a single frame + through the DMA */ /** * @} */ @@ -195,10 +206,10 @@ /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode * @{ */ -#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop) - is synchronized with the HSYNC/VSYNC signals */ -#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with - synchronization codes embedded in the data flow */ +#define DCMI_SYNCHRO_HARDWARE (0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop) + is synchronized with the HSYNC/VSYNC signals */ +#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized + with synchronization codes embedded in the data flow */ /** * @} @@ -207,7 +218,7 @@ /** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity * @{ */ -#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) /*!< Pixel clock active on Falling edge */ +#define DCMI_PCKPOLARITY_FALLING (0x00000000U) /*!< Pixel clock active on Falling edge */ #define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */ /** @@ -217,7 +228,7 @@ /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity * @{ */ -#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Vertical synchronization active Low */ +#define DCMI_VSPOLARITY_LOW (0x00000000U) /*!< Vertical synchronization active Low */ #define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */ /** @@ -227,7 +238,7 @@ /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity * @{ */ -#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */ +#define DCMI_HSPOLARITY_LOW (0x00000000U) /*!< Horizontal synchronization active Low */ #define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */ /** @@ -237,7 +248,7 @@ /** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG * @{ */ -#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) /*!< Mode JPEG Disabled */ +#define DCMI_JPEG_DISABLE (0x00000000U) /*!< Mode JPEG Disabled */ #define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */ /** @@ -247,7 +258,7 @@ /** @defgroup DCMI_Capture_Rate DCMI Capture Rate * @{ */ -#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) /*!< All frames are captured */ +#define DCMI_CR_ALL_FRAME (0x00000000U) /*!< All frames are captured */ #define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */ #define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */ @@ -258,10 +269,11 @@ /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode * @{ */ -#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */ -#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */ -#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */ -#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */ +#define DCMI_EXTEND_DATA_8B (0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */ +#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */ +#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */ +#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 |\ + DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */ /** * @} @@ -270,7 +282,7 @@ /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate * @{ */ -#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */ +#define DCMI_WINDOW_COORDINATE (0x3FFFU) /*!< Window coordinate */ /** * @} @@ -279,7 +291,7 @@ /** @defgroup DCMI_Window_Height DCMI Window Height * @{ */ -#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */ +#define DCMI_WINDOW_HEIGHT (0x1FFFU) /*!< Window Height */ /** * @} @@ -304,9 +316,11 @@ /** * @brief DCMI SR register */ -#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */ -#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */ -#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */ +#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization + between lines) */ +#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization + between frames) */ +#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */ /** * @brief DCMI RIS register */ @@ -318,7 +332,8 @@ /** * @brief DCMI MIS register */ -#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */ +#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked + interrupt status */ #define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */ #define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */ #define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */ @@ -340,11 +355,15 @@ * @param __HANDLE__ specifies the DCMI handle. * @retval None */ -#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) +#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) +#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ /** * @brief Enable the DCMI. @@ -382,8 +401,9 @@ * @retval The state of FLAG. */ #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\ -((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\ - (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__))) + ((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\ + (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) :\ + ((__HANDLE__)->Instance->SR & (__FLAG__))) /** * @brief Clear the DCMI pending flags. @@ -451,8 +471,8 @@ */ /** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions - * @{ - */ + * @{ + */ /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi); @@ -461,7 +481,8 @@ /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, + pDCMI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ /** @@ -469,8 +490,8 @@ */ /** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions - * @{ - */ + * @{ + */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length); HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi); @@ -486,24 +507,25 @@ */ /** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ + * @{ + */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize); +HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, + uint32_t YSize); HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi); -HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask); +HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask); /** * @} */ /** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions - * @{ - */ + * @{ + */ /* Peripheral State functions *************************************************/ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi); -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi); +uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi); /** * @} */ @@ -518,8 +540,24 @@ /** @defgroup DCMI_Private_Constants DCMI Private Constants * @{ */ +/** @defgroup DCMI_MIS_INDEX DCMI Mis Index + * @{ + */ #define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */ + +/** + * @} + */ + +/** @defgroup DCMI_SR_INDEX DCMI SR Index + * @{ + */ #define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */ + +/** + * @} + */ + /** * @} */ @@ -584,5 +622,3 @@ #endif #endif /* STM32F2xx_HAL_DCMI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f2xx_hal_dcmi_ex.h b/Inc/stm32f2xx_hal_dcmi_ex.h index 9d917e6..44502a3 100644 --- a/Inc/stm32f2xx_hal_dcmi_ex.h +++ b/Inc/stm32f2xx_hal_dcmi_ex.h
@@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - * <h2><center>© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.</center></h2> + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -34,4 +33,3 @@ #endif /* __STM32F2xx_HAL_DCMI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f2xx_hal_hash.h b/Inc/stm32f2xx_hal_hash.h index 5712f53..c146701 100644 --- a/Inc/stm32f2xx_hal_hash.h +++ b/Inc/stm32f2xx_hal_hash.h
@@ -117,13 +117,13 @@ { HASH_InitTypeDef Init; /*!< HASH required parameters */ - uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ @@ -434,15 +434,17 @@ /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); @@ -455,15 +457,15 @@ */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** @@ -475,9 +477,9 @@ */ /* HASH processing using DMA *************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -489,9 +491,11 @@ */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -502,9 +506,9 @@ * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -516,8 +520,8 @@ */ /* HASH-HMAC processing using DMA ********************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -529,13 +533,13 @@ /* Peripheral State methods **************************************************/ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash); -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash); +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash); +HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash); void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash); /** * @} @@ -552,19 +556,27 @@ */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); /** * @}
diff --git a/Inc/stm32f2xx_hal_nand.h b/Inc/stm32f2xx_hal_nand.h index 9dca732..7528985 100644 --- a/Inc/stm32f2xx_hal_nand.h +++ b/Inc/stm32f2xx_hal_nand.h
@@ -193,7 +193,7 @@ FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
diff --git a/Inc/stm32f2xx_hal_pccard.h b/Inc/stm32f2xx_hal_pccard.h index ef7df02..f9e23b9 100644 --- a/Inc/stm32f2xx_hal_pccard.h +++ b/Inc/stm32f2xx_hal_pccard.h
@@ -67,7 +67,7 @@ typedef struct __PCCARD_HandleTypeDef #else typedef struct -#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ { FSMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */ @@ -81,7 +81,7 @@ void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */ void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */ void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */ -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ } PCCARD_HandleTypeDef; #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) @@ -99,7 +99,7 @@ * @brief HAL PCCARD Callback pointer definition */ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /** * @} */ @@ -121,7 +121,7 @@ } while(0) #else #define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET) -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /** * @} */ @@ -136,7 +136,8 @@ */ /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, - FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); + FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, + FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard); @@ -164,7 +165,7 @@ pPCCARD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /** * @} */
diff --git a/Inc/stm32f2xx_hal_pcd.h b/Inc/stm32f2xx_hal_pcd.h index 173d4d2..247c3ee 100644 --- a/Inc/stm32f2xx_hal_pcd.h +++ b/Inc/stm32f2xx_hal_pcd.h
@@ -354,7 +354,7 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); #if defined (USB_OTG_FS) || defined (USB_OTG_HS) -HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode); +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
diff --git a/Inc/stm32f2xx_hal_rtc.h b/Inc/stm32f2xx_hal_rtc.h index e975bdc..e93c9ca 100644 --- a/Inc/stm32f2xx_hal_rtc.h +++ b/Inc/stm32f2xx_hal_rtc.h
@@ -726,7 +726,7 @@ #define RTC_TIMEOUT_VALUE 1000U -#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 connected to the RTC Alarm event */ /** * @} */
diff --git a/Inc/stm32f2xx_hal_rtc_ex.h b/Inc/stm32f2xx_hal_rtc_ex.h index b72c22f..520cf31 100644 --- a/Inc/stm32f2xx_hal_rtc_ex.h +++ b/Inc/stm32f2xx_hal_rtc_ex.h
@@ -527,13 +527,13 @@ * @brief Enable event on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** * @brief Disable event on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. @@ -715,7 +715,7 @@ * @{ */ /* Extended RTC features functions *******************************************/ -void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); /** * @}
diff --git a/Inc/stm32f2xx_hal_spi.h b/Inc/stm32f2xx_hal_spi.h index 68503e4..072c888 100644 --- a/Inc/stm32f2xx_hal_spi.h +++ b/Inc/stm32f2xx_hal_spi.h
@@ -107,7 +107,7 @@ SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -339,11 +339,12 @@ * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -444,7 +445,7 @@ __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -488,8 +489,11 @@ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -505,7 +509,7 @@ * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -517,7 +521,7 @@ * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -627,7 +631,7 @@ */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -667,17 +671,17 @@ * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -703,8 +707,8 @@ * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */
diff --git a/Inc/stm32f2xx_hal_tim.h b/Inc/stm32f2xx_hal_tim.h index 1eb13ac..235806a 100644 --- a/Inc/stm32f2xx_hal_tim.h +++ b/Inc/stm32f2xx_hal_tim.h
@@ -385,29 +385,28 @@ */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -1654,8 +1653,9 @@ #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ - ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -1708,7 +1708,6 @@ #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) @@ -2046,7 +2045,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
diff --git a/Inc/stm32f2xx_hal_usart.h b/Inc/stm32f2xx_hal_usart.h index 803f1c5..e177d46 100644 --- a/Inc/stm32f2xx_hal_usart.h +++ b/Inc/stm32f2xx_hal_usart.h
@@ -624,7 +624,7 @@ */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup USART_Private_Functions USART Private Functions +/** @addtogroup USART_Private_Functions * @{ */
diff --git a/Inc/stm32f2xx_hal_wwdg.h b/Inc/stm32f2xx_hal_wwdg.h index 3d865e5..51a7c02 100644 --- a/Inc/stm32f2xx_hal_wwdg.h +++ b/Inc/stm32f2xx_hal_wwdg.h
@@ -183,7 +183,7 @@ /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__ WWDG handle + * @param __HANDLE__: WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt @@ -296,3 +296,4 @@ #endif #endif /* STM32F2xx_HAL_WWDG_H */ +
diff --git a/Inc/stm32f2xx_ll_adc.h b/Inc/stm32f2xx_ll_adc.h index a90cc8c..14394ad 100644 --- a/Inc/stm32f2xx_ll_adc.h +++ b/Inc/stm32f2xx_ll_adc.h
@@ -1656,18 +1656,17 @@ __TEMPSENSOR_CALX_TEMP__,\ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - ((( ( \ - (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ - * 1000) \ - - \ - (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ - * 1000) \ - ) \ - ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ - ) + (__TEMPSENSOR_CALX_TEMP__) \ - ) + __ADC_RESOLUTION__) \ +(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000UL) \ + - \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000UL) \ + ) \ + ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ +) /** * @}
diff --git a/Inc/stm32f2xx_ll_dac.h b/Inc/stm32f2xx_ll_dac.h index 9207a10..1ab688c 100644 --- a/Inc/stm32f2xx_ll_dac.h +++ b/Inc/stm32f2xx_ll_dac.h
@@ -87,7 +87,6 @@ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) - #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted @@ -471,7 +470,7 @@ * @arg @ref LL_DAC_RESOLUTION_8B * @retval DAC conversion data (unit: digital value) */ -#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ / (__VREFANALOG_VOLTAGE__) \ )
diff --git a/Inc/stm32f2xx_ll_fsmc.h b/Inc/stm32f2xx_ll_fsmc.h index 771cfff..29abb61 100644 --- a/Inc/stm32f2xx_ll_fsmc.h +++ b/Inc/stm32f2xx_ll_fsmc.h
@@ -40,42 +40,42 @@ */ #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ - ((__BANK__) == FSMC_NORSRAM_BANK2) || \ - ((__BANK__) == FSMC_NORSRAM_BANK3) || \ - ((__BANK__) == FSMC_NORSRAM_BANK4)) + ((__BANK__) == FSMC_NORSRAM_BANK2) || \ + ((__BANK__) == FSMC_NORSRAM_BANK3) || \ + ((__BANK__) == FSMC_NORSRAM_BANK4)) #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) + ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) + ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ - ((__MODE__) == FSMC_ACCESS_MODE_B) || \ - ((__MODE__) == FSMC_ACCESS_MODE_C) || \ - ((__MODE__) == FSMC_ACCESS_MODE_D)) + ((__MODE__) == FSMC_ACCESS_MODE_B) || \ + ((__MODE__) == FSMC_ACCESS_MODE_C) || \ + ((__MODE__) == FSMC_ACCESS_MODE_D)) #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) + ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) + ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) + ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) + ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) + ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) + ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) + ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) + ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) + ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ - ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) + ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) @@ -88,18 +88,18 @@ #define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3) #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) + ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) + ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ - ((__STATE__) == FSMC_NAND_ECC_ENABLE)) + ((__STATE__) == FSMC_NAND_ECC_ENABLE)) #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) @@ -137,52 +137,53 @@ typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing*/ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FSMC_Memory_Type */ + This parameter can be a value of @ref FSMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ + This parameter can be a value of @ref FSMC_Wrap_Mode */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ + This parameter can be a value of @ref FSMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device + by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ + This parameter can be a value of @ref FSMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ + This parameter can be a value of @ref FSMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ + This parameter can be a value of @ref FSMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ + This parameter can be a value of @ref FSMC_Write_Burst */ } FSMC_NORSRAM_InitTypeDef; @@ -227,7 +228,7 @@ in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ + This parameter can be a value of @ref FSMC_Access_Mode */ } FSMC_NORSRAM_TimingTypeDef; /** @@ -305,7 +306,7 @@ uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FSMC_PCCARD_InitTypeDef; +} FSMC_PCCARD_InitTypeDef; /** * @} @@ -586,7 +587,7 @@ * @retval None */ #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ - |= FSMC_BCR1_MBKEN) + |= FSMC_BCR1_MBKEN) /** * @brief Disable the NORSRAM device access. @@ -595,7 +596,7 @@ * @retval None */ #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ - &= ~FSMC_BCR1_MBKEN) + &= ~FSMC_BCR1_MBKEN) /** * @} @@ -612,8 +613,9 @@ * @param __BANK__ FSMC_NAND Bank * @retval None */ -#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) +#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \ + ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN) : \ + ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) /** * @brief Disable the NAND device access. @@ -621,8 +623,9 @@ * @param __BANK__ FSMC_NAND Bank * @retval None */ -#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN): \ - CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN)) +#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \ + CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN) : \ + CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN)) /** * @} @@ -665,8 +668,9 @@ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ -#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) +#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \ + ((__INSTANCE__)->SR2 |= (__INTERRUPT__)) : \ + ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) /** * @brief Disable the NAND device interrupt. @@ -679,8 +683,9 @@ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ -#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) +#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \ + ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)) : \ + ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) /** * @brief Get flag status of the NAND device. @@ -694,8 +699,9 @@ * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval The state of FLAG (SET or RESET). */ -#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ - (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) +#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \ + (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)) : \ + (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) /** * @brief Clear flag status of the NAND device. @@ -709,8 +715,9 @@ * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval None */ -#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ - ((__INSTANCE__)->SR3 &= ~(__FLAG__))) +#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \ + ((__INSTANCE__)->SR2 &= ~(__FLAG__)) : \ + ((__INSTANCE__)->SR3 &= ~(__FLAG__))) /** * @} @@ -795,14 +802,14 @@ * @{ */ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, - FSMC_NORSRAM_InitTypeDef *Init); + const FSMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, - FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, - FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, - uint32_t ExtendedMode); + const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, - FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); + FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); /** * @} */ @@ -825,11 +832,11 @@ /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, - FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, - FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -840,8 +847,8 @@ */ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, - uint32_t Timeout); +HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); /** * @} */ @@ -855,13 +862,13 @@ /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); +HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init); HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, - FSMC_NAND_PCC_TimingTypeDef *Timing); + const FSMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, - FSMC_NAND_PCC_TimingTypeDef *Timing); + const FSMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, - FSMC_NAND_PCC_TimingTypeDef *Timing); + const FSMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); /** * @}
diff --git a/Inc/stm32f2xx_ll_iwdg.h b/Inc/stm32f2xx_ll_iwdg.h index dc0eb4d..91c3800 100644 --- a/Inc/stm32f2xx_ll_iwdg.h +++ b/Inc/stm32f2xx_ll_iwdg.h
@@ -207,7 +207,7 @@ * @arg @ref LL_IWDG_PRESCALER_128 * @arg @ref LL_IWDG_PRESCALER_256 */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->PR)); } @@ -230,7 +230,7 @@ * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->RLR)); } @@ -249,7 +249,7 @@ * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } @@ -260,7 +260,7 @@ * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } @@ -272,7 +272,7 @@ * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL); }
diff --git a/Inc/stm32f2xx_ll_rtc.h b/Inc/stm32f2xx_ll_rtc.h index 409dceb..76da8f3 100644 --- a/Inc/stm32f2xx_ll_rtc.h +++ b/Inc/stm32f2xx_ll_rtc.h
@@ -391,8 +391,8 @@ /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE * @{ */ -#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ -#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp event */ /** * @} */
diff --git a/Inc/stm32f2xx_ll_sdmmc.h b/Inc/stm32f2xx_ll_sdmmc.h index 9a78f48..1c4e24c 100644 --- a/Inc/stm32f2xx_ll_sdmmc.h +++ b/Inc/stm32f2xx_ll_sdmmc.h
@@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2018 STMicroelectronics. + * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -14,7 +14,7 @@ * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F2xx_LL_SDMMC_H @@ -300,10 +300,14 @@ #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U #define SDMMC_CARD_LOCKED 0x02000000U -#ifndef SDMMC_DATATIMEOUT -#define SDMMC_DATATIMEOUT 0xFFFFFFFFU +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ +#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#endif /* SDMMC_SWDATATIMEOUT */ + #define SDMMC_0TO7BITS 0x000000FFU #define SDMMC_8TO15BITS 0x0000FF00U #define SDMMC_16TO23BITS 0x00FF0000U
diff --git a/Inc/stm32f2xx_ll_spi.h b/Inc/stm32f2xx_ll_spi.h index 10d9772..a14e286 100644 --- a/Inc/stm32f2xx_ll_spi.h +++ b/Inc/stm32f2xx_ll_spi.h
@@ -55,53 +55,66 @@ uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -317,7 +330,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -347,7 +360,7 @@ * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -375,7 +388,7 @@ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -404,7 +417,7 @@ * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -433,7 +446,7 @@ * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -473,7 +486,7 @@ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -501,7 +514,7 @@ * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -538,7 +551,7 @@ * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -565,7 +578,7 @@ * @arg @ref LL_SPI_DATAWIDTH_8BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF)); } @@ -609,7 +622,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -644,7 +657,7 @@ * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -655,7 +668,7 @@ * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -666,7 +679,7 @@ * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -707,7 +720,7 @@ * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -728,7 +741,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -739,7 +752,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -750,7 +763,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -761,7 +774,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -772,7 +785,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -790,7 +803,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -801,7 +814,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -874,7 +887,8 @@ /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -908,7 +922,8 @@ /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -946,7 +961,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -957,7 +972,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -968,7 +983,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1009,7 +1024,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1042,7 +1057,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1053,7 +1068,7 @@ * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1130,7 +1145,7 @@ * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); @@ -1397,7 +1412,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); } @@ -1430,7 +1445,7 @@ * @arg @ref LL_I2S_DATAFORMAT_24B * @arg @ref LL_I2S_DATAFORMAT_32B */ -__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); } @@ -1457,7 +1472,7 @@ * @arg @ref LL_I2S_POLARITY_LOW * @arg @ref LL_I2S_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); } @@ -1492,7 +1507,7 @@ * @arg @ref LL_I2S_STANDARD_PCM_SHORT * @arg @ref LL_I2S_STANDARD_PCM_LONG */ -__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); } @@ -1523,7 +1538,7 @@ * @arg @ref LL_I2S_MODE_MASTER_TX * @arg @ref LL_I2S_MODE_MASTER_RX */ -__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); } @@ -1546,7 +1561,7 @@ * @param SPIx SPI Instance * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); } @@ -1573,7 +1588,7 @@ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); } @@ -1606,7 +1621,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); } @@ -1625,7 +1640,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_RXNE(SPIx); } @@ -1636,7 +1651,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_TXE(SPIx); } @@ -1647,7 +1662,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_BSY(SPIx); } @@ -1658,7 +1673,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_OVR(SPIx); } @@ -1669,7 +1684,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); } @@ -1680,7 +1695,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_FRE(SPIx); } @@ -1694,7 +1709,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); } @@ -1816,7 +1831,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_ERR(SPIx); } @@ -1827,7 +1842,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_RXNE(SPIx); } @@ -1838,7 +1853,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_TXE(SPIx); } @@ -1879,7 +1894,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_RX(SPIx); } @@ -1912,7 +1927,7 @@ * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_TX(SPIx); } @@ -1957,7 +1972,7 @@ * @{ */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
diff --git a/Inc/stm32f2xx_ll_tim.h b/Inc/stm32f2xx_ll_tim.h index 3608090..7d3b66a 100644 --- a/Inc/stm32f2xx_ll_tim.h +++ b/Inc/stm32f2xx_ll_tim.h
@@ -562,10 +562,10 @@ /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ -#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ +#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ /** * @} @@ -825,11 +825,11 @@ #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ -#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ -#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ -#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ -#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ -#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ +#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */ +#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ +#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */ +#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */ +#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */ #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ @@ -1495,6 +1495,17 @@ } /** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + +/** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event.
diff --git a/Inc/stm32f2xx_ll_usart.h b/Inc/stm32f2xx_ll_usart.h index 7da1de6..1bbd4bc 100644 --- a/Inc/stm32f2xx_ll_usart.h +++ b/Inc/stm32f2xx_ll_usart.h
@@ -345,7 +345,7 @@ * @} */ -/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported Macros Helper * @{ */ @@ -632,7 +632,7 @@ /** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput * @param USARTx USART Instance @@ -649,7 +649,7 @@ /** * @brief Retrieve Clock pulse of the last data bit output configuration * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput * @param USARTx USART Instance @@ -664,7 +664,7 @@ /** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_SetClockPhase * @param USARTx USART Instance @@ -680,7 +680,7 @@ /** * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_GetClockPhase * @param USARTx USART Instance @@ -695,7 +695,7 @@ /** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_SetClockPolarity * @param USARTx USART Instance @@ -711,7 +711,7 @@ /** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_GetClockPolarity * @param USARTx USART Instance @@ -726,7 +726,7 @@ /** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function @@ -754,7 +754,7 @@ /** * @brief Enable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput * @param USARTx USART Instance @@ -767,7 +767,7 @@ /** * @brief Disable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput * @param USARTx USART Instance @@ -780,7 +780,7 @@ /** * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput * @param USARTx USART Instance @@ -882,7 +882,7 @@ /** * @brief Enable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl * @param USARTx USART Instance @@ -895,7 +895,7 @@ /** * @brief Disable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl * @param USARTx USART Instance @@ -908,7 +908,7 @@ /** * @brief Enable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl * @param USARTx USART Instance @@ -921,7 +921,7 @@ /** * @brief Disable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl * @param USARTx USART Instance @@ -934,7 +934,7 @@ /** * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n * CR3 CTSE LL_USART_SetHWFlowCtrl @@ -953,7 +953,7 @@ /** * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n * CR3 CTSE LL_USART_GetHWFlowCtrl @@ -1077,7 +1077,7 @@ /** * @brief Enable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_EnableIrda * @param USARTx USART Instance @@ -1090,7 +1090,7 @@ /** * @brief Disable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_DisableIrda * @param USARTx USART Instance @@ -1103,7 +1103,7 @@ /** * @brief Indicate if IrDA mode is enabled - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_IsEnabledIrda * @param USARTx USART Instance @@ -1116,7 +1116,7 @@ /** * @brief Configure IrDA Power Mode (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode * @param USARTx USART Instance @@ -1132,7 +1132,7 @@ /** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode * @param USARTx USART Instance @@ -1148,7 +1148,7 @@ /** * @brief Set Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler * @param USARTx USART Instance @@ -1163,7 +1163,7 @@ /** * @brief Return Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler * @param USARTx USART Instance @@ -1184,7 +1184,7 @@ /** * @brief Enable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK * @param USARTx USART Instance @@ -1197,7 +1197,7 @@ /** * @brief Disable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK * @param USARTx USART Instance @@ -1210,7 +1210,7 @@ /** * @brief Indicate if Smartcard NACK transmission is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK * @param USARTx USART Instance @@ -1223,7 +1223,7 @@ /** * @brief Enable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_EnableSmartcard * @param USARTx USART Instance @@ -1236,7 +1236,7 @@ /** * @brief Disable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_DisableSmartcard * @param USARTx USART Instance @@ -1249,7 +1249,7 @@ /** * @brief Indicate if Smartcard mode is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard * @param USARTx USART Instance @@ -1263,7 +1263,7 @@ /** * @brief Set Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler * @param USARTx USART Instance @@ -1278,7 +1278,7 @@ /** * @brief Return Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler * @param USARTx USART Instance @@ -1292,7 +1292,7 @@ /** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime * @param USARTx USART Instance @@ -1307,7 +1307,7 @@ /** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime * @param USARTx USART Instance @@ -1328,7 +1328,7 @@ /** * @brief Enable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex * @param USARTx USART Instance @@ -1341,7 +1341,7 @@ /** * @brief Disable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex * @param USARTx USART Instance @@ -1354,7 +1354,7 @@ /** * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex * @param USARTx USART Instance @@ -1375,7 +1375,7 @@ /** * @brief Set LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen * @param USARTx USART Instance @@ -1391,7 +1391,7 @@ /** * @brief Return LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen * @param USARTx USART Instance @@ -1406,7 +1406,7 @@ /** * @brief Enable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_EnableLIN * @param USARTx USART Instance @@ -1419,7 +1419,7 @@ /** * @brief Disable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_DisableLIN * @param USARTx USART Instance @@ -1432,7 +1432,7 @@ /** * @brief Indicate if LIN mode is enabled - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN * @param USARTx USART Instance @@ -1493,7 +1493,7 @@ * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the USART in Synchronous mode. - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1531,7 +1531,7 @@ * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also set the UART/USART in LIN mode. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function @@ -1571,7 +1571,7 @@ * - SCEN bit in the USART_CR3 register, * - IREN bit in the USART_CR3 register, * This function also sets the UART/USART in Half Duplex mode. - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1610,7 +1610,7 @@ * This function also configures Stop bits to 1.5 bits and * sets the USART in Smartcard mode (SCEN bit). * Clock Output is also enabled (CLKEN). - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1652,7 +1652,7 @@ * - SCEN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the UART/USART in IRDA mode (IREN bit). - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -1818,7 +1818,7 @@ /** * @brief Check if the USART LIN Break Detection Flag is set or not - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD * @param USARTx USART Instance @@ -1831,7 +1831,7 @@ /** * @brief Check if the USART CTS Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS * @param USARTx USART Instance @@ -1983,7 +1983,7 @@ /** * @brief Clear LIN Break Detection Flag - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll SR LBD LL_USART_ClearFlag_LBD * @param USARTx USART Instance @@ -1996,7 +1996,7 @@ /** * @brief Clear CTS Interrupt Flag - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll SR CTS LL_USART_ClearFlag_nCTS * @param USARTx USART Instance @@ -2072,7 +2072,7 @@ /** * @brief Enable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD * @param USARTx USART Instance @@ -2100,7 +2100,7 @@ /** * @brief Enable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS * @param USARTx USART Instance @@ -2168,7 +2168,7 @@ /** * @brief Disable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD * @param USARTx USART Instance @@ -2196,7 +2196,7 @@ /** * @brief Disable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS * @param USARTx USART Instance @@ -2264,7 +2264,7 @@ /** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD * @param USARTx USART Instance @@ -2288,7 +2288,7 @@ /** * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS * @param USARTx USART Instance
diff --git a/Inc/stm32f2xx_ll_usb.h b/Inc/stm32f2xx_ll_usb.h index 33bb12b..9056906 100644 --- a/Inc/stm32f2xx_ll_usb.h +++ b/Inc/stm32f2xx_ll_usb.h
@@ -92,39 +92,39 @@ */ typedef struct { - uint32_t dev_endpoints; /*!< Device Endpoints number. + uint8_t dev_endpoints; /*!< Device Endpoints number. This parameter depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t Host_channels; /*!< Host Channels number. + uint8_t Host_channels; /*!< Host Channels number. This parameter Depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t dma_enable; /*!< USB DMA state. + uint8_t dma_enable; /*!< USB DMA state. If DMA is not supported this parameter shall be set by default to zero */ - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ } USB_CfgTypeDef; @@ -502,41 +502,41 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); -uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); -uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, @@ -545,12 +545,12 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); -uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /**
diff --git a/Inc/stm32f2xx_ll_wwdg.h b/Inc/stm32f2xx_ll_wwdg.h index 6c94d2d..f941714 100644 --- a/Inc/stm32f2xx_ll_wwdg.h +++ b/Inc/stm32f2xx_ll_wwdg.h
@@ -131,7 +131,7 @@ * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); } @@ -158,7 +158,7 @@ * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Counter value */ -__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CR, WWDG_CR_T)); } @@ -191,7 +191,7 @@ * @arg @ref LL_WWDG_PRESCALER_4 * @arg @ref LL_WWDG_PRESCALER_8 */ -__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); } @@ -223,7 +223,7 @@ * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Window value */ -__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); } @@ -244,7 +244,7 @@ * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); } @@ -286,7 +286,7 @@ * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); }
diff --git a/Release_Notes.html b/Release_Notes.html index 62c4ea9..64b679f 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
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var(--universal-margin); }figcaption {color: var(--secondary-fore-color); }a {text-decoration: none; }a:link {color: var(--a-link-color); }a:visited {color: var(--a-visited-color); }a:hover, a:focus {text-decoration: underline; }.container {margin: 0 auto;padding: 0 calc(1.5 * var(--universal-padding)); }.row {box-sizing: border-box;display: flex;flex: 0 1 auto;flex-flow: row wrap;margin: 0 0 0 var(--background-margin); }.col-sm,[class^='col-sm-'],[class^='col-sm-offset-'],.row[class*='cols-sm-'] > * {box-sizing: border-box;flex: 0 0 auto;padding: 0 calc(var(--universal-padding) / 2); }.col-sm,.row.cols-sm > * {max-width: 100%;flex-grow: 1;flex-basis: 0; }.col-sm-1,.row.cols-sm-1 > * {max-width: 8.3333333333%;flex-basis: 8.3333333333%; }.col-sm-offset-0 {margin-left: 0; }.col-sm-2,.row.cols-sm-2 > * {max-width: 16.6666666667%;flex-basis: 16.6666666667%; }.col-sm-offset-1 {margin-left: 8.3333333333%; }.col-sm-3,.row.cols-sm-3 > * {max-width: 25%;flex-basis: 25%; }.col-sm-offset-2 {margin-left: 16.6666666667%; }.col-sm-4,.row.cols-sm-4 > * {max-width: 33.3333333333%;flex-basis: 33.3333333333%; }.col-sm-offset-3 {margin-left: 25%; }.col-sm-5,.row.cols-sm-5 > * {max-width: 41.6666666667%;flex-basis: 41.6666666667%; }.col-sm-offset-4 {margin-left: 33.3333333333%; }.col-sm-6,.row.cols-sm-6 > * {max-width: 50%;flex-basis: 50%; }.col-sm-offset-5 {margin-left: 41.6666666667%; }.col-sm-7,.row.cols-sm-7 > * {max-width: 58.3333333333%;flex-basis: 58.3333333333%; }.col-sm-offset-6 {margin-left: 50%; }.col-sm-8,.row.cols-sm-8 > * {max-width: 66.6666666667%;flex-basis: 66.6666666667%; }.col-sm-offset-7 {margin-left: 58.3333333333%; }.col-sm-9,.row.cols-sm-9 > * {max-width: 75%;flex-basis: 75%; }.col-sm-offset-8 {margin-left: 66.6666666667%; }.col-sm-10,.row.cols-sm-10 > * {max-width: 83.3333333333%;flex-basis: 83.3333333333%; }.col-sm-offset-9 {margin-left: 75%; }.col-sm-11,.row.cols-sm-11 > * {max-width: 91.6666666667%;flex-basis: 91.6666666667%; }.col-sm-offset-10 {margin-left: 83.3333333333%; }.col-sm-12,.row.cols-sm-12 > * {max-width: 100%;flex-basis: 100%; }.col-sm-offset-11 {margin-left: 91.6666666667%; }.col-sm-normal {order: initial; }.col-sm-first {order: -999; }.col-sm-last {order: 999; }@media screen and (min-width: 500px) {.col-md,[class^='col-md-'],[class^='col-md-offset-'],.row[class*='cols-md-'] > * {box-sizing: border-box;flex: 0 0 auto;padding: 0 calc(var(--universal-padding) / 2); }.col-md,.row.cols-md > * {max-width: 100%;flex-grow: 1;flex-basis: 0; }.col-md-1,.row.cols-md-1 > * {max-width: 8.3333333333%;flex-basis: 8.3333333333%; }.col-md-offset-0 {margin-left: 0; }.col-md-2,.row.cols-md-2 > * {max-width: 16.6666666667%;flex-basis: 16.6666666667%; }.col-md-offset-1 {margin-left: 8.3333333333%; }.col-md-3,.row.cols-md-3 > * {max-width: 25%;flex-basis: 25%; }.col-md-offset-2 {margin-left: 16.6666666667%; }.col-md-4,.row.cols-md-4 > * {max-width: 33.3333333333%;flex-basis: 33.3333333333%; }.col-md-offset-3 {margin-left: 25%; }.col-md-5,.row.cols-md-5 > * {max-width: 41.6666666667%;flex-basis: 41.6666666667%; }.col-md-offset-4 {margin-left: 33.3333333333%; }.col-md-6,.row.cols-md-6 > * {max-width: 50%;flex-basis: 50%; }.col-md-offset-5 {margin-left: 41.6666666667%; }.col-md-7,.row.cols-md-7 > * {max-width: 58.3333333333%;flex-basis: 58.3333333333%; }.col-md-offset-6 {margin-left: 50%; }.col-md-8,.row.cols-md-8 > * {max-width: 66.6666666667%;flex-basis: 66.6666666667%; }.col-md-offset-7 {margin-left: 58.3333333333%; }.col-md-9,.row.cols-md-9 > * {max-width: 75%;flex-basis: 75%; }.col-md-offset-8 {margin-left: 66.6666666667%; }.col-md-10,.row.cols-md-10 > * {max-width: 83.3333333333%;flex-basis: 83.3333333333%; }.col-md-offset-9 {margin-left: 75%; }.col-md-11,.row.cols-md-11 > * {max-width: 91.6666666667%;flex-basis: 91.6666666667%; }.col-md-offset-10 {margin-left: 83.3333333333%; }.col-md-12,.row.cols-md-12 > * {max-width: 100%;flex-basis: 100%; }.col-md-offset-11 {margin-left: 91.6666666667%; }.col-md-normal {order: initial; }.col-md-first {order: -999; }.col-md-last {order: 999; } }@media screen and (min-width: 1280px) {.col-lg,[class^='col-lg-'],[class^='col-lg-offset-'],.row[class*='cols-lg-'] > * {box-sizing: border-box;flex: 0 0 auto;padding: 0 calc(var(--universal-padding) / 2); }.col-lg,.row.cols-lg > * {max-width: 100%;flex-grow: 1;flex-basis: 0; }.col-lg-1,.row.cols-lg-1 > * {max-width: 8.3333333333%;flex-basis: 8.3333333333%; }.col-lg-offset-0 {margin-left: 0; }.col-lg-2,.row.cols-lg-2 > * {max-width: 16.6666666667%;flex-basis: 16.6666666667%; }.col-lg-offset-1 {margin-left: 8.3333333333%; }.col-lg-3,.row.cols-lg-3 > * {max-width: 25%;flex-basis: 25%; }.col-lg-offset-2 {margin-left: 16.6666666667%; }.col-lg-4,.row.cols-lg-4 > * {max-width: 33.3333333333%;flex-basis: 33.3333333333%; }.col-lg-offset-3 {margin-left: 25%; }.col-lg-5,.row.cols-lg-5 > * {max-width: 41.6666666667%;flex-basis: 41.6666666667%; }.col-lg-offset-4 {margin-left: 33.3333333333%; }.col-lg-6,.row.cols-lg-6 > * {max-width: 50%;flex-basis: 50%; }.col-lg-offset-5 {margin-left: 41.6666666667%; }.col-lg-7,.row.cols-lg-7 > * {max-width: 58.3333333333%;flex-basis: 58.3333333333%; }.col-lg-offset-6 {margin-left: 50%; }.col-lg-8,.row.cols-lg-8 > * {max-width: 66.6666666667%;flex-basis: 66.6666666667%; }.col-lg-offset-7 {margin-left: 58.3333333333%; }.col-lg-9,.row.cols-lg-9 > * {max-width: 75%;flex-basis: 75%; }.col-lg-offset-8 {margin-left: 66.6666666667%; }.col-lg-10,.row.cols-lg-10 > * {max-width: 83.3333333333%;flex-basis: 83.3333333333%; }.col-lg-offset-9 {margin-left: 75%; }.col-lg-11,.row.cols-lg-11 > * {max-width: 91.6666666667%;flex-basis: 91.6666666667%; }.col-lg-offset-10 {margin-left: 83.3333333333%; }.col-lg-12,.row.cols-lg-12 > * {max-width: 100%;flex-basis: 100%; }.col-lg-offset-11 {margin-left: 91.6666666667%; }.col-lg-normal {order: initial; }.col-lg-first {order: -999; }.col-lg-last {order: 999; } }:root {--card-back-color: #3cb4e6;--card-fore-color: #03234b;--card-border-color: #03234b; }.card {display: flex;flex-direction: column;justify-content: space-between;align-self: center;position: relative;width: 100%;background: var(--card-back-color);color: var(--card-fore-color);border: 0.0714285714rem solid var(--card-border-color);border-radius: var(--universal-border-radius);margin: var(--universal-margin);overflow: hidden; }@media screen and (min-width: 320px) {.card {max-width: 320px; } }.card > .sectione {background: var(--card-back-color);color: var(--card-fore-color);box-sizing: border-box;margin: 0;border: 0;border-radius: 0;border-bottom: 0.0714285714rem solid var(--card-border-color);padding: var(--universal-padding);width: 100%; }.card > .sectione.media {height: 200px;padding: 0;-o-object-fit: cover;object-fit: cover; }.card > .sectione:last-child {border-bottom: 0; }@media screen and (min-width: 240px) {.card.small {max-width: 240px; } }@media screen and (min-width: 480px) {.card.large {max-width: 480px; } }.card.fluid {max-width: 100%;width: auto; }.card.warning {--card-back-color: #e5b8b7;--card-fore-color: #3b234b;--card-border-color: #8c0078; }.card.error {--card-back-color: #464650;--card-fore-color: #ffffff;--card-border-color: #8c0078; }.card > .sectione.dark {--card-back-color: #3b234b;--card-fore-color: #ffffff; }.card > .sectione.double-padded {padding: calc(1.5 * var(--universal-padding)); }:root {--form-back-color: #ffe97f;--form-fore-color: #03234b;--form-border-color: #3cb4e6;--input-back-color: #ffffff;--input-fore-color: #03234b;--input-border-color: #3cb4e6;--input-focus-color: #0288d1;--input-invalid-color: #d32f2f;--button-back-color: #e2e2e2;--button-hover-back-color: #dcdcdc;--button-fore-color: #212121;--button-border-color: transparent;--button-hover-border-color: transparent;--button-group-border-color: rgba(124, 124, 124, 0.54); }form {background: var(--form-back-color);color: var(--form-fore-color);border: 0.0714285714rem solid var(--form-border-color);border-radius: var(--universal-border-radius);margin: var(--universal-margin);padding: calc(2 * var(--universal-padding)) var(--universal-padding); }fieldset {border: 0.0714285714rem solid var(--form-border-color);border-radius: var(--universal-border-radius);margin: calc(var(--universal-margin) / 4);padding: var(--universal-padding); }legend {box-sizing: border-box;display: table;max-width: 100%;white-space: normal;font-weight: 500;padding: calc(var(--universal-padding) / 2); }label {padding: calc(var(--universal-padding) / 2) var(--universal-padding); }.input-group {display: inline-block; }.input-group.fluid {display: flex;align-items: center;justify-content: center; }.input-group.fluid > input {max-width: 100%;flex-grow: 1;flex-basis: 0px; }@media screen and (max-width: 499px) {.input-group.fluid {align-items: stretch;flex-direction: column; } }.input-group.vertical {display: flex;align-items: stretch;flex-direction: column; }.input-group.vertical > input {max-width: 100%;flex-grow: 1;flex-basis: 0px; }[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button {height: auto; }[type="search"] {-webkit-appearance: textfield;outline-offset: -2px; }[type="search"]::-webkit-search-cancel-button,[type="search"]::-webkit-search-decoration {-webkit-appearance: none; }input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"],[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select {box-sizing: border-box;background: var(--input-back-color);color: var(--input-fore-color);border: 0.0714285714rem solid var(--input-border-color);border-radius: var(--universal-border-radius);margin: calc(var(--universal-margin) / 2);padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus {border-color: var(--input-focus-color);box-shadow: none; }input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid {border-color: var(--input-invalid-color);box-shadow: none; }input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] {background: var(--secondary-back-color); }select {max-width: 100%; }option {overflow: hidden;text-overflow: ellipsis; }[type="checkbox"], [type="radio"] {-webkit-appearance: none;-moz-appearance: none;appearance: none;position: relative;height: calc(1rem + var(--universal-padding) / 2);width: calc(1rem + var(--universal-padding) / 2);vertical-align: text-bottom;padding: 0;flex-basis: calc(1rem + var(--universal-padding) / 2) !important;flex-grow: 0 !important; }[type="checkbox"]:checked:before, [type="radio"]:checked:before {position: absolute; }[type="checkbox"]:checked:before {content: '\2713';font-family: sans-serif;font-size: calc(1rem + var(--universal-padding) / 2);top: calc(0rem - var(--universal-padding));left: calc(var(--universal-padding) / 4); }[type="radio"] {border-radius: 100%; }[type="radio"]:checked:before {border-radius: 100%;content: '';top: calc(0.0714285714rem + var(--universal-padding) / 2);left: calc(0.0714285714rem + var(--universal-padding) / 2);background: var(--input-fore-color);width: 0.5rem;height: 0.5rem; }:placeholder-shown {color: var(--input-fore-color); }::-ms-placeholder {color: var(--input-fore-color);opacity: 0.54; }button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner {border-style: none;padding: 0; }button, html [type="button"], [type="reset"], [type="submit"] {-webkit-appearance: button; }button {overflow: visible;text-transform: none; }button, [type="button"], [type="submit"], [type="reset"],a.button, label.button, .button,a[role="button"], label[role="button"], [role="button"] {display: inline-block;background: var(--button-back-color);color: var(--button-fore-color);border: 0.0714285714rem solid var(--button-border-color);border-radius: var(--universal-border-radius);padding: var(--universal-padding) calc(1.5 * var(--universal-padding));margin: var(--universal-margin);text-decoration: none;cursor: pointer;transition: background 0.3s; }button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus,a.button:hover,a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus,a[role="button"]:hover,a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus {background: var(--button-hover-back-color);border-color: var(--button-hover-border-color); }input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] {cursor: not-allowed;opacity: 0.75; }.button-group {display: flex;border: 0.0714285714rem solid var(--button-group-border-color);border-radius: var(--universal-border-radius);margin: var(--universal-margin); }.button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {margin: 0;max-width: 100%;flex: 1 1 auto;text-align: center;border: 0;border-radius: 0;box-shadow: none; }.button-group > :not(:first-child) {border-left: 0.0714285714rem solid var(--button-group-border-color); }@media screen and (max-width: 499px) {.button-group {flex-direction: column; }.button-group > :not(:first-child) {border: 0;border-top: 0.0714285714rem solid var(--button-group-border-color); } }button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary {--button-back-color: #1976d2;--button-fore-color: #f8f8f8; }button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus {--button-hover-back-color: #1565c0; }button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary {--button-back-color: #d32f2f;--button-fore-color: #f8f8f8; }button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus {--button-hover-back-color: #c62828; }button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary {--button-back-color: #308732;--button-fore-color: #f8f8f8; }button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus {--button-hover-back-color: #277529; }button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse {--button-back-color: #212121;--button-fore-color: #f8f8f8; }button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus {--button-hover-back-color: #111; }button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small {padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding));margin: var(--universal-margin); }button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large {padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding));margin: var(--universal-margin); }:root {--header-back-color: #03234b;--header-hover-back-color: #ffd200;--header-fore-color: #ffffff;--header-border-color: #3cb4e6;--nav-back-color: #ffffff;--nav-hover-back-color: #ffe97f;--nav-fore-color: #e6007e;--nav-border-color: #3cb4e6;--nav-link-color: #3cb4e6;--footer-fore-color: #ffffff;--footer-back-color: #03234b;--footer-border-color: #3cb4e6;--footer-link-color: #3cb4e6;--drawer-back-color: #ffffff;--drawer-hover-back-color: #ffe97f;--drawer-border-color: #3cb4e6;--drawer-close-color: #e6007e; }header {height: 2.75rem;background: var(--header-back-color);color: var(--header-fore-color);border-bottom: 0.0714285714rem solid var(--header-border-color);padding: calc(var(--universal-padding) / 4) 0;white-space: nowrap;overflow-x: auto;overflow-y: hidden; }header.row {box-sizing: content-box; }header .logo {color: var(--header-fore-color);font-size: 1.75rem;padding: var(--universal-padding) calc(2 * var(--universal-padding));text-decoration: none; }header button, header [type="button"], header .button, header [role="button"] {box-sizing: border-box;position: relative;top: calc(0rem - var(--universal-padding) / 4);height: calc(3.1875rem + var(--universal-padding) / 2);background: var(--header-back-color);line-height: calc(3.1875rem - var(--universal-padding) * 1.5);text-align: center;color: var(--header-fore-color);border: 0;border-radius: 0;margin: 0;text-transform: uppercase; }header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus {background: var(--header-hover-back-color); }nav {background: var(--nav-back-color);color: var(--nav-fore-color);border: 0.0714285714rem solid var(--nav-border-color);border-radius: var(--universal-border-radius);margin: var(--universal-margin); }nav * {padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }nav a, nav a:visited {display: block;color: var(--nav-link-color);border-radius: var(--universal-border-radius);transition: background 0.3s; }nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus {text-decoration: none;background: var(--nav-hover-back-color); }nav .sublink-1 {position: relative;margin-left: calc(2 * var(--universal-padding)); }nav .sublink-1:before {position: absolute;left: calc(var(--universal-padding) - 1 * var(--universal-padding));top: -0.0714285714rem;content: '';height: 100%;border: 0.0714285714rem solid var(--nav-border-color);border-left: 0; }nav .sublink-2 {position: relative;margin-left: calc(4 * var(--universal-padding)); }nav .sublink-2:before {position: absolute;left: calc(var(--universal-padding) - 3 * var(--universal-padding));top: -0.0714285714rem;content: '';height: 100%;border: 0.0714285714rem solid var(--nav-border-color);border-left: 0; }footer {background: var(--footer-back-color);color: var(--footer-fore-color);border-top: 0.0714285714rem solid var(--footer-border-color);padding: calc(2 * var(--universal-padding)) var(--universal-padding);font-size: 0.875rem; }footer a, footer a:visited {color: var(--footer-link-color); }header.sticky {position: -webkit-sticky;position: sticky;z-index: 1101;top: 0; }footer.sticky {position: -webkit-sticky;position: sticky;z-index: 1101;bottom: 0; }.drawer-toggle:before {display: inline-block;position: relative;vertical-align: bottom;content: '\00a0\2261\00a0';font-family: sans-serif;font-size: 1.5em; }@media screen and (min-width: 500px) {.drawer-toggle:not(.persistent) {display: none; } }[type="checkbox"].drawer {height: 1px;width: 1px;margin: -1px;overflow: hidden;position: absolute;clip: rect(0 0 0 0);-webkit-clip-path: inset(100%);clip-path: inset(100%); }[type="checkbox"].drawer + * {display: block;box-sizing: border-box;position: fixed;top: 0;width: 320px;height: 100vh;overflow-y: auto;background: var(--drawer-back-color);border: 0.0714285714rem solid var(--drawer-border-color);border-radius: 0;margin: 0;z-index: 1110;right: -320px;transition: right 0.3s; }[type="checkbox"].drawer + * .drawer-close {position: absolute;top: var(--universal-margin);right: var(--universal-margin);z-index: 1111;width: 2rem;height: 2rem;border-radius: var(--universal-border-radius);padding: var(--universal-padding);margin: 0;cursor: pointer;transition: background 0.3s; }[type="checkbox"].drawer + * .drawer-close:before {display: block;content: '\00D7';color: var(--drawer-close-color);position: relative;font-family: sans-serif;font-size: 2rem;line-height: 1;text-align: center; }[type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus {background: var(--drawer-hover-back-color); }@media screen and (max-width: 320px) {[type="checkbox"].drawer + * {width: 100%; } }[type="checkbox"].drawer:checked + * {right: 0; }@media screen and (min-width: 500px) {[type="checkbox"].drawer:not(.persistent) + * {position: static;height: 100%;z-index: 1100; }[type="checkbox"].drawer:not(.persistent) + * .drawer-close {display: none; } }:root {--table-border-color: #03234b;--table-border-separator-color: #03234b;--table-head-back-color: #03234b;--table-head-fore-color: #ffffff;--table-body-back-color: #ffffff;--table-body-fore-color: #03234b;--table-body-alt-back-color: #f4f4f4; }table {border-collapse: separate;border-spacing: 0;margin: 0;display: flex;flex: 0 1 auto;flex-flow: row wrap;padding: var(--universal-padding);padding-top: 0; }table caption {font-size: 1rem;margin: calc(2 * var(--universal-margin)) 0;max-width: 100%;flex: 0 0 100%; }table thead, table tbody {display: flex;flex-flow: row wrap;border: 0.0714285714rem solid var(--table-border-color); }table thead {z-index: 999;border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }table tbody {border-top: 0;margin-top: calc(0 - var(--universal-margin));border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }table tr {display: flex;padding: 0; }table th, table td {padding: calc(0.5 * var(--universal-padding));font-size: 0.9rem; }table th {text-align: left;background: var(--table-head-back-color);color: var(--table-head-fore-color); }table td {background: var(--table-body-back-color);color: var(--table-body-fore-color);border-top: 0.0714285714rem solid var(--table-border-color); }table:not(.horizontal) {overflow: auto;max-height: 100%; }table:not(.horizontal) thead, table:not(.horizontal) tbody {max-width: 100%;flex: 0 0 100%; }table:not(.horizontal) tr {flex-flow: row wrap;flex: 0 0 100%; }table:not(.horizontal) th, table:not(.horizontal) td {flex: 1 0 0%;overflow: hidden;text-overflow: ellipsis; }table:not(.horizontal) thead {position: sticky;top: 0; }table:not(.horizontal) tbody tr:first-child td {border-top: 0; }table.horizontal {border: 0; }table.horizontal thead, table.horizontal tbody {border: 0;flex: .2 0 0;flex-flow: row nowrap; }table.horizontal tbody {overflow: auto;justify-content: space-between;flex: .8 0 0;margin-left: 0;padding-bottom: calc(var(--universal-padding) / 4); }table.horizontal tr {flex-direction: column;flex: 1 0 auto; }table.horizontal th, table.horizontal td {width: auto;border: 0;border-bottom: 0.0714285714rem solid var(--table-border-color); }table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {border-top: 0; }table.horizontal th {text-align: right;border-left: 0.0714285714rem solid var(--table-border-color);border-right: 0.0714285714rem solid var(--table-border-separator-color); }table.horizontal thead tr:first-child {padding-left: 0; }table.horizontal th:first-child, table.horizontal td:first-child {border-top: 0.0714285714rem solid var(--table-border-color); }table.horizontal tbody tr:last-child td {border-right: 0.0714285714rem solid var(--table-border-color); }table.horizontal tbody tr:last-child td:first-child {border-top-right-radius: 0.25rem; }table.horizontal tbody tr:last-child td:last-child {border-bottom-right-radius: 0.25rem; }table.horizontal thead tr:first-child th:first-child {border-top-left-radius: 0.25rem; }table.horizontal thead tr:first-child th:last-child {border-bottom-left-radius: 0.25rem; }@media screen and (max-width: 499px) {table, table.horizontal {border-collapse: collapse;border: 0;width: 100%;display: table; }table thead, table th, table.horizontal thead, table.horizontal th {border: 0;height: 1px;width: 1px;margin: -1px;overflow: hidden;padding: 0;position: absolute;clip: rect(0 0 0 0);-webkit-clip-path: inset(100%);clip-path: inset(100%); }table tbody, table.horizontal tbody {border: 0;display: table-row-group; }table tr, table.horizontal tr {display: block;border: 0.0714285714rem solid var(--table-border-color);border-radius: var(--universal-border-radius);background: #ffffff;padding: var(--universal-padding);margin: var(--universal-margin);margin-bottom: calc(1 * var(--universal-margin)); }table th, table td, table.horizontal th, table.horizontal td {width: auto; }table td, table.horizontal td {display: block;border: 0;text-align: right; }table td:before, table.horizontal td:before {content: attr(data-label);float: left;font-weight: 600; }table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child {border-top: 0; }table tbody tr:last-child td, table.horizontal tbody tr:last-child td {border-right: 0; } }table tr:nth-of-type(2n) > td {background: var(--table-body-alt-back-color); }@media screen and (max-width: 500px) {table tr:nth-of-type(2n) {background: var(--table-body-alt-back-color); } }:root {--table-body-hover-back-color: #90caf9; }table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {background: var(--table-body-hover-back-color); }@media screen and (max-width: 500px) {table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td {background: var(--table-body-hover-back-color); } }:root {--mark-back-color: #3cb4e6;--mark-fore-color: #ffffff; }mark {background: var(--mark-back-color);color: var(--mark-fore-color);font-size: 0.95em;line-height: 1em;border-radius: var(--universal-border-radius);padding: calc(var(--universal-padding) / 4) var(--universal-padding); }mark.inline-block {display: inline-block;font-size: 1em;line-height: 1.4;padding: calc(var(--universal-padding) / 2) var(--universal-padding); }:root {--toast-back-color: #424242;--toast-fore-color: #fafafa; }.toast {position: fixed;bottom: calc(var(--universal-margin) * 3);left: 50%;transform: translate(-50%, -50%);z-index: 1111;color: var(--toast-fore-color);background: var(--toast-back-color);border-radius: calc(var(--universal-border-radius) * 16);padding: var(--universal-padding) calc(var(--universal-padding) * 3); }:root {--tooltip-back-color: #212121;--tooltip-fore-color: #fafafa; }.tooltip {position: relative;display: inline-block; }.tooltip:before, .tooltip:after {position: absolute;opacity: 0;clip: rect(0 0 0 0);-webkit-clip-path: inset(100%);clip-path: inset(100%);transition: all 0.3s;z-index: 1010;left: 50%; }.tooltip:not(.bottom):before, .tooltip:not(.bottom):after {bottom: 75%; }.tooltip.bottom:before, .tooltip.bottom:after {top: 75%; }.tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after {opacity: 1;clip: auto;-webkit-clip-path: inset(0%);clip-path: inset(0%); }.tooltip:before {content: '';background: transparent;border: var(--universal-margin) solid transparent;left: calc(50% - var(--universal-margin)); }.tooltip:not(.bottom):before {border-top-color: #212121; }.tooltip.bottom:before {border-bottom-color: #212121; }.tooltip:after {content: attr(aria-label);color: var(--tooltip-fore-color);background: var(--tooltip-back-color);border-radius: var(--universal-border-radius);padding: var(--universal-padding);white-space: nowrap;transform: translateX(-50%); }.tooltip:not(.bottom):after {margin-bottom: calc(2 * var(--universal-margin)); }.tooltip.bottom:after {margin-top: calc(2 * var(--universal-margin)); }:root {--modal-overlay-color: rgba(0, 0, 0, 0.45);--modal-close-color: #e6007e;--modal-close-hover-color: #ffe97f; }[type="checkbox"].modal {height: 1px;width: 1px;margin: -1px;overflow: hidden;position: absolute;clip: rect(0 0 0 0);-webkit-clip-path: inset(100%);clip-path: inset(100%); }[type="checkbox"].modal + div {position: fixed;top: 0;left: 0;display: none;width: 100vw;height: 100vh;background: var(--modal-overlay-color); }[type="checkbox"].modal + div .card {margin: 0 auto;max-height: 50vh;overflow: auto; }[type="checkbox"].modal + div .card .modal-close {position: absolute;top: 0;right: 0;width: 1.75rem;height: 1.75rem;border-radius: var(--universal-border-radius);padding: var(--universal-padding);margin: 0;cursor: pointer;transition: background 0.3s; }[type="checkbox"].modal + div .card .modal-close:before {display: block;content: '\00D7';color: var(--modal-close-color);position: relative;font-family: sans-serif;font-size: 1.75rem;line-height: 1;text-align: center; }[type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus {background: var(--modal-close-hover-color); }[type="checkbox"].modal:checked + div {display: flex;flex: 0 1 auto;z-index: 1200; }[type="checkbox"].modal:checked + div .card .modal-close {z-index: 1211; }:root {--collapse-label-back-color: #03234b;--collapse-label-fore-color: #ffffff;--collapse-label-hover-back-color: #3cb4e6;--collapse-selected-label-back-color: #3cb4e6;--collapse-border-color: var(--collapse-label-back-color);--collapse-selected-border-color: #ceecf8;--collapse-content-back-color: #ffffff;--collapse-selected-label-border-color: #3cb4e6; }.collapse {width: calc(100% - 2 * var(--universal-margin));opacity: 1;display: flex;flex-direction: column;margin: var(--universal-margin);border-radius: var(--universal-border-radius); }.collapse > [type="radio"], .collapse > [type="checkbox"] {height: 1px;width: 1px;margin: -1px;overflow: hidden;position: absolute;clip: rect(0 0 0 0);-webkit-clip-path: inset(100%);clip-path: inset(100%); }.collapse > label {flex-grow: 1;display: inline-block;height: 1.25rem;cursor: pointer;transition: background 0.2s;color: var(--collapse-label-fore-color);background: var(--collapse-label-back-color);border: 0.0714285714rem solid var(--collapse-selected-border-color);padding: calc(1.25 * var(--universal-padding)); }.collapse > label:hover, .collapse > label:focus {background: var(--collapse-label-hover-back-color); }.collapse > label + div {flex-basis: auto;height: 1px;width: 1px;margin: -1px;overflow: hidden;position: absolute;clip: rect(0 0 0 0);-webkit-clip-path: inset(100%);clip-path: inset(100%);transition: max-height 0.3s;max-height: 1px; }.collapse > :checked + label {background: var(--collapse-selected-label-back-color);border-color: var(--collapse-selected-label-border-color); }.collapse > :checked + label + div {box-sizing: border-box;position: relative;width: 100%;height: auto;overflow: auto;margin: 0;background: var(--collapse-content-back-color);border: 0.0714285714rem solid var(--collapse-selected-border-color);border-top: 0;padding: var(--universal-padding);clip: auto;-webkit-clip-path: inset(0%);clip-path: inset(0%);max-height: 100%; }.collapse > label:not(:first-of-type) {border-top: 0; }.collapse > label:first-of-type {border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; }.collapse > label:last-of-type:not(:first-of-type) {border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }.collapse > label:last-of-type:first-of-type {border-radius: var(--universal-border-radius); }.collapse > :checked:last-of-type:not(:first-of-type) + label {border-radius: 0; }.collapse > :checked:last-of-type + label + div {border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); }mark.tertiary {--mark-back-color: #3cb4e6; }mark.tag {padding: calc(var(--universal-padding)/2) var(--universal-padding);border-radius: 1em; }:root {--progress-back-color: #3cb4e6;--progress-fore-color: #555; }progress {display: block;vertical-align: baseline;-webkit-appearance: none;-moz-appearance: none;appearance: none;height: 0.75rem;width: calc(100% - 2 * var(--universal-margin));margin: var(--universal-margin);border: 0;border-radius: calc(2 * var(--universal-border-radius));background: var(--progress-back-color);color: var(--progress-fore-color); }progress::-webkit-progress-value {background: var(--progress-fore-color);border-top-left-radius: calc(2 * var(--universal-border-radius));border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }progress::-webkit-progress-bar {background: var(--progress-back-color); }progress::-moz-progress-bar {background: var(--progress-fore-color);border-top-left-radius: calc(2 * var(--universal-border-radius));border-bottom-left-radius: calc(2 * var(--universal-border-radius)); }progress[value="1000"]::-webkit-progress-value {border-radius: calc(2 * var(--universal-border-radius)); }progress[value="1000"]::-moz-progress-bar {border-radius: calc(2 * var(--universal-border-radius)); }progress.inline {display: inline-block;vertical-align: middle;width: 60%; }:root {--spinner-back-color: #ddd;--spinner-fore-color: #555; }@keyframes spinner-donut-anim {0% {transform: rotate(0deg); }100% {transform: rotate(360deg); } }.spinner {display: inline-block;margin: var(--universal-margin);border: 0.25rem solid var(--spinner-back-color);border-left: 0.25rem solid var(--spinner-fore-color);border-radius: 50%;width: 1.25rem;height: 1.25rem;animation: spinner-donut-anim 1.2s linear infinite; }progress.primary {--progress-fore-color: #1976d2; }progress.secondary {--progress-fore-color: #d32f2f; }progress.tertiary {--progress-fore-color: #308732; }.spinner.primary {--spinner-fore-color: #1976d2; }.spinner.secondary {--spinner-fore-color: #d32f2f; }.spinner.tertiary {--spinner-fore-color: #308732; }span[class^='icon-'] {display: inline-block;height: 1em;width: 1em;vertical-align: -0.125em;background-size: contain;margin: 0 calc(var(--universal-margin) / 4); }span[class^='icon-'].secondary {-webkit-filter: invert(25%);filter: invert(25%); }span[class^='icon-'].inverse {-webkit-filter: invert(100%);filter: invert(100%); }span.icon-alert {background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }span.icon-bookmark {background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }span.icon-calendar {background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }span.icon-credit {background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }span.icon-edit {background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' 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rel="icon" type="image/x-icon" /> + <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" /> </head> <body> <div class="row"> @@ -24,7 +24,7 @@ <h1 id="release-notes-forstm32f2xx-hal-drivers"><small>Release Notes for</small><mark>STM32F2xx HAL Drivers</mark></h1> <p>Copyright © 2017 STMicroelectronics<br /> </p> -<a href="https://www.st.com" class="logo"><img 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AAAAAAAAAAAAAAAAAAAgApj7P8B7rljbw+FKrEAAAAASUVORK5CYII=" alt="ST logo" /></a> +<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a> </center> <h1 id="purpose">Purpose</h1> <p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p> @@ -40,15 +40,110 @@ <div class="col-sm-12 col-lg-8"> <h1 id="update-history"><strong>Update History</strong></h1> <div class="collapse"> -<input type="checkbox" id="collapse-section1_2_8" checked aria-hidden="true"> <label for="collapse-section1_2_8" aria-hidden="true"><strong>V1.2.8 / 07-April-2023</strong></label> +<input type="checkbox" id="collapse-section1_2_9" checked aria-hidden="true"> <label for="collapse-section1_2_9" aria-hidden="true"><strong>V1.2.9 / 24-July-2024</strong></label> <div> <h2 id="main-changes">Main Changes</h2> <ul> <li>General updates to fix known defects and enhancements implementation.</li> +</ul> +<h2 id="contents">Contents</h2> +<ul> +<li><strong>HAL</strong> updates +<ul> +<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.</li> +</ul></li> +<li><strong>HAL/LL CORTEX</strong> driver +<ul> +<li>Update HAL_MPU_ConfigRegion() to allow the configuration of the MPU registers independently of the value of Enable/Disable field.</li> +<li>Add new APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion().</li> +</ul></li> +<li><strong>HAL/LL ADC</strong> driver +<ul> +<li>Update __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS() formula to be aligned with reference manual.</li> +</ul></li> +<li><strong>HAL FLASH</strong> driver +<ul> +<li>Remove HAL_LOCK/HAL_UNLOCK() from HAL_FLASH_Program_IT() and HAL_FLASHEx_Erase_IT() APIs.</li> +</ul></li> +<li><strong>HAL HASH</strong> driver +<ul> +<li>Read the last remaining bytes (3 or 2 or 1) of the data in a temporary variable (taking into account swap mode) and enter this variable into the HASH->DIN when the data is not a multiple of 4 bytes.</li> +</ul></li> +<li><strong>HAL CAN</strong> driver +<ul> +<li>Clarify pin configuration in driver header by removing open-drain information.</li> +</ul></li> +<li><strong>HAL I2C</strong> driver +<ul> +<li>Solve Slave No stretch not functional by using HAL Slave interface.</li> +<li>Clear ACK bit once 3 bytes to read remain to be able to send the NACK once the transfer ends.</li> +<li>Update HAL_I2C_Master_Abort_IT() API to support memory abort transfer.</li> +<li>Update the HAL I2C driver to reset PreviousState to I2C_STATE_NONE at the end of transfer.</li> +</ul></li> +<li><strong>HAL RNG</strong> driver +<ul> +<li>Improve performance by removing multiple volatile reads or writes in interrupt handler.</li> +</ul></li> +<li><strong>LL RTC_BKP</strong> driver +<ul> +<li>Correct misleading note about shadow registers.</li> +</ul></li> +<li><strong>HAL SDMMC</strong> driver +<ul> +<li>Update HAL SD processes to manage STBITERR flag.</li> +</ul></li> +<li><strong>HAL DCMI</strong> driver +<ul> +<li>Remove ‘register’ storage class specifier.</li> +</ul></li> +<li><strong>HAL SPI</strong> driver +<ul> +<li>Update HAL_SPI_TransmitReceive() API to set the bit CRCNEXT in case of one byte transaction.</li> +<li>Update IT APIs to enable interrupts after process unlock.</li> +<li>Add wait on flag TXE to be set at the end of transaction to be aligned with reference manual.</li> +</ul></li> +<li><strong>HAL/LL TIM</strong> driver +<ul> +<li>Improve performance by removing multiple volatile reads or writes in interrupt handler.</li> +<li>Update interrupt flag is cleared when the update event is generated by software.</li> +<li>Improve HAL TIM driver’s operational behavior.</li> +<li>Improve period configuration parameter check.</li> +<li>Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init().</li> +<li>Add LL_TIM_CC_IsEnabledPreload() API.</li> +</ul></li> +<li><strong>HAL UART</strong> driver +<ul> +<li>Avoid ORE flag to be cleared by a transmit process in polling mode.</li> +<li>Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.</li> +</ul></li> +<li><strong>HAL IWDG</strong> driver +<ul> +<li>Calculate the maximum IWDG Timeout period “HAL_IWDG_DEFAULT_TIMEOUT” based on a Prescaler=128 at LSI frequency=32kHz.</li> +</ul></li> +<li><strong>HAL USB_OTG</strong> driver +<ul> +<li>Fix device connection in case battery charging is used with HS instance linked to internal FS PHY.</li> +<li>ll_usb.c: increase timeout value to allow core reset to complete.</li> +<li>ll_usb.c: improve delay management to set core mode.</li> +<li>hal_hcd.c: ensure to reactivate the usb channel in case of transfer error.</li> +</ul></li> +<li><strong>LL UTILS_</strong> driver +<ul> +<li>Fix a note about Ticks parameter.</li> +</ul></li> +</ul> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section1_2_8" aria-hidden="true"> <label for="collapse-section1_2_8" aria-hidden="true"><strong>V1.2.8 / 07-April-2023</strong></label> +<div> +<h2 id="main-changes-1">Main Changes</h2> +<ul> +<li>General updates to fix known defects and enhancements implementation.</li> <li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.</li> <li>All source files: update disclaimer to add reference to the new license agreement.</li> </ul> -<h2 id="contents">Contents</h2> +<h2 id="contents-1">Contents</h2> <ul> <li><strong>HAL Generic</strong> driver <ul> @@ -183,11 +278,11 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1_2_7" aria-hidden="true"> <label for="collapse-section1_2_7" aria-hidden="true"><strong>V1.2.7 / 21-May-2021</strong></label> <div> -<h2 id="main-changes-1">Main Changes</h2> +<h2 id="main-changes-2">Main Changes</h2> <ul> <li>General updates to fix known defects.</li> </ul> -<h2 id="contents-1">Contents</h2> +<h2 id="contents-2">Contents</h2> <ul> <li><strong>HAL/LL ADC</strong> driver <ul> @@ -315,11 +410,11 @@ <div class="collapse"> <input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.2.6 / 22-October-2020</strong></label> <div> -<h2 id="main-changes-2">Main Changes</h2> +<h2 id="main-changes-3">Main Changes</h2> <ul> <li>General updates to fix known defects.</li> </ul> -<h2 id="contents-2">Contents</h2> +<h2 id="contents-3">Contents</h2> <ul> <li><strong>HAL/LL I2C</strong> driver <ul> @@ -334,7 +429,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.2.5 / 09-September-2020</strong></label> <div> -<h2 id="main-changes-3">Main Changes</h2> +<h2 id="main-changes-4">Main Changes</h2> <ul> <li>General updates to fix known defects and enhancements implementation.</li> <li><strong>HAL</strong> driver @@ -596,7 +691,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true"><strong>V1.2.4 / 31-December-2019</strong></label> <div> -<h2 id="main-changes-4">Main Changes</h2> +<h2 id="main-changes-5">Main Changes</h2> <ul> <li>General updates to fix known defects and enhancements implementation</li> <li><strong>HAL/LL GPIO</strong> update @@ -662,7 +757,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.2.3 / 26-June-2019</strong></label> <div> -<h2 id="main-changes-5">Main Changes</h2> +<h2 id="main-changes-6">Main Changes</h2> <ul> <li>General updates to fix known defects and enhancements implementation</li> <li>HAL drivers clean up: remove double casting ‘uint32_t’ and ‘U’</li> @@ -1025,7 +1120,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.2.2 / 29-September-2017</strong></label> <div> -<h2 id="main-changes-6">Main Changes</h2> +<h2 id="main-changes-7">Main Changes</h2> <ul> <li>General updates to fix known defects and enhancements implementation</li> <li>Fix compilation warning with GCC compiler</li> @@ -1091,7 +1186,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.2.1 / 14-April-2017</strong></label> <div> -<h2 id="main-changes-7">Main Changes</h2> +<h2 id="main-changes-8">Main Changes</h2> <ul> <li>General updates to fix known defects and enhancements implementation</li> <li><strong>HAL CONF Template</strong> update @@ -1112,7 +1207,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.2.0 / 17-March-2017</strong></label> <div> -<h2 id="main-changes-8">Main Changes</h2> +<h2 id="main-changes-9">Main Changes</h2> <ul> <li><strong>Add Low Layer drivers allowing performance and footprint optimization</strong> <ul> @@ -1230,7 +1325,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.1.3 / 29-June-2016</strong></label> <div> -<h2 id="main-changes-9">Main Changes</h2> +<h2 id="main-changes-10">Main Changes</h2> <ul> <li>General updates to fix known defects and enhancements implementation</li> <li>Enhance HAL delay and time base implementation: @@ -1584,7 +1679,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.1.2 / 11-December-2015</strong></label> <div> -<h2 id="main-changes-10">Main Changes</h2> +<h2 id="main-changes-11">Main Changes</h2> <ul> <li><strong>HAL RCC</strong> update <ul> @@ -1600,7 +1695,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.1.1 / 20-November-2015</strong></label> <div> -<h2 id="main-changes-11">Main Changes</h2> +<h2 id="main-changes-12">Main Changes</h2> <ul> <li>General updates to fix known defects and enhancements implementation</li> <li><strong>One change done on the HAL CRYP requires an update on the application code based on HAL V1.1.0</strong> @@ -1663,7 +1758,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.1.0 / 09-October-2015</strong></label> <div> -<h2 id="main-changes-12">Main Changes</h2> +<h2 id="main-changes-13">Main Changes</h2> <ul> <li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li> <li><strong>Macros and literals renaming to ensure compatibles across STM32 series</strong>, backward compatibility maintained thanks to new added file stm32_hal_legacy.h under /Inc/Legacy</li> @@ -1901,7 +1996,7 @@ <li>PVD macros: <ul> <li>Remove the <strong>EXTILINE</strong> parameter</li> -<li>Update to use prefix "__HAL_PWR_PVD_" instead of prefix "__HAL_PVD"</li> +<li>Update to use prefix "__HAL_PWR_PVD_" instead of prefix "__HAL_PVD"</li> </ul></li> <li>Rename HAL_PWR_PVDConfig() function by HAL_PWR_ConfigPVD()</li> </ul></li> @@ -2055,7 +2150,7 @@ <li>In stm32f2xx_it.c file, UASRTx_IRQHandler() function: add a call to HAL_IRDA_IRQHandler() function</li> </ul></li> <li>IT transmit process; the code has been updated to avoid waiting on TC flag under IRDA ISR, IrDA TC interrupt is used instead. No impact on user application</li> -<li>Rename Macros: add prefix "__HAL" +<li>Rename Macros: add prefix "__HAL" <ul> <li>__IRDA_ENABLE() by __HAL_IRDA_ENABLE()</li> <li>__IRDA_DISABLE() by __HAL_IRDA_DISABLE()</li> @@ -2239,7 +2334,7 @@ <li><ul> <li>Reading RTC current time locks the values in calendar shadow registers until Current date is read.</li> </ul></li> -<li>Rename literals: add prefix "__HAL" +<li>Rename literals: add prefix "__HAL" <ul> <li>FORMAT_BIN by RTC_FORMAT_BIN</li> <li>FORMAT_BCD by RTC_FORMAT_BCD</li> @@ -2306,7 +2401,7 @@ <li>In stm32f2xx_it.c file, UASRTx_IRQHandler() function: add a call to HAL_SMARTCARD_IRQHandler() function</li> </ul></li> <li>IT transmit process; the code has been updated to avoid waiting on TC flag under SMARTCARD ISR, SMARTCARD TC interrupt is used instead. No impact on user application</li> -<li>Rename macros: add prefix "__HAL" +<li>Rename macros: add prefix "__HAL" <ul> <li>__SMARTCARD_ENABLE() by __HAL_SMARTCARD_ENABLE()</li> <li>__SMARTCARD_DISABLE() by __HAL_SMARTCARD_DISABLE()</li> @@ -2493,7 +2588,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.0.1 / 25-March-2014</strong></label> <div> -<h2 id="main-changes-13">Main Changes</h2> +<h2 id="main-changes-14">Main Changes</h2> <ul> <li>Patch release : moved macros related to RNG from hal_rcc_ex.h to hal_rcc.h as RNG is present in all versions of the STM32F2</li> </ul> @@ -2502,7 +2597,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 07-March-2014</strong></label> <div> -<h2 id="main-changes-14">Main Changes</h2> +<h2 id="main-changes-15">Main Changes</h2> <ul> <li>First official release</li> </ul>
diff --git a/Src/stm32f2xx_hal.c b/Src/stm32f2xx_hal.c index daeb990..9ec2f07 100644 --- a/Src/stm32f2xx_hal.c +++ b/Src/stm32f2xx_hal.c
@@ -54,7 +54,7 @@ */ #define __STM32F2xx_HAL_VERSION_MAIN 0x01U /*!< [31:24] main version */ #define __STM32F2xx_HAL_VERSION_SUB1 0x02U /*!< [23:16] sub1 version */ -#define __STM32F2xx_HAL_VERSION_SUB2 0x08U /*!< [15:8] sub2 version */ +#define __STM32F2xx_HAL_VERSION_SUB2 0x09U /*!< [15:8] sub2 version */ #define __STM32F2xx_HAL_VERSION_RC 0x00U /*!< [7:0] release candidate */ #define __STM32F2xx_HAL_VERSION ((__STM32F2xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F2xx_HAL_VERSION_SUB1 << 16U)\
diff --git a/Src/stm32f2xx_hal_dac.c b/Src/stm32f2xx_hal_dac.c index a27cc29..657a198 100644 --- a/Src/stm32f2xx_hal_dac.c +++ b/Src/stm32f2xx_hal_dac.c
@@ -938,10 +938,7 @@ uint32_t result; /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } + assert_param(hdac != NULL); /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel));
diff --git a/Src/stm32f2xx_hal_dac_ex.c b/Src/stm32f2xx_hal_dac_ex.c index bc2c874..95c73a7 100644 --- a/Src/stm32f2xx_hal_dac_ex.c +++ b/Src/stm32f2xx_hal_dac_ex.c
@@ -387,7 +387,6 @@ } - /** * @} */
diff --git a/Src/stm32f2xx_hal_dcmi.c b/Src/stm32f2xx_hal_dcmi.c index 98c70f4..bdaf01a 100644 --- a/Src/stm32f2xx_hal_dcmi.c +++ b/Src/stm32f2xx_hal_dcmi.c
@@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -26,7 +37,7 @@ Synchronization Mode, code of the frame delimiter and data width using HAL_DCMI_Init() function. - (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR + (#) Configure the selected DMA stream to transfer Data from DCMI DR register to the destination memory buffer. (#) Program the required configuration through following parameters: @@ -35,7 +46,7 @@ (#) Optionally, configure and Enable the CROP feature to select a rectangular window from the received image using HAL_DCMI_ConfigCrop() - and HAL_DCMI_EnableCROP() functions + and HAL_DCMI_EnableCrop() functions (#) The capture can be stopped using HAL_DCMI_Stop() function. @@ -65,33 +76,33 @@ Use functions HAL_DCMI_RegisterCallback() to register a user callback. Function HAL_DCMI_RegisterCallback() allows to register following callbacks: - (+) FrameEventCallback : DCMI Frame Event. - (+) VsyncEventCallback : DCMI Vsync Event. - (+) LineEventCallback : DCMI Line Event. - (+) ErrorCallback : DCMI error. - (+) MspInitCallback : DCMI MspInit. - (+) MspDeInitCallback : DCMI MspDeInit. - This function takes as parameters the HAL peripheral handle, the callback ID + (+) FrameEventCallback : callback for DCMI Frame Event. + (+) VsyncEventCallback : callback for DCMI Vsync Event. + (+) LineEventCallback : callback for DCMI Line Event. + (+) ErrorCallback : callback for DCMI error detection. + (+) MspInitCallback : callback for DCMI MspInit. + (+) MspDeInitCallback : callback for DCMI MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. This function allows to reset following callbacks: - (+) FrameEventCallback : DCMI Frame Event. - (+) VsyncEventCallback : DCMI Vsync Event. - (+) LineEventCallback : DCMI Line Event. - (+) ErrorCallback : DCMI error. - (+) MspInitCallback : DCMI MspInit. - (+) MspDeInitCallback : DCMI MspDeInit. + (+) FrameEventCallback : callback for DCMI Frame Event. + (+) VsyncEventCallback : callback for DCMI Vsync Event. + (+) LineEventCallback : callback for DCMI Line Event. + (+) ErrorCallback : callback for DCMI error. + (+) MspInitCallback : callback for DCMI MspInit. + (+) MspDeInitCallback : callback for DCMI MspDeInit. By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak (overridden) functions: examples FrameEventCallback(), HAL_DCMI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DCMI_Init - and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). + reset to the legacy weak (overridden) functions in the HAL_DCMI_Init + and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -105,24 +116,16 @@ When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** - * @attention - * - * Copyright (c) 2016 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f2xx_hal.h" +#ifdef HAL_DCMI_MODULE_ENABLED +#if defined (DCMI) /** @addtogroup STM32F2xx_HAL_Driver * @{ @@ -132,19 +135,35 @@ * @{ */ -#ifdef HAL_DCMI_MODULE_ENABLED -#if defined (DCMI) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */ +/** @defgroup DCMI_Private_Constants DCMI Private Constants + * @{ + */ +/** @defgroup DCMI_Stop_TimeOut DCMI Stop Time Out + * @{ + */ +#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */ +/** + * @} + */ + +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup DCMI_Private_Functions DCMI Private Functions + * @{ + */ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma); static void DCMI_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @defgroup DCMI_Exported_Functions DCMI Exported Functions @@ -152,8 +171,8 @@ */ /** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### @@ -195,6 +214,7 @@ { /* Init the DCMI Callback settings */ #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */ hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ @@ -317,8 +337,8 @@ * @} */ /** @defgroup DCMI_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * + * @brief IO operation functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -344,8 +364,9 @@ */ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) { + uint32_t tmp_length = Length; /* Initialize the second memory address */ - uint32_t SecondMemAddress = 0; + uint32_t SecondMemAddress; /* Check function parameters */ assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode)); @@ -378,11 +399,18 @@ hdcmi->XferSize = 0; hdcmi->pBuffPtr = 0; - if (Length <= 0xFFFFU) + if (tmp_length <= 0xFFFFU) { /* Enable the DMA Stream */ - if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, tmp_length) != HAL_OK) { + /* Set Error Code */ + hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA; + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_READY; + /* Release Lock */ + __HAL_UNLOCK(hdcmi); + /* Return function status */ return HAL_ERROR; } } @@ -393,7 +421,7 @@ /* Initialize transfer parameters */ hdcmi->XferCount = 1; - hdcmi->XferSize = Length; + hdcmi->XferSize = tmp_length; hdcmi->pBuffPtr = pData; /* Get the number of buffer */ @@ -408,11 +436,18 @@ hdcmi->XferTransferNumber = hdcmi->XferCount; /* Update second memory address */ - SecondMemAddress = (uint32_t)(pData + (4 * hdcmi->XferSize)); + SecondMemAddress = (uint32_t)(pData + (4U * hdcmi->XferSize)); /* Start DMA multi buffer transfer */ if (HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize) != HAL_OK) { + /* Set Error Code */ + hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA; + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_READY; + /* Release Lock */ + __HAL_UNLOCK(hdcmi); + /* Return function status */ return HAL_ERROR; } } @@ -435,7 +470,7 @@ */ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi) { - register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U); + uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U); HAL_StatusTypeDef status = HAL_OK; /* Process locked */ @@ -450,7 +485,8 @@ /* Check if the DCMI capture effectively disabled */ do { - if (count-- == 0U) + count-- ; + if (count == 0U) { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; @@ -458,8 +494,7 @@ status = HAL_TIMEOUT; break; } - } - while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U); + } while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U); /* Disable the DCMI */ __HAL_DCMI_DISABLE(hdcmi); @@ -488,7 +523,7 @@ */ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi) { - register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U); + uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U); HAL_StatusTypeDef status = HAL_OK; /* Process locked */ @@ -505,7 +540,8 @@ /* Check if the DCMI capture effectively disabled */ do { - if (count-- == 0U) + count-- ; + if (count == 0U) { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; @@ -516,8 +552,7 @@ status = HAL_TIMEOUT; break; } - } - while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U); + } while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U); } /* Process Unlocked */ __HAL_UNLOCK(hdcmi); @@ -542,7 +577,7 @@ /* Change DCMI state */ hdcmi->State = HAL_DCMI_STATE_BUSY; - /* Disable Capture */ + /* Enable Capture */ hdcmi->Instance->CR |= DCMI_CR_CAPTURE; } /* Process Unlocked */ @@ -578,7 +613,10 @@ hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; /* Abort the DMA Transfer */ - (void)HAL_DMA_Abort_IT(hdcmi->DMA_Handle); + if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK) + { + DCMI_DMAError(hdcmi->DMA_Handle); + } } /* Overflow interrupt management ********************************************/ if ((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI) @@ -679,6 +717,8 @@ */ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcmi); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_DCMI_LineEventCallback could be implemented in the user file */ @@ -721,8 +761,8 @@ */ /** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * + * @brief Peripheral Control functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -746,7 +786,8 @@ * @param Y0 DCMI window Y offset * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize) +HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, + uint32_t YSize) { /* Process Locked */ __HAL_LOCK(hdcmi); @@ -833,7 +874,7 @@ * the embedded synchronization delimiters unmasks. * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask) +HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask) { /* Process Locked */ __HAL_LOCK(hdcmi); @@ -861,8 +902,8 @@ */ /** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### @@ -882,32 +923,40 @@ * the configuration information for DCMI. * @retval HAL state */ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi) { return hdcmi->State; } /** -* @brief Return the DCMI error code -* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * @brief Return the DCMI error code + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. -* @retval DCMI Error Code -*/ -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) + * @retval DCMI Error Code + */ +uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi) { return hdcmi->ErrorCode; } #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) /** - * @brief DCMI Callback registering - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param CallbackID dcmi Callback ID - * @param pCallback pointer to DCMI_CallbackTypeDef structure - * @retval status + * @brief Register a User DCMI Callback + * To be used instead of the weak predefined callback + * @param hdcmi DCMI handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID + * @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID + * @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID + * @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID + * @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, + pDCMI_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -987,10 +1036,18 @@ } /** - * @brief DCMI Callback Unregistering - * @param hdcmi dcmi handle - * @param CallbackID dcmi Callback ID - * @retval status + * @brief Unregister a DCMI Callback + * DCMI callback is redirected to the weak predefined callback + * @param hdcmi DCMI handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID + * @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID + * @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID + * @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID + * @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID) { @@ -1005,15 +1062,15 @@ break; case HAL_DCMI_VSYNC_EVENT_CB_ID : - hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ + hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ break; case HAL_DCMI_LINE_EVENT_CB_ID : - hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ + hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ break; case HAL_DCMI_ERROR_CB_ID : - hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */ + hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_DCMI_MSPINIT_CB_ID : @@ -1067,52 +1124,65 @@ /** * @} */ + +/** + * @} + */ + /* Private functions ---------------------------------------------------------*/ /** @defgroup DCMI_Private_Functions DCMI Private Functions * @{ */ /** -* @brief DMA conversion complete callback. -* @param hdma pointer to a DMA_HandleTypeDef structure that contains -* the configuration information for the specified DMA module. -* @retval None -*/ + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) { - uint32_t tmp = 0; + uint32_t tmp ; DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - if (hdcmi->XferCount != 0) + if (hdcmi->XferCount != 0U) { /* Update memory 0 address location */ - tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT); - if (((hdcmi->XferCount % 2) == 0) && (tmp != 0)) + tmp = ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR) & DMA_SxCR_CT); + if (((hdcmi->XferCount % 2U) == 0U) && (tmp != 0U)) { - tmp = hdcmi->DMA_Handle->Instance->M0AR; - HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY0); + tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR; + (void)HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U * hdcmi->XferSize)), MEMORY0); hdcmi->XferCount--; } /* Update memory 1 address location */ - else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0) + else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U) { - tmp = hdcmi->DMA_Handle->Instance->M1AR; - HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY1); + tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR; + (void)HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U * hdcmi->XferSize)), MEMORY1); hdcmi->XferCount--; } + else + { + /* Nothing to do */ + } } /* Update memory 0 address location */ - else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0) + else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) != 0U) { - hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr; + ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR = hdcmi->pBuffPtr; } /* Update memory 1 address location */ - else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0) + else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U) { tmp = hdcmi->pBuffPtr; - hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4 * hdcmi->XferSize)); + ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR = (tmp + (4U * hdcmi->XferSize)); hdcmi->XferCount = hdcmi->XferTransferNumber; } + else + { + /* Nothing to do */ + } /* Check if the frame is transferred */ if (hdcmi->XferCount == hdcmi->XferTransferNumber) @@ -1160,10 +1230,6 @@ /** * @} */ - -/** - * @} - */ #endif /* DCMI */ #endif /* HAL_DCMI_MODULE_ENABLED */ /** @@ -1173,5 +1239,3 @@ /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f2xx_hal_dcmi_ex.c b/Src/stm32f2xx_hal_dcmi_ex.c index aa737d2..7700981 100644 --- a/Src/stm32f2xx_hal_dcmi_ex.c +++ b/Src/stm32f2xx_hal_dcmi_ex.c
@@ -30,4 +30,3 @@ /* Exported functions --------------------------------------------------------*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f2xx_hal_flash.c b/Src/stm32f2xx_hal_flash.c index 5f145a6..9ef7a4d 100644 --- a/Src/stm32f2xx_hal_flash.c +++ b/Src/stm32f2xx_hal_flash.c
@@ -215,9 +215,6 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); @@ -362,9 +359,7 @@ /* Disable Error source interrupt */ __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); + } }
diff --git a/Src/stm32f2xx_hal_flash_ex.c b/Src/stm32f2xx_hal_flash_ex.c index 3f0a8a7..aad856a 100644 --- a/Src/stm32f2xx_hal_flash_ex.c +++ b/Src/stm32f2xx_hal_flash_ex.c
@@ -205,9 +205,6 @@ { HAL_StatusTypeDef status = HAL_OK; - /* Process Locked */ - __HAL_LOCK(&pFlash); - /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
diff --git a/Src/stm32f2xx_hal_hash.c b/Src/stm32f2xx_hal_hash.c index d552527..8919c44 100644 --- a/Src/stm32f2xx_hal_hash.c +++ b/Src/stm32f2xx_hal_hash.c
@@ -268,10 +268,10 @@ */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size); static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout); @@ -751,7 +751,8 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -777,7 +778,7 @@ * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -792,7 +793,7 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -809,7 +810,8 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -835,7 +837,7 @@ * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -850,7 +852,7 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -898,7 +900,7 @@ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -922,7 +924,7 @@ * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -936,7 +938,7 @@ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -952,7 +954,7 @@ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -977,7 +979,7 @@ * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -991,7 +993,7 @@ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1060,7 +1062,7 @@ * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1090,7 +1092,7 @@ * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1147,7 +1149,8 @@ * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -1166,7 +1169,8 @@ * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -1208,7 +1212,7 @@ * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -1226,7 +1230,7 @@ * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1237,7 +1241,6 @@ */ - /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode * @brief HMAC processing functions using DMA modes. * @@ -1274,7 +1277,7 @@ * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1293,7 +1296,7 @@ * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1340,7 +1343,7 @@ * @param hhash HASH handle. * @retval HAL HASH state */ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash) { return hhash->State; } @@ -1353,7 +1356,7 @@ * @param hhash HASH handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) +HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash) { return hhash->Status; } @@ -1591,7 +1594,7 @@ * @param hhash pointer to a HASH_HandleTypeDef structure. * @retval HASH Error Code */ -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash) { /* Return HASH Error Code */ return hhash->ErrorCode; @@ -1785,13 +1788,13 @@ * suspension time is stored in the handle for resumption later on. * @retval HAL status */ -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; uint32_t tmp; - for (buffercounter = 0U; buffercounter < Size / 4U; buffercounter++) + for (buffercounter = 0U; buffercounter < (Size / 4U); buffercounter++) { /* Write input data 4 bytes at a time */ HASH->DIN = *(uint32_t *)inputaddr; @@ -1799,10 +1802,10 @@ /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter * 4 + 4U) < Size)) + if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (((buffercounter * 4U) + 4U) < Size)) { /* wait for flag BUSY not set before Wait for DINIS = 1*/ - if (buffercounter * 4 >= 64U) + if ((buffercounter * 4U) >= 64U) { if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { @@ -1823,14 +1826,14 @@ /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashInCount = Size - (buffercounter * 4 + 4U); + hhash->HashInCount = Size - ((buffercounter * 4U) + 4U); } else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) { /* Save current reading and writing locations of Input and Output buffers */ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ - hhash->HashKeyCount = Size - (buffercounter * 4 + 4U); + hhash->HashKeyCount = Size - ((buffercounter * 4U) + 4U); } else { @@ -1850,17 +1853,17 @@ /* At this point, all the data have been entered to the Peripheral: exit */ - if (Size % 4U != 0U) + if ((Size % 4U) != 0U) { if (hhash->Init.DataType == HASH_DATATYPE_16B) { /* Write remaining input data */ - if (Size % 4U <= 2) + if ((Size % 4U) <= 2U) { HASH->DIN = (uint32_t) * (uint16_t *)inputaddr; } - if (Size % 4U == 3) + if ((Size % 4U) == 3U) { HASH->DIN = *(uint32_t *)inputaddr; } @@ -1870,19 +1873,19 @@ || (hhash->Init.DataType == HASH_DATATYPE_1B)) /* byte swap or bit swap or */ { /* Write remaining input data */ - if (Size % 4U == 1) + if ((Size % 4U) == 1U) { HASH->DIN = (uint32_t) * (uint8_t *)inputaddr; } - if (Size % 4U == 2) + if ((Size % 4U) == 2U) { HASH->DIN = (uint32_t) * (uint16_t *)inputaddr; } - if (Size % 4U == 3) + if ((Size % 4U) == 3U) { tmp = *(uint8_t *)inputaddr; - tmp |= *(uint8_t *)(inputaddr + 1U) << 8U ; - tmp |= *(uint8_t *)(inputaddr + 2U) << 16U; + tmp |= (uint32_t) * (uint8_t *)(inputaddr + 1U) << 8U; + tmp |= (uint32_t) * (uint8_t *)(inputaddr + 2U) << 16U; HASH->DIN = tmp; } @@ -1891,7 +1894,6 @@ { HASH->DIN = *(uint32_t *)inputaddr; } - /*hhash->HashInCount += 4U;*/ } @@ -1904,7 +1906,7 @@ * @param Size message digest size in bytes. * @retval None */ -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; @@ -1937,7 +1939,6 @@ } - /** * @brief Handle HASH processing Timeout. * @param hhash HASH handle. @@ -2423,10 +2424,11 @@ * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2458,7 +2460,7 @@ /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Set the phase */ @@ -2474,7 +2476,7 @@ /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; Size_tmp = hhash->HashInCount; } /* ... or multi-buffer HASH processing end */ @@ -2482,7 +2484,7 @@ { /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; + pInBuffer_tmp = (const uint8_t *)pInBuffer; Size_tmp = Size; /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); @@ -2560,9 +2562,10 @@ * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2594,7 +2597,7 @@ /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ } @@ -2605,7 +2608,7 @@ /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Check if initialization phase has already be performed */ @@ -2663,7 +2666,8 @@ * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -2773,7 +2777,6 @@ } - /** * @brief Initialize the HASH peripheral, next process pInBuffer then * read the computed digest in interruption mode. @@ -2785,7 +2788,8 @@ * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2834,6 +2838,19 @@ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ } + else if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) && (SizeVar < 4U)) + { + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) + { + /* It remains data to enter and the Peripheral is ready to trigger DINIE,carry on as usual. + Update HashInCount and pHashInBuffPtr accordingly. */ + hhash->HashInCount = SizeVar; + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; + /* Update the configuration of the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(SizeVar); + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + } + } else { initialization_skipped = 1; /* info user later on in case of multi-buffer */ @@ -2937,7 +2954,8 @@ * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; @@ -3109,7 +3127,8 @@ * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3173,7 +3192,6 @@ } - /** * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then * read the computed digest in interruption mode. @@ -3187,7 +3205,8 @@ * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3282,7 +3301,6 @@ } - /** * @brief Initialize the HASH peripheral in HMAC mode then initiate the required * DMA transfers to feed the key and the input buffer to the Peripheral. @@ -3298,7 +3316,8 @@ * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize;
diff --git a/Src/stm32f2xx_hal_hcd.c b/Src/stm32f2xx_hal_hcd.c index 7e788b8..8df2d18 100644 --- a/Src/stm32f2xx_hal_hcd.c +++ b/Src/stm32f2xx_hal_hcd.c
@@ -1279,7 +1279,7 @@ */ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1598,7 +1598,7 @@ */ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; uint32_t num_packets; @@ -1720,12 +1720,6 @@ else { hhcd->hc[chnum].urb_state = URB_NOTREADY; - - /* Re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; } } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); @@ -1839,7 +1833,7 @@ */ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t pktsts; uint32_t pktcnt; @@ -1905,7 +1899,7 @@ */ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0; __IO uint32_t hprt0_dup;
diff --git a/Src/stm32f2xx_hal_i2c.c b/Src/stm32f2xx_hal_i2c.c index 8246fcb..63dbded 100644 --- a/Src/stm32f2xx_hal_i2c.c +++ b/Src/stm32f2xx_hal_i2c.c
@@ -5690,15 +5690,11 @@ /* Enable Acknowledge */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); } - else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP) + else { /* Generate Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); } - else - { - /* Do nothing */ - } /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
diff --git a/Src/stm32f2xx_hal_i2s.c b/Src/stm32f2xx_hal_i2s.c index 3f891a6..7e14aae 100644 --- a/Src/stm32f2xx_hal_i2s.c +++ b/Src/stm32f2xx_hal_i2s.c
@@ -796,15 +796,14 @@ return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -915,15 +914,14 @@ return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1013,15 +1011,14 @@ return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1040,6 +1037,8 @@ hi2s->TxXferCount = Size; } + __HAL_UNLOCK(hi2s); + /* Enable TXE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); @@ -1050,7 +1049,6 @@ __HAL_I2S_ENABLE(hi2s); } - __HAL_UNLOCK(hi2s); return HAL_OK; } @@ -1079,15 +1077,14 @@ return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1106,6 +1103,8 @@ hi2s->RxXferCount = Size; } + __HAL_UNLOCK(hi2s); + /* Enable RXNE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); @@ -1116,7 +1115,6 @@ __HAL_I2S_ENABLE(hi2s); } - __HAL_UNLOCK(hi2s); return HAL_OK; } @@ -1143,15 +1141,14 @@ return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1193,12 +1190,7 @@ return HAL_ERROR; } - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } + __HAL_UNLOCK(hi2s); /* Check if the I2S Tx request is already enabled */ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) @@ -1207,7 +1199,13 @@ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); } - __HAL_UNLOCK(hi2s); + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + return HAL_OK; } @@ -1234,15 +1232,14 @@ return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1290,12 +1287,7 @@ return HAL_ERROR; } - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } + __HAL_UNLOCK(hi2s); /* Check if the I2S Rx request is already enabled */ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) @@ -1304,7 +1296,13 @@ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); } - __HAL_UNLOCK(hi2s); + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + return HAL_OK; }
diff --git a/Src/stm32f2xx_hal_iwdg.c b/Src/stm32f2xx_hal_iwdg.c index 89d0600..d9878d0 100644 --- a/Src/stm32f2xx_hal_iwdg.c +++ b/Src/stm32f2xx_hal_iwdg.c
@@ -91,7 +91,6 @@ the reload register @endverbatim - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -121,7 +120,8 @@ The timeout value is multiplied by 1000 to be converted in milliseconds. LSI startup time is also considered here by adding LSI_STARTUP_TIME converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / (LSI_VALUE / 128U)) + \ + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_RVU | IWDG_SR_PVU) /** * @}
diff --git a/Src/stm32f2xx_hal_mmc.c b/Src/stm32f2xx_hal_mmc.c index 2f1a3d7..c41599b 100644 --- a/Src/stm32f2xx_hal_mmc.c +++ b/Src/stm32f2xx_hal_mmc.c
@@ -2328,7 +2328,7 @@ if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; return HAL_ERROR; }
diff --git a/Src/stm32f2xx_hal_nand.c b/Src/stm32f2xx_hal_nand.c index 5a70612..2bf27d2 100644 --- a/Src/stm32f2xx_hal_nand.c +++ b/Src/stm32f2xx_hal_nand.c
@@ -506,7 +506,7 @@ * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig) { hnand->Config.PageSize = pDeviceConfig->PageSize; hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
diff --git a/Src/stm32f2xx_hal_pccard.c b/Src/stm32f2xx_hal_pccard.c index 2361d7e..fd998d9 100644 --- a/Src/stm32f2xx_hal_pccard.c +++ b/Src/stm32f2xx_hal_pccard.c
@@ -162,7 +162,8 @@ * @retval HAL status */ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, - FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming) + FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, + FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming) { /* Check the PCCARD controller state */ if (hpccard == NULL) @@ -186,7 +187,7 @@ #else /* Initialize the low level hardware (MSP) */ HAL_PCCARD_MspInit(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ } /* Initialize the PCCARD state */ @@ -233,7 +234,7 @@ #else /* De-Initialize the low level hardware (MSP) */ HAL_PCCARD_MspDeInit(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /* Configure the PCCARD registers with their reset values */ FSMC_PCCARD_DeInit(hpccard->Instance); @@ -306,8 +307,9 @@ */ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U; - uint8_t status = 0; + uint32_t timeout = 0U; + uint32_t index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -318,6 +320,9 @@ return HAL_BUSY; } + /* Initialize timeout value */ + timeout = PCCARD_TIMEOUT_READ_ID; + /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; @@ -370,8 +375,9 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U; - uint8_t status = 0; + uint32_t timeout = 0U; + uint32_t index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -382,6 +388,9 @@ return HAL_BUSY; } + /* Initialize timeout value */ + timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR; + /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; @@ -447,8 +456,9 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U; - uint8_t status = 0; + uint32_t timeout = 0U; + uint32_t index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -459,6 +469,9 @@ return HAL_BUSY; } + /* Initialize timeout value */ + timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR; + /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; @@ -521,7 +534,7 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus) { uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR; - uint8_t status = 0; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -623,7 +636,7 @@ hpccard->ItCallback(hpccard); #else HAL_PCCARD_ITCallback(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /* Clear PCCARD interrupt Rising edge pending bit */ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE); @@ -637,7 +650,7 @@ hpccard->ItCallback(hpccard); #else HAL_PCCARD_ITCallback(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /* Clear PCCARD interrupt Level pending bit */ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL); @@ -651,7 +664,7 @@ hpccard->ItCallback(hpccard); #else HAL_PCCARD_ITCallback(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /* Clear PCCARD interrupt Falling edge pending bit */ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE); @@ -665,7 +678,7 @@ hpccard->ItCallback(hpccard); #else HAL_PCCARD_ITCallback(hpccard); -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /* Clear PCCARD interrupt FIFO empty pending bit */ __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT); @@ -822,7 +835,7 @@ __HAL_UNLOCK(hpccard); return status; } -#endif +#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ /** * @} @@ -865,7 +878,8 @@ */ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard) { - uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U; + uint32_t timeout = PCCARD_TIMEOUT_STATUS; + uint32_t status_pccard = 0U; /* Check the PCCARD controller state */ if (hpccard->State == HAL_PCCARD_STATE_BUSY) @@ -901,7 +915,8 @@ */ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard) { - uint8_t data = 0U, status_pccard = PCCARD_BUSY; + uint8_t data = 0U; + uint8_t status_pccard = PCCARD_BUSY; /* Check the PCCARD controller state */ if (hpccard->State == HAL_PCCARD_STATE_BUSY)
diff --git a/Src/stm32f2xx_hal_pcd.c b/Src/stm32f2xx_hal_pcd.c index bcc367a..ae9999a 100644 --- a/Src/stm32f2xx_hal_pcd.c +++ b/Src/stm32f2xx_hal_pcd.c
@@ -1897,9 +1897,9 @@ * @param testmode USB Device high speed test mode * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; switch (testmode) @@ -2001,9 +2001,9 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { USB_OTG_EPTypeDef *ep; - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; if (hpcd->Init.dma_enable == 1U) @@ -2112,9 +2112,9 @@ */ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
diff --git a/Src/stm32f2xx_hal_rng.c b/Src/stm32f2xx_hal_rng.c index a49894b..acaf0e9 100644 --- a/Src/stm32f2xx_hal_rng.c +++ b/Src/stm32f2xx_hal_rng.c
@@ -689,15 +689,16 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; /* RNG clock error interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } - else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; @@ -728,7 +729,7 @@ } /* Check RNG data ready interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) { /* Generate random number once, so disable the IT */ __HAL_RNG_DISABLE_IT(hrng);
diff --git a/Src/stm32f2xx_hal_rtc.c b/Src/stm32f2xx_hal_rtc.c index 30fe52c..71cae35 100644 --- a/Src/stm32f2xx_hal_rtc.c +++ b/Src/stm32f2xx_hal_rtc.c
@@ -6,8 +6,8 @@ * This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: * + Initialization and de-initialization functions - * + RTC Calendar (Time and Date) configuration functions - * + RTC Alarms (Alarm A and Alarm B) configuration functions + * + Calendar (Time and Date) configuration functions + * + Alarms (Alarm A and Alarm B) configuration functions * + Peripheral Control functions * + Peripheral State functions * @@ -121,6 +121,12 @@ *** Callback registration *** ============================================= [..] + When the compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all + callbacks are set to the corresponding weak functions. + This is the recommended configuration in order to optimize memory/code + consumption footprint/performances. + [..] The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. @@ -152,25 +158,21 @@ [..] By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, all callbacks are set to the corresponding weak functions: - examples AlarmAEventCallback(), WakeUpTimerEventCallback(). + examples AlarmAEventCallback(), TimeStampEventCallback(). Exception done for MspInit() and MspDeInit() callbacks that are reset to the - legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only - when these callbacks are null (not registered beforehand). + legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these + callbacks are null (not registered beforehand). If not, MspInit() or MspDeInit() are not null, HAL_RTC_Init()/HAL_RTC_DeInit() keep and use the user MspInit()/MspDeInit() callbacks (registered beforehand). [..] Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. - Exception done MspInit()/MspDeInit() that can be registered/unregistered + Exception done for MspInit() and MspDeInit() that can be registered/unregistered in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state. Thus registered (user) MspInit()/MspDeInit() callbacks can be used during the Init/DeInit. - In that case first register the MspInit()/MspDeInit() user callbacks - using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() - or HAL_RTC_Init() functions. - [..] - When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all - callbacks are set to the corresponding weak functions. + In that case first register the MspInit()/MspDeInit() user callbacks using + HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() or HAL_RTC_Init() + functions. @endverbatim ****************************************************************************** @@ -426,9 +428,9 @@ * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID - * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Event Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID MSP Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID MSP DeInit callback ID * @param pCallback pointer to the Callback function * @retval HAL status */ @@ -523,9 +525,9 @@ * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID - * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Event Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID MSP Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID MSP DeInit callback ID * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) @@ -1006,7 +1008,7 @@ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); @@ -1039,7 +1041,7 @@ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t) sAlarm->AlarmMask)); @@ -1048,16 +1050,15 @@ /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Alarm register */ if (sAlarm->Alarm == RTC_ALARM_A) { - /* Disable the Alarm A */ + /* Disable Alarm A */ __HAL_RTC_ALARMA_DISABLE(hrtc); /* In case interrupt mode is used, the interrupt source must be disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - /* Clear the Alarm flag */ + /* Clear Alarm A flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); /* Get tick */ @@ -1080,19 +1081,20 @@ } } + /* Configure Alarm A register */ hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm state: Enable Alarm */ + /* Enable Alarm A */ __HAL_RTC_ALARMA_ENABLE(hrtc); } else { - /* Disable the Alarm B */ + /* Disable Alarm B */ __HAL_RTC_ALARMB_DISABLE(hrtc); /* In case interrupt mode is used, the interrupt source must be disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - /* Clear the Alarm flag */ + /* Clear Alarm B flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); /* Get tick */ @@ -1115,8 +1117,9 @@ } } + /* Configure Alarm B register */ hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm state: Enable Alarm */ + /* Enable Alarm B */ __HAL_RTC_ALARMB_ENABLE(hrtc); } @@ -1192,7 +1195,7 @@ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); @@ -1225,7 +1228,7 @@ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t) sAlarm->AlarmMask)); @@ -1234,13 +1237,12 @@ /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Alarm register */ if (sAlarm->Alarm == RTC_ALARM_A) { - /* Disable the Alarm A */ + /* Disable Alarm A */ __HAL_RTC_ALARMA_DISABLE(hrtc); - /* Clear the Alarm flag */ + /* Clear Alarm A flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ @@ -1261,18 +1263,19 @@ } } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U); + /* Configure Alarm A register */ hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm state: Enable Alarm */ + /* Enable Alarm A */ __HAL_RTC_ALARMA_ENABLE(hrtc); - /* Configure the Alarm interrupt */ + /* Enable Alarm A interrupt */ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA); } else { - /* Disable the Alarm B */ + /* Disable Alarm B */ __HAL_RTC_ALARMB_DISABLE(hrtc); - /* Clear the Alarm flag */ + /* Clear Alarm B flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); /* Reload the counter */ @@ -1296,14 +1299,15 @@ } } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U); + /* Configure Alarm B register */ hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm state: Enable Alarm */ + /* Enable Alarm B */ __HAL_RTC_ALARMB_ENABLE(hrtc); - /* Configure the Alarm interrupt */ + /* Enable Alarm B interrupt */ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); } - /* RTC Alarm Interrupt Configuration: EXTI configuration */ + /* Enable and configure the EXTI line associated to the RTC Alarm interrupt */ __HAL_RTC_ALARM_EXTI_ENABLE_IT(); __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); @@ -1355,7 +1359,7 @@ /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ + /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) @@ -1383,7 +1387,7 @@ /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ + /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) @@ -1476,7 +1480,7 @@ */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Clear the EXTI's line Flag for RTC Alarm */ + /* Clear the EXTI flag associated to the RTC Alarm interrupt */ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); /* Get the Alarm A interrupt source enable status */
diff --git a/Src/stm32f2xx_hal_rtc_ex.c b/Src/stm32f2xx_hal_rtc_ex.c index bacc521..bcfa52e 100644 --- a/Src/stm32f2xx_hal_rtc_ex.c +++ b/Src/stm32f2xx_hal_rtc_ex.c
@@ -58,7 +58,7 @@ *** Tamper configuration *** ============================ [..] - (+) To Enable the RTC Tamper and configure the Tamper filter count, trigger + (+) To enable the RTC Tamper and configure the Tamper filter count, trigger Edge or Level according to the Tamper filter value (if equal to 0 Edge else Level), sampling frequency, precharge or discharge and Pull-UP use the HAL_RTCEx_SetTamper() function. @@ -96,8 +96,8 @@ 0 to 62. (+) In order to measure the clock deviation, a 512 Hz clock is output for calibration. - (+) The RTC Coarse Digital Calibration value and sign can be calibrated using - the HAL_RTCEx_SetCoarseCalib() function. + (+) To configure the RTC Coarse Digital Calibration value and sign use the + HAL_RTCEx_SetCoarseCalib() function. @endverbatim ****************************************************************************** @@ -272,7 +272,7 @@ /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* RTC Timestamp Interrupt Configuration: EXTI configuration */ + /* Enable and configure the EXTI line associated to the RTC Timestamp and Tamper interrupts */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); @@ -303,7 +303,7 @@ /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ + /* In case interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); /* Get the RTC_CR register and clear the bits to be configured */ @@ -493,7 +493,7 @@ /* Copy desired configuration into configuration register */ hrtc->Instance->TAFCR = tmpreg; - /* RTC Tamper Interrupt Configuration: EXTI configuration */ + /* Enable and configure the EXTI line associated to the RTC Timestamp and Tamper interrupts */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); @@ -543,7 +543,7 @@ */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Clear the EXTI's Flag for RTC Timestamp and Tamper */ + /* Clear the EXTI flag associated to the RTC Timestamp and Tamper interrupts */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); /* Get the Timestamp interrupt source enable status */ @@ -894,7 +894,7 @@ /* Configure the Wakeup Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - /* RTC wakeup timer Interrupt Configuration: EXTI configuration */ + /* Enable and configure the EXTI line associated to the RTC Wakeup Timer interrupt */ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); @@ -936,7 +936,7 @@ /* Disable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ + /* In case interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT); /* Get tick */ @@ -995,7 +995,7 @@ */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Clear the EXTI's line Flag for RTC WakeUpTimer */ + /* Clear the EXTI flag associated to the RTC Wakeup Timer interrupt */ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /* Get the pending status of the Wakeup timer Interrupt */ @@ -1111,7 +1111,7 @@ /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); - tmp = (uint32_t) & (hrtc->Instance->BKP0R); + tmp = (uint32_t) &(hrtc->Instance->BKP0R); tmp += (BackupRegister * 4U); /* Write the specified register */ @@ -1134,7 +1134,7 @@ /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); - tmp = (uint32_t) & (hrtc->Instance->BKP0R); + tmp = (uint32_t) &(hrtc->Instance->BKP0R); tmp += (BackupRegister * 4U); /* Read the specified register */
diff --git a/Src/stm32f2xx_hal_sd.c b/Src/stm32f2xx_hal_sd.c index c600d18..1e67f06 100644 --- a/Src/stm32f2xx_hal_sd.c +++ b/Src/stm32f2xx_hal_sd.c
@@ -403,7 +403,6 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { uint32_t errorstate; - HAL_StatusTypeDef status; SD_InitTypeDef Init; /* Default SDIO peripheral configuration for SD card initialization */ @@ -415,11 +414,7 @@ Init.ClockDiv = SDIO_INIT_CLK_DIV; /* Initialize SDIO peripheral interface with default configuration */ - status = SDIO_Init(hsd->Instance, Init); - if(status != HAL_OK) - { - return HAL_ERROR; - } + SDIO_Init(hsd->Instance, Init); /* Disable SDIO Clock */ __HAL_SD_DISABLE(hsd); @@ -2868,7 +2863,7 @@ } } - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -2896,7 +2891,7 @@ *pData = SDIO_ReadFIFO(hsd->Instance); pData++; - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3088,7 +3083,7 @@ break; } - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; }
diff --git a/Src/stm32f2xx_hal_spi.c b/Src/stm32f2xx_hal_spi.c index 8d1aa34..c82cd4f 100644 --- a/Src/stm32f2xx_hal_spi.c +++ b/Src/stm32f2xx_hal_spi.c
@@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -190,7 +191,8 @@ @note The max SPI frequency depend on SPI data size (8bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -765,38 +767,35 @@ * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; uint16_t initial_TxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -835,7 +834,7 @@ { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -845,7 +844,7 @@ /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -854,9 +853,9 @@ /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -866,7 +865,7 @@ { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; } @@ -875,7 +874,7 @@ /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; } @@ -884,9 +883,9 @@ /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -911,19 +910,18 @@ __HAL_SPI_CLEAR_OVRFLAG(hspi); } + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -941,12 +939,10 @@ __IO uint32_t tmpreg = 0U; #endif /* USE_SPI_CRC */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -956,18 +952,17 @@ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1026,9 +1021,9 @@ /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1050,9 +1045,9 @@ /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1069,8 +1064,8 @@ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Receive last data in 16 Bit mode */ @@ -1088,8 +1083,9 @@ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC to Flush DR and RXNE flag */ @@ -1114,18 +1110,17 @@ } #endif /* USE_SPI_CRC */ + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -1138,8 +1133,8 @@ * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; uint32_t tmp_mode; @@ -1151,14 +1146,10 @@ /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1168,18 +1159,20 @@ initial_TxXferCount = Size; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1191,7 +1184,7 @@ hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1219,7 +1212,7 @@ { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -1237,7 +1230,7 @@ /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1263,9 +1256,9 @@ } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1274,7 +1267,7 @@ { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; @@ -1291,7 +1284,7 @@ /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1317,9 +1310,9 @@ } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1333,8 +1326,9 @@ { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC */ tmpreg = READ_REG(hspi->Instance->DR); @@ -1348,17 +1342,17 @@ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - errorcode = HAL_ERROR; hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - goto error; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Clear overrun flag in 2 Lines communication mode because received is not read */ @@ -1367,18 +1361,19 @@ __HAL_SPI_CLEAR_OVRFLAG(hspi); } + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** @@ -1389,9 +1384,8 @@ * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1399,14 +1393,12 @@ if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } /* Process Locked */ @@ -1415,7 +1407,7 @@ /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1463,8 +1455,7 @@ /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1477,13 +1468,10 @@ */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1496,8 +1484,7 @@ if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } /* Process Locked */ @@ -1558,8 +1545,7 @@ /* Enable RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1571,11 +1557,11 @@ * @param Size amount of data to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1585,16 +1571,15 @@ tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } /* Process locked */ @@ -1608,7 +1593,7 @@ /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1648,8 +1633,7 @@ /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** @@ -1660,9 +1644,8 @@ * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1670,25 +1653,23 @@ /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1733,9 +1714,9 @@ { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -1745,16 +1726,16 @@ __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -1769,15 +1750,12 @@ */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1791,15 +1769,14 @@ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); } - /* Process Locked */ - __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1847,9 +1824,9 @@ { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -1859,16 +1836,16 @@ __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -1881,12 +1858,11 @@ * @param Size amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); @@ -1895,26 +1871,25 @@ /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1923,7 +1898,7 @@ /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1968,9 +1943,9 @@ { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -1989,9 +1964,9 @@ { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2000,16 +1975,17 @@ /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2375,9 +2351,11 @@ { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -2667,7 +2645,7 @@ * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -2679,7 +2657,7 @@ * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -2706,7 +2684,7 @@ */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -2763,7 +2741,7 @@ */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -2852,7 +2830,7 @@ */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -2932,7 +2910,7 @@ */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -2950,7 +2928,7 @@ */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -2968,7 +2946,7 @@ */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -2986,7 +2964,7 @@ */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3009,7 +2987,7 @@ */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3031,7 +3009,7 @@ */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); __IO uint32_t count; hspi->hdmatx->XferAbortCallback = NULL; @@ -3096,7 +3074,7 @@ */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3218,7 +3196,7 @@ */ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3311,7 +3289,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3459,7 +3437,7 @@ */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3485,7 +3463,7 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3606,6 +3584,13 @@ */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) {
diff --git a/Src/stm32f2xx_hal_sram.c b/Src/stm32f2xx_hal_sram.c index 2d907eb..04738f3 100644 --- a/Src/stm32f2xx_hal_sram.c +++ b/Src/stm32f2xx_hal_sram.c
@@ -208,7 +208,7 @@ /* Initialize SRAM extended mode timing Interface */ (void)FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, - hsram->Init.ExtendedMode); + hsram->Init.ExtendedMode); /* Enable the NORSRAM device */ __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); @@ -1037,6 +1037,7 @@ */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1059,6 +1060,7 @@ */ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1081,6 +1083,7 @@ */ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */
diff --git a/Src/stm32f2xx_hal_tim.c b/Src/stm32f2xx_hal_tim.c index 602e79d..30037a4 100644 --- a/Src/stm32f2xx_hal_tim.c +++ b/Src/stm32f2xx_hal_tim.c
@@ -3831,7 +3831,7 @@ if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3863,7 +3863,7 @@ { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) @@ -3893,7 +3893,7 @@ { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) @@ -3923,7 +3923,7 @@ { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) @@ -3953,7 +3953,7 @@ { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else @@ -3966,7 +3966,7 @@ { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else @@ -3979,7 +3979,7 @@ { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else @@ -3992,7 +3992,7 @@ { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else @@ -4479,7 +4479,8 @@ * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) { HAL_StatusTypeDef status; @@ -6944,7 +6945,6 @@ tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx))
diff --git a/Src/stm32f2xx_hal_tim_ex.c b/Src/stm32f2xx_hal_tim_ex.c index 85e84f5..2af37ec 100644 --- a/Src/stm32f2xx_hal_tim_ex.c +++ b/Src/stm32f2xx_hal_tim_ex.c
@@ -835,7 +835,7 @@ /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1081,17 +1081,6 @@ (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1317,7 +1306,7 @@ /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -2122,7 +2111,7 @@ */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2136,7 +2125,7 @@ */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2151,7 +2140,7 @@ } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -2302,15 +2291,6 @@ TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } else { /* nothing to do */ @@ -2379,13 +2359,13 @@ { uint32_t tmp; - tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ } /** * @}
diff --git a/Src/stm32f2xx_hal_uart.c b/Src/stm32f2xx_hal_uart.c index 806d935..3ea2da5 100644 --- a/Src/stm32f2xx_hal_uart.c +++ b/Src/stm32f2xx_hal_uart.c
@@ -1783,21 +1783,18 @@ status = UART_Start_Receive_DMA(huart, pData, Size); /* Check Rx process has been successfully started */ - if (status == HAL_OK) + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_IDLEFLAG(huart); - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } + __HAL_UART_CLEAR_IDLEFLAG(huart); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; } return status;
diff --git a/Src/stm32f2xx_hal_usart.c b/Src/stm32f2xx_hal_usart.c index dcc8ea9..32d42ea 100644 --- a/Src/stm32f2xx_hal_usart.c +++ b/Src/stm32f2xx_hal_usart.c
@@ -2083,6 +2083,9 @@ /** * @} */ +/** + * @} + */ /** @defgroup USART_Private_Functions USART Private Functions * @{ @@ -2798,10 +2801,6 @@ * @} */ -/** - * @} - */ - #endif /* HAL_USART_MODULE_ENABLED */ /** * @}
diff --git a/Src/stm32f2xx_hal_wwdg.c b/Src/stm32f2xx_hal_wwdg.c index 9cc9b12..617928f 100644 --- a/Src/stm32f2xx_hal_wwdg.c +++ b/Src/stm32f2xx_hal_wwdg.c
@@ -122,7 +122,6 @@ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt @endverbatim - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -418,3 +417,4 @@ /** * @} */ +
diff --git a/Src/stm32f2xx_ll_fsmc.c b/Src/stm32f2xx_ll_fsmc.c index d4f52dc..5c0c20d 100644 --- a/Src/stm32f2xx_ll_fsmc.c +++ b/Src/stm32f2xx_ll_fsmc.c
@@ -60,7 +60,7 @@ * @{ */ #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) \ - || defined(HAL_SRAM_MODULE_ENABLED) + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FSMC_LL FSMC Low Layer * @brief FSMC driver modules @@ -193,7 +193,7 @@ * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, - FSMC_NORSRAM_InitTypeDef *Init) + const FSMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -273,7 +273,7 @@ * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, - FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) + FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); @@ -310,7 +310,7 @@ * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, - FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) + const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ @@ -325,13 +325,14 @@ assert_param(IS_FSMC_NORSRAM_BANK(Bank)); /* Set FSMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FSMC_BTR1_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FSMC_BTR1_DATAST_Pos) | - ((Timing->BusTurnAroundDuration) << FSMC_BTR1_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FSMC_BTR1_DATLAT_Pos) | - (Timing->AccessMode))); + Device->BTCR[Bank + 1U] = + (Timing->AddressSetupTime << FSMC_BTR1_ADDSET_Pos) | + (Timing->AddressHoldTime << FSMC_BTR1_ADDHLD_Pos) | + (Timing->DataSetupTime << FSMC_BTR1_DATAST_Pos) | + (Timing->BusTurnAroundDuration << FSMC_BTR1_BUSTURN_Pos) | + ((Timing->CLKDivision - 1U) << FSMC_BTR1_CLKDIV_Pos) | + ((Timing->DataLatency - 2U) << FSMC_BTR1_DATLAT_Pos) | + Timing->AccessMode; return HAL_OK; } @@ -349,8 +350,8 @@ * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, - FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, - uint32_t ExtendedMode) + const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) { /* Check the parameters */ assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); @@ -494,7 +495,7 @@ * @param Init Pointer to NAND Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) +HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FSMC_NAND_DEVICE(Device)); @@ -542,7 +543,7 @@ * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, - FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FSMC_NAND_DEVICE(Device)); @@ -582,7 +583,7 @@ * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, - FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FSMC_NAND_DEVICE(Device)); @@ -729,8 +730,8 @@ * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, - uint32_t Timeout) +HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) { uint32_t tickstart; @@ -820,7 +821,7 @@ * @param Init Pointer to PCCARD Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) +HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FSMC_PCCARD_DEVICE(Device)); @@ -854,7 +855,7 @@ * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, - FSMC_NAND_PCC_TimingTypeDef *Timing) + const FSMC_NAND_PCC_TimingTypeDef *Timing) { /* Check the parameters */ assert_param(IS_FSMC_PCCARD_DEVICE(Device)); @@ -883,7 +884,7 @@ * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, - FSMC_NAND_PCC_TimingTypeDef *Timing) + const FSMC_NAND_PCC_TimingTypeDef *Timing) { /* Check the parameters */ assert_param(IS_FSMC_PCCARD_DEVICE(Device)); @@ -912,7 +913,7 @@ * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, - FSMC_NAND_PCC_TimingTypeDef *Timing) + const FSMC_NAND_PCC_TimingTypeDef *Timing) { /* Check the parameters */ assert_param(IS_FSMC_PCCARD_DEVICE(Device));
diff --git a/Src/stm32f2xx_ll_spi.c b/Src/stm32f2xx_ll_spi.c index 097ebf6..1ed0a4e 100644 --- a/Src/stm32f2xx_ll_spi.c +++ b/Src/stm32f2xx_ll_spi.c
@@ -119,7 +119,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -168,8 +168,9 @@ /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) @@ -345,7 +346,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx) { return LL_SPI_DeInit(SPIx); }
diff --git a/Src/stm32f2xx_ll_tim.c b/Src/stm32f2xx_ll_tim.c index 4d067b3..e025d04 100644 --- a/Src/stm32f2xx_ll_tim.c +++ b/Src/stm32f2xx_ll_tim.c
@@ -748,8 +748,6 @@ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -777,8 +775,10 @@ if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -827,8 +827,6 @@ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -856,8 +854,10 @@ if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -906,8 +906,6 @@ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -935,8 +933,10 @@ if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -985,8 +985,6 @@ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1014,7 +1012,6 @@ if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the Output Idle state */ @@ -1036,7 +1033,6 @@ return SUCCESS; } - /** * @brief Configure the TIMx input channel 1. * @param TIMx Timer Instance @@ -1161,7 +1157,7 @@ (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
diff --git a/Src/stm32f2xx_ll_usb.c b/Src/stm32f2xx_ll_usb.c index f767f2c..5477e95 100644 --- a/Src/stm32f2xx_ll_usb.c +++ b/Src/stm32f2xx_ll_usb.c
@@ -518,7 +518,7 @@ * @arg USB_OTG_SPEED_FULL: Full speed mode * @retval Hal status */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -534,7 +534,7 @@ * @arg USBD_HS_SPEED: High speed mode * @arg USBD_FS_SPEED: Full speed mode */ -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint8_t speed; @@ -563,7 +563,7 @@ * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -601,7 +601,7 @@ * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -640,7 +640,7 @@ * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -687,7 +687,7 @@ * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -901,7 +901,7 @@ * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { __IO uint32_t count = 0U; HAL_StatusTypeDef ret = HAL_OK; @@ -965,7 +965,7 @@ * 1 : DMA feature used * @retval HAL status */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -996,7 +996,7 @@ * @param len Number of bytes to read * @retval pointer to destination buffer */ -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { uint32_t USBx_BASE = (uint32_t)USBx; uint8_t *pDest = dest; @@ -1038,7 +1038,7 @@ * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -1069,7 +1069,7 @@ * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t epnum = (uint32_t)ep->num; @@ -1139,7 +1139,7 @@ * This parameter can be a value from 0 to 255 * @retval HAL status */ -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1154,7 +1154,7 @@ * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1171,7 +1171,7 @@ * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1204,7 +1204,7 @@ * @param chnum Channel number * @retval USB Channel Interrupt status */ -uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1220,7 +1220,7 @@ * @param USBx Selected device * @retval USB Device OUT EP interrupt status */ -uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1236,7 +1236,7 @@ * @param USBx Selected device * @retval USB Device IN EP interrupt status */ -uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1254,7 +1254,7 @@ * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ -uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1272,7 +1272,7 @@ * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ -uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t tmpreg; @@ -1306,7 +1306,7 @@ * 0 : Host * 1 : Device */ -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { return ((USBx->GINTSTS) & 0x1U); } @@ -1316,7 +1316,7 @@ * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1338,10 +1338,10 @@ * @param psetup pointer to setup packet * @retval HAL status */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); if (gSNPSiD > USB_OTG_CORE_ID_300A) { @@ -1508,7 +1508,7 @@ * HCFG_6_MHZ : Low Speed 6 MHz Clock * @retval HAL status */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1538,7 +1538,7 @@ * @note (1)The application must wait at least 10 ms * before clearing the reset bit. */ -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1565,7 +1565,7 @@ * 1 : Activate VBUS * @retval HAL status */ -HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) { uint32_t USBx_BASE = (uint32_t)USBx; __IO uint32_t hprt0 = 0U; @@ -1788,7 +1788,7 @@ /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ if (dma == 1U) { - if ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) + if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) { USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | @@ -2035,7 +2035,7 @@ * @param USBx Selected device * @retval HAL state */ -uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -2049,7 +2049,7 @@ * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t hcnum = (uint32_t)hc_num; @@ -2133,7 +2133,7 @@ * This parameter can be a value from 1 to 15 * @retval HAL state */ -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t chnum = (uint32_t)ch_num; @@ -2222,7 +2222,7 @@ * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -2240,7 +2240,7 @@ * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx;
diff --git a/Src/stm32f2xx_ll_utils.c b/Src/stm32f2xx_ll_utils.c index c872c6d..3a24c5f 100644 --- a/Src/stm32f2xx_ll_utils.c +++ b/Src/stm32f2xx_ll_utils.c
@@ -339,28 +339,25 @@ latency = LL_FLASH_LATENCY_0; } } - if (status != ERROR) - { - LL_FLASH_SetLatency(latency); + LL_FLASH_SetLatency(latency); - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - timeout = 2; - do - { + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2; + do + { /* Wait for Flash latency to be updated */ getlatency = LL_FLASH_GetLatency(); timeout--; - } while ((getlatency != latency) && (timeout > 0)); + } while ((getlatency != latency) && (timeout > 0)); - if(getlatency != latency) - { - status = ERROR; - } - else - { - status = SUCCESS; - } + if(getlatency != latency) + { + status = ERROR; + } + else + { + /* No thing to do */ } } return status;