Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1 | /** |
| 2 | ****************************************************************************** |
| 3 | * @file stm32f2xx_hal_i2s.h |
| 4 | * @author MCD Application Team |
| 5 | * @brief Header file of I2S HAL module. |
| 6 | ****************************************************************************** |
| 7 | * @attention |
| 8 | * |
Ali Labbene | e334a50 | 2022-02-08 15:02:11 +0100 | [diff] [blame] | 9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved. |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 11 | * |
Ali Labbene | e334a50 | 2022-02-08 15:02:11 +0100 | [diff] [blame] | 12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * in the root directory of this software component. |
| 14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 15 | * |
| 16 | ****************************************************************************** |
| 17 | */ |
| 18 | |
| 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| 20 | #ifndef STM32F2xx_HAL_I2S_H |
| 21 | #define STM32F2xx_HAL_I2S_H |
| 22 | |
| 23 | #ifdef __cplusplus |
| 24 | extern "C" { |
| 25 | #endif |
| 26 | |
| 27 | /* Includes ------------------------------------------------------------------*/ |
| 28 | #include "stm32f2xx_hal_def.h" |
| 29 | |
| 30 | /** @addtogroup STM32F2xx_HAL_Driver |
| 31 | * @{ |
| 32 | */ |
| 33 | |
| 34 | /** @addtogroup I2S |
| 35 | * @{ |
| 36 | */ |
| 37 | |
| 38 | /* Exported types ------------------------------------------------------------*/ |
| 39 | /** @defgroup I2S_Exported_Types I2S Exported Types |
| 40 | * @{ |
| 41 | */ |
| 42 | |
| 43 | /** |
| 44 | * @brief I2S Init structure definition |
| 45 | */ |
| 46 | typedef struct |
| 47 | { |
| 48 | uint32_t Mode; /*!< Specifies the I2S operating mode. |
| 49 | This parameter can be a value of @ref I2S_Mode */ |
| 50 | |
| 51 | uint32_t Standard; /*!< Specifies the standard used for the I2S communication. |
| 52 | This parameter can be a value of @ref I2S_Standard */ |
| 53 | |
| 54 | uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. |
| 55 | This parameter can be a value of @ref I2S_Data_Format */ |
| 56 | |
| 57 | uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. |
| 58 | This parameter can be a value of @ref I2S_MCLK_Output */ |
| 59 | |
| 60 | uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. |
| 61 | This parameter can be a value of @ref I2S_Audio_Frequency */ |
| 62 | |
| 63 | uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. |
| 64 | This parameter can be a value of @ref I2S_Clock_Polarity */ |
| 65 | |
| 66 | uint32_t ClockSource; /*!< Specifies the I2S Clock Source. |
| 67 | This parameter can be a value of @ref I2S_Clock_Source */ |
| 68 | } I2S_InitTypeDef; |
| 69 | |
| 70 | /** |
| 71 | * @brief HAL State structures definition |
| 72 | */ |
| 73 | typedef enum |
| 74 | { |
| 75 | HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ |
| 76 | HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ |
| 77 | HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ |
| 78 | HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ |
| 79 | HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ |
| 80 | HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ |
| 81 | HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ |
| 82 | } HAL_I2S_StateTypeDef; |
| 83 | |
| 84 | /** |
| 85 | * @brief I2S handle Structure definition |
| 86 | */ |
| 87 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1) |
| 88 | typedef struct __I2S_HandleTypeDef |
| 89 | #else |
| 90 | typedef struct |
| 91 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
| 92 | { |
| 93 | SPI_TypeDef *Instance; /*!< I2S registers base address */ |
| 94 | |
| 95 | I2S_InitTypeDef Init; /*!< I2S communication parameters */ |
| 96 | |
| 97 | uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ |
| 98 | |
| 99 | __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ |
| 100 | |
| 101 | __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ |
| 102 | |
| 103 | uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ |
| 104 | |
| 105 | __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ |
| 106 | |
| 107 | __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter |
| 108 | (This field is initialized at the |
| 109 | same value as transfer size at the |
| 110 | beginning of the transfer and |
| 111 | decremented when a sample is received |
| 112 | NbSamplesReceived = RxBufferSize-RxBufferCount) */ |
| 113 | DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ |
| 114 | |
| 115 | DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ |
| 116 | |
| 117 | __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ |
| 118 | |
| 119 | __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ |
| 120 | |
| 121 | __IO uint32_t ErrorCode; /*!< I2S Error code |
| 122 | This parameter can be a value of @ref I2S_Error */ |
| 123 | |
| 124 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
| 125 | void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ |
| 126 | void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ |
| 127 | void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ |
| 128 | void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ |
| 129 | void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ |
| 130 | void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ |
| 131 | void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ |
| 132 | |
| 133 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
| 134 | } I2S_HandleTypeDef; |
| 135 | |
| 136 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
| 137 | /** |
| 138 | * @brief HAL I2S Callback ID enumeration definition |
| 139 | */ |
| 140 | typedef enum |
| 141 | { |
| 142 | HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */ |
| 143 | HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */ |
| 144 | HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */ |
| 145 | HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */ |
| 146 | HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */ |
| 147 | HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */ |
| 148 | HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */ |
| 149 | |
| 150 | } HAL_I2S_CallbackIDTypeDef; |
| 151 | |
| 152 | /** |
| 153 | * @brief HAL I2S Callback pointer definition |
| 154 | */ |
| 155 | typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ |
| 156 | |
| 157 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
| 158 | /** |
| 159 | * @} |
| 160 | */ |
| 161 | |
| 162 | /* Exported constants --------------------------------------------------------*/ |
| 163 | /** @defgroup I2S_Exported_Constants I2S Exported Constants |
| 164 | * @{ |
| 165 | */ |
| 166 | /** @defgroup I2S_Error I2S Error |
| 167 | * @{ |
| 168 | */ |
| 169 | #define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */ |
| 170 | #define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ |
| 171 | #define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */ |
| 172 | #define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */ |
| 173 | #define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */ |
| 174 | #define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */ |
| 175 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
| 176 | #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ |
| 177 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 178 | #define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 179 | /** |
| 180 | * @} |
| 181 | */ |
| 182 | |
| 183 | /** @defgroup I2S_Mode I2S Mode |
| 184 | * @{ |
| 185 | */ |
| 186 | #define I2S_MODE_SLAVE_TX (0x00000000U) |
| 187 | #define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) |
| 188 | #define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) |
| 189 | #define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)) |
| 190 | /** |
| 191 | * @} |
| 192 | */ |
| 193 | |
| 194 | /** @defgroup I2S_Standard I2S Standard |
| 195 | * @{ |
| 196 | */ |
| 197 | #define I2S_STANDARD_PHILIPS (0x00000000U) |
| 198 | #define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) |
| 199 | #define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) |
| 200 | #define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)) |
| 201 | #define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)) |
| 202 | /** |
| 203 | * @} |
| 204 | */ |
| 205 | |
| 206 | /** @defgroup I2S_Data_Format I2S Data Format |
| 207 | * @{ |
| 208 | */ |
| 209 | #define I2S_DATAFORMAT_16B (0x00000000U) |
| 210 | #define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) |
| 211 | #define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) |
| 212 | #define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) |
| 213 | /** |
| 214 | * @} |
| 215 | */ |
| 216 | |
| 217 | /** @defgroup I2S_MCLK_Output I2S MCLK Output |
| 218 | * @{ |
| 219 | */ |
| 220 | #define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE) |
| 221 | #define I2S_MCLKOUTPUT_DISABLE (0x00000000U) |
| 222 | /** |
| 223 | * @} |
| 224 | */ |
| 225 | |
| 226 | /** @defgroup I2S_Audio_Frequency I2S Audio Frequency |
| 227 | * @{ |
| 228 | */ |
| 229 | #define I2S_AUDIOFREQ_192K (192000U) |
| 230 | #define I2S_AUDIOFREQ_96K (96000U) |
| 231 | #define I2S_AUDIOFREQ_48K (48000U) |
| 232 | #define I2S_AUDIOFREQ_44K (44100U) |
| 233 | #define I2S_AUDIOFREQ_32K (32000U) |
| 234 | #define I2S_AUDIOFREQ_22K (22050U) |
| 235 | #define I2S_AUDIOFREQ_16K (16000U) |
| 236 | #define I2S_AUDIOFREQ_11K (11025U) |
| 237 | #define I2S_AUDIOFREQ_8K (8000U) |
| 238 | #define I2S_AUDIOFREQ_DEFAULT (2U) |
| 239 | /** |
| 240 | * @} |
| 241 | */ |
| 242 | |
| 243 | /** @defgroup I2S_Clock_Polarity I2S Clock Polarity |
| 244 | * @{ |
| 245 | */ |
| 246 | #define I2S_CPOL_LOW (0x00000000U) |
| 247 | #define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) |
| 248 | /** |
| 249 | * @} |
| 250 | */ |
| 251 | |
| 252 | /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition |
| 253 | * @{ |
| 254 | */ |
| 255 | #define I2S_IT_TXE SPI_CR2_TXEIE |
| 256 | #define I2S_IT_RXNE SPI_CR2_RXNEIE |
| 257 | #define I2S_IT_ERR SPI_CR2_ERRIE |
| 258 | /** |
| 259 | * @} |
| 260 | */ |
| 261 | |
| 262 | /** @defgroup I2S_Flags_Definition I2S Flags Definition |
| 263 | * @{ |
| 264 | */ |
| 265 | #define I2S_FLAG_TXE SPI_SR_TXE |
| 266 | #define I2S_FLAG_RXNE SPI_SR_RXNE |
| 267 | |
| 268 | #define I2S_FLAG_UDR SPI_SR_UDR |
| 269 | #define I2S_FLAG_OVR SPI_SR_OVR |
| 270 | #define I2S_FLAG_FRE SPI_SR_FRE |
| 271 | |
| 272 | #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE |
| 273 | #define I2S_FLAG_BSY SPI_SR_BSY |
| 274 | |
| 275 | #define I2S_FLAG_MASK (SPI_SR_RXNE\ |
| 276 | | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) |
| 277 | /** |
| 278 | * @} |
| 279 | */ |
| 280 | |
| 281 | /** @defgroup I2S_Clock_Source I2S Clock Source |
| 282 | * @{ |
| 283 | */ |
| 284 | #define I2S_CLOCK_PLL 0x00000000U |
| 285 | #define I2S_CLOCK_EXTERNAL 0x00000001U |
| 286 | /** |
| 287 | * @} |
| 288 | */ |
| 289 | /** |
| 290 | * @} |
| 291 | */ |
| 292 | |
| 293 | /* Exported macros -----------------------------------------------------------*/ |
| 294 | /** @defgroup I2S_Exported_macros I2S Exported Macros |
| 295 | * @{ |
| 296 | */ |
| 297 | |
| 298 | /** @brief Reset I2S handle state |
| 299 | * @param __HANDLE__ specifies the I2S Handle. |
| 300 | * @retval None |
| 301 | */ |
| 302 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
| 303 | #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
| 304 | (__HANDLE__)->State = HAL_I2S_STATE_RESET; \ |
| 305 | (__HANDLE__)->MspInitCallback = NULL; \ |
| 306 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
| 307 | } while(0) |
| 308 | #else |
| 309 | #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) |
| 310 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
| 311 | |
| 312 | /** @brief Enable the specified SPI peripheral (in I2S mode). |
| 313 | * @param __HANDLE__ specifies the I2S Handle. |
| 314 | * @retval None |
| 315 | */ |
| 316 | #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) |
| 317 | |
| 318 | /** @brief Disable the specified SPI peripheral (in I2S mode). |
| 319 | * @param __HANDLE__ specifies the I2S Handle. |
| 320 | * @retval None |
| 321 | */ |
| 322 | #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) |
| 323 | |
| 324 | /** @brief Enable the specified I2S interrupts. |
| 325 | * @param __HANDLE__ specifies the I2S Handle. |
| 326 | * @param __INTERRUPT__ specifies the interrupt source to enable or disable. |
| 327 | * This parameter can be one of the following values: |
| 328 | * @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
| 329 | * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
| 330 | * @arg I2S_IT_ERR: Error interrupt enable |
| 331 | * @retval None |
| 332 | */ |
| 333 | #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) |
| 334 | |
| 335 | /** @brief Disable the specified I2S interrupts. |
| 336 | * @param __HANDLE__ specifies the I2S Handle. |
| 337 | * @param __INTERRUPT__ specifies the interrupt source to enable or disable. |
| 338 | * This parameter can be one of the following values: |
| 339 | * @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
| 340 | * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
| 341 | * @arg I2S_IT_ERR: Error interrupt enable |
| 342 | * @retval None |
| 343 | */ |
| 344 | #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) |
| 345 | |
| 346 | /** @brief Checks if the specified I2S interrupt source is enabled or disabled. |
| 347 | * @param __HANDLE__ specifies the I2S Handle. |
| 348 | * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. |
| 349 | * @param __INTERRUPT__ specifies the I2S interrupt source to check. |
| 350 | * This parameter can be one of the following values: |
| 351 | * @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
| 352 | * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
| 353 | * @arg I2S_IT_ERR: Error interrupt enable |
| 354 | * @retval The new state of __IT__ (TRUE or FALSE). |
| 355 | */ |
| 356 | #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ |
| 357 | & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| 358 | |
| 359 | /** @brief Checks whether the specified I2S flag is set or not. |
| 360 | * @param __HANDLE__ specifies the I2S Handle. |
| 361 | * @param __FLAG__ specifies the flag to check. |
| 362 | * This parameter can be one of the following values: |
| 363 | * @arg I2S_FLAG_RXNE: Receive buffer not empty flag |
| 364 | * @arg I2S_FLAG_TXE: Transmit buffer empty flag |
| 365 | * @arg I2S_FLAG_UDR: Underrun flag |
| 366 | * @arg I2S_FLAG_OVR: Overrun flag |
| 367 | * @arg I2S_FLAG_FRE: Frame error flag |
| 368 | * @arg I2S_FLAG_CHSIDE: Channel Side flag |
| 369 | * @arg I2S_FLAG_BSY: Busy flag |
| 370 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| 371 | */ |
| 372 | #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
| 373 | |
| 374 | /** @brief Clears the I2S OVR pending flag. |
| 375 | * @param __HANDLE__ specifies the I2S Handle. |
| 376 | * @retval None |
| 377 | */ |
| 378 | #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ |
| 379 | __IO uint32_t tmpreg_ovr = 0x00U; \ |
| 380 | tmpreg_ovr = (__HANDLE__)->Instance->DR; \ |
| 381 | tmpreg_ovr = (__HANDLE__)->Instance->SR; \ |
| 382 | UNUSED(tmpreg_ovr); \ |
| 383 | }while(0U) |
| 384 | /** @brief Clears the I2S UDR pending flag. |
| 385 | * @param __HANDLE__ specifies the I2S Handle. |
| 386 | * @retval None |
| 387 | */ |
| 388 | #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ |
| 389 | __IO uint32_t tmpreg_udr = 0x00U;\ |
| 390 | tmpreg_udr = ((__HANDLE__)->Instance->SR);\ |
| 391 | UNUSED(tmpreg_udr); \ |
| 392 | }while(0U) |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 393 | /** @brief Flush the I2S DR Register. |
| 394 | * @param __HANDLE__ specifies the I2S Handle. |
| 395 | * @retval None |
| 396 | */ |
| 397 | #define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ |
| 398 | __IO uint32_t tmpreg_dr = 0x00U;\ |
| 399 | tmpreg_dr = ((__HANDLE__)->Instance->DR);\ |
| 400 | UNUSED(tmpreg_dr); \ |
| 401 | }while(0U) |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 402 | /** |
| 403 | * @} |
| 404 | */ |
| 405 | |
| 406 | /* Exported functions --------------------------------------------------------*/ |
| 407 | /** @addtogroup I2S_Exported_Functions |
| 408 | * @{ |
| 409 | */ |
| 410 | |
| 411 | /** @addtogroup I2S_Exported_Functions_Group1 |
| 412 | * @{ |
| 413 | */ |
| 414 | /* Initialization/de-initialization functions ********************************/ |
| 415 | HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); |
| 416 | HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); |
| 417 | void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); |
| 418 | void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); |
| 419 | |
| 420 | /* Callbacks Register/UnRegister functions ***********************************/ |
| 421 | #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) |
| 422 | HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, |
| 423 | pI2S_CallbackTypeDef pCallback); |
| 424 | HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); |
| 425 | #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ |
| 426 | /** |
| 427 | * @} |
| 428 | */ |
| 429 | |
| 430 | /** @addtogroup I2S_Exported_Functions_Group2 |
| 431 | * @{ |
| 432 | */ |
| 433 | /* I/O operation functions ***************************************************/ |
| 434 | /* Blocking mode: Polling */ |
| 435 | HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); |
| 436 | HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); |
| 437 | |
| 438 | /* Non-Blocking mode: Interrupt */ |
| 439 | HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| 440 | HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| 441 | void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); |
| 442 | |
| 443 | /* Non-Blocking mode: DMA */ |
| 444 | HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| 445 | HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); |
| 446 | |
| 447 | HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); |
| 448 | HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); |
| 449 | HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); |
| 450 | |
| 451 | /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ |
| 452 | void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); |
| 453 | void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); |
| 454 | void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); |
| 455 | void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); |
| 456 | void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); |
| 457 | /** |
| 458 | * @} |
| 459 | */ |
| 460 | |
| 461 | /** @addtogroup I2S_Exported_Functions_Group3 |
| 462 | * @{ |
| 463 | */ |
| 464 | /* Peripheral Control and State functions ************************************/ |
| 465 | HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); |
| 466 | uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); |
| 467 | /** |
| 468 | * @} |
| 469 | */ |
| 470 | |
| 471 | /** |
| 472 | * @} |
| 473 | */ |
| 474 | |
| 475 | /* Private types -------------------------------------------------------------*/ |
| 476 | /* Private variables ---------------------------------------------------------*/ |
| 477 | /* Private constants ---------------------------------------------------------*/ |
| 478 | /* Private macros ------------------------------------------------------------*/ |
| 479 | /** @defgroup I2S_Private_Macros I2S Private Macros |
| 480 | * @{ |
| 481 | */ |
| 482 | |
| 483 | /** @brief Check whether the specified SPI flag is set or not. |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 484 | * @param __SR__ copy of I2S SR register. |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 485 | * @param __FLAG__ specifies the flag to check. |
| 486 | * This parameter can be one of the following values: |
| 487 | * @arg I2S_FLAG_RXNE: Receive buffer not empty flag |
| 488 | * @arg I2S_FLAG_TXE: Transmit buffer empty flag |
| 489 | * @arg I2S_FLAG_UDR: Underrun error flag |
| 490 | * @arg I2S_FLAG_OVR: Overrun flag |
| 491 | * @arg I2S_FLAG_CHSIDE: Channel side flag |
| 492 | * @arg I2S_FLAG_BSY: Busy flag |
| 493 | * @retval SET or RESET. |
| 494 | */ |
| 495 | #define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ |
| 496 | & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) |
| 497 | |
| 498 | /** @brief Check whether the specified SPI Interrupt is set or not. |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 499 | * @param __CR2__ copy of I2S CR2 register. |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 500 | * @param __INTERRUPT__ specifies the SPI interrupt source to check. |
| 501 | * This parameter can be one of the following values: |
| 502 | * @arg I2S_IT_TXE: Tx buffer empty interrupt enable |
| 503 | * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable |
| 504 | * @arg I2S_IT_ERR: Error interrupt enable |
| 505 | * @retval SET or RESET. |
| 506 | */ |
| 507 | #define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\ |
| 508 | & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| 509 | |
| 510 | /** @brief Checks if I2S Mode parameter is in allowed range. |
| 511 | * @param __MODE__ specifies the I2S Mode. |
| 512 | * This parameter can be a value of @ref I2S_Mode |
| 513 | * @retval None |
| 514 | */ |
| 515 | #define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ |
| 516 | ((__MODE__) == I2S_MODE_SLAVE_RX) || \ |
| 517 | ((__MODE__) == I2S_MODE_MASTER_TX) || \ |
| 518 | ((__MODE__) == I2S_MODE_MASTER_RX)) |
| 519 | |
| 520 | #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ |
| 521 | ((__STANDARD__) == I2S_STANDARD_MSB) || \ |
| 522 | ((__STANDARD__) == I2S_STANDARD_LSB) || \ |
| 523 | ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ |
| 524 | ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) |
| 525 | |
| 526 | #define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ |
| 527 | ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ |
| 528 | ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ |
| 529 | ((__FORMAT__) == I2S_DATAFORMAT_32B)) |
| 530 | |
| 531 | #define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ |
| 532 | ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) |
| 533 | |
| 534 | #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ |
| 535 | ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ |
| 536 | ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) |
| 537 | |
| 538 | /** @brief Checks if I2S Serial clock steady state parameter is in allowed range. |
| 539 | * @param __CPOL__ specifies the I2S serial clock steady state. |
| 540 | * This parameter can be a value of @ref I2S_Clock_Polarity |
| 541 | * @retval None |
| 542 | */ |
| 543 | #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ |
| 544 | ((__CPOL__) == I2S_CPOL_HIGH)) |
| 545 | |
| 546 | #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \ |
| 547 | ((CLOCK) == I2S_CLOCK_PLL)) |
| 548 | /** |
| 549 | * @} |
| 550 | */ |
| 551 | |
| 552 | /** |
| 553 | * @} |
| 554 | */ |
| 555 | |
| 556 | /** |
| 557 | * @} |
| 558 | */ |
| 559 | |
| 560 | #ifdef __cplusplus |
| 561 | } |
| 562 | #endif |
| 563 | |
| 564 | #endif /* STM32F2xx_HAL_I2S_H */ |
Tasnim | f6f6991 | 2023-04-27 17:51:41 +0100 | [diff] [blame] | 565 | |