Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1 | /** |
| 2 | ****************************************************************************** |
| 3 | * @file stm32f2xx_hal_tim.h |
| 4 | * @author MCD Application Team |
| 5 | * @brief Header file of TIM HAL module. |
| 6 | ****************************************************************************** |
| 7 | * @attention |
| 8 | * |
Ali Labbene | e334a50 | 2022-02-08 15:02:11 +0100 | [diff] [blame] | 9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved. |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 11 | * |
Ali Labbene | e334a50 | 2022-02-08 15:02:11 +0100 | [diff] [blame] | 12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * in the root directory of this software component. |
| 14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 15 | * |
| 16 | ****************************************************************************** |
| 17 | */ |
| 18 | |
| 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| 20 | #ifndef STM32F2xx_HAL_TIM_H |
| 21 | #define STM32F2xx_HAL_TIM_H |
| 22 | |
| 23 | #ifdef __cplusplus |
| 24 | extern "C" { |
| 25 | #endif |
| 26 | |
| 27 | /* Includes ------------------------------------------------------------------*/ |
| 28 | #include "stm32f2xx_hal_def.h" |
| 29 | |
| 30 | /** @addtogroup STM32F2xx_HAL_Driver |
| 31 | * @{ |
| 32 | */ |
| 33 | |
| 34 | /** @addtogroup TIM |
| 35 | * @{ |
| 36 | */ |
| 37 | |
| 38 | /* Exported types ------------------------------------------------------------*/ |
| 39 | /** @defgroup TIM_Exported_Types TIM Exported Types |
| 40 | * @{ |
| 41 | */ |
| 42 | |
| 43 | /** |
| 44 | * @brief TIM Time base Configuration Structure definition |
| 45 | */ |
| 46 | typedef struct |
| 47 | { |
| 48 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
| 49 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
| 50 | |
| 51 | uint32_t CounterMode; /*!< Specifies the counter mode. |
| 52 | This parameter can be a value of @ref TIM_Counter_Mode */ |
| 53 | |
| 54 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
| 55 | Auto-Reload Register at the next update event. |
| 56 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
| 57 | |
| 58 | uint32_t ClockDivision; /*!< Specifies the clock division. |
| 59 | This parameter can be a value of @ref TIM_ClockDivision */ |
| 60 | |
| 61 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
| 62 | reaches zero, an update event is generated and counting restarts |
| 63 | from the RCR value (N). |
| 64 | This means in PWM mode that (N+1) corresponds to: |
| 65 | - the number of PWM periods in edge-aligned mode |
| 66 | - the number of half PWM period in center-aligned mode |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 67 | GP timers: this parameter must be a number between Min_Data = 0x00 and |
| 68 | Max_Data = 0xFF. |
| 69 | Advanced timers: this parameter must be a number between Min_Data = 0x0000 and |
| 70 | Max_Data = 0xFFFF. */ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 71 | |
| 72 | uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. |
| 73 | This parameter can be a value of @ref TIM_AutoReloadPreload */ |
| 74 | } TIM_Base_InitTypeDef; |
| 75 | |
| 76 | /** |
| 77 | * @brief TIM Output Compare Configuration Structure definition |
| 78 | */ |
| 79 | typedef struct |
| 80 | { |
| 81 | uint32_t OCMode; /*!< Specifies the TIM mode. |
| 82 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
| 83 | |
| 84 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
| 85 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
| 86 | |
| 87 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
| 88 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
| 89 | |
| 90 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
| 91 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
| 92 | @note This parameter is valid only for timer instances supporting break feature. */ |
| 93 | |
| 94 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
| 95 | This parameter can be a value of @ref TIM_Output_Fast_State |
| 96 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
| 97 | |
| 98 | |
| 99 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
| 100 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
| 101 | @note This parameter is valid only for timer instances supporting break feature. */ |
| 102 | |
| 103 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
| 104 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
| 105 | @note This parameter is valid only for timer instances supporting break feature. */ |
| 106 | } TIM_OC_InitTypeDef; |
| 107 | |
| 108 | /** |
| 109 | * @brief TIM One Pulse Mode Configuration Structure definition |
| 110 | */ |
| 111 | typedef struct |
| 112 | { |
| 113 | uint32_t OCMode; /*!< Specifies the TIM mode. |
| 114 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
| 115 | |
| 116 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
| 117 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
| 118 | |
| 119 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
| 120 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
| 121 | |
| 122 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
| 123 | This parameter can be a value of @ref TIM_Output_Compare_N_Polarity |
| 124 | @note This parameter is valid only for timer instances supporting break feature. */ |
| 125 | |
| 126 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
| 127 | This parameter can be a value of @ref TIM_Output_Compare_Idle_State |
| 128 | @note This parameter is valid only for timer instances supporting break feature. */ |
| 129 | |
| 130 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
| 131 | This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State |
| 132 | @note This parameter is valid only for timer instances supporting break feature. */ |
| 133 | |
| 134 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
| 135 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
| 136 | |
| 137 | uint32_t ICSelection; /*!< Specifies the input. |
| 138 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
| 139 | |
| 140 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
| 141 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 142 | } TIM_OnePulse_InitTypeDef; |
| 143 | |
| 144 | /** |
| 145 | * @brief TIM Input Capture Configuration Structure definition |
| 146 | */ |
| 147 | typedef struct |
| 148 | { |
| 149 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
| 150 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
| 151 | |
| 152 | uint32_t ICSelection; /*!< Specifies the input. |
| 153 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
| 154 | |
| 155 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
| 156 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
| 157 | |
| 158 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
| 159 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 160 | } TIM_IC_InitTypeDef; |
| 161 | |
| 162 | /** |
| 163 | * @brief TIM Encoder Configuration Structure definition |
| 164 | */ |
| 165 | typedef struct |
| 166 | { |
| 167 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
| 168 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
| 169 | |
| 170 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 171 | This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 172 | |
| 173 | uint32_t IC1Selection; /*!< Specifies the input. |
| 174 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
| 175 | |
| 176 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
| 177 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
| 178 | |
| 179 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
| 180 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 181 | |
| 182 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 183 | This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 184 | |
| 185 | uint32_t IC2Selection; /*!< Specifies the input. |
| 186 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
| 187 | |
| 188 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
| 189 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
| 190 | |
| 191 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
| 192 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 193 | } TIM_Encoder_InitTypeDef; |
| 194 | |
| 195 | /** |
| 196 | * @brief Clock Configuration Handle Structure definition |
| 197 | */ |
| 198 | typedef struct |
| 199 | { |
| 200 | uint32_t ClockSource; /*!< TIM clock sources |
| 201 | This parameter can be a value of @ref TIM_Clock_Source */ |
| 202 | uint32_t ClockPolarity; /*!< TIM clock polarity |
| 203 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
| 204 | uint32_t ClockPrescaler; /*!< TIM clock prescaler |
| 205 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
| 206 | uint32_t ClockFilter; /*!< TIM clock filter |
| 207 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 208 | } TIM_ClockConfigTypeDef; |
| 209 | |
| 210 | /** |
| 211 | * @brief TIM Clear Input Configuration Handle Structure definition |
| 212 | */ |
| 213 | typedef struct |
| 214 | { |
| 215 | uint32_t ClearInputState; /*!< TIM clear Input state |
| 216 | This parameter can be ENABLE or DISABLE */ |
| 217 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
| 218 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
| 219 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
| 220 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
| 221 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 222 | This parameter must be 0: When OCRef clear feature is used with ETR source, |
| 223 | ETR prescaler must be off */ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 224 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
| 225 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 226 | } TIM_ClearInputConfigTypeDef; |
| 227 | |
| 228 | /** |
| 229 | * @brief TIM Master configuration Structure definition |
| 230 | */ |
| 231 | typedef struct |
| 232 | { |
| 233 | uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection |
| 234 | This parameter can be a value of @ref TIM_Master_Mode_Selection */ |
| 235 | uint32_t MasterSlaveMode; /*!< Master/slave mode selection |
| 236 | This parameter can be a value of @ref TIM_Master_Slave_Mode |
| 237 | @note When the Master/slave mode is enabled, the effect of |
| 238 | an event on the trigger input (TRGI) is delayed to allow a |
| 239 | perfect synchronization between the current timer and its |
| 240 | slaves (through TRGO). It is not mandatory in case of timer |
| 241 | synchronization mode. */ |
| 242 | } TIM_MasterConfigTypeDef; |
| 243 | |
| 244 | /** |
| 245 | * @brief TIM Slave configuration Structure definition |
| 246 | */ |
| 247 | typedef struct |
| 248 | { |
| 249 | uint32_t SlaveMode; /*!< Slave mode selection |
| 250 | This parameter can be a value of @ref TIM_Slave_Mode */ |
| 251 | uint32_t InputTrigger; /*!< Input Trigger source |
| 252 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
| 253 | uint32_t TriggerPolarity; /*!< Input Trigger polarity |
| 254 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
| 255 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler |
| 256 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
| 257 | uint32_t TriggerFilter; /*!< Input trigger filter |
| 258 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 259 | |
| 260 | } TIM_SlaveConfigTypeDef; |
| 261 | |
| 262 | /** |
| 263 | * @brief TIM Break input(s) and Dead time configuration Structure definition |
| 264 | * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable |
| 265 | * filter and polarity. |
| 266 | */ |
| 267 | typedef struct |
| 268 | { |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 269 | uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ |
| 270 | |
| 271 | uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ |
| 272 | |
| 273 | uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ |
| 274 | |
| 275 | uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
| 276 | |
| 277 | uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ |
| 278 | |
| 279 | uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ |
| 280 | |
| 281 | uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 282 | |
| 283 | uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
| 284 | |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 285 | } TIM_BreakDeadTimeConfigTypeDef; |
| 286 | |
| 287 | /** |
| 288 | * @brief HAL State structures definition |
| 289 | */ |
| 290 | typedef enum |
| 291 | { |
| 292 | HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ |
| 293 | HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
| 294 | HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
| 295 | HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
| 296 | HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ |
| 297 | } HAL_TIM_StateTypeDef; |
| 298 | |
| 299 | /** |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 300 | * @brief TIM Channel States definition |
| 301 | */ |
| 302 | typedef enum |
| 303 | { |
| 304 | HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ |
| 305 | HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ |
| 306 | HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ |
| 307 | } HAL_TIM_ChannelStateTypeDef; |
| 308 | |
| 309 | /** |
| 310 | * @brief DMA Burst States definition |
| 311 | */ |
| 312 | typedef enum |
| 313 | { |
| 314 | HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ |
| 315 | HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ |
| 316 | HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ |
| 317 | } HAL_TIM_DMABurstStateTypeDef; |
| 318 | |
| 319 | /** |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 320 | * @brief HAL Active channel structures definition |
| 321 | */ |
| 322 | typedef enum |
| 323 | { |
| 324 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ |
| 325 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ |
| 326 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ |
| 327 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ |
| 328 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ |
| 329 | } HAL_TIM_ActiveChannel; |
| 330 | |
| 331 | /** |
| 332 | * @brief TIM Time Base Handle Structure definition |
| 333 | */ |
| 334 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| 335 | typedef struct __TIM_HandleTypeDef |
| 336 | #else |
| 337 | typedef struct |
| 338 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| 339 | { |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 340 | TIM_TypeDef *Instance; /*!< Register base address */ |
| 341 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
| 342 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
| 343 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
| 344 | This array is accessed by a @ref DMA_Handle_index */ |
| 345 | HAL_LockTypeDef Lock; /*!< Locking object */ |
| 346 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
| 347 | __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ |
| 348 | __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ |
| 349 | __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 350 | |
| 351 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| 352 | void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ |
| 353 | void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ |
| 354 | void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ |
| 355 | void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ |
| 356 | void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ |
| 357 | void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ |
| 358 | void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ |
| 359 | void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ |
| 360 | void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ |
| 361 | void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ |
| 362 | void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ |
| 363 | void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ |
| 364 | void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ |
| 365 | void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ |
| 366 | void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ |
| 367 | void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ |
| 368 | void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ |
| 369 | void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ |
| 370 | void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ |
| 371 | void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ |
| 372 | void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ |
| 373 | void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ |
| 374 | void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ |
| 375 | void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ |
| 376 | void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ |
| 377 | void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ |
| 378 | void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ |
| 379 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| 380 | } TIM_HandleTypeDef; |
| 381 | |
| 382 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| 383 | /** |
| 384 | * @brief HAL TIM Callback ID enumeration definition |
| 385 | */ |
| 386 | typedef enum |
| 387 | { |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 388 | HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ |
| 389 | , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ |
| 390 | , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ |
| 391 | , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ |
| 392 | , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ |
| 393 | , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ |
| 394 | , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ |
| 395 | , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ |
| 396 | , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ |
| 397 | , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ |
| 398 | , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ |
| 399 | , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ |
| 400 | , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ |
| 401 | , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ |
| 402 | , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ |
| 403 | , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ |
| 404 | , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ |
| 405 | , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 406 | |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 407 | , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ |
| 408 | , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ |
| 409 | , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ |
| 410 | , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ |
| 411 | , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ |
| 412 | , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ |
| 413 | , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ |
| 414 | , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ |
| 415 | , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 416 | } HAL_TIM_CallbackIDTypeDef; |
| 417 | |
| 418 | /** |
| 419 | * @brief HAL TIM Callback pointer definition |
| 420 | */ |
| 421 | typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ |
| 422 | |
| 423 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| 424 | |
| 425 | /** |
| 426 | * @} |
| 427 | */ |
| 428 | /* End of exported types -----------------------------------------------------*/ |
| 429 | |
| 430 | /* Exported constants --------------------------------------------------------*/ |
| 431 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
| 432 | * @{ |
| 433 | */ |
| 434 | |
| 435 | /** @defgroup TIM_ClearInput_Source TIM Clear Input Source |
| 436 | * @{ |
| 437 | */ |
| 438 | #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ |
| 439 | #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ |
| 440 | /** |
| 441 | * @} |
| 442 | */ |
| 443 | |
| 444 | /** @defgroup TIM_DMA_Base_address TIM DMA Base Address |
| 445 | * @{ |
| 446 | */ |
| 447 | #define TIM_DMABASE_CR1 0x00000000U |
| 448 | #define TIM_DMABASE_CR2 0x00000001U |
| 449 | #define TIM_DMABASE_SMCR 0x00000002U |
| 450 | #define TIM_DMABASE_DIER 0x00000003U |
| 451 | #define TIM_DMABASE_SR 0x00000004U |
| 452 | #define TIM_DMABASE_EGR 0x00000005U |
| 453 | #define TIM_DMABASE_CCMR1 0x00000006U |
| 454 | #define TIM_DMABASE_CCMR2 0x00000007U |
| 455 | #define TIM_DMABASE_CCER 0x00000008U |
| 456 | #define TIM_DMABASE_CNT 0x00000009U |
| 457 | #define TIM_DMABASE_PSC 0x0000000AU |
| 458 | #define TIM_DMABASE_ARR 0x0000000BU |
| 459 | #define TIM_DMABASE_RCR 0x0000000CU |
| 460 | #define TIM_DMABASE_CCR1 0x0000000DU |
| 461 | #define TIM_DMABASE_CCR2 0x0000000EU |
| 462 | #define TIM_DMABASE_CCR3 0x0000000FU |
| 463 | #define TIM_DMABASE_CCR4 0x00000010U |
| 464 | #define TIM_DMABASE_BDTR 0x00000011U |
| 465 | #define TIM_DMABASE_DCR 0x00000012U |
| 466 | #define TIM_DMABASE_DMAR 0x00000013U |
| 467 | /** |
| 468 | * @} |
| 469 | */ |
| 470 | |
| 471 | /** @defgroup TIM_Event_Source TIM Event Source |
| 472 | * @{ |
| 473 | */ |
| 474 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ |
| 475 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ |
| 476 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ |
| 477 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ |
| 478 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ |
| 479 | #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ |
| 480 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ |
| 481 | #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ |
| 482 | /** |
| 483 | * @} |
| 484 | */ |
| 485 | |
| 486 | /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity |
| 487 | * @{ |
| 488 | */ |
| 489 | #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ |
| 490 | #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ |
| 491 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
| 492 | /** |
| 493 | * @} |
| 494 | */ |
| 495 | |
| 496 | /** @defgroup TIM_ETR_Polarity TIM ETR Polarity |
| 497 | * @{ |
| 498 | */ |
| 499 | #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ |
| 500 | #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ |
| 501 | /** |
| 502 | * @} |
| 503 | */ |
| 504 | |
| 505 | /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler |
| 506 | * @{ |
| 507 | */ |
| 508 | #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ |
| 509 | #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ |
| 510 | #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ |
| 511 | #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ |
| 512 | /** |
| 513 | * @} |
| 514 | */ |
| 515 | |
| 516 | /** @defgroup TIM_Counter_Mode TIM Counter Mode |
| 517 | * @{ |
| 518 | */ |
| 519 | #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ |
| 520 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ |
| 521 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ |
| 522 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ |
| 523 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ |
| 524 | /** |
| 525 | * @} |
| 526 | */ |
| 527 | |
| 528 | /** @defgroup TIM_ClockDivision TIM Clock Division |
| 529 | * @{ |
| 530 | */ |
| 531 | #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ |
| 532 | #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ |
| 533 | #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ |
| 534 | /** |
| 535 | * @} |
| 536 | */ |
| 537 | |
| 538 | /** @defgroup TIM_Output_Compare_State TIM Output Compare State |
| 539 | * @{ |
| 540 | */ |
| 541 | #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ |
| 542 | #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ |
| 543 | /** |
| 544 | * @} |
| 545 | */ |
| 546 | |
| 547 | /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload |
| 548 | * @{ |
| 549 | */ |
| 550 | #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ |
| 551 | #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ |
| 552 | |
| 553 | /** |
| 554 | * @} |
| 555 | */ |
| 556 | |
| 557 | /** @defgroup TIM_Output_Fast_State TIM Output Fast State |
| 558 | * @{ |
| 559 | */ |
| 560 | #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ |
| 561 | #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ |
| 562 | /** |
| 563 | * @} |
| 564 | */ |
| 565 | |
| 566 | /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State |
| 567 | * @{ |
| 568 | */ |
| 569 | #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ |
| 570 | #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ |
| 571 | /** |
| 572 | * @} |
| 573 | */ |
| 574 | |
| 575 | /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity |
| 576 | * @{ |
| 577 | */ |
| 578 | #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ |
| 579 | #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ |
| 580 | /** |
| 581 | * @} |
| 582 | */ |
| 583 | |
| 584 | /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity |
| 585 | * @{ |
| 586 | */ |
| 587 | #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ |
| 588 | #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ |
| 589 | /** |
| 590 | * @} |
| 591 | */ |
| 592 | |
| 593 | /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State |
| 594 | * @{ |
| 595 | */ |
| 596 | #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ |
| 597 | #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ |
| 598 | /** |
| 599 | * @} |
| 600 | */ |
| 601 | |
| 602 | /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State |
| 603 | * @{ |
| 604 | */ |
| 605 | #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ |
| 606 | #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ |
| 607 | /** |
| 608 | * @} |
| 609 | */ |
| 610 | |
| 611 | /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity |
| 612 | * @{ |
| 613 | */ |
| 614 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ |
| 615 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ |
| 616 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ |
| 617 | /** |
| 618 | * @} |
| 619 | */ |
| 620 | |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 621 | /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity |
| 622 | * @{ |
| 623 | */ |
| 624 | #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ |
| 625 | #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ |
| 626 | /** |
| 627 | * @} |
| 628 | */ |
| 629 | |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 630 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
| 631 | * @{ |
| 632 | */ |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 633 | #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ |
| 634 | #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 635 | #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
| 636 | /** |
| 637 | * @} |
| 638 | */ |
| 639 | |
| 640 | /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler |
| 641 | * @{ |
| 642 | */ |
| 643 | #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ |
| 644 | #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ |
| 645 | #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ |
| 646 | #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ |
| 647 | /** |
| 648 | * @} |
| 649 | */ |
| 650 | |
| 651 | /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode |
| 652 | * @{ |
| 653 | */ |
| 654 | #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ |
| 655 | #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ |
| 656 | /** |
| 657 | * @} |
| 658 | */ |
| 659 | |
| 660 | /** @defgroup TIM_Encoder_Mode TIM Encoder Mode |
| 661 | * @{ |
| 662 | */ |
| 663 | #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
| 664 | #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ |
| 665 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ |
| 666 | /** |
| 667 | * @} |
| 668 | */ |
| 669 | |
| 670 | /** @defgroup TIM_Interrupt_definition TIM interrupt Definition |
| 671 | * @{ |
| 672 | */ |
| 673 | #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ |
| 674 | #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ |
| 675 | #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ |
| 676 | #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ |
| 677 | #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ |
| 678 | #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ |
| 679 | #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ |
| 680 | #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ |
| 681 | /** |
| 682 | * @} |
| 683 | */ |
| 684 | |
| 685 | /** @defgroup TIM_Commutation_Source TIM Commutation Source |
| 686 | * @{ |
| 687 | */ |
| 688 | #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ |
| 689 | #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ |
| 690 | /** |
| 691 | * @} |
| 692 | */ |
| 693 | |
| 694 | /** @defgroup TIM_DMA_sources TIM DMA Sources |
| 695 | * @{ |
| 696 | */ |
| 697 | #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ |
| 698 | #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ |
| 699 | #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ |
| 700 | #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ |
| 701 | #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ |
| 702 | #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ |
| 703 | #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ |
| 704 | /** |
| 705 | * @} |
| 706 | */ |
| 707 | |
| 708 | /** @defgroup TIM_Flag_definition TIM Flag Definition |
| 709 | * @{ |
| 710 | */ |
| 711 | #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ |
| 712 | #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ |
| 713 | #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ |
| 714 | #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ |
| 715 | #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ |
| 716 | #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ |
| 717 | #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ |
| 718 | #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ |
| 719 | #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ |
| 720 | #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ |
| 721 | #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ |
| 722 | #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ |
| 723 | /** |
| 724 | * @} |
| 725 | */ |
| 726 | |
| 727 | /** @defgroup TIM_Channel TIM Channel |
| 728 | * @{ |
| 729 | */ |
| 730 | #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ |
| 731 | #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ |
| 732 | #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ |
| 733 | #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ |
| 734 | #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ |
| 735 | /** |
| 736 | * @} |
| 737 | */ |
| 738 | |
| 739 | /** @defgroup TIM_Clock_Source TIM Clock Source |
| 740 | * @{ |
| 741 | */ |
| 742 | #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ |
| 743 | #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ |
| 744 | #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ |
| 745 | #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ |
| 746 | #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ |
| 747 | #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ |
| 748 | #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ |
| 749 | #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ |
| 750 | #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ |
| 751 | #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ |
| 752 | /** |
| 753 | * @} |
| 754 | */ |
| 755 | |
| 756 | /** @defgroup TIM_Clock_Polarity TIM Clock Polarity |
| 757 | * @{ |
| 758 | */ |
| 759 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
| 760 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
| 761 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
| 762 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
| 763 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
| 764 | /** |
| 765 | * @} |
| 766 | */ |
| 767 | |
| 768 | /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler |
| 769 | * @{ |
| 770 | */ |
| 771 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
| 772 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
| 773 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
| 774 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
| 775 | /** |
| 776 | * @} |
| 777 | */ |
| 778 | |
| 779 | /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity |
| 780 | * @{ |
| 781 | */ |
| 782 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
| 783 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
| 784 | /** |
| 785 | * @} |
| 786 | */ |
| 787 | |
| 788 | /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler |
| 789 | * @{ |
| 790 | */ |
| 791 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
| 792 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
| 793 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
| 794 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
| 795 | /** |
| 796 | * @} |
| 797 | */ |
| 798 | |
| 799 | /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state |
| 800 | * @{ |
| 801 | */ |
| 802 | #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ |
| 803 | #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ |
| 804 | /** |
| 805 | * @} |
| 806 | */ |
| 807 | |
| 808 | /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state |
| 809 | * @{ |
| 810 | */ |
| 811 | #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ |
| 812 | #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ |
| 813 | /** |
| 814 | * @} |
| 815 | */ |
| 816 | /** @defgroup TIM_Lock_level TIM Lock level |
| 817 | * @{ |
| 818 | */ |
| 819 | #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ |
| 820 | #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ |
| 821 | #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ |
| 822 | #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ |
| 823 | /** |
| 824 | * @} |
| 825 | */ |
| 826 | |
| 827 | /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable |
| 828 | * @{ |
| 829 | */ |
| 830 | #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ |
| 831 | #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ |
| 832 | /** |
| 833 | * @} |
| 834 | */ |
| 835 | |
| 836 | /** @defgroup TIM_Break_Polarity TIM Break Input Polarity |
| 837 | * @{ |
| 838 | */ |
| 839 | #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ |
| 840 | #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ |
| 841 | /** |
| 842 | * @} |
| 843 | */ |
| 844 | |
| 845 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable |
| 846 | * @{ |
| 847 | */ |
| 848 | #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 849 | #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 850 | /** |
| 851 | * @} |
| 852 | */ |
| 853 | |
| 854 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
| 855 | * @{ |
| 856 | */ |
| 857 | #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ |
| 858 | #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ |
| 859 | #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ |
| 860 | #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ |
| 861 | #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ |
| 862 | #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ |
| 863 | #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ |
| 864 | #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ |
| 865 | /** |
| 866 | * @} |
| 867 | */ |
| 868 | |
| 869 | /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode |
| 870 | * @{ |
| 871 | */ |
| 872 | #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ |
| 873 | #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ |
| 874 | /** |
| 875 | * @} |
| 876 | */ |
| 877 | |
| 878 | /** @defgroup TIM_Slave_Mode TIM Slave mode |
| 879 | * @{ |
| 880 | */ |
| 881 | #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ |
| 882 | #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ |
| 883 | #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ |
| 884 | #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ |
| 885 | #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ |
| 886 | /** |
| 887 | * @} |
| 888 | */ |
| 889 | |
| 890 | /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes |
| 891 | * @{ |
| 892 | */ |
| 893 | #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ |
| 894 | #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ |
| 895 | #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ |
| 896 | #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ |
| 897 | #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ |
| 898 | #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ |
| 899 | #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ |
| 900 | #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ |
| 901 | /** |
| 902 | * @} |
| 903 | */ |
| 904 | |
| 905 | /** @defgroup TIM_Trigger_Selection TIM Trigger Selection |
| 906 | * @{ |
| 907 | */ |
| 908 | #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ |
| 909 | #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ |
| 910 | #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ |
| 911 | #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ |
| 912 | #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ |
| 913 | #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ |
| 914 | #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ |
| 915 | #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ |
| 916 | #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ |
| 917 | /** |
| 918 | * @} |
| 919 | */ |
| 920 | |
| 921 | /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity |
| 922 | * @{ |
| 923 | */ |
| 924 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
| 925 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
| 926 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
| 927 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
| 928 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
| 929 | /** |
| 930 | * @} |
| 931 | */ |
| 932 | |
| 933 | /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler |
| 934 | * @{ |
| 935 | */ |
| 936 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
| 937 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
| 938 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
| 939 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
| 940 | /** |
| 941 | * @} |
| 942 | */ |
| 943 | |
| 944 | /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection |
| 945 | * @{ |
| 946 | */ |
| 947 | #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ |
| 948 | #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ |
| 949 | /** |
| 950 | * @} |
| 951 | */ |
| 952 | |
| 953 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
| 954 | * @{ |
| 955 | */ |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 956 | #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 957 | #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 958 | #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 959 | #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 960 | #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 961 | #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 962 | #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 963 | #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 964 | #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 965 | #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 966 | #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 967 | #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 968 | #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 969 | #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 970 | #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 971 | #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 972 | #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 973 | #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 974 | /** |
| 975 | * @} |
| 976 | */ |
| 977 | |
| 978 | /** @defgroup DMA_Handle_index TIM DMA Handle Index |
| 979 | * @{ |
| 980 | */ |
| 981 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ |
| 982 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
| 983 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
| 984 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
| 985 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
| 986 | #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ |
| 987 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ |
| 988 | /** |
| 989 | * @} |
| 990 | */ |
| 991 | |
| 992 | /** @defgroup Channel_CC_State TIM Capture/Compare Channel State |
| 993 | * @{ |
| 994 | */ |
| 995 | #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ |
| 996 | #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ |
| 997 | #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ |
| 998 | #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ |
| 999 | /** |
| 1000 | * @} |
| 1001 | */ |
| 1002 | |
| 1003 | /** |
| 1004 | * @} |
| 1005 | */ |
| 1006 | /* End of exported constants -------------------------------------------------*/ |
| 1007 | |
| 1008 | /* Exported macros -----------------------------------------------------------*/ |
| 1009 | /** @defgroup TIM_Exported_Macros TIM Exported Macros |
| 1010 | * @{ |
| 1011 | */ |
| 1012 | |
| 1013 | /** @brief Reset TIM handle state. |
| 1014 | * @param __HANDLE__ TIM handle. |
| 1015 | * @retval None |
| 1016 | */ |
| 1017 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 1018 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
| 1019 | (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ |
| 1020 | (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1021 | (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1022 | (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1023 | (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1024 | (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1025 | (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1026 | (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1027 | (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1028 | (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ |
| 1029 | (__HANDLE__)->Base_MspInitCallback = NULL; \ |
| 1030 | (__HANDLE__)->Base_MspDeInitCallback = NULL; \ |
| 1031 | (__HANDLE__)->IC_MspInitCallback = NULL; \ |
| 1032 | (__HANDLE__)->IC_MspDeInitCallback = NULL; \ |
| 1033 | (__HANDLE__)->OC_MspInitCallback = NULL; \ |
| 1034 | (__HANDLE__)->OC_MspDeInitCallback = NULL; \ |
| 1035 | (__HANDLE__)->PWM_MspInitCallback = NULL; \ |
| 1036 | (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ |
| 1037 | (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ |
| 1038 | (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ |
| 1039 | (__HANDLE__)->Encoder_MspInitCallback = NULL; \ |
| 1040 | (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ |
| 1041 | (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ |
| 1042 | (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1043 | } while(0) |
| 1044 | #else |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 1045 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
| 1046 | (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ |
| 1047 | (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1048 | (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1049 | (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1050 | (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1051 | (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1052 | (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1053 | (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1054 | (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
| 1055 | (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ |
| 1056 | } while(0) |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1057 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| 1058 | |
| 1059 | /** |
| 1060 | * @brief Enable the TIM peripheral. |
| 1061 | * @param __HANDLE__ TIM handle |
| 1062 | * @retval None |
| 1063 | */ |
| 1064 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
| 1065 | |
| 1066 | /** |
| 1067 | * @brief Enable the TIM main Output. |
| 1068 | * @param __HANDLE__ TIM handle |
| 1069 | * @retval None |
| 1070 | */ |
| 1071 | #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) |
| 1072 | |
| 1073 | /** |
| 1074 | * @brief Disable the TIM peripheral. |
| 1075 | * @param __HANDLE__ TIM handle |
| 1076 | * @retval None |
| 1077 | */ |
| 1078 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
| 1079 | do { \ |
| 1080 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ |
| 1081 | { \ |
| 1082 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ |
| 1083 | { \ |
| 1084 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
| 1085 | } \ |
| 1086 | } \ |
| 1087 | } while(0) |
| 1088 | |
| 1089 | /** |
| 1090 | * @brief Disable the TIM main Output. |
| 1091 | * @param __HANDLE__ TIM handle |
| 1092 | * @retval None |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 1093 | * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been |
| 1094 | * disabled |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1095 | */ |
| 1096 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
| 1097 | do { \ |
| 1098 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ |
| 1099 | { \ |
| 1100 | if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ |
| 1101 | { \ |
| 1102 | (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ |
| 1103 | } \ |
| 1104 | } \ |
| 1105 | } while(0) |
| 1106 | |
| 1107 | /** |
| 1108 | * @brief Disable the TIM main Output. |
| 1109 | * @param __HANDLE__ TIM handle |
| 1110 | * @retval None |
| 1111 | * @note The Main Output Enable of a timer instance is disabled unconditionally |
| 1112 | */ |
| 1113 | #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) |
| 1114 | |
| 1115 | /** @brief Enable the specified TIM interrupt. |
| 1116 | * @param __HANDLE__ specifies the TIM Handle. |
| 1117 | * @param __INTERRUPT__ specifies the TIM interrupt source to enable. |
| 1118 | * This parameter can be one of the following values: |
| 1119 | * @arg TIM_IT_UPDATE: Update interrupt |
| 1120 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
| 1121 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
| 1122 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
| 1123 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
| 1124 | * @arg TIM_IT_COM: Commutation interrupt |
| 1125 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
| 1126 | * @arg TIM_IT_BREAK: Break interrupt |
| 1127 | * @retval None |
| 1128 | */ |
| 1129 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
| 1130 | |
| 1131 | /** @brief Disable the specified TIM interrupt. |
| 1132 | * @param __HANDLE__ specifies the TIM Handle. |
| 1133 | * @param __INTERRUPT__ specifies the TIM interrupt source to disable. |
| 1134 | * This parameter can be one of the following values: |
| 1135 | * @arg TIM_IT_UPDATE: Update interrupt |
| 1136 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
| 1137 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
| 1138 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
| 1139 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
| 1140 | * @arg TIM_IT_COM: Commutation interrupt |
| 1141 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
| 1142 | * @arg TIM_IT_BREAK: Break interrupt |
| 1143 | * @retval None |
| 1144 | */ |
| 1145 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
| 1146 | |
| 1147 | /** @brief Enable the specified DMA request. |
| 1148 | * @param __HANDLE__ specifies the TIM Handle. |
| 1149 | * @param __DMA__ specifies the TIM DMA request to enable. |
| 1150 | * This parameter can be one of the following values: |
| 1151 | * @arg TIM_DMA_UPDATE: Update DMA request |
| 1152 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
| 1153 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
| 1154 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
| 1155 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
| 1156 | * @arg TIM_DMA_COM: Commutation DMA request |
| 1157 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
| 1158 | * @retval None |
| 1159 | */ |
| 1160 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
| 1161 | |
| 1162 | /** @brief Disable the specified DMA request. |
| 1163 | * @param __HANDLE__ specifies the TIM Handle. |
| 1164 | * @param __DMA__ specifies the TIM DMA request to disable. |
| 1165 | * This parameter can be one of the following values: |
| 1166 | * @arg TIM_DMA_UPDATE: Update DMA request |
| 1167 | * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request |
| 1168 | * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request |
| 1169 | * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request |
| 1170 | * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request |
| 1171 | * @arg TIM_DMA_COM: Commutation DMA request |
| 1172 | * @arg TIM_DMA_TRIGGER: Trigger DMA request |
| 1173 | * @retval None |
| 1174 | */ |
| 1175 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
| 1176 | |
| 1177 | /** @brief Check whether the specified TIM interrupt flag is set or not. |
| 1178 | * @param __HANDLE__ specifies the TIM Handle. |
| 1179 | * @param __FLAG__ specifies the TIM interrupt flag to check. |
| 1180 | * This parameter can be one of the following values: |
| 1181 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
| 1182 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
| 1183 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
| 1184 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
| 1185 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
| 1186 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
| 1187 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
| 1188 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
| 1189 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
| 1190 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
| 1191 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
| 1192 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
| 1193 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| 1194 | */ |
| 1195 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
| 1196 | |
| 1197 | /** @brief Clear the specified TIM interrupt flag. |
| 1198 | * @param __HANDLE__ specifies the TIM Handle. |
| 1199 | * @param __FLAG__ specifies the TIM interrupt flag to clear. |
| 1200 | * This parameter can be one of the following values: |
| 1201 | * @arg TIM_FLAG_UPDATE: Update interrupt flag |
| 1202 | * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag |
| 1203 | * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag |
| 1204 | * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag |
| 1205 | * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag |
| 1206 | * @arg TIM_FLAG_COM: Commutation interrupt flag |
| 1207 | * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag |
| 1208 | * @arg TIM_FLAG_BREAK: Break interrupt flag |
| 1209 | * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag |
| 1210 | * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag |
| 1211 | * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag |
| 1212 | * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag |
| 1213 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| 1214 | */ |
| 1215 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
| 1216 | |
| 1217 | /** |
| 1218 | * @brief Check whether the specified TIM interrupt source is enabled or not. |
| 1219 | * @param __HANDLE__ TIM handle |
| 1220 | * @param __INTERRUPT__ specifies the TIM interrupt source to check. |
| 1221 | * This parameter can be one of the following values: |
| 1222 | * @arg TIM_IT_UPDATE: Update interrupt |
| 1223 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
| 1224 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
| 1225 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
| 1226 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
| 1227 | * @arg TIM_IT_COM: Commutation interrupt |
| 1228 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
| 1229 | * @arg TIM_IT_BREAK: Break interrupt |
| 1230 | * @retval The state of TIM_IT (SET or RESET). |
| 1231 | */ |
| 1232 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ |
| 1233 | == (__INTERRUPT__)) ? SET : RESET) |
| 1234 | |
| 1235 | /** @brief Clear the TIM interrupt pending bits. |
| 1236 | * @param __HANDLE__ TIM handle |
| 1237 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
| 1238 | * This parameter can be one of the following values: |
| 1239 | * @arg TIM_IT_UPDATE: Update interrupt |
| 1240 | * @arg TIM_IT_CC1: Capture/Compare 1 interrupt |
| 1241 | * @arg TIM_IT_CC2: Capture/Compare 2 interrupt |
| 1242 | * @arg TIM_IT_CC3: Capture/Compare 3 interrupt |
| 1243 | * @arg TIM_IT_CC4: Capture/Compare 4 interrupt |
| 1244 | * @arg TIM_IT_COM: Commutation interrupt |
| 1245 | * @arg TIM_IT_TRIGGER: Trigger interrupt |
| 1246 | * @arg TIM_IT_BREAK: Break interrupt |
| 1247 | * @retval None |
| 1248 | */ |
| 1249 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
| 1250 | |
| 1251 | /** |
| 1252 | * @brief Indicates whether or not the TIM Counter is used as downcounter. |
| 1253 | * @param __HANDLE__ TIM handle. |
| 1254 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 1255 | * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode |
| 1256 | * or Encoder mode. |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1257 | */ |
| 1258 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
| 1259 | |
| 1260 | /** |
| 1261 | * @brief Set the TIM Prescaler on runtime. |
| 1262 | * @param __HANDLE__ TIM handle. |
| 1263 | * @param __PRESC__ specifies the Prescaler new value. |
| 1264 | * @retval None |
| 1265 | */ |
| 1266 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
| 1267 | |
| 1268 | /** |
| 1269 | * @brief Set the TIM Counter Register value on runtime. |
| 1270 | * @param __HANDLE__ TIM handle. |
| 1271 | * @param __COUNTER__ specifies the Counter register new value. |
| 1272 | * @retval None |
| 1273 | */ |
| 1274 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
| 1275 | |
| 1276 | /** |
| 1277 | * @brief Get the TIM Counter Register value on runtime. |
| 1278 | * @param __HANDLE__ TIM handle. |
| 1279 | * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) |
| 1280 | */ |
| 1281 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) |
| 1282 | |
| 1283 | /** |
| 1284 | * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. |
| 1285 | * @param __HANDLE__ TIM handle. |
| 1286 | * @param __AUTORELOAD__ specifies the Counter register new value. |
| 1287 | * @retval None |
| 1288 | */ |
| 1289 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
| 1290 | do{ \ |
| 1291 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
| 1292 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
| 1293 | } while(0) |
| 1294 | |
| 1295 | /** |
| 1296 | * @brief Get the TIM Autoreload Register value on runtime. |
| 1297 | * @param __HANDLE__ TIM handle. |
| 1298 | * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) |
| 1299 | */ |
| 1300 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) |
| 1301 | |
| 1302 | /** |
| 1303 | * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. |
| 1304 | * @param __HANDLE__ TIM handle. |
| 1305 | * @param __CKD__ specifies the clock division value. |
| 1306 | * This parameter can be one of the following value: |
| 1307 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
| 1308 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
| 1309 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
| 1310 | * @retval None |
| 1311 | */ |
| 1312 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
| 1313 | do{ \ |
| 1314 | (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ |
| 1315 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
| 1316 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
| 1317 | } while(0) |
| 1318 | |
| 1319 | /** |
| 1320 | * @brief Get the TIM Clock Division value on runtime. |
| 1321 | * @param __HANDLE__ TIM handle. |
| 1322 | * @retval The clock division can be one of the following values: |
| 1323 | * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT |
| 1324 | * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT |
| 1325 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
| 1326 | */ |
| 1327 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
| 1328 | |
| 1329 | /** |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 1330 | * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() |
| 1331 | * function. |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1332 | * @param __HANDLE__ TIM handle. |
| 1333 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1334 | * This parameter can be one of the following values: |
| 1335 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1336 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1337 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1338 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1339 | * @param __ICPSC__ specifies the Input Capture4 prescaler new value. |
| 1340 | * This parameter can be one of the following values: |
| 1341 | * @arg TIM_ICPSC_DIV1: no prescaler |
| 1342 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
| 1343 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
| 1344 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
| 1345 | * @retval None |
| 1346 | */ |
| 1347 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
| 1348 | do{ \ |
| 1349 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
| 1350 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
| 1351 | } while(0) |
| 1352 | |
| 1353 | /** |
| 1354 | * @brief Get the TIM Input Capture prescaler on runtime. |
| 1355 | * @param __HANDLE__ TIM handle. |
| 1356 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1357 | * This parameter can be one of the following values: |
| 1358 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
| 1359 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
| 1360 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
| 1361 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
| 1362 | * @retval The input capture prescaler can be one of the following values: |
| 1363 | * @arg TIM_ICPSC_DIV1: no prescaler |
| 1364 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
| 1365 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
| 1366 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
| 1367 | */ |
| 1368 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
| 1369 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
| 1370 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ |
| 1371 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
| 1372 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) |
| 1373 | |
| 1374 | /** |
| 1375 | * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. |
| 1376 | * @param __HANDLE__ TIM handle. |
| 1377 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1378 | * This parameter can be one of the following values: |
| 1379 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1380 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1381 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1382 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1383 | * @param __COMPARE__ specifies the Capture Compare register new value. |
| 1384 | * @retval None |
| 1385 | */ |
| 1386 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
| 1387 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ |
| 1388 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ |
| 1389 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ |
| 1390 | ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) |
| 1391 | |
| 1392 | /** |
| 1393 | * @brief Get the TIM Capture Compare Register value on runtime. |
| 1394 | * @param __HANDLE__ TIM handle. |
| 1395 | * @param __CHANNEL__ TIM Channel associated with the capture compare register |
| 1396 | * This parameter can be one of the following values: |
| 1397 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
| 1398 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
| 1399 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
| 1400 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
| 1401 | * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) |
| 1402 | */ |
| 1403 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
| 1404 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ |
| 1405 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ |
| 1406 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ |
| 1407 | ((__HANDLE__)->Instance->CCR4)) |
| 1408 | |
| 1409 | /** |
| 1410 | * @brief Set the TIM Output compare preload. |
| 1411 | * @param __HANDLE__ TIM handle. |
| 1412 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1413 | * This parameter can be one of the following values: |
| 1414 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1415 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1416 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1417 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1418 | * @retval None |
| 1419 | */ |
| 1420 | #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
| 1421 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ |
| 1422 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ |
| 1423 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ |
| 1424 | ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) |
| 1425 | |
| 1426 | /** |
| 1427 | * @brief Reset the TIM Output compare preload. |
| 1428 | * @param __HANDLE__ TIM handle. |
| 1429 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1430 | * This parameter can be one of the following values: |
| 1431 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1432 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1433 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1434 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1435 | * @retval None |
| 1436 | */ |
| 1437 | #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
| 1438 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ |
| 1439 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ |
| 1440 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ |
| 1441 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) |
| 1442 | |
| 1443 | /** |
| 1444 | * @brief Enable fast mode for a given channel. |
| 1445 | * @param __HANDLE__ TIM handle. |
| 1446 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1447 | * This parameter can be one of the following values: |
| 1448 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1449 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1450 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1451 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1452 | * @note When fast mode is enabled an active edge on the trigger input acts |
| 1453 | * like a compare match on CCx output. Delay to sample the trigger |
| 1454 | * input and to activate CCx output is reduced to 3 clock cycles. |
| 1455 | * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. |
| 1456 | * @retval None |
| 1457 | */ |
| 1458 | #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ |
| 1459 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ |
| 1460 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ |
| 1461 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ |
| 1462 | ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) |
| 1463 | |
| 1464 | /** |
| 1465 | * @brief Disable fast mode for a given channel. |
| 1466 | * @param __HANDLE__ TIM handle. |
| 1467 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1468 | * This parameter can be one of the following values: |
| 1469 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1470 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1471 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1472 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1473 | * @note When fast mode is disabled CCx output behaves normally depending |
| 1474 | * on counter and CCRx values even when the trigger is ON. The minimum |
| 1475 | * delay to activate CCx output when an active edge occurs on the |
| 1476 | * trigger input is 5 clock cycles. |
| 1477 | * @retval None |
| 1478 | */ |
| 1479 | #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ |
| 1480 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ |
| 1481 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ |
| 1482 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ |
| 1483 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) |
| 1484 | |
| 1485 | /** |
| 1486 | * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. |
| 1487 | * @param __HANDLE__ TIM handle. |
| 1488 | * @note When the URS bit of the TIMx_CR1 register is set, only counter |
| 1489 | * overflow/underflow generates an update interrupt or DMA request (if |
| 1490 | * enabled) |
| 1491 | * @retval None |
| 1492 | */ |
| 1493 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) |
| 1494 | |
| 1495 | /** |
| 1496 | * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. |
| 1497 | * @param __HANDLE__ TIM handle. |
| 1498 | * @note When the URS bit of the TIMx_CR1 register is reset, any of the |
| 1499 | * following events generate an update interrupt or DMA request (if |
| 1500 | * enabled): |
| 1501 | * _ Counter overflow underflow |
| 1502 | * _ Setting the UG bit |
| 1503 | * _ Update generation through the slave mode controller |
| 1504 | * @retval None |
| 1505 | */ |
| 1506 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) |
| 1507 | |
| 1508 | /** |
| 1509 | * @brief Set the TIM Capture x input polarity on runtime. |
| 1510 | * @param __HANDLE__ TIM handle. |
| 1511 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1512 | * This parameter can be one of the following values: |
| 1513 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1514 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| 1515 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| 1516 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| 1517 | * @param __POLARITY__ Polarity for TIx source |
| 1518 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
| 1519 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
| 1520 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
| 1521 | * @retval None |
| 1522 | */ |
| 1523 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
| 1524 | do{ \ |
| 1525 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
| 1526 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
| 1527 | }while(0) |
| 1528 | |
| 1529 | /** |
| 1530 | * @} |
| 1531 | */ |
| 1532 | /* End of exported macros ----------------------------------------------------*/ |
| 1533 | |
| 1534 | /* Private constants ---------------------------------------------------------*/ |
| 1535 | /** @defgroup TIM_Private_Constants TIM Private Constants |
| 1536 | * @{ |
| 1537 | */ |
| 1538 | /* The counter of a timer instance is disabled only if all the CCx and CCxN |
| 1539 | channels have been disabled */ |
| 1540 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
| 1541 | #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) |
| 1542 | /** |
| 1543 | * @} |
| 1544 | */ |
| 1545 | /* End of private constants --------------------------------------------------*/ |
| 1546 | |
| 1547 | /* Private macros ------------------------------------------------------------*/ |
| 1548 | /** @defgroup TIM_Private_Macros TIM Private Macros |
| 1549 | * @{ |
| 1550 | */ |
| 1551 | #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ |
| 1552 | ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) |
| 1553 | |
| 1554 | #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ |
| 1555 | ((__BASE__) == TIM_DMABASE_CR2) || \ |
| 1556 | ((__BASE__) == TIM_DMABASE_SMCR) || \ |
| 1557 | ((__BASE__) == TIM_DMABASE_DIER) || \ |
| 1558 | ((__BASE__) == TIM_DMABASE_SR) || \ |
| 1559 | ((__BASE__) == TIM_DMABASE_EGR) || \ |
| 1560 | ((__BASE__) == TIM_DMABASE_CCMR1) || \ |
| 1561 | ((__BASE__) == TIM_DMABASE_CCMR2) || \ |
| 1562 | ((__BASE__) == TIM_DMABASE_CCER) || \ |
| 1563 | ((__BASE__) == TIM_DMABASE_CNT) || \ |
| 1564 | ((__BASE__) == TIM_DMABASE_PSC) || \ |
| 1565 | ((__BASE__) == TIM_DMABASE_ARR) || \ |
| 1566 | ((__BASE__) == TIM_DMABASE_RCR) || \ |
| 1567 | ((__BASE__) == TIM_DMABASE_CCR1) || \ |
| 1568 | ((__BASE__) == TIM_DMABASE_CCR2) || \ |
| 1569 | ((__BASE__) == TIM_DMABASE_CCR3) || \ |
| 1570 | ((__BASE__) == TIM_DMABASE_CCR4) || \ |
| 1571 | ((__BASE__) == TIM_DMABASE_BDTR)) |
| 1572 | |
| 1573 | #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
| 1574 | |
| 1575 | #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ |
| 1576 | ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ |
| 1577 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
| 1578 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
| 1579 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) |
| 1580 | |
| 1581 | #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ |
| 1582 | ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ |
| 1583 | ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) |
| 1584 | |
| 1585 | #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ |
| 1586 | ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) |
| 1587 | |
| 1588 | #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ |
| 1589 | ((__STATE__) == TIM_OCFAST_ENABLE)) |
| 1590 | |
| 1591 | #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ |
| 1592 | ((__POLARITY__) == TIM_OCPOLARITY_LOW)) |
| 1593 | |
| 1594 | #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ |
| 1595 | ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) |
| 1596 | |
| 1597 | #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ |
| 1598 | ((__STATE__) == TIM_OCIDLESTATE_RESET)) |
| 1599 | |
| 1600 | #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ |
| 1601 | ((__STATE__) == TIM_OCNIDLESTATE_RESET)) |
| 1602 | |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 1603 | #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ |
| 1604 | ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) |
| 1605 | |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1606 | #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ |
| 1607 | ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ |
| 1608 | ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) |
| 1609 | |
| 1610 | #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ |
| 1611 | ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ |
| 1612 | ((__SELECTION__) == TIM_ICSELECTION_TRC)) |
| 1613 | |
| 1614 | #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ |
| 1615 | ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ |
| 1616 | ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ |
| 1617 | ((__PRESCALER__) == TIM_ICPSC_DIV8)) |
| 1618 | |
| 1619 | #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ |
| 1620 | ((__MODE__) == TIM_OPMODE_REPETITIVE)) |
| 1621 | |
| 1622 | #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ |
| 1623 | ((__MODE__) == TIM_ENCODERMODE_TI2) || \ |
| 1624 | ((__MODE__) == TIM_ENCODERMODE_TI12)) |
| 1625 | |
| 1626 | #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
| 1627 | |
| 1628 | #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
| 1629 | ((__CHANNEL__) == TIM_CHANNEL_2) || \ |
| 1630 | ((__CHANNEL__) == TIM_CHANNEL_3) || \ |
| 1631 | ((__CHANNEL__) == TIM_CHANNEL_4) || \ |
| 1632 | ((__CHANNEL__) == TIM_CHANNEL_ALL)) |
| 1633 | |
| 1634 | #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
| 1635 | ((__CHANNEL__) == TIM_CHANNEL_2)) |
| 1636 | |
| 1637 | #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
| 1638 | ((__CHANNEL__) == TIM_CHANNEL_2) || \ |
| 1639 | ((__CHANNEL__) == TIM_CHANNEL_3)) |
| 1640 | |
| 1641 | #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ |
| 1642 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
| 1643 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ |
| 1644 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ |
| 1645 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ |
| 1646 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ |
| 1647 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ |
| 1648 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ |
| 1649 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ |
| 1650 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) |
| 1651 | |
| 1652 | #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ |
| 1653 | ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
| 1654 | ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ |
| 1655 | ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ |
| 1656 | ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
| 1657 | |
| 1658 | #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ |
| 1659 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ |
| 1660 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ |
| 1661 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) |
| 1662 | |
| 1663 | #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
| 1664 | |
| 1665 | #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
| 1666 | ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
| 1667 | |
| 1668 | #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
| 1669 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
| 1670 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
| 1671 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) |
| 1672 | |
| 1673 | #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
| 1674 | |
| 1675 | #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ |
| 1676 | ((__STATE__) == TIM_OSSR_DISABLE)) |
| 1677 | |
| 1678 | #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ |
| 1679 | ((__STATE__) == TIM_OSSI_DISABLE)) |
| 1680 | |
| 1681 | #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ |
| 1682 | ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ |
| 1683 | ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ |
| 1684 | ((__LEVEL__) == TIM_LOCKLEVEL_3)) |
| 1685 | |
| 1686 | #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) |
| 1687 | |
| 1688 | |
| 1689 | #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ |
| 1690 | ((__STATE__) == TIM_BREAK_DISABLE)) |
| 1691 | |
| 1692 | #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ |
| 1693 | ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) |
| 1694 | |
| 1695 | #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ |
| 1696 | ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) |
| 1697 | |
| 1698 | #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ |
| 1699 | ((__SOURCE__) == TIM_TRGO_ENABLE) || \ |
| 1700 | ((__SOURCE__) == TIM_TRGO_UPDATE) || \ |
| 1701 | ((__SOURCE__) == TIM_TRGO_OC1) || \ |
| 1702 | ((__SOURCE__) == TIM_TRGO_OC1REF) || \ |
| 1703 | ((__SOURCE__) == TIM_TRGO_OC2REF) || \ |
| 1704 | ((__SOURCE__) == TIM_TRGO_OC3REF) || \ |
| 1705 | ((__SOURCE__) == TIM_TRGO_OC4REF)) |
| 1706 | |
| 1707 | #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
| 1708 | ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) |
| 1709 | |
| 1710 | #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ |
| 1711 | ((__MODE__) == TIM_SLAVEMODE_RESET) || \ |
| 1712 | ((__MODE__) == TIM_SLAVEMODE_GATED) || \ |
| 1713 | ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ |
| 1714 | ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) |
| 1715 | |
| 1716 | #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ |
| 1717 | ((__MODE__) == TIM_OCMODE_PWM2)) |
| 1718 | |
| 1719 | #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ |
| 1720 | ((__MODE__) == TIM_OCMODE_ACTIVE) || \ |
| 1721 | ((__MODE__) == TIM_OCMODE_INACTIVE) || \ |
| 1722 | ((__MODE__) == TIM_OCMODE_TOGGLE) || \ |
| 1723 | ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ |
| 1724 | ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) |
| 1725 | |
| 1726 | #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
| 1727 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
| 1728 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
| 1729 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
| 1730 | ((__SELECTION__) == TIM_TS_TI1F_ED) || \ |
| 1731 | ((__SELECTION__) == TIM_TS_TI1FP1) || \ |
| 1732 | ((__SELECTION__) == TIM_TS_TI2FP2) || \ |
| 1733 | ((__SELECTION__) == TIM_TS_ETRF)) |
| 1734 | |
| 1735 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
| 1736 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
| 1737 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
| 1738 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
| 1739 | ((__SELECTION__) == TIM_TS_NONE)) |
| 1740 | |
| 1741 | #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
| 1742 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
| 1743 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ |
| 1744 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
| 1745 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
| 1746 | |
| 1747 | #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ |
| 1748 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ |
| 1749 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ |
| 1750 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) |
| 1751 | |
| 1752 | #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
| 1753 | |
| 1754 | #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ |
| 1755 | ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) |
| 1756 | |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 1757 | #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
| 1758 | ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
| 1759 | ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
| 1760 | ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
| 1761 | ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
| 1762 | ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
| 1763 | ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
| 1764 | ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
| 1765 | ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1766 | ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
| 1767 | ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
| 1768 | ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
| 1769 | ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
| 1770 | ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
| 1771 | ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
| 1772 | ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
| 1773 | ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
| 1774 | ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) |
| 1775 | |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 1776 | #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) |
| 1777 | |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1778 | #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
| 1779 | |
| 1780 | #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) |
| 1781 | |
| 1782 | #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) |
| 1783 | |
| 1784 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
| 1785 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
| 1786 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ |
| 1787 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
| 1788 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) |
| 1789 | |
| 1790 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
| 1791 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ |
| 1792 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ |
| 1793 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ |
| 1794 | ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) |
| 1795 | |
| 1796 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
| 1797 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
| 1798 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ |
| 1799 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ |
| 1800 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) |
| 1801 | |
| 1802 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
| 1803 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
| 1804 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
| 1805 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
| 1806 | ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) |
| 1807 | |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 1808 | #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ |
| 1809 | (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ |
| 1810 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ |
| 1811 | ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ |
| 1812 | (__HANDLE__)->ChannelState[3]) |
| 1813 | |
| 1814 | #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ |
| 1815 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ |
| 1816 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ |
| 1817 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ |
| 1818 | ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) |
| 1819 | |
| 1820 | #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ |
| 1821 | (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ |
| 1822 | (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ |
| 1823 | (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ |
| 1824 | (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ |
| 1825 | } while(0) |
| 1826 | |
| 1827 | #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ |
| 1828 | (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ |
| 1829 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ |
| 1830 | ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ |
| 1831 | (__HANDLE__)->ChannelNState[3]) |
| 1832 | |
| 1833 | #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ |
| 1834 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ |
| 1835 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ |
| 1836 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ |
| 1837 | ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) |
| 1838 | |
| 1839 | #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 1840 | (__HANDLE__)->ChannelNState[0] = \ |
| 1841 | (__CHANNEL_STATE__); \ |
| 1842 | (__HANDLE__)->ChannelNState[1] = \ |
| 1843 | (__CHANNEL_STATE__); \ |
| 1844 | (__HANDLE__)->ChannelNState[2] = \ |
| 1845 | (__CHANNEL_STATE__); \ |
| 1846 | (__HANDLE__)->ChannelNState[3] = \ |
| 1847 | (__CHANNEL_STATE__); \ |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 1848 | } while(0) |
| 1849 | |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1850 | /** |
| 1851 | * @} |
| 1852 | */ |
| 1853 | /* End of private macros -----------------------------------------------------*/ |
| 1854 | |
| 1855 | /* Include TIM HAL Extended module */ |
| 1856 | #include "stm32f2xx_hal_tim_ex.h" |
| 1857 | |
| 1858 | /* Exported functions --------------------------------------------------------*/ |
| 1859 | /** @addtogroup TIM_Exported_Functions TIM Exported Functions |
| 1860 | * @{ |
| 1861 | */ |
| 1862 | |
| 1863 | /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions |
| 1864 | * @brief Time Base functions |
| 1865 | * @{ |
| 1866 | */ |
| 1867 | /* Time Base functions ********************************************************/ |
| 1868 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
| 1869 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
| 1870 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
| 1871 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
| 1872 | /* Blocking mode: Polling */ |
| 1873 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
| 1874 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
| 1875 | /* Non-Blocking mode: Interrupt */ |
| 1876 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
| 1877 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
| 1878 | /* Non-Blocking mode: DMA */ |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 1879 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1880 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
| 1881 | /** |
| 1882 | * @} |
| 1883 | */ |
| 1884 | |
| 1885 | /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions |
| 1886 | * @brief TIM Output Compare functions |
| 1887 | * @{ |
| 1888 | */ |
| 1889 | /* Timer Output Compare functions *********************************************/ |
| 1890 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
| 1891 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
| 1892 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
| 1893 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
| 1894 | /* Blocking mode: Polling */ |
| 1895 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1896 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1897 | /* Non-Blocking mode: Interrupt */ |
| 1898 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1899 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1900 | /* Non-Blocking mode: DMA */ |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 1901 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, |
| 1902 | uint16_t Length); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1903 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1904 | /** |
| 1905 | * @} |
| 1906 | */ |
| 1907 | |
| 1908 | /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions |
| 1909 | * @brief TIM PWM functions |
| 1910 | * @{ |
| 1911 | */ |
| 1912 | /* Timer PWM functions ********************************************************/ |
| 1913 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
| 1914 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
| 1915 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
| 1916 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
| 1917 | /* Blocking mode: Polling */ |
| 1918 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1919 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1920 | /* Non-Blocking mode: Interrupt */ |
| 1921 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1922 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1923 | /* Non-Blocking mode: DMA */ |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 1924 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, |
| 1925 | uint16_t Length); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 1926 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1927 | /** |
| 1928 | * @} |
| 1929 | */ |
| 1930 | |
| 1931 | /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions |
| 1932 | * @brief TIM Input Capture functions |
| 1933 | * @{ |
| 1934 | */ |
| 1935 | /* Timer Input Capture functions **********************************************/ |
| 1936 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
| 1937 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
| 1938 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
| 1939 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
| 1940 | /* Blocking mode: Polling */ |
| 1941 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1942 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1943 | /* Non-Blocking mode: Interrupt */ |
| 1944 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1945 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1946 | /* Non-Blocking mode: DMA */ |
| 1947 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
| 1948 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1949 | /** |
| 1950 | * @} |
| 1951 | */ |
| 1952 | |
| 1953 | /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions |
| 1954 | * @brief TIM One Pulse functions |
| 1955 | * @{ |
| 1956 | */ |
| 1957 | /* Timer One Pulse functions **************************************************/ |
| 1958 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
| 1959 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
| 1960 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
| 1961 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
| 1962 | /* Blocking mode: Polling */ |
| 1963 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| 1964 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| 1965 | /* Non-Blocking mode: Interrupt */ |
| 1966 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| 1967 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
| 1968 | /** |
| 1969 | * @} |
| 1970 | */ |
| 1971 | |
| 1972 | /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions |
| 1973 | * @brief TIM Encoder functions |
| 1974 | * @{ |
| 1975 | */ |
| 1976 | /* Timer Encoder functions ****************************************************/ |
| 1977 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); |
| 1978 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
| 1979 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
| 1980 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
| 1981 | /* Blocking mode: Polling */ |
| 1982 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1983 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1984 | /* Non-Blocking mode: Interrupt */ |
| 1985 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1986 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1987 | /* Non-Blocking mode: DMA */ |
| 1988 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, |
| 1989 | uint32_t *pData2, uint16_t Length); |
| 1990 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1991 | /** |
| 1992 | * @} |
| 1993 | */ |
| 1994 | |
| 1995 | /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management |
| 1996 | * @brief IRQ handler management |
| 1997 | * @{ |
| 1998 | */ |
| 1999 | /* Interrupt Handler functions ***********************************************/ |
| 2000 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
| 2001 | /** |
| 2002 | * @} |
| 2003 | */ |
| 2004 | |
| 2005 | /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions |
| 2006 | * @brief Peripheral Control functions |
| 2007 | * @{ |
| 2008 | */ |
| 2009 | /* Control functions *********************************************************/ |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 2010 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, |
| 2011 | uint32_t Channel); |
| 2012 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, |
| 2013 | uint32_t Channel); |
| 2014 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, |
| 2015 | uint32_t Channel); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 2016 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, |
| 2017 | uint32_t OutputChannel, uint32_t InputChannel); |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 2018 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, |
| 2019 | const TIM_ClearInputConfigTypeDef *sClearInputConfig, |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 2020 | uint32_t Channel); |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 2021 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 2022 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 2023 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); |
| 2024 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 2025 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 2026 | uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 2027 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 2028 | uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 2029 | uint32_t BurstLength, uint32_t DataLength); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 2030 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
| 2031 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
| 2032 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 2033 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
rihab kouki | cc54dd7 | 2021-06-07 15:36:20 +0100 | [diff] [blame] | 2034 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, |
| 2035 | uint32_t BurstLength, uint32_t DataLength); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 2036 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
| 2037 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 2038 | uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 2039 | /** |
| 2040 | * @} |
| 2041 | */ |
| 2042 | |
| 2043 | /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions |
| 2044 | * @brief TIM Callbacks functions |
| 2045 | * @{ |
| 2046 | */ |
| 2047 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
| 2048 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
| 2049 | void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); |
| 2050 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
| 2051 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
| 2052 | void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); |
| 2053 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
| 2054 | void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); |
| 2055 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
| 2056 | void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); |
| 2057 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
| 2058 | |
| 2059 | /* Callbacks Register/UnRegister functions ***********************************/ |
| 2060 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| 2061 | HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, |
| 2062 | pTIM_CallbackTypeDef pCallback); |
| 2063 | HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); |
| 2064 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| 2065 | |
| 2066 | /** |
| 2067 | * @} |
| 2068 | */ |
| 2069 | |
| 2070 | /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions |
| 2071 | * @brief Peripheral State functions |
| 2072 | * @{ |
| 2073 | */ |
| 2074 | /* Peripheral State functions ************************************************/ |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 2075 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); |
| 2076 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); |
| 2077 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); |
| 2078 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); |
| 2079 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); |
| 2080 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); |
Ali Labbene | c75ace9 | 2020-10-05 10:33:46 +0100 | [diff] [blame] | 2081 | |
| 2082 | /* Peripheral Channel state functions ************************************************/ |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 2083 | HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); |
| 2084 | HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); |
| 2085 | HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 2086 | /** |
| 2087 | * @} |
| 2088 | */ |
| 2089 | |
| 2090 | /** |
| 2091 | * @} |
| 2092 | */ |
| 2093 | /* End of exported functions -------------------------------------------------*/ |
| 2094 | |
| 2095 | /* Private functions----------------------------------------------------------*/ |
| 2096 | /** @defgroup TIM_Private_Functions TIM Private Functions |
| 2097 | * @{ |
| 2098 | */ |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 2099 | void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 2100 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
Ali Labbene | 0a7d9c8 | 2022-05-13 17:01:16 +0100 | [diff] [blame] | 2101 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 2102 | void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, |
| 2103 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); |
| 2104 | |
Eya | 644d2f0 | 2020-01-29 12:30:25 +0100 | [diff] [blame] | 2105 | void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); |
| 2106 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
| 2107 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
| 2108 | void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); |
| 2109 | void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); |
| 2110 | |
| 2111 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| 2112 | void TIM_ResetCallback(TIM_HandleTypeDef *htim); |
| 2113 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| 2114 | |
| 2115 | /** |
| 2116 | * @} |
| 2117 | */ |
| 2118 | /* End of private functions --------------------------------------------------*/ |
| 2119 | |
| 2120 | /** |
| 2121 | * @} |
| 2122 | */ |
| 2123 | |
| 2124 | /** |
| 2125 | * @} |
| 2126 | */ |
| 2127 | |
| 2128 | #ifdef __cplusplus |
| 2129 | } |
| 2130 | #endif |
| 2131 | |
| 2132 | #endif /* STM32F2xx_HAL_TIM_H */ |